CN117438376B - 一种基于二维材料的互补性场效应晶体管及制备方法 - Google Patents
一种基于二维材料的互补性场效应晶体管及制备方法 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Abstract
本发明涉及半导体技术领域,公开了一种基于二维半导体材料的互补性场效应晶体管的制备方法:清洗衬底;在所述衬底上制备标记层;制备第一沟道材料;在第一沟道材料表面制备第一源漏电极;对第一沟道材料进行氧掺杂;在所述第一源漏电极和第一沟道材料表面上沉积第一栅介质,并在第一栅介质上制备栅电极,从而制备得到底部场效应晶体管;制备背栅,在所述底部场效应晶体管上沉积第二栅介质;在第二栅介质表面形成第二沟道材料;在第二沟道材料上制备第二源漏电极,得到顶部场效应晶体管后便完成CFET的制备。本发明制备的CFET中第一、第二沟道材料为同一种二维材料,相较基于不同沟道材料的CFET,本发明的CFET具有更高的成本效益和更低的制备难度。
Description
技术领域
本发明属于半导体器件技术领域,特别是涉及一种基于二维材料的互补性场效应晶体管及制备方法。
背景技术
在半导体器件中,随着硅晶体管的特征尺寸持续微缩,由于短沟道效应,基于传统平面结构的互补金属氧化物半导体器件(Complementary Metal-Oxide-Semiconductor,CMOS)进一步提高集成度将变得愈发困难。因此,新的三维器件架构被提出,如互补性场效应晶体管(Complementary Field-EffectTransistor ,CFET),CFET是由NMOS和PMOS晶体管垂直堆叠而成,并且两者共用同一个栅极,可以减小芯片单元近一半的面积,实现更高的集成度。同时其在功耗和性能表现方面也有优势,所以CFET提供了将摩尔定律继续向更小的技术节点发展的巨大前景。
基于传统的体半导体材料(如硅、锗等)的互补性场效应晶体管,由于短沟道效应的影响,随着沟道长度和沟道厚度减小,性能是趋向于退化的,这使得器件的微缩潜力是受限的。二维半导体材料具有原子级的厚度和无悬挂键的表面,使其可以有效地免疫短沟道效应的影响,有望替代硅等传统半导体材料而应用于下一代电子和光电子器件。因此,基于二维半导体材料的互补性场效应晶体管可以进一步提高器件的集成度。
现有的基于二维半导体材料的互补性场效应晶体管,NMOS和PMOS采用不同的沟道材料,由于不同的二维材料在其制备过程中具有不同的要求和反应机理,所以需要针对其特定的生长机制开发相应的制备工艺,对于器件制备来说,增加了工艺流程步骤,不利于成本控制和效率提升。
发明内容
本发明的目的是提供一种基于二维半导体材料的互补性场效应晶体管的制备方法,使用同一种二维半导体材料作为底部和顶部晶体管的沟道材料,可以简化器件的制备流程,具有更高的成本效益。
为了实现上述的目的,本发明提供了一种基于二维半导体材料的互补性场效应晶体管的制备方法,包括:
S1:准备清洁的衬底;
S2:在所述衬底上制备标记层;
S3:将二维材料薄膜转移至所述衬底表面,用作所述互补性场效应晶体管的第一沟道材料;
S4:采用电子束光刻和电子束蒸发工艺在所述沟道材料表面制备第一源漏电极;
S5:通过在氧气氛围中退火对所述沟道材料进行氧掺杂;
S6:在所述第一源漏电极和第一沟道材料表面上沉积第一栅介质,并通过电子束蒸发工艺在所述第一栅介质上制备栅电极,从而制备得到底部场效应晶体管;
S7:制备背栅,在所述底部场效应晶体管上沉积第二栅介质;
S8:使用等离子体刻蚀工艺对所述第一源漏电极区域上的介质进行选择性刻蚀获得通孔;
S9:将二维材料薄膜转移至所述第二栅介质表面,用作所述互补性场效应晶体管的第二沟道材料;
S10:通过电子束光刻和电子束蒸发工艺在所述第二沟道材料上制备第二源漏电极,从而得到了顶部场效应晶体管,完成了所述互补性场效应晶体管的制备。
根据本发明的一个实施方式,所述衬底为二氧化硅衬底或硅衬底。
根据本发明的一个实施方式,步骤S2中,标记层的制备方法为:在所述衬底表面旋涂光刻胶,使用电子束光刻完成标记层的图案转移,通过电子束蒸发在所述的图案上制备物理标记,用作转移后二维材料的定位标记和版图不同层之间的对准标记。
根据本发明的一个实施方式,步骤S3中和S9中采用的二维材料相同,所述二维材料为二硫化钼、二硒化钼、二碲化钼、二硫化钨、二硒化钨、二硒化铼、二硒化锡、三硒化二铟或碲化镓。
根据本发明的一个实施方式,步骤S5中,所述氧气氛围退火条件为氩气与氧气流量比为8:1-10:1,退火温度为200-220摄氏度。
根据本发明的一个实施方式,所述第一栅介质和第二栅介质通过原子层沉积二氧化铪薄膜得到,所述第一栅介质的前驱体为四(乙基甲基胺)铪和臭氧。
根据本发明的一个实施方式,所述二氧化铪薄膜厚度为5-20纳米。
根据本发明的一个实施方式,所述第一、第二源漏电极使用的金属为镍、钛、钌、铑、钯、银、锇、铱、铂、金、钛、铝、铬、锗、钼、钨、铜、钴或铁中的一种或两种以上组合。
根据本发明的一个实施方式,步骤S8中的通孔用于所述第一源漏电极与第二源漏电极之间的互连。
根据本发明的另一个方面,本发明还提供了利用上述方法制备的一种基于二维半导体材料的互补性场效应晶体管。
总体而言,通过本发明所构思的以上技术方案与现有技术相比,主要具备以下的技术优点:
(1)本发明提供的半导体器件制备方法,采用了转移或是直接沉积的方式一层层地将沟道材料、栅介质、栅电极、源漏接触金属堆叠而得到CFET器件,相较于以选择性刻蚀、沟道释放、保形性沉积、隔离层形成等作为关键工艺的CFET制备技术,本发明提出的半导体器件制备方法简化了工艺流程,具有更高的成本效益。
(2)本发明所述的半导体器件的制备方法中,使用了二维半导体材料,替代了传统的半导体材料,这是由于二维半导体材料具有原子级厚度和无悬挂键表面的特点,使其可以在纳米厚度的情况下维持高质量的晶格和良好的迁移率。此外,将PMOS和NMOS垂直堆叠在一起的CFET架构,放弃了传统的并排PMOS和NMOS布置,可以突破n-p间距的瓶颈,因此本发明提出的堆叠二维半导体材料晶体管的先进架构能进一步减少半导体技术节点,从而有利于未来的半导体器件进一步微缩。
(3)本发明方法制备的CFET器件,其底部和顶部的场效应晶体管采用了同一种二维半导体材料作为沟道材料,实现了CFET器件中具有同质沟道的N型晶体管和P型晶体管的集成。
附图说明
图1为本发明实施例提供的一种基于二维半导体材料的CFET的制备方法的流程框图。
图2至图9为本发明实例提供的一种基于二维半导体材料的CFET制备流程过程中的结构变化示意图。
附图标记:11为硅衬底,112为二氧化硅,111为硅,211为二碲化钼薄膜(a),212为10纳米铂和30纳米金的源漏接触金属,213为第一栅介质,214为第一栅电极,311为第二栅介质,312为二碲化钼薄膜(b),313为20纳米镍和40纳米金的源漏接触金属。
具体实施方式
为了使本发明所述制备方法更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。此外,在以下的说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
互补场效应晶体管器件(Complementary Field Effect Transistor,可缩写为CFET)包括垂直堆叠的N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor,可缩写为NMOS)晶体管和P型金属-氧化物-半导体(P-Metal-Oxide-Semiconductor,可缩写为PMOS)晶体管,以提高CMOS器件的集成密度。
总的来说,本发明基于二维半导体材料二碲化钼制备互补性场效应晶体管,使用原子层沉积设备生长栅介质薄膜、电子束蒸发设备沉积金属、电子束光刻设备实现图案转移,本实例场效应晶体管的沟道材料为二碲化钼,具有双极性的传输特性。除二碲化钼外还可以扩展到其他二维材料,金属接触可以为镍等其他金属,可以根据需求选择沟道材料与接触金属。
为了更好的说明本发明实施例提供的一种基于二维半导体材料二碲化钼的CFET器件制备方法,下面通过实施例做进一步的举例说明。
实施例1
一种基于二维材料二碲化钼的CFET器件制备方法,其流程如图1所示,具体包括如下步骤:
S1,衬底清洗:如图2所示,使用硅111和二氧化硅112共同作为硅衬底11,为了去除表面的颗粒和杂质,需要对其进行清洗,配置去离子水:氨水 = 5:1溶液,其中去离子水为150毫升,倒入烧杯中,在热板上加热至70 ℃,加入双氧水,加热溶液至110 ℃,溶液冒泡后,放入硅片,加热10 min后取出,使用去离子水清洗硅片表面,之后使用氮气枪吹干即可。
S2,制备标记层:清洗后的硅衬底11上没有可以用来标记的参照物,为了方便对后续转移到硅衬底11上的二维材料进行位置标定,需要在硅衬底11上制备标记层。在清洗后的硅衬底11上滴聚甲基丙烯酸甲酯电子束光刻胶(PMMA A4),覆盖硅衬底11表面的三分之二的区域,使用匀胶机旋涂光刻胶,转速为3000转每分钟,时间为60秒;在热板上烘胶,温度为180摄氏度,时间为90秒;使用电子束光刻设备以标记层为版图进行曝光;显影液为甲基异丁基酮(MIBK)与异丙醇(IPA)质量比为1比3的混合溶液,将硅衬底11浸入溶液50秒,取出后使用IPA清洗30秒,使用氮气枪吹干;使用电子束蒸发设备沉积金属,沉积的金属为20纳米的镍和40纳米的金;将衬底浸入50摄氏度的丙酮溶液中20 min,之后使用注射器冲洗将未曝光区域的光刻胶和金属剥离下来,剥离后使用IPA清洗,再用氮气枪吹干。
S3,机械剥离和转移第一沟道材料:将块状的二碲化钼材料贴于3×3厘米大小的硬胶上,使用另一片硬胶与贴有材料的硬胶对撕,重复4到8次后使得材料厚度达到适当的厚度;使用黏性更强的软胶将硬胶上的材料转移软胶上,过程是软胶贴合在硬胶上,等待10-20分钟,再呈45度角缓慢撕开软胶;然后如图3所示,将软胶上的二碲化钼薄膜(a)211转移至S2中制备好的硅衬底11上,具体过程为先使软胶从硅衬底11的一侧缓慢贴合至硅衬底11上,等待20-30分钟后,将软胶呈45度角缓慢撕开;将硅衬底11浸入丙酮溶液中12小时,再用异丙醇清洗,氮气枪吹干。
S4,制备第一沟道材料上的第一源漏电极:旋涂PMMA A4电子束光刻胶、烘胶、电子束光刻、显影、电子束蒸发沉积、剥离等工艺流程同S2制备标记层是一致的,所不同的是电子束光刻步骤中使用的版图不同,步骤S4使用的是第一源漏接触层的版图设计;另一个不同是电子束蒸发的金属为10纳米的铂和30纳米的金,两者构成了10纳米铂和30纳米金的源漏接触金属212,如图4所示。
S5,氧气退火掺杂:使用石英管管式炉对S4制备的器件进行退火处理,退火时,通入10比1流量的氩气和氧气的混合气体,其中氩气的流量为100标准立方米每分钟(sccm),温度为200摄氏度,时间为3小时。
S6,制备第一栅电极:使用原子层沉积设备生长二氧化铪作为第一栅介质213,如图5所示,前驱体为四(乙基甲基胺)铪和臭氧,反应温度设定为90摄氏度,每生长一个循环,厚度大约增加0.1纳米,生长总循环为100次,最终生长的二氧化铪介质的厚度为10纳米;第一栅电极214使用电子束蒸发设备沉积,如图6所示,沉积的金属为10纳米的铂和30纳米的金,具体工艺流程如匀胶、烘胶、电子束光刻、显影、电子束沉积、剥离等与S2中制备标记层一致,不同点在于电子束光刻的版图为第一栅极层。至此,底部的晶体管制备完成,在器件类型上底部的晶体管为顶栅结构。
S7,制备第二栅电极:由于CFET结构中的底部和顶部的晶体管共用一个栅电极,因此顶部的背栅结构晶体管的第二栅电极制备只需沉积一层栅介质即可,使用原子层沉积设备沉积二氧化铪作为第二栅介质311,如图7所示,工艺细节与S6制备第一栅介质中的一致。
S8,互连通孔形成:由于在S6、S7步骤中,制备第一栅极和第二栅极时,第一源漏电极上有栅介质覆盖,为了实现底部场效应晶体管和顶部场效应晶体管的源或漏电极的互连,需要对第一源漏电极区域上的栅介质进行选择性刻蚀形成通孔。在S7所制备器件表面滴AR-P617电子束光刻胶,以4000转每分钟的速度匀胶60秒,后在150摄氏度热板上烘干60秒;使用电子束曝光设备曝光通孔区域版图;使用反应离子刻蚀(RIE)设备刻蚀,功率为3瓦;浸入N-甲基吡咯烷酮(NMP)溶液中12小时去胶,后用异丙醇浸泡清洗,氮气枪吹干。
S9,第二沟道材料的定向转移:通过硬胶对撕减薄二碲化钼材料至合适的厚度,然后转移至软胶上,剥离和转移的工艺细节与S3中一致;使用光学显微镜和三维微操纵系统作为辅助工具进行定向转移,光学显微镜用于确定待转移的二碲化钼薄膜,使用三维微操纵系统将待转移的二碲化钼薄膜(b)312转移至目标区域,如图8所示,使得顶部的第二沟道材料在底部的第一沟道材料的垂直方向上。
S10,制备第二沟道材料上的第二源漏电极:旋涂PMMA A4电子束光刻胶、烘胶、电子束光刻、显影、电子束蒸发沉积、剥离等工艺流程同S2制备标记层是一致的,所不同的是电子束光刻步骤中使用的版图不同,这里使用的是第二源漏层的版图设计,电子束蒸发的金属为20纳米的镍和40纳米的金,两者形成了20纳米镍和40纳米金的源漏接触金属313,如图9所示,至此CFET器件制备完成。
由以上实施例可知,本发明提供的基于二维材料的CFET器件制备方法,使用机械剥离和转移的方式得到二碲化钼做沟道材料,原子层沉积的二氧化铪做栅介质,电子束蒸发沉积金属电极,器件制备过程中,相应的沟道材料、栅极、源漏层是一层层地堆叠而成,工艺流程得到简化,降低了制备难度,具有更高的成本效益。
本领域的技术人员容易理解,以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,包括:
S1:准备清洁的衬底;
S2:在所述衬底上制备标记层;
S3:将二维材料薄膜转移至所述衬底表面,用作所述互补性场效应晶体管的第一沟道材料;
S4:采用电子束光刻和电子束蒸发工艺在所述沟道材料表面制备第一源漏电极;
S5:通过在氧气氛围中退火对所述沟道材料进行氧掺杂;
S6:在所述第一源漏电极和第一沟道材料表面上沉积第一栅介质,并通过电子束蒸发工艺在所述第一栅介质上制备栅电极,从而制备得到底部场效应晶体管;
S7:制备背栅,在所述底部场效应晶体管上沉积第二栅介质;
S8:使用等离子体刻蚀工艺对所述第一源漏电极区域上的介质进行选择性刻蚀获得通孔;
S9:将二维材料薄膜转移至所述第二栅介质表面,用作所述互补性场效应晶体管的第二沟道材料;
S10:通过电子束光刻和电子束蒸发工艺在所述第二沟道材料上制备第二源漏电
极,从而得到了顶部场效应晶体管,完成了所述互补性场效应晶体管的制备;
其中,步骤S3中和S9中采用的二维材料相同,所述二维材料为二硫化钼、二硒化钼、二碲化钼、二硫化钨、二硒化钨、二硒化铼、二硒化锡、三硒化二铟或碲化镓。
2.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,所述衬底为二氧化硅衬底或硅衬底。
3.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,步骤S2中,标记层的制备方法为:在所述衬底表面旋涂光刻胶,使用电子束光刻完成标记层的图案转移,通过电子束蒸发在所述的图案上制备物理标记,用作转移后二维材料的定位标记和版图不同层之间的对准标记。
4.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,步骤S5中,所述氧气氛围退火条件为氩气与氧气流量比为8:1-10:1,退火温度为200-220摄氏度。
5.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,所述第一栅介质和第二栅介质通过原子层沉积二氧化铪薄膜得到,所述第一栅介质的前驱体为四(乙基甲基胺)铪和臭氧。
6.根据权利要求5所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,所述二氧化铪薄膜厚度为5-20纳米。
7.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,所述第一源漏电极和第二源漏电极使用的金属为镍、钛、钌、铑、钯、银、锇、铱、铂、金、钛、铝、铬、锗、钼、钨、铜、钴或铁中的一种或两种以上组合。
8.根据权利要求1所述的一种基于二维材料的互补性场效应晶体管的制备方法,其特征在于,步骤S8中的通孔用于所述第一源漏电极与第二源漏电极之间的互连。
9.一种如权利要求1-8任一项方法制备的基于二维材料的互补性场效应晶体管。
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