WO2021008417A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2021008417A1
WO2021008417A1 PCT/CN2020/100851 CN2020100851W WO2021008417A1 WO 2021008417 A1 WO2021008417 A1 WO 2021008417A1 CN 2020100851 W CN2020100851 W CN 2020100851W WO 2021008417 A1 WO2021008417 A1 WO 2021008417A1
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Prior art keywords
data line
array substrate
metal lead
section
hole
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PCT/CN2020/100851
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English (en)
French (fr)
Inventor
张跳梅
霍宇飞
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/280,446 priority Critical patent/US20210384225A1/en
Publication of WO2021008417A1 publication Critical patent/WO2021008417A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • On-screen aperture technology can effectively increase the screen-to-body ratio of the display device and improve user experience.
  • the edges of the openings are very prone to micro cracks, resulting in poor display and reduced life of the display device.
  • the embodiments of the present disclosure provide an embodiment of the present disclosure to provide an array substrate, a display panel, and a display device.
  • an array substrate having a display area defined therein, and the array substrate includes:
  • the anti-cracking dam is arranged on one side of the array substrate and located in the display area, and is arranged to define a through hole extending through the array substrate in a surrounding manner;
  • Metal leads are arranged to at least partially surround the anti-cracking dam
  • the first data line includes a first section and a second section separated from each other by the through hole;
  • the first section of the first data line is connected to the first end of the metal lead, and the second section of the first data line is connected to the second end of the metal lead.
  • the array substrate further includes:
  • a partition wall is arranged to at least partially surround the anti-cracking dam and is configured to block moisture and oxygen from passing through the through hole 200 into the portion of the display area located on the outside of the partition wall away from the through hole;
  • the metal lead is arranged between the isolation wall and the anti-cracking dam.
  • the metal lead is arranged such that the distance between it and the through hole is smaller than the distance between it and the crack prevention dam.
  • the isolation wall is provided with a first gap and a second gap, and a first section of the first data line is connected to the metal lead through the first gap; The second section of the first data line is connected to the metal lead through the second gap.
  • the first data line crosses the isolation wall at a layer different from that where the isolation wall is located by bridging or overlapping.
  • the first data line extends through the isolation wall at the same layer as the isolation wall and keeps the isolation wall intact.
  • the partition wall is formed with a lateral hole through which the first data line extends, and the outer surface of the first data line closely abuts against the lateral hole.
  • the inner wall establishes a sealed connection between the two, and the surface of the partition wall except for the lateral hole is continuous.
  • the array substrate further includes a second data line, and the second data line includes a first segment, a second segment, and a third segment that are sequentially connected; wherein, the The first section of the second data line is arranged in parallel with the first section of the first data line, and the third section of the second data line is arranged in parallel with the second section of the first data line; the second data The second section of the wire is bent and arranged on the side of the partition wall away from the through hole.
  • the second section of the second data line is spaced apart from the isolation wall from the outside at a uniform interval.
  • the through hole is a circular hole
  • the partition wall is correspondingly in the form of a circular ring or a partial circular ring
  • the second section of the second data line is The through holes have a circular arc shape with a common center.
  • the partition wall is in the form of a circular ring or a partial circular ring arranged concentrically with the through hole, and the second section of the second data line is connected to the through hole. It is arranged concentrically with the partition wall.
  • the metal lead includes a first metal lead and a second metal lead that are insulated from each other; the number of the first data line is two; wherein,
  • the first section and the second section of one of the first data lines are respectively connected to both ends of the first metal lead; the first section and the second section of the other one of the first data lines are respectively connected to the The two ends of the second metal lead are connected.
  • the first metal lead and the second metal lead are respectively located on opposite sides of the through hole, and the first metal lead and the second metal lead
  • the leads are all arc-shaped leads arranged to be bent in directions away from the through holes.
  • the first metal lead and the second metal lead are arc-shaped leads that are arranged oppositely in a diameter direction and protrude outward.
  • the metal lead surrounds the crack prevention dam at least one circle.
  • the array substrate further includes:
  • a detection transistor the first end of the detection transistor is electrically connected to the power line, the control end and the second end of the detection transistor are connected to the first section of the first data line, and the The second connection is used to connect with the source driver;
  • the detection transistor is configured to be turned off under the control of the data signal loaded on the control terminal of the detection transistor, and turned on after the metal lead is broken, so that the voltage on the power line is applied to the first data line The first paragraph.
  • a display panel including the above-mentioned array substrate.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the arrangement of a detection transistor according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a sectional structure of an array substrate according to an embodiment of the present disclosure along the cutting line B'B" shown in FIG. 1.
  • a structure When a structure is “on” another structure, it may mean that a certain structure is integrally formed on another structure, or that a certain structure is “directly” arranged on another structure, or that a certain structure is “indirectly” arranged on another structure through another structure. On other structures.
  • an array substrate in the first aspect of the embodiments of the present disclosure, is provided, as shown in FIGS. 1, 2, 3, and 5, the array substrate defines a display area A, and the array substrate also specifically includes a crack prevention dam 300, metal leads 400 and a first data line; wherein the crack prevention dam 300 is arranged on one side of the back plate 100 of the array substrate and is located in the display area A , And arranged to define a through hole 200 extending therethrough through the array substrate in a surrounding manner, whereby the crack prevention dam 300 is configured to suppress cracks at the edge of the through hole 200 and prevent cracks from moving away from the through hole.
  • the metal lead 400 is arranged to at least partially surround the anti-cracking dam 300, for example, it specifically includes at least two lead sections arranged to at least partially surround the anti-cracking dam 300 and electrically insulated from each other (for example, the first lead section 410, the second lead segment 420);
  • the first data line includes: a first segment 511 and a second segment 512 separated from each other by the through hole 200; the first segment 511 of the first data line is connected to a lead of the metal lead 400
  • the first end of the segment (for example, the first lead segment 410), the second segment 512 of the first data line is connected to the second end of the lead segment of the metal lead 400, and the second end is different from the first end, or even
  • the second end and the first end are arranged opposite to each other.
  • the array substrate of the present disclosure is provided with a through hole 200. If there is a crack around the through hole 200, the metal lead 400 arranged around the through hole 200 will be broken, which will cause the first section 511 of the first data line and the first data line
  • the second segment 512 of the first data line cannot be electrically connected to each other via the metal wire 400 between the two, so that the data signal cannot be effectively loaded to the first segment 511 of the first data line or the second segment 512 of the first data line.
  • the sub-pixels connected to the first segment 511 of the first data line or the second segment 512 of the first data line cannot receive data signals, resulting in abnormal display of these sub-pixels, indicating that there is a crack around the through hole 200.
  • the array substrate is provided with a plurality of data lines 500 to provide data signals to each sub-pixel.
  • one end of the data line 500 is, for example, connected to the source driver of the display device to receive the data signal provided by the source driver; the data line 500 is, for example, connected to a plurality of sub-pixels, so as to load the data signals on each sub-pixel one by one. Pixels; for example, each sub-pixel is configured to independently emit light according to the data signal loaded by each.
  • the first data line is at least one of the data lines 500 on the array substrate. It can be understood that when the metal lead 400 is not broken, the first section 511 of the first data line and the second section 512 of the first data line are electrically connected, and the data signal loaded on the first data line is, for example, simultaneously loaded on the first data line.
  • the first segment 511 of the first data line and the second segment 512 of the first data line cannot be electrically connected, so the data signal can only be applied to the first data line for connection with the source driver.
  • the sub-pixels connected to it display abnormality due to the inability to load the data signal.
  • the end of the second segment 512 of the first data line away from the first segment 511 of the first data line is connected to a bonding pad, and the bonding pad is used to connect to the source driver;
  • the data signal provided by the source driver can be first applied to the second segment 512 of the first data line, and then applied to the first segment 511 of the first data line through the metal lead 400.
  • each sub-pixel connected to the first segment 511 of the first data line displays abnormally, and only the second segment of the first data line
  • Each sub-pixel connected to 512 can be displayed normally.
  • the sub-pixel includes, for example, a light-emitting element and a driving circuit for driving the light-emitting element to emit light; wherein, the sub-pixel display abnormality, for example, specifically refers to the abnormal light emission of the light-emitting element, especially refers to the light-emitting element not emitting light when it should emit light Or emit light when it shouldn't.
  • Loading the data signal to the sub-pixels for example, refers to loading the data signal to the driving circuit, and the driving circuit then drives the light-emitting element to emit light according to the loaded data signal.
  • the light-emitting element may emit light or not emit light under the driving of the driving circuit, and display abnormality. That is, when the data signal cannot be applied to the sub-pixel, the light-emitting element may emit light under the driving of some driving circuits; and the light-emitting element may not emit light under the driving of other driving circuits. Regardless of whether the light-emitting element emits light or does not emit light, the display abnormality of the sub-pixel can be clearly observed, which does not affect the determination of whether there is a crack around the through hole 200.
  • the driving circuit includes, for example, a driving transistor, a capacitor, a data writing transistor, and a reset transistor.
  • the driving transistor, the data writing transistor, and the reset transistor each have a first terminal and a first terminal. Two ends and control ends.
  • the first end of the driving transistor is connected, for example, to the first power supply, more specifically, for example, connected to the high-level power supply VDD;
  • the second end of the driving transistor is, for example, connected to the input terminal of the light-emitting element;
  • the output terminal of is, for example, connected to the second voltage, more specifically, for example, to the low-level power supply VSS.
  • the control terminal of the driving transistor is, for example, connected to the capacitor, the first terminal of the data writing transistor, and the first terminal of the reset transistor; the second terminal of the data writing transistor is, for example, configured to load a data signal.
  • the second end of the reset transistor is, for example, configured to load a reset signal, and the reset signal is preset to a value that turns on the driving transistor. In this way, when the data signal cannot be loaded to the second terminal of the data writing transistor, the control terminal of the drive transistor is always loaded by the reset signal, so that the drive transistor remains always on.
  • the sub-pixel display is abnormal, which can be manifested as the sub-pixel presents a light-emitting state during the light-emitting stage no matter what data signal is loaded to the sub-pixel; for example, when the array substrate would originally display a black screen, the sub-pixel actually emits light .
  • the driving circuit includes, for example, a driving transistor, a capacitor, a data writing transistor, and a reset transistor, wherein the driving transistor, the data writing transistor, and the reset transistor each have a first End, second end and control end.
  • the first end of the driving transistor is connected to, for example, a first power source, and more specifically, to a high-level power source;
  • the second end of the driving transistor is, for example, connected to the input terminal of the light-emitting element;
  • the output terminal is, for example, connected to the second voltage, and more specifically, to a low-level power supply.
  • the control terminal of the driving transistor is, for example, connected to the capacitor, the first terminal of the data writing transistor, and the first terminal of the reset transistor; the second terminal of the data writing transistor is, for example, configured to load a data signal.
  • the second terminal of the reset transistor is configured to load a reset signal, and the reset signal is preset to a value that turns off the driving transistor. In this way, when the data signal cannot be loaded to the second terminal of the data writing transistor, the control terminal of the drive transistor is always loaded by the reset signal, so that the drive transistor remains always off.
  • the sub-pixel display is abnormal, which can be manifested in that no matter what data signal is loaded to the sub-pixel, the sub-pixel does not emit light during the light-emitting stage; for example, when the array substrate originally displays a white screen, the sub-pixel actually Does not emit light.
  • the array substrate of the present disclosure further includes, for example, an isolation wall 600, which is arranged to at least partially surround the crack prevention dam 300 and is thus configured to block moisture, oxygen, etc.
  • the array substrate (especially the part outside the partition wall 600 in the display area A of the array substrate) is entered through the through hole 200 to protect each sub-pixel of the array substrate from moisture and oxygen; for example, the metal wire 400 is provided on the partition wall 600 and the anti-cracking dam 300, and more specifically arranged as close to the through hole 200 as possible (ie, specifically, the metal lead 400 is arranged such that the distance between it and the through hole 200 is greater than the distance between it and the anti-cracking dam 300 The spacing is smaller), therefore, the comparison between the actual display state of the sub-pixels connected by the metal wire 400 and the expected display state under normal connection conditions (that is, when there is no crack around the through hole 200) can reflect the through hole 200 in time. Surrounding cracks, and this comparison of display states is more sensitive to small cracks around the through
  • the isolation wall 600 is provided with, for example, a first notch 601 and a second notch 602, and the first section 511 of the first data line is connected to the metal lead 400 through the first notch 601.
  • the first lead segment 410 or the upper end of the second lead segment 420 of the metal lead 400 shown in the figure the second segment 512 of the first data line is connected to the metal lead 400 (for example, the metal lead shown in the figure) through the second gap 602
  • the lower end of the first lead segment 410 or the lower end of the second lead segment 420 of the lead 400 can cross the isolation wall 600 without the need for bridging, overlapping, or the like, which facilitates the simplified structure and manufacturing process of the array substrate.
  • the first data line for example, crosses the isolation wall 600 at a layer different from that where the isolation wall is located by bridging, overlapping, or other switching methods; Or extend through the partition wall 600 in the same layer as the partition wall, and keep the partition wall 600 intact (in this case, for example, the partition wall is formed with a lateral hole through which the first data line extends, and the second The outer surface of a data line closely abuts against the inner wall of the lateral hole, for example, a sealed connection is formed between the two, and the surface of the partition wall except the lateral hole is continuous). In this way, the integrity of the partition wall 600 is not damaged, and the effect of blocking water vapor is not reduced, thereby ensuring the life and performance of the array substrate.
  • the data line 500 of the array substrate further includes, for example, a second data line
  • the second data line includes a first segment connected in sequence. 521, the second segment 522, and the third segment 523; wherein the first segment 521 of the second data line is arranged in parallel with the first segment 511 of the first data line, and the third segment 523 of the second data line is connected to the first data line
  • the second section 512 of the second data line is arranged in parallel; the second section 522 of the second data line is curvedly arranged on the side of the partition wall 600 away from the through hole 200 (more specifically, for example, spaced apart from the partition wall 600 from the outside at a uniform interval).
  • the second data line is arranged to bypass the through hole 200 from the outside of the partition wall 600 so that it is far away from the through hole 200, reducing the risk of it being attacked by cracks and water vapor from the direction of the through hole 200.
  • the through hole 200 is, for example, in the form of a circle
  • the partition wall 600 is correspondingly, for example, a ring or a partial ring (more specifically, for example, The second section 522 of the second data line is arranged concentrically with the through hole 200), and the second section 522 of the second data line is correspondingly, for example, in the form of a circular arc, that is, a partial ring section, and the second section 522 of the second data line is shared with the through hole 200.
  • the center of the circle (more specifically, for example, arranged concentrically with the through hole 200 and the partition wall 600).
  • the number of first data lines is, for example, two;
  • the metal lead 400 includes, for example, two lead segments insulated from each other, for example, the A metal lead 410 and a second metal lead 420; among them, the first section 511 and the second section 512 of a first data line are respectively connected to both ends of the first metal lead 410; the second section of the other first data line A section 511 and a second section 512 are respectively connected to two ends of the second metal lead 420.
  • the first metal wire 410 and the second metal wire 420 more specifically, to use the display conditions of the sub-pixels connected to the first metal wire 410 and the second metal wire 420 to detect cracks at different positions, respectively.
  • the first metal lead 410 and the second metal lead 420 are disposed away from each other in the respective middle sections (for example, oppositely disposed in the diameter direction and facing Outer protruding) arc-shaped lead.
  • the metal lead 400 is, for example, arranged to surround the crack prevention dam 300 at least one circle to ensure that the metal lead 400 can detect cracks in any direction around the through hole 200.
  • the metal lead 400 is arranged in a circle and a half around the crack prevention dam 300, for example.
  • the array substrate further includes a power line 700 and a detection transistor 800, wherein the first end of the detection transistor 800 (that is, the power supply end) and the The power line 700 is electrically connected, the control terminal and the second terminal of the detection transistor 800 are connected to the first section 511 of the first data line, and the second section 512 of the first data line is connected to the source driver connection.
  • the detection transistor 800 is selected to be the same type as the driving transistor of the driving circuit, and when the data signal is directly applied to the detection transistor 800 and the driving transistor, the detection transistor 800 and the driving transistor are turned off.
  • the detection transistor 800 is turned off, and the data signal can be normally loaded to the first segment 511 of the first data line and the second segment 512 of the first data line, which are connected to the first data line. Each sub-pixel can be displayed normally.
  • the data signal can only be loaded to the second segment 512 of the first data line, and only the sub-pixels connected to the second segment 512 of the first data line can be displayed normally; and at the same time, the data signal cannot be loaded To the first segment 511 of the first data line, the detection transistor 800 is turned on under the driving of the voltage on the power line 700, so that the voltage on the power line 700 replaces the data signal and is applied to the sub-pixel, so that the sub-pixel displays abnormality.
  • the power supply line 700 is connected to, for example, a high-level power supply VDD so that the voltage applied thereto is a high-level voltage.
  • VDD high-level power supply
  • each sub-pixel connected to the first segment 511 of the first data line does not emit light.
  • the embodiments of the present disclosure also provide a display panel, which includes any of the array substrates described in the above-mentioned array substrate embodiments.
  • the display panel is, for example, an OLED (organic light emitting diode) display panel, an LCD (liquid crystal display panel) or other types of display panels. Since the display panel has any one of the array substrates described in the above-mentioned array substrate embodiments, it has the same beneficial effects, which will not be repeated in this disclosure.
  • the embodiments of the present disclosure also provide a display device, which includes any one of the display panels described in the above display panel embodiments.
  • the display device is, for example, a mobile phone screen with a hole in the screen, a notebook screen with a hole in the screen, or other types of display devices. Since the display device has any one of the display panels described in the above-mentioned display panel embodiments, it has the same beneficial effects, which will not be repeated in this disclosure.
  • the array substrate, display panel, and display device provided by the embodiments of the present disclosure have at least the following superior technical effects:
  • the metal leads will break, which will cause the first section of the first data line and the second section of the first data line to be unable to be electrically connected, so that The data signal cannot be effectively loaded to the first segment of the first data line or the second segment of the first data line.
  • the sub-pixels connected to the first segment of the first data line or the second segment of the first data line cannot receive the data signal, resulting in abnormal display of these sub-pixels, indicating that there is a crack around the through hole. In this way, it can be judged whether there is a crack around the through hole by observing whether the sub-pixel connected to the first data line has a display abnormality.
  • the detection effect is intuitive and clear, but also real-time detection of the crack around the through hole can be realized during display, and Even if the array substrate is assembled into a display panel or a display device, it can still detect whether there are cracks around the through hole in real time during display. In this way, the array substrate can effectively detect the cracks at the edge of the through hole and improve the quality control level of the aperture screen.

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Abstract

本公开提供了一种阵列基板、显示面板和显示装置，属于显示技术领域。该阵列基板中限定有显示区，所述阵列基板包括防裂坝、金属引线和第一数据线，其中，所述防裂坝设置于阵列基板的一侧上且位于显示区内且布置成以围绕的方式限定在其中延伸贯穿所述阵列基板的通孔；所述金属引线布置成至少部分地围绕所述防裂坝；所述第一数据线包括由所述通孔而彼此间隔开的第一段和第二段；所述第一数据线的第一段连接所述金属引线的一端，所述第一数据线的第二段连接所述金属引线的另一端。

Description

阵列基板、显示面板和显示装置
相关申请的交叉引用
本公开实施例要求于2019年7月18日递交中国专利局的、申请号为201910649960.3的中国专利申请的权益，该申请的全部内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板和显示装置。
背景技术
屏上开孔技术能够有效提升显示装置的屏占比，提高用户体验。然而，开孔边缘非常容易出现微小裂纹，造成显示装置显示不良和寿命减小。相关技术中缺乏有效检测开孔屏的孔边缘裂纹以控制开孔屏品质的方案。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的相关技术的信息。
发明内容
为至少部分地克服上述相关技术中的缺陷和/或不足，本公开的实施例提供了一种本公开的实施例提供一种阵列基板、显示面板和显示装置。
本公开实施例采用如下技术方案：
根据本公开的第一个方面，提供一种阵列基板，所述阵列基板中限定有显示区，所述阵列基板包括：
防裂坝，设置于阵列基板的一侧上且位于显示区内，且布置成以围绕的方式限定在其中延伸贯穿所述阵列基板的通孔；
金属引线，布置成至少部分地围绕所述防裂坝；
第一数据线，包括由所述通孔而彼此间隔开的第一段和第二段；
所述第一数据线的第一段连接所述金属引线的第一端，所述第一数据线的第二段连接所述金属引线的第二端。
在本公开的一种示例性实施例中，所述阵列基板还包括：
隔离壁，布置成至少部分地环绕所述防裂坝，且配置成阻挡水分和氧气穿过通孔 200进入位于所述隔离壁的背离所述通孔的外侧的所述显示区的部分；所述金属引线设于所述隔离壁与所述防裂坝之间。
在本公开的一种示例性实施例中，金属引线布置成其与所述通孔之间的间距比其与所述防裂坝之间的间距更小。
在本公开的一种示例性实施例中，所述隔离壁设置有第一缺口和第二缺口，所述第一数据线的第一段通过所述第一缺口连接所述金属引线；所述第一数据线的第二段通过所述第二缺口连接所述金属引线。
在本公开的一种示例性实施例中，所述第一数据线在与隔离壁所在层不同的层通过桥接、搭接跨过所述隔离壁。
在本公开的一种示例性实施例中，所述第一数据线在与隔离壁相同的层延伸穿过所述隔离壁且使得隔离壁保持完整。
在本公开的一种示例性实施例中，所述隔离壁上形成有供第一数据线延伸穿过的侧向孔且所述第一数据线的外部表面紧密抵靠所述侧向孔的内壁以在二者之间建立密封连接，所述隔离壁的除所述侧向孔以外的表面是连续的。
在本公开的一种示例性实施例中，所述阵列基板还包括第二数据线，所述第二数据线包括依次连接的第一段、第二段和第三段；其中，所述第二数据线的第一段与所述第一数据线的第一段平行设置，所述第二数据线的第三段与所述第一数据线的第二段平行设置；所述第二数据线的第二段弯曲地设于所述隔离壁远离所述通孔的一侧。
在本公开的一种示例性实施例中，第二数据线的第二段以均一的间距从外侧与所述隔离壁间隔开。
在本公开的一种示例性实施例中，所述通孔为圆形孔，所述隔离壁相应地呈圆环或部分圆环的形式，且所述第二数据线的第二段为与所述通孔共圆心的圆弧形。
在本公开的一种示例性实施例中，所述隔离壁呈与所述通孔同心布置的圆环或部分圆环的形式，且所述第二数据线的第二段与所述通孔和所述隔离壁两者同心布置。
在本公开的一种示例性实施例中，所述金属引线包括相互绝缘的第一金属引线和第二金属引线；所述第一数据线的数量为两根；其中，
一根所述第一数据线的第一段和第二段分别与所述第一金属引线的两端连接；另一根所述第一数据线的第一段和第二段分别与所述第二金属引线的两端连接。
在本公开的一种示例性实施例中，所述第一金属引线和所述第二金属引线分别位于所述通孔的相对的两侧，且所述第一金属引线和所述第二金属引线均为布置成分别 沿着背离所述通孔的方向弯曲的弧形引线。
在本公开的一种示例性实施例中，所述第一金属引线和所述第二金属引线是在直径方向上相反设置且向外凸出的弧形引线。
在本公开的一种示例性实施例中，所述金属引线环绕所述防裂坝至少一圈。
在本公开的一种示例性实施例中，所述阵列基板还包括：
电源线；
检测晶体管，所述检测晶体管的第一端与所述电源线电连接，所述检测晶体管的控制端和第二端与所述第一数据线的第一段连接，所述第一数据线的第二段连接用于与源极驱动器连接；
所述检测晶体管配置成在加载于所述检测晶体管的控制端的数据信号的控制下截止，以及在所述金属引线断裂后导通以使得所述电源线上的电压加载至所述第一数据线的第一段。
根据本公开的第二个方面，提供一种显示面板，包括上述的阵列基板。
根据本公开的第三个方面，提供一种显示装置，包括上述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例中所需要使用的附图作简单地介绍，显而易见地，下面所介绍的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是本公开一实施方式的阵列基板的结构的示意图。
图2是本公开一实施方式的阵列基板的结构的示意图。
图3是本公开一实施方式的阵列基板的结构的示意图。
图4是本公开一实施方式的检测晶体管的设置的示意图。
图5是本公开一实施方式的阵列基板沿图1所示的剖切线B’B”的剖切结构的示意图。
具体实施方式
为了使本公开实施例的目的、技术方案和优点更加清楚，现在将参考附图更全面 地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员，并且基于本公开实施例中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开实施例保护的范围。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。附图中各部件尺寸和形状不反映本公开的实施例的阵列基板、显示面板和显示装置的部件的真实比例，目的只是示意说明本公开的实施例内容。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开的实施例的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开的实施例。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开的实施例。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
根据本公开实施例的总体技术构思，在本公开实施方式的第一方面中，提供一种阵列基板，如图1、图2、图3和图5所示，该阵列基板中限定有显示区A，且该阵列基板还具体地包括防裂坝300、金属引线400和第一数据线；其中，所述防裂坝300设置于阵列基板的背板100的一侧上且位于显示区A内，且布置成以围绕的方式限定了在其中延伸贯穿所述阵列基板的通孔200，由此所述防裂坝300被配置成用于抑制通孔200边缘的裂纹以及抑制裂纹向远离通孔200的方向延伸；金属引线400布置成至少部分地围绕防裂坝300，例如其具体地包括布置成至少部分地围绕防裂坝300且彼此电绝缘的至少两个引线段(例如第一引线段410、第二引线段420)；第一数据线包括：由通孔200而彼此间隔开的第一段511和第二段512；第一数据线的第一段511 连接金属引线400的一个引线段(例如第一引线段410)的第一端，第一数据线的第二段512连接金属引线400的该引线段的第二端，所述第二端不同于所述第一端，甚至所述第二端与所述第一端布置成彼此相反。
本公开的阵列基板开设有通孔200，若通孔200周围存在裂纹，则围绕所述通孔200布置的金属引线400会断裂，将导致第一数据线的第一段511和第一数据线的第二段512不能经由二者之间的金属引线400而彼此电连接，使得数据信号不能有效加载至第一数据线的第一段511或第一数据线的第二段512。如此，第一数据线的第一段511或第一数据线的第二段512所连接的子像素不能接收数据信号，导致这些子像素显示异常，提示通孔200周围存在裂纹。如此，可以通过观察第一数据线所连接的子像素是否出现显示异常来判断通孔200周围是否存在裂纹，不仅检测效果直观明了，而且可以在显示时实现对通孔200周围的裂纹的实时检测，而且即便该阵列基板组装成为显示面板或显示装置的一部分，其依然可以在显示时实时检测通孔200周围是否存在裂纹。如此，该阵列基板可以有效检测通孔200边缘的裂纹，提高开孔屏的质量控制水平。
下面结合附图对本公开实施方式提供的阵列基板的各部件进行详细说明：
阵列基板例如设置有多根数据线500，以向各个子像素提供数据信号。其中，数据线500的一端例如用于与显示装置的源极驱动器连接，以便接收源极驱动器提供的数据信号；数据线500例如连接多个子像素，以便将其上的数据信号逐一加载至各个子像素；各个子像素例如配置成根据各自加载的数据信号而独立发光。
第一数据线为阵列基板上的数据线500中的至少一根。可以理解的是，当金属引线400不断裂时，第一数据线的第一段511和第一数据线的第二段512电连接，加载于第一数据线上的数据信号例如同时加载至第一数据线的第一段511和第一数据线的第二段512；因此连接于第一数据线的第一段511和第一数据线的第二段512的各个子像素均可以被加载各自的数据信号，这些子像素均可以正常显示。
当金属引线400断裂时，第一数据线的第一段511和第一数据线的第二段512不能够电连接，因此数据信号只能够加载至第一数据线用于与源极驱动器连接的那一段，另外一段则因无法加载数据信号而导致与之连接的子像素显示异常。举例而言，第一数据线的第二段512远离第一数据线的第一段511的一端与一绑定焊盘连接，该绑定焊盘用于与源极驱动器连接；如此，在金属引线400不存在断裂的正常运行情况下，源极驱动器提供的数据信号可以首先加载至第一数据线的第二段512，并通过金属引 线400进而加载至第一数据线的第一段511。当金属引线400断裂时，数据信号不能加载至第一数据线的第一段511，则第一数据线的第一段511所连接的各个子像素显示异常，仅第一数据线的第二段512所连接的各个子像素可以正常显示。
本公开中，子像素例如包括发光元件和用于驱动发光元件发光的驱动电路；其中，子像素显示异常，例如具体指的是发光元件的发光异常，尤其是指发光元件在应该发光时而未发光或者在不应该发光时发光。数据信号加载至子像素，例如指的是数据信号加载至驱动电路，驱动电路继而根据所加载的数据信号而驱动发光元件发光。
可以理解的是，当数据信号不能加载至子像素时，发光元件可能在驱动电路的驱动下发光或者不发光，呈现出显示异常。即，当数据信号不能加载至子像素时，在某些驱动电路的驱动下，发光元件可能发光；在另一些驱动电路的驱动下，发光元件可能不发光。无论发光元件发光或者不发光，子像素的显示异常可以被明显的观察到，其并不影响对通孔200周围是否存在裂纹的判断。
举例而言，在本公开的一种实施方式中，驱动电路例如包括驱动晶体管、电容器、数据写入晶体管和复位晶体管，其中，驱动晶体管、数据写入晶体管和复位晶体管各自具有第一端、第二端和控制端。作为示例，在示例性的具体布置中，驱动晶体管的第一端例如连接第一电源，更具体地例如连接高电平电源VDD；驱动晶体管的第二端例如连接发光元件的输入端；发光元件的输出端例如连接第二电压，更具体地例如连接低电平电源VSS。驱动晶体管的控制端例如连接电容器、数据写入晶体管的第一端和复位晶体管的第一端；数据写入晶体管的第二端例如配置成用于加载数据信号。复位晶体管的第二端例如配置成用于加载复位信号，且复位信号预先设置为使得驱动晶体管导通的值。如此，当数据信号不能加载至数据写入晶体管的第二端时，驱动晶体管的控制端一直被复位信号加载，使得驱动晶体管保持一直导通。在此情形下，子像素显示异常，可以表现为无论向子像素加载何种数据信号，子像素在发光阶段呈现发光状态；例如，当阵列基板原本将会显示黑色画面时，子像素实际上发光。
再举例而言，在本公开的另一种替代实施方式中，驱动电路例如包括驱动晶体管、电容器、数据写入晶体管和复位晶体管，其中，驱动晶体管、数据写入晶体管和复位晶体管各自具有第一端、第二端和控制端。作为示例，在示例性的具体布置中，驱动晶体管的第一端例如连接第一电源，更具体地例如连接高电平电源；驱动晶体管的第二端例如连接发光元件的输入端；发光元件的输出端例如连接第二电压，更具体地例如连接低电平电源。驱动晶体管的控制端例如连接电容器、数据写入晶体管的第一端 和复位晶体管的第一端；数据写入晶体管的第二端例如配置成用于加载数据信号。复位晶体管的第二端例如配置成用于加载复位信号，且复位信号预先设置成使得驱动晶体管截止的值。如此，当数据信号不能加载至数据写入晶体管的第二端时，驱动晶体管的控制端一直被复位信号加载，使得驱动晶体管保持一直截止。在此情形下，子像素显示异常，可以表现为无论向子像素加载何种数据信号，子像素在发光阶段呈现不发光状态；例如，当阵列基板原本将会显示白色画面时，子像素实际上不发光。
如图1、图2和图3所示，本公开的阵列基板还例如包括隔离壁600，隔离壁600布置成至少部分地环绕防裂坝300，且由此配置成用于阻挡水分和氧气等通过通孔200周围进入阵列基板(特别是阵列基板的显示区A中的位于隔离壁600外部的部分)，保护阵列基板的各个子像素免受水分和氧气影响；金属引线400例如设于隔离壁600与防裂坝300之间，并且更具体地布置成尽可能贴近通孔200(即具体地，金属引线400设置成其与通孔200之间的间距比其与防裂坝300之间的间距更小)，由此，金属引线400所连接的子像素的实际显示状态与正常连接情况下(即通孔200周围不存在裂纹的情况下)的预期显示状态的对比能够及时反映通孔200周围的裂纹，并且这种显示状态的对比对于通孔200周围的小裂纹更敏感。
在本公开的一种实施方式中，如图1所示，隔离壁600例如设置有第一缺口601和第二缺口602，第一数据线的第一段511通过第一缺口601连接金属引线400(例如图示的金属引线400的第一引线段410的上端或第二引线段420的上端)；第一数据线的第二段512通过第二缺口602连接金属引线400(例如图示的金属引线400的第一引线段410的下端或第二引线段420的下端)。如此，第一数据线例如无需通过桥接、搭接等转接方式即可跨过隔离壁600，便利了简化阵列基板的结构和制备工序。
在本公开的另一种实施方式中，如图2和图3所示，第一数据线例如在与隔离壁所在层不同的层通过桥接、搭接或者其他转接方式跨过隔离壁600；或者在与隔离壁相同的层延伸穿过隔离壁600，且使得隔离壁600保持完整(在这种情况下例如隔离壁上形成有供第一数据线延伸穿过的侧向孔且所述第一数据线的外部表面紧密抵靠所述侧向孔的内壁，例如二者之间形成密封连接，所述隔离壁的除所述侧向孔以外的表面是连续的)。如此，不破坏隔离壁600的完整性，避免降低其阻挡水汽的效果，进而保证阵列基板的寿命和性能。
在本公开的示例性实施例中，例如，如图1、图2和图3所示，阵列基板的数据线500中还例如包括第二数据线，第二数据线包括依次连接的第一段521、第二段522 和第三段523；其中，第二数据线的第一段521与第一数据线的第一段511平行设置，第二数据线的第三段523与第一数据线的第二段512平行设置；第二数据线的第二段522弯曲地设于隔离壁600远离通孔200的一侧(更具体地例如以均一的间距从外侧与隔离壁600间隔开)。如此，第二数据线布置成从隔离壁600外侧绕过通孔200，使得其远离通孔200，减小了其受到来自通孔200方向的裂纹和水汽侵袭的风险。
在本公开的一种实施方式中，如图1、图2和图3所示，通孔200例如为圆形的形式，隔离壁600相应地例如呈圆环或部分圆环(更具体地例如与通孔200同心布置)的形式，且第二数据线的第二段522相应地例如为圆弧形即部分圆环段的形式，且第二数据线的第二段522与通孔200共圆心(更具体地例如与通孔200和隔离壁600同心布置)。
在本公开的一种实施方式中，如图1和图2所示，第一数据线的数量例如为两根；则金属引线400例如包括相互绝缘的两个引线段，例如分别图示为第一金属引线410和第二金属引线420；其中，一根第一数据线的第一段511和第二段512分别与第一金属引线410的两端连接；另一根第一数据线的第一段511和第二段512分别与第二金属引线420的两端连接。如此，便利了利用第一金属引线410和第二金属引线420(更具体地利用与第一金属引线410和第二金属引线420相连的子像素的显示状况)分别检测不同位置的裂纹。
在本公开的示例性实施例中，例如，如图1和图2所示，第一金属引线410和第二金属引线420是各自中间部段彼此背离设置(例如在直径方向上相反设置且向外凸出)的弧形引线。
在本公开的一种实施方式中，如图3所示，金属引线400例如布置成环绕防裂坝300至少一圈，以保证金属引线400能够检测通孔200周围任意方向的裂纹。举例而言，金属引线400例如布置成绕防裂坝300一圈半。
在本公开的一种实施方式中，如图4所示，阵列基板例如还包括电源线700和一检测晶体管800，其中，所述检测晶体管800的第一端(即其供电端)与所述电源线700电连接，所述检测晶体管800的控制端和第二端与所述第一数据线的第一段511连接，所述第一数据线的第二段512连接用于与源极驱动器连接。其中，检测晶体管800例如选择为与驱动电路的驱动晶体管的类型相同，且数据信号直接加载于检测晶体管800和驱动晶体管时，检测晶体管800和驱动晶体管截止。
如此，当金属引线400不断裂时，检测晶体管800截止，数据信号可以正常的加 载至第一数据线的第一段511和第一数据线的第二段512，连接于第一数据线上的各个子像素可以正常显示。当金属引线400断裂时，数据信号可以仅加载至第一数据线的第二段512，仅连接于第一数据线的第二段512的各个子像素可以正常显示；而同时，数据信号无法加载至第一数据线的第一段511，因此在电源线700上的电压的驱动下检测晶体管800导通，使得电源线700上的电压替代数据信号而加载至子像素，使得子像素显示异常。
在本公开的示例性实施例中，电源线700例如连接高电平电源VDD，使得其上加载的电压为高电平电压。在本公开的示例性实施例中，例如，当金属引线400断裂时，连接于第一数据线的第一段511上的各个子像素不发光。
本公开实施方式还提供一种显示面板，该显示面板包括上述阵列基板实施方式所描述的任意一种阵列基板。该显示面板例如是OLED(有机发光二极管)显示面板、LCD(液晶显示面板)或者其他类型的显示面板。由于该显示面板具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
本公开实施方式还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的任意一种显示面板。该显示装置例如是屏内开孔的手机屏幕、屏内开孔的笔记本屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板实施方式所描述的任意一种显示面板，因此具有相同的有益效果，本公开在此不再赘述。
相较于相关技术，基于上述技术方案，本公开实施例提供的阵列基板、显示面板和显示装置至少具有下列优越的技术效果：
本公开提供的阵列基板、显示面板和显示装置，若通孔周围存在裂纹，则金属引线会断裂，将导致第一数据线的第一段和第一数据线的第二段不能电连接，使得数据信号不能有效加载至第一数据线的第一段或第一数据线的第二段。如此，第一数据线的第一段或第一数据线的第二段所连接的子像素不能接受数据信号，导致这些子像素显示异常，提示通孔周围存在裂纹。如此，可以通过观察第一数据线所连接的子像素是否出现显示异常来判断通孔周围是否存在裂纹，不仅检测效果直观明了，而且可以在显示时实现对通孔周围的裂纹的实时检测，而且即便该阵列基板组装成为显示面板或显示装置，其依然可以在显示时实时检测通孔周围是否存在裂纹。如此，该阵列基板可以有效检测通孔边缘的裂纹，提高开孔屏的质量控制水平。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开实施例权利要求及其等同技术所限定的保护范围内，而不脱离本公开实施例的精神和范围。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (18)

  1. 一种阵列基板，所述阵列基板中限定有显示区，其中，所述阵列基板包括：
    防裂坝，设置于阵列基板的一侧上且位于显示区内，且布置成以围绕的方式限定在其中延伸贯穿所述阵列基板的通孔；
    金属引线，布置成至少部分地围绕所述防裂坝；
    第一数据线，包括由所述通孔而彼此间隔开的第一段和第二段；
    所述第一数据线的第一段连接所述金属引线的第一端，所述第一数据线的第二段连接所述金属引线的第二端。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    隔离壁，布置成至少部分地环绕所述防裂坝，且配置成阻挡水分和氧气穿过通孔200进入位于所述隔离壁的背离所述通孔的外侧的所述显示区的部分；所述金属引线设于所述隔离壁与所述防裂坝之间。
  3. 根据权利要求2所述的阵列基板，其中，金属引线布置成其与所述通孔之间的间距比其与所述防裂坝之间的间距更小。
  4. 根据权利要求2所述的阵列基板，其中，所述隔离壁设置有第一缺口和第二缺口，所述第一数据线的第一段通过所述第一缺口连接所述金属引线；所述第一数据线的第二段通过所述第二缺口连接所述金属引线。
  5. 根据权利要求2所述的阵列基板，其中，所述第一数据线在与隔离壁所在层不同的层通过桥接、搭接跨过所述隔离壁。
  6. 根据权利要求2所述的阵列基板，其中，所述第一数据线在与隔离壁相同的层延伸穿过所述隔离壁且使得隔离壁保持完整。
  7. 根据权利要求6所述的阵列基板，其中，所述隔离壁上形成有供第一数据线延伸穿过的侧向孔且所述第一数据线的外部表面紧密抵靠所述侧向孔的内壁以在二者之间建立密封连接，所述隔离壁的除所述侧向孔以外的表面是连续的。
  8. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括第二数据线，所述第二数据线包括依次连接的第一段、第二段和第三段；其中，所述第二数据线的第一段与所述第一数据线的第一段平行设置，所述第二数据线的第三段与所述第一数据线的第二段平行设置；所述第二数据线的第二段弯曲地设于所述隔离壁远离所述通孔的一侧。
  9. 根据权利要求8所述的阵列基板，其中，第二数据线的第二段以均一的间距从外侧与所述隔离壁间隔开。
  10. 根据权利要求8所述的阵列基板，其中，所述通孔为圆形孔，所述隔离壁相应地呈圆环或部分圆环的形式，且所述第二数据线的第二段为与所述通孔共圆心的圆弧形的形式。
  11. 根据权利要求10所述的阵列基板，其中，所述隔离壁呈与所述通孔同心布置的圆环或部分圆环的形式，且所述第二数据线的第二段与所述通孔和所述隔离壁两者同心布置。
  12. 根据权利要求1～11任一项所述的阵列基板，其中，所述金属引线包括相互绝缘的第一金属引线和第二金属引线；所述第一数据线的数量为两根；其中，
    一根所述第一数据线的第一段和第二段分别与所述第一金属引线的两端连接；另一根所述第一数据线的第一段和第二段分别与所述第二金属引线的两端连接。
  13. 根据权利要求12所述的阵列基板，其中，所述第一金属引线和所述第二金属引线分别位于所述通孔的相对的两侧，且所述第一金属引线和所述第二金属引线均为布置成分别沿着背离所述通孔的方向弯曲的弧形引线。
  14. 根据权利要求13所述的阵列基板，其中，所述第一金属引线和所述第二金属引线是在直径方向上相反设置且向外凸出的弧形引线。
  15. 根据权利要求1～11任一项所述的阵列基板，其中，所述金属引线环绕所述防裂坝至少一圈。
  16. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    电源线；
    检测晶体管，所述检测晶体管的第一端与所述电源线电连接，所述检测晶体管的控制端和第二端与所述第一数据线的第一段连接，所述第一数据线的第二段与源极驱动器连接；所述检测晶体管配置成在加载于所述检测晶体管的控制端的数据信号的控制下截止，以及在所述金属引线断裂后导通以使得所述电源线上的电压加载至所述第一数据线的第一段。
  17. 一种显示面板，其中，包括权利要求1～16任一项所述的阵列基板。
  18. 一种显示装置，其中，包括权利要求17所述的显示面板。
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