WO2021005872A1 - Substrat pour dispositif électronique et procédé de production associé - Google Patents

Substrat pour dispositif électronique et procédé de production associé Download PDF

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WO2021005872A1
WO2021005872A1 PCT/JP2020/018262 JP2020018262W WO2021005872A1 WO 2021005872 A1 WO2021005872 A1 WO 2021005872A1 JP 2020018262 W JP2020018262 W JP 2020018262W WO 2021005872 A1 WO2021005872 A1 WO 2021005872A1
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substrate
single crystal
silicon single
electronic device
bonded
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PCT/JP2020/018262
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English (en)
Japanese (ja)
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和徳 萩本
正三郎 後藤
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信越半導体株式会社
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Priority to EP20837097.3A priority Critical patent/EP3998376A4/fr
Priority to US17/617,091 priority patent/US11705330B2/en
Priority to CN202080044129.6A priority patent/CN113994032A/zh
Publication of WO2021005872A1 publication Critical patent/WO2021005872A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to a substrate for an electronic device and a method for manufacturing the same.
  • Nitride semiconductors such as GaN and AlN can be used for manufacturing high electron mobility transistors (HEMTs) and high withstand voltage electronic devices using two-dimensional electron gas.
  • HEMTs high electron mobility transistors
  • a nitride wafer in which these nitride semiconductors are grown on a substrate, and a sapphire substrate or a SiC substrate is used as the substrate.
  • epitaxial growth by vapor phase growth on a silicon substrate is used in order to increase the diameter and reduce the cost of the substrate.
  • the fabrication of an epitaxial growth film by vapor phase growth on a silicon substrate is advantageous in terms of device productivity and heat dissipation because a substrate having a larger diameter can be used than a sapphire substrate or a SiC substrate.
  • the stress due to the difference in lattice constant and the difference in coefficient of thermal expansion tends to increase the warp and plastic deformation, and the stress is reduced by the growth conditions and the relaxation layer.
  • Patent Document 1 discloses an epitaxial substrate for an electronic device in which a high resistance substrate is bonded to a low resistance substrate to control the warp shape as an epitaxial layer AlN / Si (1000 ⁇ cm or more) / Si (100 ⁇ cm or less).
  • Patent Document 2 discloses an epitaxial substrate for an electronic device in which a low resistance CZ substrate is bonded to a high resistance FZ substrate to suppress warpage as an epitaxial layer AlN / Si (CZ low resistance) / Si (FZ high resistance). Has been done.
  • the present invention has been made to solve the above problems, and is an electronic device capable of suppressing warpage and being used for a high pressure resistant product in a substrate for an electronic device in which a nitride semiconductor film is formed on a silicon substrate. It is an object of the present invention to provide a substrate for use and a method for manufacturing the same.
  • the present invention is a substrate for an electronic device in which a nitride semiconductor film is formed on a silicon single crystal bonded substrate.
  • the bonded substrate is a substrate obtained by bonding a plurality of silicon single crystal substrates, and has a thickness of more than 2000 ⁇ m.
  • the plurality of silicon single crystal substrates provide a substrate manufactured by the CZ method and having a resistivity of 0.1 ⁇ cm or less for an electronic device.
  • a plurality of silicon single crystal substrates are made into substrates manufactured by the CZ method having a resistivity of 0.1 ⁇ cm or less, and the thickness of the bonded substrate is made thicker than 2000 ⁇ m. Since the strength of the bonded substrate is significantly increased, the warpage of the substrate for an electronic device due to the formed nitride semiconductor film can be suppressed. Therefore, it is particularly suitable as a substrate for an electronic device used for a high withstand voltage product.
  • the plurality of silicon single crystal substrates have an oxygen concentration of 3.0 ⁇ 10 17 to 1 ⁇ 10 18 organisms / cm 3 (ASTM'79).
  • the bonded substrate is preferably one in which a plurality of CZ silicon single crystal substrates are bonded via a SiO 2 film.
  • the stress caused by the nitride semiconductor film can be relaxed, and a thicker nitride semiconductor film can be formed.
  • the present invention is a method for manufacturing a substrate for an electronic device in which a nitride semiconductor film is formed on a silicon single crystal bonded substrate.
  • a method for manufacturing a substrate for an electronic device which comprises using a plurality of silicon single crystal substrates having a resistivity of 0.1 ⁇ cm or less produced by the CZ method.
  • a substrate for an electronic device of the present invention a plurality of CZ silicon single crystal substrates having a resistivity of 0.1 ⁇ cm or less are used, and the thickness of the bonded substrate is made thicker than 2000 ⁇ m to increase the strength. Since the bonded substrate can be produced, it is possible to suppress the warp of the substrate for an electronic device when the nitride semiconductor film is formed. Therefore, it is particularly suitable as a method for manufacturing a substrate for an electronic device used for a high withstand voltage product.
  • the plurality of silicon single crystal substrates those having an oxygen concentration of 3.0 ⁇ 10 17 to 1 ⁇ 10 18 atoms / cm 3 (ASTM'79) are preferably used.
  • the step of forming the bonding substrate it is preferable to bond a plurality of CZ silicon single crystal substrates via a SiO 2 film.
  • the stress applied during the growth of the nitride can be relaxed, and the nitride semiconductor film can be formed thicker.
  • a plurality of silicon single crystal substrates are used as substrates manufactured by the CZ method having a resistivity of 0.1 ⁇ cm or less, and the thickness of the bonded substrate is more than 2000 ⁇ m.
  • the strength of the bonded substrate is significantly increased, so that the warpage of the substrate for an electronic device due to the formed nitride semiconductor film can be suppressed. Therefore, it is particularly suitable for a substrate for an electronic device used for a high withstand voltage product.
  • the present inventors have repeatedly studied the electronic device substrate in which the warpage generated due to the difference in the coefficient of thermal expansion is suppressed and the manufacturing method thereof. As a result, it was found that warpage was remarkably suppressed by using a substrate in which a plurality of CZ silicon single crystal substrates having a low resistance were bonded and the thickness was thicker than 2000 ⁇ m, and the present invention was completed.
  • the present invention is a substrate for an electronic device in which a nitride semiconductor film is formed on a silicon single crystal bonded substrate.
  • the bonded substrate is a substrate obtained by bonding a plurality of silicon single crystal substrates, and has a thickness of more than 2000 ⁇ m.
  • the plurality of silicon single crystal substrates are substrates manufactured by the CZ method and having a resistivity of 0.1 ⁇ cm or less, which is a substrate for electronic devices.
  • the substrate for an electronic device of the present invention is a substrate in which a nitride semiconductor film is formed on a silicon single crystal bonded substrate. Further, in the present invention, the bonded substrate is a substrate obtained by bonding a plurality of silicon single crystal substrates manufactured by the CZ method.
  • FIG. 1 shows a conceptual diagram of the substrate for an electronic device of the present invention.
  • the substrate 10 for an electronic device of the present invention is a bonding substrate 6 in which a silicon single crystal substrate 1 and a silicon single crystal substrate 2 (a plurality of silicon single crystal substrates) are bonded.
  • the bonding form between the plurality of silicon single crystal substrates is not particularly limited, but an adhesive layer can be provided.
  • FIG. 1A shows a structure having an adhesive layer 3 between a silicon single crystal substrate 1 and a silicon single crystal substrate 2.
  • the adhesive layer is not particularly limited, but may be, for example, an oxide film (SiO 2 ). Further, FIG.
  • FIG. 1B shows a structure in which the adhesive layer 3 is not provided between the silicon single crystal substrate 1 and the silicon single crystal substrate 2.
  • the adhesive layer 3 is not provided between the silicon single crystal substrate 1 and the silicon single crystal substrate 2.
  • the oxide film by thinning the oxide film before bonding, only oxygen of the oxide film is diffused by the bonding heat treatment after bonding, and a structure without an oxide film can be obtained at the bonding interface.
  • the number of silicon single crystal substrates to be bonded is not limited to two, and may be three or more. In the following, a case where the bonded substrate is a substrate obtained by bonding two silicon single crystal substrates will be described with reference to FIG. 1.
  • the silicon single crystal substrate 1 and the silicon single crystal substrate 2 are silicon single crystal substrates manufactured by the CZ method (hereinafter, may be simply referred to as CZ single crystal substrates), and the resistivity is 0.1 ⁇ cm or less.
  • the thickness of the bonded substrate after bonding is made thicker than 2000 ⁇ m.
  • the oxygen concentration is preferably 3.0 ⁇ 10 17 to 1 ⁇ 10 18 ASTM / cm 3 (ASTM'79).
  • the CZ single crystal contains oxygen, which improves the strength and hardness of the substrate.
  • the occurrence of slip in the CZ single crystal substrate can be prevented by the oxygen concentration and that of 3.0 ⁇ 10 17 ⁇ 1 ⁇ 10 18 atoms / cm 3 (ASTM'79).
  • the intermediate layer 4 may be formed between the silicon single crystal substrate 2 and the device layer 5.
  • the intermediate layer 4 functions as a buffer layer inserted for improving the crystallinity of the device layer and controlling the stress. Since the intermediate layer 4 can be manufactured by the same equipment as the nitride semiconductor film, it is desirable that the intermediate layer 4 is made of nitride.
  • a device layer 5 made of a thin film of nitrides such as GaN, AlN, InN, AlGaN, InGaN, and AlInN is formed on the silicon single crystal substrate 2.
  • the intermediate layer 4 it can be assumed that the device layer 5 is formed on the intermediate layer 4.
  • the device layer 5 can be grown by vapor phase growth such as MOVPE method or sputtering.
  • the nitride thin film can be 1 to 20 ⁇ m and can be designed according to the device.
  • gallium nitride has a lattice constant difference of 17% and a thermal expansion coefficient difference of 116% from a Si (111) single crystal, and stress is applied to a thin film or a substrate during growth at a high temperature. Further, since the wafer is heated to 1000 ° C. or higher during growth, when the wafer is stressed, it does not break brittlely but exhibits ductility, causing dislocations and plastic deformation.
  • the thickness of the substrate is made sufficiently thick, and the CZ single crystal substrate having a resistivity of 0.1 ⁇ cm or less is used to prevent plastic deformation during growth and reduce warpage. can do.
  • the lower limit of the resistivity is not particularly limited and can be appropriately determined, and can be a value larger than 0 ⁇ cm.
  • the thickness of the bonded substrate thicker than 2000 ⁇ m, the strength of the bonded substrate is increased, so that the warpage of the substrate for an electronic device due to the formed nitride semiconductor film can be further suppressed. Therefore, it is particularly suitable as a substrate for an electronic device used for a high withstand voltage product.
  • the upper limit of the thickness is not particularly limited and can be appropriately determined, but 4800 ⁇ m is sufficient.
  • the present invention is a method for manufacturing a substrate for an electronic device in which a nitride semiconductor film is formed on a silicon single crystal bonded substrate.
  • a method for manufacturing a substrate for an electronic device which comprises using a plurality of silicon single crystal substrates having a resistivity of 0.1 ⁇ cm or less produced by the CZ method.
  • a plurality of silicon single crystal substrates are bonded to form a bonded substrate having a thickness of more than 2000 ⁇ m.
  • a plurality of silicon single crystal substrates those having a resistivity of 0.1 ⁇ cm or less manufactured by the CZ method, which is hard and has excellent strength, are used.
  • a plurality of silicon single crystal substrates having an oxygen concentration of 3.0 ⁇ 10 17 to 1 ⁇ 10 18 atoms / cm 3 (ASTM'79).
  • ASTM'79 an oxygen concentration of 3.0 ⁇ 10 17 to 1 ⁇ 10 18 organisms / cm 3
  • the method of joining a plurality of silicon single crystal substrates is not particularly limited, but it is preferable to bond them with an oxide film. Further, by thinning the oxide film before bonding, only oxygen of the oxide film is diffused by the bonding heat treatment after bonding, and a structure without an oxide film can be formed at the bonding interface. By adhering the silicon single crystal substrate with the oxide film in this way, the stress applied during the growth of the nitride can be relaxed.
  • the thickness of each of the plurality of silicon single crystal substrates is 1000 ⁇ m or more.
  • the thickness of each of the plurality of silicon single crystal substrates is 1000 ⁇ m or more.
  • a bonded substrate can be manufactured.
  • the nitride semiconductor film is epitaxially grown on the bonded substrate manufactured as described above.
  • the intermediate layer can be formed before the growth of the nitride semiconductor film.
  • a bonded substrate having high strength can be produced by using a plurality of CZ silicon single crystal substrates having a resistivity of 0.1 ⁇ cm or less and further increasing the thickness of the bonded substrate to more than 2000 ⁇ m. Therefore, it is possible to suppress the warp of the substrate for the electronic device when the nitride semiconductor film is formed. Therefore, it is particularly suitable as a method for manufacturing a substrate for an electronic device used for a high withstand voltage product.
  • Example 1 Two wafers (diameter 150 mm, crystal orientation (111)) having a resistivity of 0.007 ⁇ cm and an oxygen concentration of 7 ⁇ 10 17 atoms / cm 3 (ASTM'79) and a thickness of 1100 ⁇ m of a CZ silicon single crystal substrate were prepared. .. Next, a substrate for an electronic device as shown in FIG. 1 (a) was produced as follows. The CZ silicon single crystal substrate (base wafer) 1 and the CZ silicon single crystal substrate (bond wafer) 2 polished on both sides were thermally oxidized to form a SiO 2 film having a thickness of 100 nm in each. Then, through the bonding step, the bonding heat treatment was performed at 1150 ° C. for 2 hours.
  • the surface oxide film was removed by immersing in 10% HF to prepare a obtained bonded substrate having a thickness of 2200 ⁇ m (two 1100 ⁇ m substrates + bonding layer 200 nm). Then, the produced bonded substrate was epitaxially grown with an 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in a MOVPE furnace. The warpage of the wafer after epitaxial growth was 10 ⁇ m.
  • Comparative Example 1 a substrate was produced in the same manner as in Example 1 except that the thickness of the CZ silicon single crystal substrate was changed. Wafers (diameter 150 mm, crystal orientation (111)) with a resistivity of 0.007 ⁇ cm and an oxygen concentration of 7 ⁇ 10 17 atoms / cm 3 (ASTM'79) and CZ silicon single crystal substrates with thicknesses of 500 ⁇ m and 625 ⁇ m, respectively, are 2 I prepared a sheet.
  • the CZ silicon single crystal substrate (base wafer) is thermally oxidized (thickness 100 nm)
  • the double-sided polished CZ silicon single crystal substrate (bond wafer) is thermally oxidized (thickness 100 nm)
  • the bonding heat treatment is performed at 1150 ° C. through a bonding process. I went there for 2 hours.
  • the oxide film removal the surface oxide film was removed by immersing in 10% HF, and the obtained bond having a thickness of 1000 ⁇ m (2 500 ⁇ m substrates + 200 nm bonding layer) and 1250 ⁇ m (2 625 ⁇ m substrates + 200 nm bonding layer) was obtained.
  • a substrate was prepared.
  • each bonded substrate was epitaxially grown with 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in the same MOVPE furnace.
  • the warpage of the wafer having a substrate thickness of 1250 ⁇ m was 20 ⁇ m.
  • the thickness was 50 ⁇ m.
  • Comparative Example 2 In Comparative Example 2, a bonded substrate was prepared by laminating an FZ silicon single crystal substrate and a CZ silicon single crystal substrate, and an epitaxial layer was grown on the produced bonded substrate.
  • Wafers (diameter 150 mm, crystal orientation (111)) having a thickness of 625 ⁇ m and 675 ⁇ m for each single crystal substrate were prepared.
  • the CZ silicon single crystal substrate (base wafer) is thermally oxidized (thickness 100 nm)
  • the double-sided polished FZ silicon single crystal substrate (bond wafer) is thermally oxidized (thickness 100 nm)
  • the bonding heat treatment is performed at 1150 ° C. through a bonding process. I went there for 2 hours.
  • the surface oxide film was removed by immersing in 10% HF, and the obtained bond having a thickness of 1250 ⁇ m (2 625 ⁇ m substrates + 200 nm bonding layer) and 1350 ⁇ m (2 675 ⁇ m substrates + 200 nm bonding layer) was obtained.
  • a substrate was prepared.
  • each bonded substrate was epitaxially grown with 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in the same MOVPE furnace.
  • the warpage of the wafer having a substrate thickness of 1250 ⁇ m was 25 ⁇ m.
  • the thickness was 15 ⁇ m.
  • Comparative Example 3 a bonded substrate was prepared by bonding FZ silicon single crystal substrates to each other, and an epitaxial layer was grown on the produced bonded substrate.
  • Two FZ silicon single crystal substrates with a resistance of 5000 ⁇ cm and a nitrogen concentration of 8 ⁇ 10 14 atoms / cm 3 with thicknesses of 625 ⁇ m and 675 ⁇ m (diameter 150 mm, crystal orientation (111)) were prepared.
  • the substrate (base wafer) 1 is thermally oxidized (thickness 100 nm), the FZ silicon single crystal substrate (bonded wafer) 2 polished on both sides is thermally oxidized (thickness 100 nm), and after a bonding step, a bonding heat treatment is performed at 1150 ° C. I went for a while. Then, as an oxide film removal, the surface oxide film was removed by immersing in 10% HF, and the obtained bond having a thickness of 1250 ⁇ m (2 625 ⁇ m substrates + 200 nm bonding layer) and 1350 ⁇ m (2 675 ⁇ m substrates + 200 nm bonding layer) was obtained. A substrate was prepared.
  • each bonded substrate was epitaxially grown with 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in the same MOVPE furnace.
  • the warpage of the wafer having a substrate thickness of 1250 ⁇ m was 30 ⁇ m.
  • the thickness was 20 ⁇ m.
  • Comparative Example 4 In Comparative Example 4, the thickness of the CZ silicon single crystal substrate was made thinner than that of Comparative Example 1, and the substrate was produced in the same manner as in Comparative Example 1.
  • ASTM'79 oxygen concentration of 7 ⁇ 10 17 organisms / cm 3
  • the CZ silicon single crystal substrate (base wafer) 1 is thermally oxidized (thickness 50 nm)
  • the CZ silicon single crystal substrate (bond wafer) 2 polished on both sides is thermally oxidized (thickness 50 nm)
  • the bonding heat treatment is performed through a bonding process. It was carried out at 1150 ° C. for 2 hours.
  • the oxide film removal the surface oxide film was removed by immersing in 10% HF to prepare a obtained bonded substrate having a thickness of 800 ⁇ m (two 400 ⁇ m substrates + a bonding layer of 100 nm).
  • the substrate was epitaxially grown with 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in a MOVPE furnace. The warpage of the wafer was 200 ⁇ m.
  • Comparative Example 5 In Comparative Example 5, the epitaxial layer was grown without laminating the CZ silicon single crystal substrate.
  • a wafer (diameter 150 mm, crystal orientation (111)) having a resistivity of 0.007 ⁇ cm or less and an oxygen concentration of 7 ⁇ 10 17 atoms / cm 3 (ASTM'79) and a substrate thickness of 625 ⁇ m was prepared. .. Then, the substrate was epitaxially grown with 8 ⁇ m-thick GaN (intermediate layer: 4 ⁇ m, device layer 4 ⁇ m) in a MOVPE furnace. The warpage of the wafer was 300 ⁇ m.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an example, and any object having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect and effect is the present invention. Is included in the technical scope of.

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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

La présente invention concerne un substrat destiné à un dispositif électronique et obtenu par formation d'un film semi-conducteur au nitrure sur un substrat lié de silicium monocristallin. Le substrat destiné à un dispositif électronique se caractérise en ce que le substrat lié s'obtient par collage d'une pluralité de substrats de silicium monocristallin et présente une épaisseur supérieure à 2 000 µm et en ce que la pluralité de substrats de silicium monocristallin sont produits selon un procédé de Chzochralski et présentent une résistivité inférieure ou égale à 0,1 Ω.cm. La présente invention concerne donc : un substrat, destiné à un dispositif électronique et obtenu par formation d'un film semi-conducteur au nitrure sur un substrat de silicium, présentant peu de gauchissement et pouvant être utilisé dans un article à haute tension de tenue ; et un procédé de production du substrat destiné à un dispositif électronique.
PCT/JP2020/018262 2019-07-11 2020-04-30 Substrat pour dispositif électronique et procédé de production associé WO2021005872A1 (fr)

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EP20837097.3A EP3998376A4 (fr) 2019-07-11 2020-04-30 Substrat pour dispositif électronique et procédé de production associé
US17/617,091 US11705330B2 (en) 2019-07-11 2020-04-30 Substrate for electronic device and method for producing the same
CN202080044129.6A CN113994032A (zh) 2019-07-11 2020-04-30 电子器件用基板及其制造方法

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JP2019129089A JP7279552B2 (ja) 2019-07-11 2019-07-11 電子デバイス用基板およびその製造方法

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JP7279552B2 (ja) * 2019-07-11 2023-05-23 信越半導体株式会社 電子デバイス用基板およびその製造方法
JP6863423B2 (ja) * 2019-08-06 2021-04-21 信越半導体株式会社 電子デバイス用基板およびその製造方法
WO2023228868A1 (fr) * 2022-05-27 2023-11-30 信越半導体株式会社 Substrat pour dispositif électronique et son procédé de production

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JP7279552B2 (ja) 2023-05-23
EP3998376A4 (fr) 2023-07-12
US11705330B2 (en) 2023-07-18
JP2021014376A (ja) 2021-02-12
CN113994032A (zh) 2022-01-28
US20220238326A1 (en) 2022-07-28
EP3998376A1 (fr) 2022-05-18

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