WO2020252876A1 - 一种薄膜晶体管基板及其制备方法 - Google Patents

一种薄膜晶体管基板及其制备方法 Download PDF

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WO2020252876A1
WO2020252876A1 PCT/CN2019/100865 CN2019100865W WO2020252876A1 WO 2020252876 A1 WO2020252876 A1 WO 2020252876A1 CN 2019100865 W CN2019100865 W CN 2019100865W WO 2020252876 A1 WO2020252876 A1 WO 2020252876A1
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layer
thin film
source
film transistor
active layer
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赵文群
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the invention relates to the technical field of display panels, in particular to a thin film transistor substrate and a preparation method thereof.
  • Thin Film Transistor plays an important role in active matrix driving liquid crystal display devices and is a core component of flat panel displays. Each display integrates millions or even hundreds of millions of TFT devices.
  • Amorphous silicon thin film transistors have a simple manufacturing process and low cost, but their mobility is relatively low; low-temperature polysilicon thin film transistors have high mobility, but high cost and complex manufacturing processes.
  • inorganic metal oxides such as ZnO, SnO2, In2O3, or their multi-element mixtures (IGZO). These inorganic metal oxides all exhibit n-type semiconductor characteristics, which greatly limits the development of CMOS devices and digital integrated circuits.
  • Cuprous iodide CuI is a green and environmentally friendly material, in which copper and iodine are widely present in nature; CuI is an intrinsic P-type semiconductor with a wide band gap, with a band gap of 3.1 eV, transparent under visible light; CuI has growth Low temperature, high mobility (intrinsic carrier mobility 44cm2/Vs), low price and other advantages. Compared with other P-type semiconductors, the use of CuI to prepare high-performance devices has greater potential.
  • An object of the present invention is to provide a thin film transistor substrate, which can solve the problem of poor structural stability of the cuprous iodide thin film transistor in the prior art.
  • the present invention provides a thin film transistor substrate, including a substrate, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source and drain layer, an organic layer, and a pixel electrode layer arranged in sequence;
  • the material used for the active layer is cuprous iodide.
  • the active layer defines a channel region, a non-channel region, and a source-drain doped region, and the active layer in the source-drain doped region is doped with iodine ion.
  • the active layer defines a channel region, a non-channel region, and a source-drain doped region, and the active layer in the source-drain doped region is doped with zinc ion.
  • the present invention also provides a method for preparing the thin film transistor substrate of the present invention, which includes the following steps:
  • Step S1 providing a substrate, and depositing a copper iodide thin film layer on the substrate to form an active layer;
  • Step S2 depositing a gate insulating layer and a gate layer, and conducting the active layer;
  • Step S3 deposit an interlayer dielectric layer, and set a first via hole on the interlayer dielectric layer; deposit a source/drain layer, and form the source/drain layer pattern after etching; deposit an organic layer, on the organic layer A second via hole is arranged on the upper surface; the pixel electrode layer is deposited, and the pixel electrode is formed by etching.
  • the method for depositing the cuprous iodide thin film layer includes atomization spray method, hydrothermal method, chemical deposition method, pulsed laser deposition, and reactive magnetron sputtering. One of the shots.
  • the step S1 further includes decomposing the iodide ions in the cuprous iodide thin film layer, and the method of decomposing the iodide ions in the cuprous iodide thin film layer includes inert One of a gas annealing treatment method, a water vapor degradation treatment method, and a near room temperature photolysis method using ultraviolet light.
  • step S2 conducting the conductive layer on the active layer includes the following steps:
  • Step S21 coating a first photoresist layer, photoresist ashing is performed on the first photoresist layer, and the region formed by the ashing defines the source and drain doped regions;
  • Step S22 doping with ion implantation to the active layer in the source and drain doped regions and the non-channel region.
  • the thickness of the gate insulating layer in the source and drain doped regions is greater than the thickness of the gate insulating layer in the non-channel region.
  • the ion is an iodide ion.
  • the ion is a zinc ion.
  • the material used for the gate insulating layer includes silicon oxide or silicon nitride.
  • the material used for the gate layer includes aluminum metal, copper metal, or molybdenum metal.
  • the present invention provides a thin film transistor substrate and a preparation method thereof, which can be decomposed in the cuprous iodide thin film through inert gas annealing treatment, water vapor annealing treatment or ultraviolet light near room temperature.
  • the technology of iodide ions obtains a stable and high-quality cuprous iodide thin film.
  • the prepared cuprous iodide thin film transistor structure has low operating voltage and excellent electrical performance. It is a low-power, high-performance CMOS device. Development has laid a good scientific foundation.
  • the active layer is doped with ions implanted through the gate insulating layers of different thicknesses, directly forming a difference in doping concentration, reducing the manufacturing process and saving costs.
  • FIG. 1 is a schematic structural diagram of a thin film transistor substrate provided by Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor substrate provided by Embodiment 1 of the present invention
  • step S1 is a schematic diagram of the structure of the thin film transistor substrate in step S1 in the manufacturing method provided by the embodiment 1 of the present invention
  • FIG. 4 is a schematic diagram of the structure of the thin film transistor substrate in step S2 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of the structure of the thin film transistor substrate in step S3 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor substrate in step S4 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the thin film transistor substrate in step S5 in the preparation method provided by the embodiment 1 of the present invention.
  • step S6 is a schematic diagram of the structure of the thin film transistor substrate in step S6 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the thin film transistor substrate in step S7 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 10 is a schematic diagram of the structure of the thin film transistor substrate in step S8 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 11 is a schematic diagram of the structure of the thin film transistor substrate in step S9 in the manufacturing method provided by the embodiment 1 of the present invention.
  • step S10 is a schematic diagram of the structure of the thin film transistor substrate in step S10 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 13 is a schematic diagram of the structure of the thin film transistor substrate in step S11 in the manufacturing method provided by the embodiment 1 of the present invention.
  • step S12 is a schematic diagram of the structure of the thin film transistor substrate in step S12 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 1 shows the thin film transistor substrate provided by this embodiment.
  • the thin film transistor substrate includes a substrate 10, a first active layer 21, and a second active layer arranged in sequence.
  • the material used for the first active layer 21 and the second active layer 22 is cuprous iodide.
  • the cuprous iodide thin film transistor structure has a low operating voltage and excellent electrical performance.
  • the first active layer 21 defines a channel region 25, a non-channel region 24 and a source-drain doped region 23.
  • the first active layer 21 in the source-drain doped region 23 is doped with iodine ions, At this time, it is P-type doping.
  • the ions doped in the first active layer 21 in the source and drain doped regions 23 may also be zinc ions, and in this case, it is N-type doping.
  • FIG. 2 shows a flowchart of the method for preparing the thin film transistor substrate provided by this embodiment, including the following steps:
  • Step S1 Provide a substrate 10, and deposit a copper iodide thin film layer 20 on the substrate 10;
  • FIG. 3 is a schematic diagram of the structure of the thin film transistor substrate in step S1 of the manufacturing method provided by this embodiment.
  • the method for depositing the cuprous iodide thin film layer includes one of atomization spray method, hydrothermal method, chemical deposition method, pulsed laser deposition and reactive magnetron sputtering, which can be determined as required, and is not limited here. .
  • Step S1 also includes decomposing iodide ions in the cuprous iodide film layer 20 to obtain a cuprous iodide film with good stability and high quality.
  • the method for decomposing iodide ions in the cuprous iodide thin film layer 20 includes one of an inert gas annealing treatment method, a water vapor degradation treatment method, and a photolysis method using ultraviolet light at near room temperature.
  • Step S2 photoresist coating, exposure development and etching are performed on the cuprous iodide thin film layer to form the first active layer 21 and the second active layer 22;
  • FIG. 4 shows a schematic diagram of the structure of the thin film transistor substrate in step S2 of the manufacturing method provided by this embodiment.
  • Step S3 Deposit a gate insulating layer 30 and a gate layer 40 on the first active layer 21 and the second active layer 22 in sequence, coat the first photoresist layer 11 and the second photoresist layer 12, and define the gate Layer pattern
  • FIG. 5 is a schematic diagram of the structure of the thin film transistor substrate in step S3 of the manufacturing method provided in this embodiment.
  • the material used for the gate insulating layer 30 may be silicon oxide or silicon nitride, which is not limited herein.
  • the material used for the gate layer 40 can be aluminum metal, copper metal, or molybdenum metal, which is not limited herein.
  • Step S4 After the gate layer is etched, the first gate layer 41 and the second gate layer 42 are formed, and the third photoresist layer 13 is coated on the second photoresist layer 12 to form a protective layer, and then the gate is insulated The layer 30 is etched to form a gate insulating layer pattern;
  • FIG. 6 shows a schematic diagram of the structure of the thin film transistor substrate in step S4 of the manufacturing method provided by this embodiment.
  • Step S5 Perform photoresist ashing on the first photoresist layer 11, and the region formed by the ashing defines the source and drain doped regions 23;
  • FIG. 7 shows a schematic diagram of the structure of the thin film transistor substrate in step S5 of the manufacturing method provided in this embodiment.
  • Step S6 etching the first gate layer 41 under the source and drain doped regions 23;
  • FIG. 8 is a schematic diagram of the structure of the thin film transistor substrate in step S6 of the manufacturing method provided by this embodiment.
  • Step S7 implanting first ions into the first active layer 21 in the source and drain doped regions 23 and the non-channel region 24 for doping;
  • FIG. 9 is a schematic diagram of the structure of the thin film transistor substrate in step S7 of the manufacturing method provided by this embodiment.
  • the thickness of the gate insulating layer 30 in the source and drain doped region 23 is greater than the thickness of the gate insulating layer in the non-channel region 14, and the first active layer 21 in the source and drain doped region 23 forms ion doping.
  • the impurity concentration is higher than the formation ion doping concentration of the first active layer 21 in the non-channel region 24.
  • the first ion is iodide ion or zinc ion.
  • Zinc ion is used as the first ion, which will form N-type doping.
  • Step S8 peeling off the first photoresist layer 11, the second photoresist layer 12 and the third photoresist layer 13;
  • FIG. 10 shows a schematic diagram of the structure of the thin film transistor substrate in step S8 of the manufacturing method provided by this embodiment.
  • Step S9 etching the gate insulating layer 30;
  • FIG. 11 is a schematic diagram of the structure of the thin film transistor substrate in step S9 of the manufacturing method provided by this embodiment.
  • Step S10 depositing a fourth photoresist layer 14 on the first gate layer 41, and implanting second ions into the second active layer 22 for doping;
  • FIG. 12 is a schematic diagram of the structure of the thin film transistor substrate in step S10 of the manufacturing method provided by this embodiment.
  • the second ion and the first ion are different types of ions; in this embodiment, the second ion is an iodide ion or a zinc ion.
  • Step S11 peeling off the fourth photoresist layer 14;
  • FIG. 13 is a schematic diagram of the structure of the thin film transistor substrate in step S11 in the manufacturing method provided by this embodiment.
  • Step S12 deposit the interlayer dielectric layer 50, and provide first via holes on the interlayer dielectric layer 50 and the gate insulating layer 30; deposit the source and drain layer 60, and form the source and drain layer patterns after etching; deposit the organic layer 70 , A second via hole is provided on the organic layer; the pixel electrode layer 80 is deposited, and the pixel electrode is formed by etching;
  • FIG. 14 is a schematic diagram of the structure of the thin film transistor substrate in step S112 in the manufacturing method provided by this embodiment.
  • the present invention provides a thin film transistor substrate and a preparation method thereof, which are obtained through inert gas annealing treatment, water vapor annealing treatment, or photolysis of iodide ions in cuprous iodide thin film by ultraviolet light at near room temperature.
  • Good stability, high-quality cuprous iodide thin film, the prepared cuprous iodide thin film transistor structure has low operating voltage and excellent electrical performance, laying a good scientific foundation for the development of low-power, high-performance CMOS devices .
  • the active layer is doped with ions implanted through the gate insulating layers of different thicknesses, directly forming a difference in doping concentration, reducing the manufacturing process and saving costs.

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Abstract

本发明提供一种薄膜晶体管基板及其制备方法，薄膜晶体管基板包括依次设置的基板、有源层、栅极绝缘层、栅极层、层间介质层、源漏极层、有机层和像素电极层；其中所述有源层的材料采用碘化亚铜。

Description

一种薄膜晶体管基板及其制备方法 技术领域
本发明涉及显示面板技术领域，特别涉及一种薄膜晶体管基板及其制备方法。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）在有源矩阵驱动液晶显示器件中发挥了重要的作用，是平板显示的核心部件，每台显示器都集成了数百万甚至上亿个TFT器件。非晶硅薄膜晶体管制程简单成本低，但是其迁移率比较低；低温多晶硅薄膜晶体管虽然迁移率高，但是成本高，而且制程复杂。
目前研究与应用最多的半导体材料为无机金属氧化物，如ZnO、SnO2、In2O3，或其多元的混合物（IGZO）。这些无机金属氧化物均展现n型半导体特征，这极大的限制了CMOS器件与数字集成电路的发展。
然而基于p型半导体器件应用比较少，主要是由于电化学性能适宜于p型半导体材料的相对较少和环境稳定性差等缺点。碘化亚铜CuI是一种绿色环保材料，其中铜和碘元素广泛存在于自然界中；CuI是一种宽禁带的本征P型半导体，带隙3.1ev，在可见光下透明；CuI具有生长温度低，迁移率高（本征载流子迁移率44cm2/Vs），价格低廉等优点。相比其他P型半导体，用CuI制备高性能器件具有更大的潜能。
我们知道在电场下，CuI具有极高载流子浓度且很难控制，导致CuI器件的稳定性很差。
因此，确有必要来开发一种新型的薄膜晶体管基板，以克服现有技术的缺陷。
 技术问题
本发明的一个目的是提供一种薄膜晶体管基板，其能够解决现有技术中碘化亚铜薄膜晶体管结构稳定性很差的问题。
 技术解决方案
为实现上述目的，本发明提供一种薄膜晶体管基板，包括依次设置的基板、有源层、栅极绝缘层、栅极层、层间介质层、源漏极层、有机层和像素电极层；其中所述有源层采用的材料为碘化亚铜。
进一步的，在其他实施方式中，其中所述有源层定义有沟道区、非沟道区和源漏极掺杂区，所述源漏极掺杂区内的有源层掺杂有碘离子。
进一步的，在其他实施方式中，其中所述有源层定义有沟道区、非沟道区和源漏极掺杂区，所述源漏极掺杂区内的有源层掺杂有锌离子。
本发明还提供一种制备本发明涉及的所述薄膜晶体管基板的方法，包括以下步骤：
步骤S1：提供一基板，在所述基板上沉积碘化亚铜薄膜层，形成有源层；
步骤S2：沉积栅极绝缘层和栅极层，对所述有源层进行导体化；
步骤S3：沉积层间介质层，在所述层间介质层上设置第一过孔；沉积源漏极层，刻蚀后形成所述源漏极层图案；沉积有机层，在所述有机层上设置第二过孔；沉积像素电极层，通过刻蚀形成像素电极。
进一步的，在其他实施方式中，其中在所述步骤S1中，沉积所述碘化亚铜薄膜层的方法包括雾化喷雾法、水热法、化学沉积法、脉冲激光沉积和反应磁控溅射中的一种。
进一步的，在其他实施方式中，其中在所述步骤S1中，还包括分解所述碘化亚铜薄膜层中的碘离子，分解所述碘化亚铜薄膜层中的碘离子的方法包括惰性气体退火处理方法、水蒸气退化处理方法和利用紫外光近室温光分解方法中的一种。
进一步的，在其他实施方式中，其中在步骤S2中，对所述有源层进行导体化包括以下步骤：
步骤S21：涂布第一光阻层，对所述第一光阻层进行光阻灰化，灰化形成的区域定义出源漏极掺杂区域；
步骤S22：对所述源漏极掺杂区域和非沟道区域内的所述有源层注入离子进行掺杂。
进一步的，在其他实施方式中，其中在步骤S22中，所述源漏极掺杂区域内的所述栅极绝缘层的厚度大于非沟道区域内的所述栅极绝缘层的厚度。
进一步的，在其他实施方式中，其中所述离子为碘离子。
进一步的，在其他实施方式中，其中所述离子为锌离子。
进一步的，在其他实施方式中，其中所述栅极绝缘层采用的材料包括氧化硅或氮化硅。
进一步的，在其他实施方式中，其中所述栅极层采用的材料包括铝金属或铜金属或钼金属。
 有益效果
相对于现有技术，本发明的有益效果在于：本发明提供一种薄膜晶体管基板及其制备方法，通过惰性气体退火处理、水蒸汽退火处理或利用紫外光近室温光分解碘化亚铜薄膜中碘离子的技术，获得稳定性好，质量高的碘化亚铜薄膜，制备得到的碘化亚铜薄膜晶体管结构具有低的操作电压，优异的电学性能，为低功耗、高性能CMOS器件的发展奠定良好的科学基础。此外，在制备薄膜晶体管基板的过程中，透过不同厚度的栅极绝缘层对有源层注入离子进行掺杂，直接形成掺杂浓度差，减少了制程，节约了成本。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1提供的薄膜晶体管基板的结构示意图；
图2为本发明实施例1提供的薄膜晶体管基板的制备方法的流程图；
图3为本发明实施例1提供的制备方法中步骤S1时薄膜晶体管基板的结构示意图；
图4为本发明实施例1提供的制备方法中步骤S2时薄膜晶体管基板的结构示意图；
图5为本发明实施例1提供的制备方法中步骤S3时薄膜晶体管基板的结构示意图；
图6为本发明实施例1提供的制备方法中步骤S4时薄膜晶体管基板的结构示意图；
图7为本发明实施例1提供的制备方法中步骤S5时薄膜晶体管基板的结构示意图；
图8为本发明实施例1提供的制备方法中步骤S6时薄膜晶体管基板的结构示意图；
图9为本发明实施例1提供的制备方法中步骤S7时薄膜晶体管基板的结构示意图；
图10为本发明实施例1提供的制备方法中步骤S8时薄膜晶体管基板的结构示意图；
图11为本发明实施例1提供的制备方法中步骤S9时薄膜晶体管基板的结构示意图；
图12为本发明实施例1提供的制备方法中步骤S10时薄膜晶体管基板的结构示意图；
图13为本发明实施例1提供的制备方法中步骤S11时薄膜晶体管基板的结构示意图；
图14为本发明实施例1提供的制备方法中步骤S12时薄膜晶体管基板的结构示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
实施例1
本实施例提供一种薄膜晶体管基板，请参阅图1，图1所示为本实施例提供的薄膜晶体管基板，薄膜晶体管基板包括依次设置的基板10、第一有源层21和第二有源层22、栅极绝缘层30、第一栅极层41和第二栅极层42、层间介质层50、源漏极层60、有机层70和像素电极层80。
其中第一有源层21和第二有源层22采用的材料为碘化亚铜，碘化亚铜薄膜晶体管结构具有低的操作电压，优异的电学性能。
其中，第一有源层21定义有沟道区25、非沟道区24和源漏极掺杂区23，源漏极掺杂区23内的第一有源层21掺杂有碘离子，此时为P型掺杂。在其他实施方式中，源漏极掺杂区23内的第一有源层21掺杂的离子也可以为锌离子，此时为N型掺杂。
实施例2
本实施例提供一种实施例1涉及的所述薄膜晶体管基板的制备方法，请参阅图2，图2所示为本实施例提供的薄膜晶体管基板的制备方法的流程图，包括以下步骤：
步骤S1：提供一基板10，在基板10上沉积碘化亚铜薄膜层20；
请参阅图3，图3所示为本实施例提供的制备方法中步骤S1时薄膜晶体管基板的结构示意图。
沉积所述碘化亚铜薄膜层的方法包括雾化喷雾法、水热法、化学沉积法、脉冲激光沉积和反应磁控溅射中的一种，可随需要而定，在此不做限定。
步骤S1还包括分解碘化亚铜薄膜层20中的碘离子，获得稳定性好、高质量的碘化亚铜薄膜。
分解碘化亚铜薄膜层20中的碘离子的方法包括惰性气体退火处理方法、水蒸气退化处理方法和利用紫外光近室温光分解方法中的一种。
步骤S2：对碘化亚铜薄膜层进行光阻涂布、曝光显影及刻蚀，形成第一有源层21和第二有源层22；
请参阅图4，图4所示为本实施例提供的制备方法中步骤S2时薄膜晶体管基板的结构示意图。
步骤S3：在第一有源层21和第二有源层22上依次沉积栅极绝缘层30和栅极层40，涂布第一光阻层11和第二光阻层12，定义栅极层图案；
请参阅图5，图5所示为本实施例提供的制备方法中步骤S3时薄膜晶体管基板的结构示意图。
在本实施例中，栅极绝缘层30采用的材料可以是氧化硅或氮化硅，在此不做限定。
在本实施例中，栅极层40采用的材料可以为铝金属或铜金属或钼金属，在此不做限定。
步骤S4：对栅极层刻蚀后形成第一栅极层41和第二栅极层42，在第二光阻层上12涂布第三光阻层13形成保护层，接着对栅极绝缘层30进行刻蚀形成栅极绝缘层图案；
请参阅图6，图6所示为本实施例提供的制备方法中步骤S4时薄膜晶体管基板的结构示意图。
步骤S5：对第一光阻层11进行光阻灰化，灰化形成的区域定义出源漏极掺杂区域23；
请参阅图7，图7所示为本实施例提供的制备方法中步骤S5时薄膜晶体管基板的结构示意图。
步骤S6：刻蚀源漏极掺杂区域23下的第一栅极层41；
请参阅图8，图8所示为本实施例提供的制备方法中步骤S6时薄膜晶体管基板的结构示意图。
步骤S7：对源漏极掺杂区域23和非沟道区域24内的第一有源层21注入第一离子进行掺杂；
请参阅图9，图9所示为本实施例提供的制备方法中步骤S7时薄膜晶体管基板的结构示意图。
其中源漏极掺杂区域23内的栅极绝缘层30的厚度大于非沟道区域14内的栅极绝缘层的厚度，源漏极掺杂区域23内的第一有源层21形成离子掺杂浓度比非沟道区域24内的第一有源层21形成离子掺杂浓度高。利用源漏极掺杂区域23和非沟道区域24内的栅极绝缘层30的厚度不同，源漏极掺杂区域23和非沟道区域24内的第一有源层21形成离子掺杂浓度差，减少了制程，节约了成本。
在本实施例中，第一离子为碘离子或锌离子。第一离子采用锌离子，会形成N型掺杂。
步骤S8：剥离第一光阻层11、第二光阻层12和第三光阻层13；
请参阅图10，图10所示为本实施例提供的制备方法中步骤S8时薄膜晶体管基板的结构示意图。
步骤S9：对栅极绝缘层30进行刻蚀；
请参阅图11，图11所示为本实施例提供的制备方法中步骤S9时薄膜晶体管基板的结构示意图。
步骤S10：在第一栅极层41上沉积第四光阻层14，对第二有源层22注入第二离子进行掺杂；
请参阅图12，图12所示为本实施例提供的制备方法中步骤S10时薄膜晶体管基板的结构示意图。
其中第二离子与第一离子为不同种类的离子；在本实施例中，第二离子为碘离子或锌离子。
步骤S11：剥离第四光阻层14；
请参阅图13，图13所示为本实施例提供的制备方法中步骤S11时薄膜晶体管基板的结构示意图。
步骤S12：沉积层间介质层50，在层间介质层50和栅极绝缘层30上设置第一过孔；沉积源漏极层60，刻蚀后形成源漏极层图案；沉积有机层70，在有机层上设置第二过孔；沉积像素电极层80，通过刻蚀形成像素电极；
请参阅图14，图14所示为本实施例提供的制备方法中步骤S112时薄膜晶体管基板的结构示意图。
本发明的有益效果在于：本发明提供一种薄膜晶体管基板及其制备方法，通过惰性气体退火处理、水蒸汽退火处理或利用紫外光近室温光分解碘化亚铜薄膜中碘离子的技术，获得稳定性好，质量高的碘化亚铜薄膜，制备得到的碘化亚铜薄膜晶体管结构具有低的操作电压，优异的电学性能，为低功耗、高性能CMOS器件的发展奠定良好的科学基础。此外，在制备薄膜晶体管基板的过程中，透过不同厚度的栅极绝缘层对有源层注入离子进行掺杂，直接形成掺杂浓度差，减少了制程，节约了成本。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种薄膜晶体管基板，包括依次设置的基板、有源层、栅极绝缘层、栅极层、层间介质层、源漏极层、有机层和像素电极层；其中，所述有源层采用的材料为碘化亚铜。
  2. 根据权利要求1所述的薄膜晶体管基板，其中，所述有源层定义有沟道区、非沟道区和源漏极掺杂区，所述源漏极掺杂区内的有源层掺杂有碘离子。
  3. 根据权利要求1所述的薄膜晶体管基板，其中，所述有源层定义有沟道区、非沟道区和源漏极掺杂区，所述源漏极掺杂区内的有源层掺杂有锌离子。
  4. 一种制备权利要求1所述薄膜晶体管基板的方法，其中，包括以下步骤：
    步骤S1：提供一基板，在所述基板上沉积碘化亚铜薄膜层，形成有源层；
    步骤S2：沉积栅极绝缘层和栅极层，对所述有源层进行导体化；
    步骤S3：沉积层间介质层，在所述层间介质层上设置第一过孔；沉积源漏极层，刻蚀后形成所述源漏极层图案；沉积有机层，在所述有机层上设置第二过孔；沉积像素电极层，通过刻蚀形成像素电极。
  5. 根据权利要求4所述的制备方法，其中，在所述步骤S1中，沉积所述碘化亚铜薄膜层的方法包括雾化喷雾法、水热法、化学沉积法、脉冲激光沉积和反应磁控溅射中的一种。
  6. 根据权利要求4所述的制备方法，其中，在所述步骤S1中，还包括分解所述碘化亚铜薄膜层中的碘离子，分解所述碘化亚铜薄膜层中的碘离子的方法包括惰性气体退火处理方法、水蒸气退化处理方法和利用紫外光近室温光分解方法中的一种。
  7. 根据权利要求4所述的制备方法，其中，在步骤S2中，对所述有源层进行导体化包括以下步骤：
    步骤S21：涂布第一光阻层，对所述第一光阻层进行光阻灰化，灰化形成的区域定义出源漏极掺杂区域；
    步骤S22：对所述源漏极掺杂区域和非沟道区域内的所述有源层注入离子进行掺杂。
  8. 根据权利要求7所述的制备方法，其中，在步骤S22中，所述源漏极掺杂区域内的所述栅极绝缘层的厚度大于非沟道区域内的所述栅极绝缘层的厚度。
  9. 根据权利要求7所述的制备方法，其中，所述离子为碘离子。
  10. 根据权利要求7所述的制备方法，其中，所述离子为锌离子。
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