WO2020248612A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2020248612A1
WO2020248612A1 PCT/CN2020/074965 CN2020074965W WO2020248612A1 WO 2020248612 A1 WO2020248612 A1 WO 2020248612A1 CN 2020074965 W CN2020074965 W CN 2020074965W WO 2020248612 A1 WO2020248612 A1 WO 2020248612A1
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WO
WIPO (PCT)
Prior art keywords
substrate
metal layer
display panel
orthographic projection
electrode
Prior art date
Application number
PCT/CN2020/074965
Other languages
English (en)
French (fr)
Inventor
贾溪洋
吴剑龙
朱正勇
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2020248612A1 publication Critical patent/WO2020248612A1/zh
Priority to US17/365,194 priority Critical patent/US11937466B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • This application relates to the field of display technology, in particular to a display panel.
  • the gate potential of the driving transistor determines the gray scale of the display. There is no overlapping capacitance between the gate of the driving transistor and the data line, but the lateral parasitic capacitance between them is unavoidable. As the resolution of the display panel increases, the pixel layout space becomes smaller and smaller, and the parasitic capacitance between the gate of the driving transistor and the data line becomes larger. The voltage change on the data line will be coupled to the gate of the driving transistor, thereby causing crosstalk.
  • the present application provides a display panel that can reduce the coupling capacitance between the gate of the driving transistor and the data line, thereby reducing the crosstalk phenomenon.
  • a technical solution adopted in this application is to provide a display panel, the display panel comprising: a substrate; a first metal layer located on one side of the substrate and including the gate of a driving transistor; and a second metal layer located on The first metal layer is far away from the substrate and includes a first substrate of a storage capacitor, the orthographic projection of the first substrate on the substrate and the orthographic projection of the gate on the substrate Partially overlap; the third metal layer, located on the side of the second metal layer away from the substrate, includes a data line, the orthographic projection of the data line on the substrate and the gate on the substrate The orthographic projections on the first shielding electrode do not overlap; the first shielding electrode has a fixed potential, and the orthographic projection of the grid on the substrate is located on the front of the first shielding electrode and the first substrate on the substrate. Projecting.
  • the display panel provided by the present application includes a first shielding electrode, the first shielding electrode has a fixed potential, and the orthographic projection of the gate of the driving transistor on the substrate is located between the first shielding electrode and the storage capacitor.
  • the first substrate is in an orthographic projection on the substrate.
  • the lateral coupling capacitance between the data line and the gate of the driving transistor is shielded by the coupling capacitance between the gate and the first shield electrode, thereby reducing the influence of the voltage change on the data line on the gate voltage of the driving transistor; and
  • the first shielding electrode has a fixed potential, and the fixed potential of the first shielding electrode is not easily coupled to change during the operation of the display panel, so that the gate voltage of the driving transistor is kept as stable as possible, and the crosstalk phenomenon is improved.
  • FIG. 1 is a schematic plan view of an embodiment of a display panel of this application
  • FIG. 2 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 1;
  • FIG. 4 is a schematic plan view of another embodiment of the display panel of this application.
  • FIG. 5 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 4;
  • FIG. 6 is a schematic cross-sectional view of another embodiment of the display panel in FIG. 4;
  • FIG. 7 is a schematic cross-sectional view of another embodiment of the display panel of this application.
  • FIG. 8 is a schematic plan view of another embodiment of the display panel of this application.
  • FIG. 9 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 8;
  • FIG. 10 is a schematic plan view of another embodiment of the display panel of this application.
  • FIG. 1 is a schematic plan view of an embodiment of the display panel of the present application
  • FIG. 2 is a schematic cross-sectional view of an embodiment of the display panel in FIG.
  • the display panel includes a substrate 10 (not shown in FIG. 1), a first metal layer M1, a second metal layer M2, a third metal layer M3, and a first shield electrode 18.
  • the substrate 10 may be a hard substrate or a flexible substrate
  • the hard substrate may be a glass substrate, a silicon substrate, etc.
  • the flexible substrate may be polyimide or the like.
  • the first metal layer M1 is located on the side of the substrate 10, and the material of the first metal layer M1 may be molybdenum Mo or the like.
  • the first metal layer M1 includes the gate 12 of the driving transistor; of course, in this embodiment, the first metal layer M1 may also include other, for example, the gates of other switching transistors, multiple scan lines SCAN, and storage capacitors.
  • One substrate e.g., lower substrate, etc.
  • the second metal layer M2 is located on the side of the first metal layer M1 away from the substrate 10.
  • the first metal layer M1 and the second metal layer M2 can be separated by an insulating layer, and the material of the second metal layer M2 can be molybdenum Mo Wait.
  • the second metal layer M2 includes the first substrate 14 (for example, the upper substrate) of the storage capacitor.
  • the orthographic projection of the first substrate 14 on the substrate 10 and the orthographic projection of the gate electrode 12 on the substrate 10 partially overlap; In the direction of the paper in FIG. 1, the first substrate 14 only covers a part of the gate electrode 12.
  • the second metal layer M2 may also include others, for example, the reference voltage line 11 and the like.
  • the third metal layer M3 is located on the side of the second metal layer M2 away from the substrate 10.
  • the third metal layer M3 and the second metal layer M2 can be separated by an insulating layer, and the material of the third metal layer M3 can be aluminum Al Wait.
  • the third metal layer M3 includes a data line 16, and the orthographic projection of the data line 16 on the substrate 10 does not coincide with the orthographic projection of the gate electrode 12 on the substrate 10.
  • the third metal layer M3 may also include others, for example, the power supply voltage line 13 and the like.
  • the first shielding electrode 18 has a fixed potential.
  • the orthographic projection of the grid 12 on the substrate 10 is in the orthographic projection of the first shielding electrode 18 and the first substrate 14 on the substrate 10, that is, perpendicular to the paper in FIG. In the surface direction, the first substrate 14 only covers a part of the gate 12 of the driving transistor, and the area where the gate 12 of the driving transistor protrudes from the first substrate 14 is covered by the first shield electrode 18.
  • the material of the first shield electrode 18 may be molybdenum Mo, aluminum Al, or the like.
  • the lateral coupling capacitance between the data line 16 and the gate 12 of the driving transistor is shielded by the coupling capacitance between the gate 12 and the first shield electrode 18, thereby reducing the impact of the voltage change on the data line 16 on the driving
  • the first shielding electrode 18 is connected to the power supply voltage line 13, and the power supply voltage line 13 receives a constant DC voltage signal.
  • the DC voltage signal is not easy to change during the operation of the display panel, thereby making the gate of the driving transistor
  • the pole 12 voltage is kept as stable as possible, and the crosstalk phenomenon is improved.
  • the first shielding electrode 18 is located on the fourth metal layer M4, the fourth metal layer M4 is located between the third metal layer M3 and the second metal layer M2, and the fourth metal
  • the layer M4 and the third metal layer M3 are separated by an insulating layer, and the fourth metal layer M4 and the second metal layer M2 are separated by an insulating layer; the first shield electrode 18 and the power supply voltage line 13 are on the substrate
  • the orthographic projection on the substrate 10 has an overlapping area (not labeled).
  • the first shield electrode 18 and the power supply voltage line 13 are connected through the first connecting hole A, and the orthographic projection of the first connecting hole A on the substrate 10 is located in the overlapping area.
  • the first connection hole A may be filled with conductive material, so that the first shield electrode 18 is electrically connected to the power supply voltage line 13, and the fixed potential of the first shield electrode 18 is the power supply voltage.
  • the above-mentioned way of designing the first shield electrode 18 is relatively simple, and the implementation process is relatively convenient.
  • FIG. 3 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 1.
  • the first shielding electrode 18a is located on the fourth metal layer M4a, and the fourth metal layer M4a is located on the side of the third metal layer M3a away from the substrate 10a.
  • the first shielding electrode 18a and the power supply voltage line 13a have an overlap with the orthographic projection on the substrate 10a. In the area, the first shield electrode 18a and the power supply voltage line 13a are connected through the second connection hole B, and the orthographic projection of the second connection hole B on the substrate 10a is located in the overlap area.
  • the second connection hole B may be filled with conductive material, so that the first shield electrode 18a is electrically connected to the power supply voltage line 13a, and the fixed potential of the first shield electrode 18a is the power supply voltage.
  • FIG. 4 is a schematic plan view of another embodiment of the display panel of this application
  • FIG. 5 is a schematic cross-sectional view of an embodiment of the display panel in FIG.
  • the display panel provided by this embodiment further includes: a first connecting wire 15 located in the third metal layer M3b, the first connecting wire 15 is connected to the gate 12b through the third connecting hole C,
  • the orthographic projection of a shielding electrode 18b on the substrate 10b is also at least partially coincident with the orthographic projection of the first connecting wire 15 on the substrate 10b.
  • the first connection line 15 is connected to the gate 12b, and the potential of the first connection line 15 and the gate 12b are the same.
  • FIG. 6 is a schematic cross-sectional view of another embodiment of the display panel in FIG. 4.
  • the difference between this embodiment and the embodiment in FIG. 5 is that the display panel further includes a semiconductor layer 17.
  • the semiconductor layer 17 may include the source S, the drain D, etc. of the driving transistor, which may be located between the substrate 10c and the first metal layer M1c, and includes a first region H.
  • the first region H is connected to the first region H through the fourth connection hole E.
  • a connecting wire 15c is connected; wherein, the orthographic projection of the first shield electrode 18c on the substrate 10c is also at least partially coincident with the orthographic projection of the first region H on the substrate 10c.
  • the first region H is connected to the gate electrode 12c through a first connection line 15c, and the potential of the first region H and the gate electrode 12c are the same.
  • the lateral coupling capacitance between the data line 16c or other signal lines and the first region H is shielded by the coupling capacitance between the first region H and the first shield electrode 18c, thereby reducing the data line 16c or
  • the influence of voltage changes on other signal lines on the first region H further reduces the influence on the gate electrode 12c of the driving transistor.
  • the first region H'in the above embodiment can also be shielded by introducing the second shielding electrode 19.
  • FIG. 7, is a schematic cross-sectional view of another embodiment of the display panel of this application.
  • the second shielding electrode 19 is located on the second metal layer M2d, and the second shielding electrode 19 can be formed when the second metal layer M2d is patterned.
  • the second shield electrode 19 is connected to the power supply voltage line 13d.
  • the orthographic projection of the second shield electrode 19 and the power supply voltage line 13d on the substrate 10d has an overlapping area, and the second shield electrode 19 and the power supply voltage line 13d can be directly connected through Hole connection, at this time, the second shield electrode 19 has a fixed potential, and the fixed potential is the power supply voltage.
  • the orthographic projection of the second shielding electrode 19 on the substrate 10d and the orthographic projection of the first region H′ on the substrate 10d at least partially overlap.
  • the lateral coupling capacitance between the data line 16d or other signal lines and the first region H' is shielded by the coupling capacitance between the first region H'and the second shield electrode 19, thereby reducing the data line 16d or
  • the influence of voltage changes on other signal lines on the first region H′ further reduces the influence on the gate electrode 12d of the driving transistor.
  • FIG. 8 is a schematic plan view of another embodiment of the display panel of this application
  • FIG. 9 is a schematic cross-sectional view of an embodiment of the display panel in FIG. 8.
  • the first shield electrode 18e is connected to the reference voltage line 11e.
  • the reference voltage line 11e may be located in the second metal layer M2e.
  • the reference voltage line 11e receives a constant DC voltage signal.
  • the reference voltage on the reference voltage line 11e is not easily affected by the display panel.
  • the coupling effect of other signal lines is not easy to change during the operation of the display panel, so that the voltage of the gate 12e of the driving transistor is kept as stable as possible, and the crosstalk phenomenon is improved.
  • the first shield electrode 18e is located on the fourth metal layer M4e, and the fourth metal layer M4e is located on the side of the third metal layer M3e away from the substrate 10e; the display panel further includes a second connecting wire 20 located on the third metal layer M4e.
  • the second connecting wire 20 is connected to the reference voltage line 11e through the fifth connecting hole F, and the other end of the second connecting wire 20 is connected to the first shield electrode 18e through the sixth connecting hole G.
  • the display panel when the display panel includes a first connecting wire 15e located on the third metal layer M3e connected to the gate 12e of the driving transistor, as shown in FIG. 9, the first shielding electrode 18e is on the substrate 10e
  • the orthographic projection of may further cover at least part of the orthographic projection of the first connecting line 15e on the substrate 10e.
  • the first shield electrode 18e is on the substrate
  • the projection on 10e can further cover at least part of the projection of the first area H′′ on the substrate 10e.
  • at least part of the first region H" can also be covered by introducing a second shielding electrode as shown in FIG.
  • FIG. 10 is a schematic plan view of another embodiment of the display panel of this application.
  • the orthographic projection of the first shield electrode 18f on the substrate (not shown in FIG. 10) in the above-mentioned several embodiments is also connected to the data line 16f.
  • the orthographic projections on the substrate partially overlap.
  • the parasitic capacitance between the data line and the gate of the driving transistor is obtained by software simulation. As shown in FIG. 1, when the first shield electrode 18 is not included in the display panel, the parasitic capacitance coupled between the data line 16 and the gate electrode 12 of the driving transistor is 0.045 fF; when the first shield electrode 18 is introduced into the display panel At this time, the parasitic capacitance coupled between the data line 16 and the gate 12 of the driving transistor is 0.022 fF, and the parasitic capacitance is reduced by 48%.

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Abstract

提供了一种显示面板，所述显示面板包括：衬底（10）；第一金属层（M1），位于所述衬底一侧，包括驱动晶体管的栅极（12）；第二金属层（M2），位于所述第一金属层远离所述衬底一侧，包括存储电容的第一基板（14），所述第一基板在所述衬底上的正投影与所述栅极在所述衬底上的正投影部分重合；第三金属层（M3），位于所述第二金属层远离所述衬底一侧，包括数据线（16），所述数据线在所述衬底上的正投影与所述栅极在所述衬底上的正投影不重合；第一屏蔽电极（18），具有固定电位，所述栅极在所述衬底上的正投影位于所述第一屏蔽电极和所述第一基板在所述衬底上的正投影中。通过上述方式，本申请能够降低驱动晶体管的栅极和数据线之间的耦合电容，进而降低串扰现象。

Description

显示面板 技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板。
背景技术
对于有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，驱动晶体管的栅极电位决定了显示的灰阶。驱动晶体管的栅极与数据线之间没有交叠电容，但是他们二者之间的侧向寄生电容是无法避免的。随着显示面板的分辨率的提高，像素布局空间越来越小，驱动晶体管的栅极与数据线之间的寄生电容越来越大。数据线上的电压变化会耦合到驱动晶体管的栅极，进而产生串扰现象。
为此，在进一步提高显示面板分辨率的发展趋势下，驱动晶体管的栅极和数据线之间的串扰现象亟待解决。
发明内容
本申请提供一种显示面板，能够降低驱动晶体管的栅极和数据线之间的耦合电容，进而降低串扰现象。
本申请采用的一个技术方案是：提供一种显示面板，所述显示面板包括：衬底；第一金属层，位于所述衬底一侧，包括驱动晶体管的栅极；第二金属层，位于所述第一金属层远离所述衬底一侧，包括存储电容的第一基板，所述第一基板在所述衬底上的正投影与所述栅极在所述衬底上的正投影部分重合；第三金属层，位于所述第二金属层远离所述衬底一侧，包括数据线，所述数据线在所述衬底上的正投影与所述栅极在所述衬底上的正投影不重合；第一屏蔽电极，具有固定电位，所述栅极在所述衬底上的正投影位于所述第一屏蔽电极和所述第一基板在所述衬底上的正投影中。
本申请的有益效果是：本申请所提供的显示面板中包括第一屏蔽电极，第一屏蔽电极具有固定电位，驱动晶体管的栅极在衬底上的正投影位于第一屏蔽电极和存储电容的第一基板在衬底上的正投影中。数据线与驱动晶体管的栅极之间的侧向耦合电容被栅极与第一屏蔽电极之间的耦合电容屏蔽，进而降低数据线上的电压变化对驱动晶体管的栅极电压的影响；且由于第一屏蔽电极具有固定电位，该第一屏蔽电极的固定电位在显示面板工作过程中不容易被耦合发 生变化，进而使得驱动晶体管的栅极电压尽量保持为稳定的波形，串扰现象得到改善。
【附图说明】
图1为本申请显示面板一实施方式的平面示意图；
图2为图1中显示面板一实施方式的剖面示意图；
图3为图1中显示面板一实施方式的剖面示意图；
图4为本申请显示面板另一实施方式的平面示意图；
图5为图4中显示面板一实施方式的剖面示意图；
图6为图4中显示面板另一实施方式的剖面示意图；
图7为本申请显示面板另一实施方式的剖面示意图；
图8为本申请显示面板又一实施方式的平面示意图；
图9为图8中显示面板一实施方式的剖面示意图；
图10为本申请显示面板又一实施方式的平面示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本申请保护的范围。
请参阅图1-图2，图1为本申请显示面板一实施方式的平面示意图，图2为图1中显示面板一实施方式的剖面示意图。该显示面板包括衬底10(图1中未示)、第一金属层M1、第二金属层M2、第三金属层M3和第一屏蔽电极18。
具体而言，衬底10可以为硬质衬底或者柔性衬底，硬质衬底可以为玻璃基板、硅基板等；柔性衬底可以为聚酰亚胺等。
第一金属层M1位于衬底10一侧，第一金属层M1的材质可以为钼Mo等。第一金属层M1包括驱动晶体管的栅极12；当然，在本实施例中，第一金属层M1还可以包括其他，例如，其他开关晶体管的栅极、多个扫描线SCAN、存储电容的其中一个基板(例如，下基板)等。
第二金属层M2位于第一金属层M1远离衬底10一侧，第一金属层M1和第二金属层M2之间可以用绝缘层间隔开，第二金属层M2的材质可以为钼Mo 等。第二金属层M2包括存储电容的第一基板14(例如，上基板)，第一基板14在衬底10上的正投影与栅极12在衬底10上的正投影部分重合；即在垂直于图1中纸面方向上，第一基板14仅覆盖部分栅极12。当然，在本实施例中，第二金属层M2还可以包括其他，例如，参考电压线11等。
第三金属层M3位于第二金属层M2远离衬底10一侧，第三金属层M3与第二金属层M2之间可以用绝缘层间隔开，第三金属层M3的材质可以为铝Al等。第三金属层M3包括数据线16，数据线16在衬底10上的正投影与栅极12在衬底10上的正投影不重合。当然，在本实施例中，第三金属层M3还可以包括其他，例如，电源电压线13等。
第一屏蔽电极18，具有固定电位，栅极12在衬底10上的正投影位于第一屏蔽电极18和第一基板14在衬底10上的正投影中，即在垂直于图1中纸面方向上，第一基板14仅覆盖部分驱动晶体管的栅极12，驱动晶体管的栅极12从第一基板14中凸出的区域被第一屏蔽电极18覆盖。第一屏蔽电极18的材质可以为钼Mo、铝Al等。
通过上述设计方式，数据线16与驱动晶体管的栅极12之间的侧向耦合电容被栅极12与第一屏蔽电极18之间的耦合电容屏蔽，进而降低数据线16上的电压变化对驱动晶体管的栅极12电压的影响；且由于第一屏蔽电极18具有固定电位，第一屏蔽电极18的固定电位在显示面板工作过程中不容易被耦合发生变化，进而使得驱动晶体管的栅极12电压尽量保持为稳定的波形，串扰现象得到改善。
在一个实施方式中，第一屏蔽电极18和电源电压线13连接，电源电压线13接收恒定的直流电压信号，在显示面板工作过程中该直流电压信号不容易发生变化，进而使得驱动晶体管的栅极12电压尽量保持为稳定的波形，串扰现象得到改善。
在一个应用场景中，请继续参阅图1和图2，第一屏蔽电极18位于第四金属层M4，第四金属层M4位于第三金属层M3和第二金属层M2之间，第四金属层M4与第三金属层M3之间利用绝缘层间隔开，第四金属层M4与第二金属层M2之间利用绝缘层间隔开；第一屏蔽电极18与电源电压线13在衬底10上的正投影具有重合区域(未标示)，第一屏蔽电极18与电源电压线13通过第一连接孔A连接，第一连接孔A在衬底10上的正投影位于该重合区域内。第一连接孔A内可以填充有导电材料，进而使得第一屏蔽电极18与电源电压线13 电连接，第一屏蔽电极18的固定电位为电源电压。上述设计第一屏蔽电极18的方式较为简单，实现过程较为方便。
在另一个应用场景中，请一并参阅图1和图3，图3为图1中显示面板一实施方式的剖面示意图。第一屏蔽电极18a位于第四金属层M4a，第四金属层M4a位于第三金属层M3a远离衬底10a一侧，第一屏蔽电极18a与电源电压线13a在衬底10a上的正投影具有重合区域，第一屏蔽电极18a与电源电压线13a通过第二连接孔B连接，第二连接孔B在衬底10a上的正投影位于该重合区域内。第二连接孔B内可以填充有导电材料，进而使得第一屏蔽电极18a与电源电压线13a电连接，第一屏蔽电极18a的固定电位为电源电压。上述设计第一屏蔽电极18a的方式较为简单，实现过程较为方便。
在另一个实施方式中，请参阅图4-图5，图4为本申请显示面板另一实施方式的平面示意图，图5为图4中显示面板一实施方式的剖面示意图，本实施例与图3中实施例的区别在于，本实施例所提供的显示面板还包括：第一连接线15，位于第三金属层M3b，第一连接线15通过第三连接孔C与栅极12b连接，第一屏蔽电极18b在衬底10b上的正投影还与第一连接线15在衬底10b上的正投影至少部分重合。第一连接线15与栅极12b连接，第一连接线15与栅极12b的电位相同。第一连接线15与数据线16b之间存在侧向耦合电容，数据线16b上的电压变化会耦合到第一连接线15，进而影响到驱动晶体管的栅极12b；此时，通过上述设计方式，数据线16b与第一连接线15之间的侧向耦合电容被第一连接线15与第一屏蔽电极18b之间的耦合电容屏蔽，进而降低数据线16b上的电压变化对第一连接线15的影响，进一步降低对驱动晶体管栅极12b的影响。
在又一个实施方式中，请参阅图6，图6为图4中显示面板另一实施方式的剖面示意图，该实施方式与图5中实施例的区别在于，显示面板还包括半导体层17，该半导体层17可以包括驱动晶体管的源极S、漏极D等，其可位于衬底10c与第一金属层M1c之间，包括第一区域H，第一区域H通过第四连接孔E与第一连接线15c连接；其中，第一屏蔽电极18c在衬底10c上的正投影还与第一区域H在衬底10c上的正投影至少部分重合。第一区域H通过第一连接线15c与栅极12c连接，第一区域H与栅极12c的电位相同。第一区域H与数据线16c或其他信号线之间存在侧向耦合电容，数据线16c或其他信号线上的电压变化会耦合到第一区域H，进而影响到驱动晶体管的栅极12c；此时，通过上述设计方式，数据线16c或其他信号线与第一区域H之间的侧向耦合电容被第一区域 H与第一屏蔽电极18c之间的耦合电容屏蔽，进而降低数据线16c或其他信号线上的电压变化对第一区域H的影响，进一步降低对驱动晶体管栅极12c的影响。
当然，在其他实施方式中，也可通过引入第二屏蔽电极19的方式屏蔽上述实施例中的第一区域H'，请参阅图7，图7为本申请显示面板另一实施方式的剖面示意图，第二屏蔽电极19位于第二金属层M2d，可在图案化第二金属层M2d的时候形成该第二屏蔽电极19。第二屏蔽电极19与电源电压线13d连接，例如，第二屏蔽电极19与电源电压线13d在衬底10d上的正投影具有重合区域，第二屏蔽电极19和电源电压线13d可直接通过连接孔连接，此时第二屏蔽电极19具有固定电位，固定电位为电源电压。第二屏蔽电极19在衬底10d上的正投影与第一区域H'在衬底10d上的正投影至少部分重合。通过上述设计方式，数据线16d或其他信号线与第一区域H'之间的侧向耦合电容被第一区域H'与第二屏蔽电极19之间的耦合电容屏蔽，进而降低数据线16d或其他信号线上的电压变化对第一区域H'的影响，进一步降低对驱动晶体管栅极12d的影响。
在又一个实施方式中，请参阅图8-图9，图8为本申请显示面板又一实施方式的平面示意图，图9为图8中显示面板一实施方式的剖面示意图。第一屏蔽电极18e和参考电压线11e连接，参考电压线11e可以位于第二金属层M2e，参考电压线11e接收恒定的直流电压信号，参考电压线11e上的参考电压不太容易受到显示面板中其他信号线的耦合影响，在显示面板工作过程中不容易发生变化，进而使得驱动晶体管的栅极12e电压尽量保持为稳定的波形，串扰现象得到改善。
在一个应用场景中，第一屏蔽电极18e位于第四金属层M4e，第四金属层M4e位于第三金属层M3e远离衬底10e一侧；显示面板还包括第二连接线20，位于第三金属层M3e，第二连接线20的一端通过第五连接孔F与参考电压线11e连接，第二连接线20的另一端通过第六连接孔G与第一屏蔽电极18e连接。上述设计第一屏蔽电极18e的方式较为简单，实现过程较为方便。
在又一个应用场景中，当显示面板包括与驱动晶体管的栅极12e连接的位于第三金属层M3e的第一连接线15e时，如图9所示，第一屏蔽电极18e在衬底10e上的正投影还可进一步覆盖至少部分第一连接线15e在衬底10e上的正投影。
在又一个应用场景中，当显示面板还包括半导体层17e时，且半导体层17e中的第一区域H″与第一连接线15e连接，如图9所示，第一屏蔽电极18e在衬 底10e上的投影还可进一步覆盖至少部分第一区域H″在衬底10e上的投影。当然，此时也可通过引入如图7中所示的第二屏蔽电极覆盖至少部分第一区域H″。
在又一个实施方式中，请参阅图10，图10为本申请显示面板又一实施方式的平面示意图。为了进一步削弱数据线16f和驱动晶体管的栅极12f之间的耦合电容，上述几种实施例中的第一屏蔽电极18f在衬底(图10中未示)上的正投影还与数据线16f在衬底上的正投影部分重合。
下面以具体的实验数据对本申请所提供的显示面板作进一步说明。
首先，采用软件模拟的方式获得数据线与驱动晶体管的栅极之间的寄生电容。如图1中所示，当显示面板中不包含第一屏蔽电极18时，数据线16与驱动晶体管的栅极12之间耦合的寄生电容为0.045fF；当显示面板中引入第一屏蔽电极18时，数据线16与驱动晶体管的栅极12之间耦合的寄生电容为0.022fF，寄生电容降低了48％。
其次，进行实际串扰指标验证。如图1中所示，当显示面板中不包含第一屏蔽电极18时，串扰达标率为7/15；当显示面板中包含第一屏蔽电极18时，串扰达标率为50/50；可以看出，串扰改善效果明显，测试样本达标率较高。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (12)

  1. 一种显示面板，包括：
    衬底；
    第一金属层，位于所述衬底一侧，包括驱动晶体管的栅极；
    第二金属层，位于所述第一金属层远离所述衬底一侧，包括存储电容的第一基板，所述第一基板在所述衬底上的正投影与所述栅极在所述衬底上的正投影部分重合；
    第三金属层，位于所述第二金属层远离所述衬底一侧，包括数据线，所述数据线在所述衬底上的正投影与所述栅极在所述衬底上的正投影不重合；
    第一屏蔽电极，具有固定电位，所述栅极在所述衬底上的正投影位于所述第一屏蔽电极和所述第一基板在所述衬底上的正投影中。
  2. 根据权利要求1所述的显示面板，其中，
    所述第三金属层还包括电源电压线，所述第一屏蔽电极和所述电源电压线连接。
  3. 根据权利要求2所述的显示面板，其中，
    所述第一屏蔽电极位于第四金属层，所述第四金属层位于所述第三金属层和所述第二金属层之间，所述第一屏蔽电极与所述电源电压线在所述衬底上的正投影具有重合区域，所述第一屏蔽电极与所述电源电压线通过第一连接孔连接。
  4. 根据权利要求2所述的显示面板，其中，所述第一屏蔽电极位于第四金属层，所述第四金属层位于所述第三金属层远离所述衬底一侧，所述第一屏蔽电极与所述电源电压线在所述衬底上的正投影具有重合区域，所述第一屏蔽电极与所述电源电压线通过第二连接孔连接。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    第一连接线，位于所述第三金属层，所述第一连接线通过第三连接孔与所述栅极连接，所述第一屏蔽电极在所述衬底上的正投影还与所述第一连接线在所述衬底上的正投影至少部分重合。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    半导体层，位于所述衬底与所述第一金属层之间，包括第一区域，所述第一区域通过第四连接孔与所述第一连接线连接；
    其中，所述第一屏蔽电极在所述衬底上的正投影还与所述第一区域在所述 衬底上的正投影至少部分重合。
  7. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    半导体层，位于所述衬底与所述第一金属层之间，包括第一区域，所述第一区域通过第四连接孔与所述第一连接线连接；
    第二屏蔽电极，位于所述第二金属层，与所述电源电压线连接，所述第二屏蔽电极在所述衬底上的正投影与所述第一区域在所述衬底上的正投影至少部分重合。
  8. 根据权利要求1所述的显示面板，其中，
    所述第二金属层还包括参考电压线，所述第一屏蔽电极和所述参考电压线连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一屏蔽电极位于第四金属层，所述第四金属层位于所述第三金属层远离所述衬底一侧；
    所述显示面板还包括第二连接线，位于所述第三金属层，所述第二连接线的一端通过第五连接孔与所述参考电压线连接，所述第二连接线的另一端通过第六连接孔与所述第一屏蔽电极连接。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：
    第一连接线，位于所述第三金属层，所述第一连接线通过第三连接孔与所述栅极连接，所述第一屏蔽电极在所述衬底上的正投影还与所述第一连接线在所述衬底上的正投影至少部分重合。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    半导体层，位于所述衬底与所述第一金属层之间，包括第一区域，所述第一区域通过第四连接孔与所述第一连接线连接；
    其中，所述第一屏蔽电极在所述衬底上的正投影还与所述第一区域在所述衬底上的正投影至少部分重合。
  12. 根据权利要求1所述的显示面板，其中，所述第一屏蔽电极在所述衬底上的正投影还与所述数据线在所述衬底上的正投影部分重合。
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