WO2020248318A1 - 一种支持宽频率范围的双向自适应时钟电路 - Google Patents

一种支持宽频率范围的双向自适应时钟电路 Download PDF

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Publication number
WO2020248318A1
WO2020248318A1 PCT/CN2019/095202 CN2019095202W WO2020248318A1 WO 2020248318 A1 WO2020248318 A1 WO 2020248318A1 CN 2019095202 W CN2019095202 W CN 2019095202W WO 2020248318 A1 WO2020248318 A1 WO 2020248318A1
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clock
signal
circuit
delay
adaptive
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PCT/CN2019/095202
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English (en)
French (fr)
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单伟伟
陆旻熠
万亮
时龙兴
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东南大学
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Priority to US16/957,724 priority Critical patent/US11139805B1/en
Publication of WO2020248318A1 publication Critical patent/WO2020248318A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
    • G04F5/10—Apparatus for producing preselected time intervals for use as timing standards using electric or electronic resonators
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

Definitions

  • the invention relates to a bidirectional adaptive clock circuit supporting a wide frequency range, which is realized by digital logic and belongs to the technical field of basic electronic circuits.
  • Adaptive voltage adjustment technology is a very effective technical method to reduce PVT timing margin.
  • a monitoring unit to monitor the timing information of the circuit
  • adaptive voltage adjustment is performed according to the feedback timing information.
  • AVS technology the PVT timing margin can be reduced or even completely eliminated, thereby improving the energy efficiency of the circuit.
  • Razor Take the classic online timing monitoring unit Razor as an example.
  • the circuit is mainly composed of a flip-flop, a high-level transparent latch, an exclusive OR gate and a data selector.
  • the delay length of the data path meets the setup time requirement of the flip-flop, and the value sampled by the flip-flop and the latch is the same; when the timing is wrong, the latch can be correct because it is in the transparent phase at the clock high level
  • the data is sampled, and the trigger cannot sample the correct value because the data arrives too late or the short path problem.
  • the system After detecting the circuit timing error, the system starts to enter the data recovery and error correction phase, and in the next cycle, the correct value sampled by the latch is transmitted to the flip-flop through the data selector to ensure that the system data is correct.
  • the timing situation during the current circuit operation can be obtained.
  • the system can adjust the voltage of the target circuit according to the timing monitoring information fed back by the monitoring unit to realize the energy-efficient design of the chip.
  • the timing margin of the chip is small.
  • the current clock needs to be quickly stretched (ie, frequency down) to improve the timing. margin.
  • the timing margin of the chip can also be reduced by performing a reasonable compression operation on the clock, thereby improving chip performance and reducing power consumption.
  • the currently announced clock stretching methods are mainly clock division, DLL and PLL configuration.
  • the frequency division method can achieve immediate frequency reduction, but the frequency reduction often fails to achieve fine-grained operations.
  • the integer frequency division of the clock makes the chip frequency decrease greatly and the working performance is greatly reduced.
  • Using DLL can generate multiple phase clocks, using the fast deviation detection module to detect whether there is a fast deviation, and then by switching between different phase clocks, using the phase difference between the phase clocks to achieve rapid changes to the clock cycle,
  • the DLL-based method has a long response time, a large power consumption area, and cannot adapt to low frequencies, and has certain limitations.
  • the method of using PLL dynamic configuration can achieve a relatively small range of rapid frequency adjustment, it has high applicable frequency, high design complexity, and low versatility, and is not suitable for low-cost embedded chip applications.
  • the purpose of the present invention is to address the shortcomings of the above-mentioned background technology and provide a bidirectional adaptive clock circuit with faster response time and finer stretch scale, and can adjust the stretch or compression of the clock adaptively according to the current working conditions Therefore, the timing margin can be minimized.
  • the present invention performs fine-grained rapid stretching or compression of the clock under the control signal, achieving low cost, complete circuit structure, and realizing high-precision stretching of clock signals in a wide frequency range Or compressed fine-grained operation solves the technical problem that the existing clock signal circuit needs to sacrifice a certain accuracy cost in exchange for the area cost and the supported frequency adjustment range is narrow.
  • a two-way adaptive clock circuit supporting a wide frequency range includes:
  • the phase clock generation module uses the system clock to generate N clocks with different phases, where N is an integer greater than 1;
  • the phase clock selection module selects a suitable target phase clock output from the system clock and N phase clocks according to the adaptive clock selection control signal, so as to realize the operation of stretching or compressing the system clock in the current period;
  • Adaptive clock stretching or compression adjustment circuit module real-time monitoring of the delay information of the delay unit in the chip, and feedback the information to the control module;
  • the control module generates an adaptive clock selection control signal according to the delay information fed back by the adaptive clock stretch or compression adjustment circuit module.
  • the adaptive clock stretching or compression adjustment circuit module includes:
  • the one-two frequency divider circuit uses the D flip-flop to divide the input adaptive clock clk_out of the module by two to obtain the frequency-divided clock;
  • a copy of the critical path module which is composed of multi-level combinational logic gates in series, used to simulate the critical path delay information
  • a monitoring unit group circuit composed of N/2 monitoring units (Transition Detector, TD) and N/2 high-level transparent latches, used to monitor the delay information of the current circuit and guide the clock stretching or compression Volume selection
  • Select one or two data selector circuit according to whether the circuit timing is tight or not, choose to stretch or compress the current system clock, and control the input signal of the monitoring unit group to be the timing warning signal provided by the online timing monitoring unit or copy the critical path
  • the delay signal of the current circuit is obtained and passed to the control module.
  • the phase clock generation module includes:
  • a dual delay line structure phase clock generation circuit including two delay lines, the first delay line is a fast delay line, the delay is shorter, and supports the generation of high-frequency phase clocks; the second delay line is a slow delay line, which delays The time is longer and supports the generation of low-frequency phase clocks.
  • Each delay line is composed of N/2-stage delay units connected in series, and each stage of delay unit is followed by an inverter to generate an inverted clock signal, generating a total of N clocks with different phases.
  • the dual delay line structure is controlled by an M data selector, and only one delay line works at the same time.
  • the difference between fast and slow delay lines is that the single-stage delay unit uses a different number of basic units. Among them, the number of delay units of the fast delay line is more than that of the slow delay line, so the delay time is smaller.
  • a Time-Digital-Converter (TDC) circuit uses M phase clocks generated by a phase clock generating circuit to detect delay line information, where M is less than or equal to N/2. After the system is powered on, the TDC circuit detects the delay of the fast delay line by default. If the M output values of the TDC circuit contain 0 and 1, the frequency meets the requirements of the fast delay line, and keep using the current fast delay line to generate the phase clock; if the M output values of the TDC circuit only contain 0, the frequency does not meet the fast delay line If required, switch to a slow delay line to generate a phase clock.
  • phase clock selection module includes:
  • a phase clock receiving circuit including N low-level transparent latches and N AND gates, is used to correctly receive the adaptive clock selection control signal from the control module.
  • the N-bit adaptive clock selection control signal is used as the data input signal of the N latches, and the N phase clocks are respectively used as the clock input signal of the N latches, which are synchronized with the corresponding control signal.
  • the N latches The data output signal and its clock input signal are ANDed through the AND gate respectively;
  • An N input OR gate circuit used to select and output the target phase clock clk_out.
  • the two-way adaptive clock circuit disclosed in the present invention can support the adjustment of a wide frequency range.
  • the dual delay line structure is adopted to realize the phase clock generation module to meet the requirements of different frequency ranges.
  • Each delay line has a different minimum unit delay accuracy. Among them, one delay line only works at a higher frequency, while the other delay line only works at a lower frequency.
  • the present invention places the entire adaptive clock circuit in a fixed high voltage domain instead of a variable voltage domain, so as to avoid the effect of rapid deviation caused by low voltage on circuit performance.
  • the bidirectional adaptive clock circuit disclosed in the present invention can adaptively adjust the stretching or compression amount of the clock according to the current working conditions, and has the technical advantages of faster response time and finer stretching scale, and determines the timing stretching or compression
  • the amount of clock stretching or compression required for rapid deviations in different PVT environments is different. When the PVT environment is poor, the amount of clock stretching or compression required is larger. When the environment is better, it is smaller. Therefore, the present invention introduces a clock stretching or compression adjustment circuit, and using TD to monitor the timing of the signal carrying the critical path delay information, the timing stretch suitable for the current PVT environment can be obtained. Or compression. Compared with other traditional clock stretching methods, this method can not only complete the response within one cycle, but also stretch the system clock to a finer degree, ensuring that the chip can resolve circuit timing violations Without too much performance loss.
  • the two-way adaptive clock circuit disclosed by the present invention has a relatively small area and power consumption cost.
  • the present invention realizes the required circuit functions through digital logic.
  • the circuit structure is simplified and the effect is good. It is especially suitable for the adaptation based on online timing monitoring. Voltage frequency adjustment circuit.
  • Figure 1 is a block diagram of a bidirectional adaptive clock circuit supporting a wide frequency range.
  • Figure 2 is a schematic diagram of a bidirectional adaptive clock circuit supporting a wide frequency range.
  • Figure 3 is a timing diagram of the adaptive clock stretching amount selection.
  • Figure 4 is a timing diagram of the adaptive clock stretching principle.
  • Figure 5 shows the sequence diagram of system function verification combined with adaptive clock compression under TT_1.05V_25°C environment.
  • Figure 6 is a waveform diagram of system adaptive clock stretching under the environment of conventional voltage region TT_1.05V_25°C.
  • Figure 7 is the waveform diagram of the system adaptive clock stretching in the low voltage area TT_0.6V_25°C environment.
  • the bidirectional adaptive clock circuit supporting a wide frequency range disclosed in the present invention includes: a phase clock generation module, a phase clock selection module, an adaptive clock stretch or compression amount adjustment circuit module, and a control module.
  • the external input signals of the circuit are: system clock clk, reset signal rst, clock stretching or compression function selection signal mode, and delay line configuration signal config[1:0], and the output signal is the clock clk_out generated after adaptive clock adjustment.
  • the adaptive clock stretching or compression adjustment circuit module monitors the delay information of the delay unit in the chip in real time to detect the current operating environment of the circuit, and feeds the delay information back to the control module.
  • the control module receives the current circuit delay information monitor_wide provided by the adaptive clock stretching or compression adjustment circuit module, and generates the clock selection control signal ctrl[N:1] through the decoding circuit, and the clock selection control signal ctrl[N:1] guides The phase clock selection module selects the target phase clock clk_out from the clocks generated by the phase clock generation module to realize the stretching of the system clock under different PVT environments in a single cycle.
  • the input signal of the phase clock generation module is the system clock clk and the reset signal rst, the output signal is N phase clocks with different phases ⁇ [1]- ⁇ [N], and the phase clock generation module outputs ⁇ [1]- ⁇ [N ] To the input terminal of the phase clock selection module, the phase clock generation module outputs ⁇ [1]- ⁇ [N/2] to the input terminal of the adaptive clock stretching or compression adjustment circuit module; N is an integer greater than 1.
  • the input signals of the control module are: system clock clk, reset signal rst, and current circuit delay information monitor_wide from the adaptive clock stretch or compression adjustment circuit module, and output the N-bit clock selection control signal ctrl[N:1] to The input terminal of the phase clock selection module.
  • the adaptive clock stretch or compression adjustment circuit module uses multiple sets of TD (Transition Detector, monitoring unit) and latches to detect the timing warning signal generated by the online timing monitoring unit at the end of the critical path or copy the key
  • the delay signal generated by the path outputs the delay information monitor_wide of the current circuit.
  • the delay information of the current circuit is presented in the form of a thermometer code.
  • the boundary position of 0 and 1 in the thermometer code is the aforementioned timing warning signal or delay signal The position of the rising edge.
  • monitor_wide By passing monitor_wide to the subsequent control module, and output the clock selection control signal ctrl[N:1], instruct the system to select the appropriate target clock signal from the N phase clocks generated in the phase clock generation module to achieve the current cycle Stretch or compress the system clock in the current PVT environment.
  • the phase clock generation module is composed of two sub-circuits, which are the phase clock generation circuit and the TDC (Time-Digital-Converter) circuit.
  • the phase clock generation circuit adopts a dual delay line structure to generate phase clock signals.
  • the two delay lines are independent of each other and are composed of 20-stage delay units, and the same basic unit CLKBUFV4_7TL140_C30 is cascaded in a single delay unit.
  • the first delay line is a fast delay line with a short delay and supports the generation of a high-frequency phase clock; the second delay line is a slow delay line with a longer delay and supports the generation of a low-frequency phase clock.
  • the difference between the two delay lines is that the single-stage delay unit uses a different number of basic units.
  • the delay unit of the fast delay line is formed by cascading K (for example, 30) buffers, and the slow delay line
  • the delay unit is formed by cascading L (for example, 5) buffers.
  • the system clock clk is used as the initial input signal of the delay chain.
  • Each delay unit will produce a certain phase offset to the system clock.
  • Each delay line is composed of N/2-stage delay units in series.
  • the time unit is followed by an inverter to generate an inverted clock signal, which generates a total of N clocks with different phases.
  • the delay time between adjacent phase clocks is the delay time of 1 delay unit in the current PVT environment. According to the requirement of the system frequency, the dual delay line structure has only one delay line working.
  • the TDC circuit uses the generated M phase clocks to detect the delay line information, and M is less than or equal to N/2. After the system is powered on, the TDC circuit detects the delay of the fast delay line by default. If the M output values of the TDC circuit contain 0 and 1, the frequency meets the requirements of the fast delay line, and keep using the current fast delay line to generate the phase clock; if the M output values of the TDC circuit only contain 0, the frequency does not meet the fast delay line If required, switch to a slow delay line to generate a phase clock.
  • the adaptive clock stretching or compression adjustment circuit module includes: a two-frequency divider circuit, a replication critical path module, a monitoring unit group circuit, and a two-to-one data selector circuit.
  • the divide-by-two circuit uses a D flip-flop to divide the input adaptive clock clk_out to the module by two to obtain the divided clock.
  • the replication critical path module is composed of multi-level combinational logic gates in series, and is used to simulate the critical path delay information.
  • the monitoring unit group circuit adopts the combination of TD and high-level transparent latches to analyze the critical path timing information to obtain the adaptive clock stretch or compression information.
  • the input clock of each TD and latch combination is different Phase clock ⁇ [1]- ⁇ [N/2], the sampling result is a series of thermometer codes, such as 1111_1111_1111_0000_0000, where the junction of 1 and 0 is the position range where the rising edge of the input signal of the monitoring unit group circuit is located.
  • the application scenarios of the clock stretching and compression functions in the overall system are different, that is, when the system timing is tight, the clock needs to be stretched.
  • the online timing monitoring unit can timely monitor the high-level timing warning signal, and the system timing is relatively loose. The clock is compressed, and the online timing monitoring unit cannot effectively obtain the delay information of the critical path at this time. Therefore, an additional copy of the critical path needs to be introduced to describe the delay information of the current system.
  • the above two cases are controlled by a two-to-one data selector circuit.
  • the chip select signal mode of the one-of-two data selector circuit selects the clock stretching or compression function, and controls the input signal of the monitoring unit group according to whether the circuit timing is tight or not, thereby obtaining the current circuit delay information and transmitting it to the control module.
  • the cpr_out signal obtained by the path is input to the monitoring unit group circuit to guide the selection of the amount of clock compression.
  • the current circuit timing default value/timing margin can be obtained.
  • the reason why a high-level transparent latch is introduced in this module to cooperate with TD for monitoring is that the monitoring signal obtained by TD is a positive pulse, and its level width is less than half a period. Therefore, there may be Attenuation, it needs to be widened, and finally the monitor_wide signal is output to the control module.
  • the system continuously switches from the current phase clock to the phase lagging clock according to the monitor_wide signal given by the monitoring unit group circuit to expand the clock cycle and ease the timing tension; for the clock compression function, the system continuously monitors The monitor_wide signal given by the unit group circuit switches from the current phase clock to the phase-leading clock to compress the clock cycle and reduce the timing margin.
  • Figure 3 shows the timing diagram of the adaptive clock stretching amount selection. When the timing is normal, the signal of the critical path should arrive before the next rising edge of clk, but due to the influence of the rapid deviation, it arrives at t1, so the timing warning signal error_all is generated.
  • the critical path length is t1
  • the timing default value is t1-T.
  • the control module is composed of a state machine and a decoder.
  • the state machine controls the entire adaptive clock circuit to switch between stretch, compression and idle states.
  • the decoder circuit generates an N-bit clock selection control signal ctrl[N:1] according to the current circuit timing information monitor_wide of the adaptive clock stretch or compression adjustment circuit module to determine the selected target clock to meet the critical path timing requirements. In each cycle, only one bit of the N-bit clock selection control signal ctrl[N:1] is high, and the rest are low. Among them, the high-level control signal represents the selection of the corresponding phase clock.
  • the phase clock selection module includes a phase clock receiving circuit and an N-input OR circuit.
  • the phase clock receiving circuit includes N low-level transparent latches and N AND gates, which are used to correctly receive the adaptive clock selection control signal ctrl[N:1] from the control module.
  • the N-bit adaptive clock selection control signal is used as the data input signal of the N latches, and the N phase clocks are respectively used as the clock input signal of the N D latches. They are synchronized with the corresponding control signal to avoid the clock A glitch is generated during selection, and the data output signals of the N latches and their clock input signals are ANDed respectively through the AND gate.
  • the N input OR gate circuit is used to select and output the target phase clock clk_out.
  • the present invention uses the output clock clk_out of the adaptive clock circuit as the input clock source instead of the system clock clk. Since the adaptive clock circuit needs to respond to the external timing warning signal, the timing warning signal is synchronized with clk_out and asynchronous with the system clock clk. Therefore, in order to avoid switching the clock to the system clock after each stretching or compression is completed, it may be possible When unnecessary glitch signals are generated, the present invention changes the input clock signal from the system clock clk to clk_out, and the entire adaptive clock circuit and the platform on which it is mounted form a synchronous operation logic.
  • Figure 4 shows the timing diagram of the adaptive clock stretching principle.
  • the operation of clock stretching is to select the required target phase clock according to the different timing information of the monitored critical path, so that the entire system functions correctly and meets the timing requirements.
  • the present invention uses FIG. 4 as an example to specifically illustrate the clock stretching principle, that is, a reasonable stretching operation is performed on the system input clock signal of the previous cycle in each cycle.
  • the initial input system clock is clk.
  • the circuit proposed by the present invention is mounted on an 8-bit AES cryptographic circuit platform to perform adaptive clock stretching or compression function verification.
  • the circuit is tested for functional simulation in different PVT environments.
  • the circuit structure of each module is designed, the circuit is modeled by Verilog HDL language, and the circuit function is simulated and verified.
  • Set the number of delay units N in the two delay lines of the circuit phase clock generation module to 40 (each delay line contains 20 delay units). Put the circuit under different clock frequency conditions and different PVT conditions to simulate, and the simulation results are shown in Figure 5, Figure 6, and Figure 7.
  • Figure 5 shows the waveform diagram of the overall system function verification.
  • the system timing is relatively loose, and the error_all timing warning signal is pulled down. Therefore, the system turns on the adaptive clock compression function to compress the timing margin.
  • the flag_out function signal generated by the 8-bit AES cryptographic circuit platform is pulled high after one encryption is completed, indicating that the system function is correct in combination with the adaptive clock compression function.
  • Figure 6 shows a waveform diagram of adaptive clock stretching of the system in the conventional voltage region.
  • the error_all timing warning signal is generated.
  • the signal is immediately fed back to the adaptive clock stretching circuit, and the clock period is stretched to the clock period of 1.275ns, which effectively alleviates the system's timing tension problem under conventional voltage.
  • Figure 7 shows the waveform diagram of adaptive clock stretching in the low-voltage area.
  • the system clock frequency is 100MHz, that is, the period is 10ns.
  • the error_all timing warning signal is generated. This signal is immediately fed back to the adaptive clock stretching circuit, and the clock is stretched in the current period until the clock period is 10.42ns, which effectively alleviates the timing tension of the system under low voltage.
  • the present invention is particularly suitable for an adaptive voltage and frequency adjustment circuit based on online timing monitoring.
  • a control signal is generated to stretch the clock and increase the timing margin of the circuit, thereby avoiding circuit work errors;
  • the sequence margin is sufficient, the clock is compressed to reduce the timing margin as much as possible, thereby improving circuit performance and reducing power consumption.

Abstract

一种支持宽频率范围的双向自适应时钟电路，属于基本电子电路的技术领域。该电路由相位时钟生成模块、相位时钟选择模块、自适应时钟拉伸或压缩量调节模块以及控制模块组成。自适应时钟拉伸或压缩量调节模块能够实时监测芯片中关键路径的延时信息，并将该信息反馈到控制模块中。控制模块在接收到时钟拉伸或压缩使能信号以及拉伸或压缩尺度信号之后，从相位时钟生成模块产生的时钟中选择目标相位时钟，在当周期内完成对自适应时钟的快速调节。不需要复杂的门器件，结构稳定，功耗面积代价小，受PVT环境的影响较小，电路结构精简，电路实现简单，工作频率宽，响应时间快，适合应用在基于在线时序监测的自适应电压频率调节电路。

Description

一种支持宽频率范围的双向自适应时钟电路 技术领域
本发明涉及一种支持宽频率范围的双向自适应时钟电路，利用数字逻辑实现，属于基本电子电路的技术领域。
背景技术
随着集成电路工艺水平的不断提升，降低功耗成为了与性能提升同等重要的问题，因此，高性能和低功耗便成为了芯片设计质量的重要衡量指标，由于两者的相互制约性，通常使用能效来表征芯片设计质量的优劣，高能效是设计人员在不断努力追求的目标。然而，电路设计在制造过程以及使用环境中都有很大的不确定性，存在着PVT(Process,Voltage,Temperature)偏差，包括工艺偏差、电压波动、温度变化等，对芯片的正常工作有较大的影响。因此，为了确保芯片在复杂的外界环境中都能够正常运行工作，通常在设计电路过程中预留足够的时序余量以保证芯片在“最差情况”中能正常工作。由于这些不利的时序偏差实际上很难同时发生或根本不会发生，预留过多的时序余量显然造成了性能和功耗浪费，因而严重降低了芯片的能效。
自适应电压调节技术是一种十分有效的减少PVT时序余量的技术方法，通过利用监测单元来监测电路的时序信息，根据反馈的时序信息进行自适应电压调节。通过使用AVS技术可以减少甚至完全去除PVT时序余量，从而提升电路的能效。以经典的在线时序监测单元Razor为例，该电路主要由一个触发器、一个高电平透明的锁存器、一个异或门以及一个数据选择器组成。当时序正常时，数据路径延时长度满足触发器的建立时间要求，触发器和锁存器采样的值相同；当时序错误时，锁存器由于其在时钟高电平处于透明阶段，能够正确采样到数据，而触发器则因为数据到达时间太晚或短路径问题而无法采样正确的值。在检测到电路时序出错后，系统开始进入数据恢复纠错阶段，并在下一个周期重新将锁存器采样到的正确的值通过数据选择器传送到触发器，保证系统数据正确。
利用在线时序监测方法，检测片上时序监测单元反映的信息，便可以得到当前电路运行过程中的时序情况。系统可以根据监测单元反馈的时序监测信息对目标电路进行相应的电压调节，以实现芯片的高能效设计。当芯片数据出现错误时， 表明当前电路出现时序违约的情况，此时，芯片的时序余量较小，为了保证芯片工作正常，需要对当前时钟进行快速拉伸操作(即降频)以提高时序余量。当芯片的时序余量较大时，也可以通过对时钟进行合理的压缩操作降低时序余量，提高芯片性能，降低功耗。当前已公布的时钟拉伸方法主要是时钟分频、DLL和PLL配置。分频的方法可以实现立即降频，但是降频往往无法实现细粒度操作，对时钟进行整数倍分频使得芯片频率降低的幅度较大，工作性能大大降低。使用DLL可以产生多个相位时钟，利用快速偏差检测模块来检测是否有快速偏差产生，再通过在不同相位时钟之间进行切换，利用相位时钟之间的相位差以实现对时钟周期的快速改变，但基于DLL的方法响应时间长，功耗面积代价大，无法适应低频，有一定的局限性。此外，使用PLL动态配置的方法虽然可以实现比较小范围的快速频率调节，但适用频率高，设计复杂度高，通用性不强，不适用于低代价的嵌入式芯片应用。
发明内容
本发明的发明目的是针对上述背景技术的不足，提供了一种响应时间更快，拉伸尺度更细的双向自适应时钟电路，并可以根据当前工作条件自适应的调节时钟的拉伸或压缩量，从而可以最大限度的减少时序余量。本发明根据时序监测单元反馈的电路延时信息，在控制信号下对时钟进行细粒度的快速拉伸或压缩操作，实现代价小，电路结构完善，实现了宽频率范围内时钟信号高精度拉伸或压缩的细粒度操作，解决了现有时钟信号电路需要牺牲一定的精度代价来换取面积代价且支持的频率调节范围较窄的技术问题。
本发明为实现上述发明目的采用如下技术方案：
一种支持宽频率范围的双向自适应时钟电路包括：
相位时钟生成模块，利用系统时钟产生N个相位互不相同的时钟，N为大于1的整数；
相位时钟选择模块，根据自适应时钟选择控制信号，从系统时钟及N个相位时钟中选择合适的目标相位时钟输出，实现在当周期内对系统时钟进行拉伸或压缩的操作；
自适应时钟拉伸或压缩量调节电路模块，实时监测芯片中延时单元的延时信息，并将该信息反馈到控制模块；
控制模块，根据自适应时钟拉伸或压缩量调节电路模块反馈的延时信息，产生自适应时钟选择控制信号。
优选地，所述自适应时钟拉伸或压缩量调节电路模块包括：
一二分频电路，利用D触发器对该模块输入自适应时钟clk_out进行二分频，得到分频时钟；
一复制关键路径模块，由多级组合逻辑门串联而成，用于模拟关键路径延时信息；
一监测单元组电路，由N/2个监测单元(Transition Detector,TD)和N/2个高电平透明的锁存器组成，用于监测当前电路的延时信息，指导时钟拉伸或压缩量的选择；
一二选一数据选择器电路，根据电路时序紧张与否，选择对当前系统时钟进行拉伸或压缩，控制所述监测单元组的输入信号为在线时序监测单元提供的时序预警信号或者复制关键路径的延时信号，由此获得当前电路延时信息并传递给控制模块。
优选地，所述相位时钟生成模块包括：
一双延迟线结构相位时钟产生电路，包含两条延迟线，第一条延迟线为快速延迟线，延时较短，支持产生高频的相位时钟；第二条延迟线为慢速延迟线，延时较长，支持产生低频的相位时钟。每一条延迟线由N/2级延时单元串联而成，每一级延时单元后接一级反相器产生反相时钟信号，共产生N个相位互不相同的时钟。所述的双延迟线结构由二选一M数据选择器控制，同一时刻只有一条延迟线工作。快速和慢速延迟线的区别在于单级延时单元使用了不同数量的基本单元。其中，快速延迟线的延时单元的数量比慢速延迟线的延时单元多，因此其延迟时间更小。
一时间数字转换器(Time-Digital-Converter,TDC)电路，利用相位时钟产生电路产生的M个相位时钟检测延迟线信息，M小于等于N/2，。系统上电后，该TDC电路默认检测快速延迟线的延时情况。若TDC电路的M个输出值包含0和1，即频率符合快速延迟线要求，保持使用当前快速延迟线产生相位时钟；若TDC电路的M个输出值仅包含0，即频率不符合快速延迟线要求，则切换到慢速延迟线产生相位时钟。
另一优选地，所述相位时钟选择模块包括：
一相位时钟接收电路，包含N个低电平透明的锁存器和N个与门，用于正确地接收来自所述控制模块的自适应时钟选择控制信号。N位自适应时钟选择控制信号分别作为N个锁存器的数据输入信号，N个相位时钟分别作为N个锁存器的时钟输入信号，与对应的控制信号进行同步处理，N个锁存器的数据输出信号与其时钟输入信号分别通过与门进行与操作；
一N输入或门电路，用于选择并输出目标相位时钟clk_out。
本发明采用上述技术方案，具有以下有益效果：
(1)本发明公开的双向自适应时钟电路能够支持宽频率范围的调节，采用双延迟线结构实现相位时钟生成模块可以适应不同频率范围的要求，每条延迟线具有不同的最小单位延时精度，其中，一条延迟线只在较高的频率下工作，而另一条延迟线则只在较低频率下工作，再结合TDC电路判断延迟线延时信息，根据系统需要切换合适的延迟线产生相位时钟，为使得相位时钟稳定，本发明将整个自适应时钟电路置于固定的高电压域中而非可变电压域，以避免低电压带来的快速偏差对电路性能的影响。
(2)本发明公开的双向自适应时钟电路可根据当前工作条件自适应的调节时钟的拉伸或压缩量，具有响应时间更快、拉伸尺度更细的技术优势，确定时序拉伸或压缩量是本发明的一大难点，在不同PVT环境下发生快速偏差时所需的时钟拉伸或压缩量是不同的，在PVT环境较差时所需时钟拉伸或压缩量较大而在PVT环境较好时则较小，所以，本发明引入了时钟拉伸或压缩量调节电路，利用TD对携带关键路径延时信息的信号进行时序监测，即可得到当前PVT环境所适合的时序拉伸或压缩量，该方法相对于传统的其它时钟拉伸方法，不仅能在一个周期内完成响应，而且能够做到对系统时钟较为精细程度的拉伸，保证芯片能在解决电路时序违约的情况下而不会有太大的性能损失。
(3)本发明公开的双向自适应时钟电路面积和功耗代价较小，本发明通过数字逻辑实现所需的电路功能，电路结构精简，效果良好，尤其适合用于基于在线时序监测的自适应电压频率调节电路。
附图说明
图1为支持宽频率范围的双向自适应时钟电路的框图。
图2为支持宽频率范围的双向自适应时钟电路的原理图。
图3为自适应时钟拉伸量选择的时序图。
图4为自适应时钟拉伸原理的时序图。
图5为TT_1.05V_25℃环境下结合自适应时钟压缩的系统功能验证时序图。
图6为常规电压区TT_1.05V_25℃环境下系统自适应时钟拉伸的波形图。
图7为低电压区TT_0.6V_25℃环境下系统自适应时钟拉伸的波形图。
具体实施方式
下面结合附图对发明的技术方案进行详细说明。
如图1所示，本发明公开的支持宽频率范围的双向自适应时钟电路包括：相位时钟生成模块、相位时钟选择模块、自适应时钟拉伸或压缩量调节电路模块以及控制模块。该电路的外部输入信号为：系统时钟clk、复位信号rst、时钟拉伸或压缩功能选择信号mode以及延迟线配置信号config[1:0]，输出信号为自适应时钟调节之后产生的时钟clk_out。自适应时钟拉伸或压缩量调节电路模块实时监测芯片中延时单元的延时信息以检测当前电路的运行环境，并将该延时信息反馈到控制模块中。控制模块接收自适应时钟拉伸或压缩量调节电路模块提供的当前电路延时信息monitor_wide，通过译码电路产生时钟选择控制信号ctrl[N:1]，时钟选择控制信号ctrl[N:1]指导相位时钟选择模块从相位时钟生成模块产生的时钟中选择目标相位时钟clk_out，实现在单周期内对不同PVT环境下系统时钟的拉伸。
相位时钟生成模块的输入信号为系统时钟clk以及复位信号rst，输出信号为N个具有不同相位的相位时钟Φ[1]-Φ[N]，相位时钟生成模块输出Φ[1]-Φ[N]到相位时钟选择模块的输入端，相位时钟生成模块输出Φ[1]-Φ[N/2]到自适应时钟拉伸或压缩量调节电路模块的输入端；N为大于1的整数。
自适应时钟拉伸或压缩量调节电路模块的输入信号为：系统时钟clk、复位信号rst、相位时钟Φ[i](i＝1，2…N/2)以及时钟拉伸或压缩功能选择信号mode，输出当前电路延时信息monitor_wide到控制模块的输入端。
控制模块的输入信号为：系统时钟clk、复位信号rst以及来自自适应时钟拉伸或压缩量调节电路模块的当前电路延时信息monitor_wide，输出N位的时钟选择控制信号ctrl[N:1]到相位时钟选择模块的输入端。
相位时钟选择模块的输入信号为：系统时钟clk、复位信号rst、相位时钟Φ[i](i＝1，2…N)以及来自控制模块的控制信号ctrl[N:1]，输出经过拉伸或压缩的时钟clk_out。
如图2所示，自适应时钟拉伸或压缩量调节电路模块是利用多组TD(Transition Detector,监测单元)和锁存器检测关键路径末端的在线时序监测单元产生的时序预警信号或者复制关键路径产生的延时信号，输出当前电路的延时信息monitor_wide，当前电路的延时信息以温度计码的形式呈现，温度计码中0和1的交界位置即为前面所述时序预警信号或延时信号的上升沿所在位置。通过将monitor_wide传递给后续的控制模块中，输出时钟选择控制信号ctrl[N:1]，指导系统从相位时钟生成模块中产生的N个相位时钟中选择合适的目标时钟信号，实现在当前周期内对当前PVT环境下的系统时钟进行拉伸或压缩。
相位时钟生成模块由两个子电路组成，分别是相位时钟产生电路以及TDC(Time-Digital-Converter,时间数字转换器)电路。相位时钟产生电路采用双延迟线结构产生相位时钟信号，两条延迟线相互独立，均由20级延时单元组成，且单个延时单元中均采用相同的基本单元CLKBUFV4_7TL140_C30级联而成。第一条延迟线为快速延迟线，延时较短，支持产生高频的相位时钟；第二条延迟线为慢速延迟线，延时较长，支持产生低频的相位时钟。两条延迟线的构成区别在于单级延时单元使用了不同数量的基本单元，其中，快速延迟线的延时单元由K个(例如30个)缓冲器级联而成，慢速延迟线的延时单元由L个(例如5个)缓冲器级联而成。以系统时钟clk作为延时链的初始输入信号，每一级延时单元对系统时钟将产生一定的相位偏移，每一条延迟线由N/2级延时单元串联而成，每一级延时单元后接一级反相器产生反相时钟信号，共产生N个相位互不相同的时钟。对于每一条延迟线上产生的相位时钟，相邻相位时钟之间的延迟时间即为在当前PVT环境下的1个延时单元的延迟时间。该双延迟线结构根据系统频率的需要，同时只有一条延迟线工作。TDC电路利用产生的M个相位时钟检测延迟线信息，M小于等于N/2。系统上电后，该TDC电路默认检测快速延迟线的延时情况。若TDC电路的M个输出值包含0和1，即频率符合快速延迟线要求，保持使用当前快速延迟线产生相位时钟；若TDC电路的M个输出值仅包含0，即频率不符合快速延迟线要求，则切换到慢速延迟线产生相位时钟。
自适应时钟拉伸或压缩量调节电路模块包括：二分频电路、复制关键路径模块、监测单元组电路以及一个二选一数据选择器电路。二分频电路利用D触发器对该模块输入自适应时钟clk_out进行二分频得到分频时钟。复制关键路径模块由多级组合逻辑门串联而成，用于模拟关键路径延时信息。监测单元组电路采用TD和高电平透明的锁存器组合的方式，对关键路径时序信息进行分析得到自适应时钟拉伸或压缩量信息，每个TD和锁存器组合的输入时钟为不同的相位时钟Φ[1]-Φ[N/2]，则采样结果为一串温度计码，例如1111_1111_1111_0000_0000，其中，1和0交界处为监测单元组电路输入信号上升沿所在的位置范围。时钟拉伸和压缩功能在整体系统中的应用场景不同，即系统时序紧张时需要对时钟进行拉伸操作，在线时序监测单元可以及时监测到高电平时序预警信号，系统时序相对宽松时需要对时钟进行压缩操作，在线时序监测单元无法有效获取此时关键路径的延时信息。因此，需要额外引入一条复制的关键路径来描述当前系统的延时信息。以上两种情况由一个二选一数据选择器电路控制。该二选一数据选择器电路的片选信号mode选择时钟拉伸或压缩功能，根据电路时序紧张与否，控制监测单元组的输入信号，由此获得当前电路延时信息并传递给控制模块。当mode＝0时，选择error_all信号输入监测单元组电路，error_all信号为时钟拉伸搭载的系统发出的时序预警信号，用来指导时钟拉伸量的选择；当mode＝1时，选择通过复制关键路径得到的cpr_out信号输入监测单元组电路，用来指导时钟压缩量的选择。通过TD监测error_all或者cpr_out信号跳变沿距离Φ[1]-Φ[N]上升沿的位置，便可以得到当前电路时序违约值/时序余量。本模块中引入高电平透明的锁存器配合TD进行监测的原因在于：TD得到的监控信号是一个正脉冲，其电平宽度小于半个周期，因此，可能在后续的信号传输下会有衰减，需要将其展宽，最终得到monitor_wide信号输出到控制模块。
对于时钟拉伸功能，系统持续不断地根据监测单元组电路给出的monitor_wide信号从当前相位时钟切换到相位滞后的时钟以展宽时钟周期，缓解时序紧张；对于时钟压缩功能，系统持续不断地根据监测单元组电路给出的monitor_wide信号从当前相位时钟切换到相位超前的时钟以压缩时钟周期，减少时序余量。以下以时钟拉伸功能为例说明自适应时钟拉伸量选择的功能。图3所示的是自适应时钟拉伸量选择时序图。在时序正常时关键路径的信号本应该在 clk的下一个上升沿之前到达，然而由于快速偏差的影响导致其在t1时刻才到达，因此，产生时序预警信号error_all。由此可知关键路径长度为t1，时序违约值为t1-T。相位时钟Φi与系统时钟clk之间的延时差为△T*i(i＝1，2，…N/2，ΔT为两个相位时钟之间的延迟)，因此，最终选择的目标相位时钟Φi应满足如下条件：
△T*(i-1)<t1<△T*i，
即若error_all信号的跳变发生在第i-1和第i个TD的监测窗口之间，那么通过将当前相位时钟拉伸△T*i，即从当前相位时钟切换到第i个相位时钟，则能涵盖关键路径的延时，因此该拉伸量是合理的。
控制模块由状态机以及译码器组成。状态机控制整个自适应时钟电路在拉伸、压缩和空闲状态之间切换。译码器电路根据自适应时钟拉伸或压缩量调节电路模块的当前电路时序信息monitor_wide产生N位时钟选择控制信号ctrl[N:1]，判断选择的目标时钟，以满足关键路径时序的需要。在每个周期内，N位时钟选择控制信号ctrl[N:1]只有一位为高电平，其余为低电平，其中，电平为高的控制信号代表选择对应的相位时钟。
相位时钟选择模块包括一相位时钟接收电路以及一N输入或门电路。相位时钟接收电路包含N个低电平透明的锁存器和N个与门，用于正确地接收来自控制模块的自适应时钟选择控制信号ctrl[N:1]。N位自适应时钟选择控制信号分别作为N个锁存器的数据输入信号，N个相位时钟分别作为N个D锁存器的时钟输入信号，与对应的控制信号进行同步处理，以避免在时钟选择时产生毛刺，N个锁存器的数据输出信号与其时钟输入信号分别通过与门进行与操作。N输入或门电路用于选择并输出目标相位时钟clk_out。
为了能让整个系统的时钟能够进行连续的拉伸或压缩，本发明将自适应时钟电路的输出时钟clk_out作为输入的时钟源，而非系统时钟clk。由于自适应时钟电路需要响应外界时序预警信号，该时序预警信号与clk_out为同步关系而与系统时钟clk为异步关系，因此，为避免每次拉伸或压缩完成后将时钟切换为系统时钟并可能产生不必要的毛刺信号，本发明将输入时钟信号由系统时钟clk改为clk_out，整个自适应时钟电路与其搭载平台构成一个同步操作的逻辑。
图4所示为自适应时钟拉伸原理时序图。时钟拉伸的操作就是根据监测关键路径时序信息的不同，选择所需的目标相位时钟，使得整个系统功能正确，满足 时序要求。本发明以图4为例具体说明时钟拉伸原理，即每个周期内对上一周期的系统输入时钟信号进行合理的拉伸操作。初始输入的系统时钟为clk，第一个周期内，系统关键路径末端的TD监测得到时序预警信号error_all反馈给监测单元组电路(TD+锁存器)生成monitor_wide信号传递给控制模块产生时钟选择控制信号ctrl[N:1]，其中，ctrl[1]＝1，ctrl[N:2]＝0，则系统选择相位时钟Φ1为目标时钟进行拉伸，即下一周期的上升沿为相位时钟Φ1的上升沿位置；第二个周期内，同样地，产生的时钟选择控制信号中ctrl[4]＝1，其余位全为0，则系统选择相位时钟Φ4为目标时钟进行拉伸，即下一周期的上升沿为相位时钟Φ4的上升沿位置。整个系统按照此规则完成时钟拉伸，时钟压缩的原理类似。
在本发明的支持宽频率范围的双向自适应时钟电路的一个具体实施案例中，将本发明提出的电路搭载在8比特AES密码电路平台上进行自适应时钟拉伸或压缩功能验证。采用SMIC提供的28nm工艺库，利用Synopsys公司提供的VCS和HSIM等软件仿真平台，在不同PVT环境下对该电路进行功能仿真测试。基于上述技术方案设计各个模块的电路结构，利用Verilog HDL语言对电路进行建模，对其电路功能进行仿真验证。设定电路相位时钟生成模块两条延迟线中延时单元数目N为40(每条延迟线包含20个延时单元)。分别将电路置于不同时钟频率条件及不同PVT条件下进行仿真，得到仿真结果如图5、图6、图7所示。
图5所示的是整体系统功能验证的波形图。设置系统当前所处PVT环境为TT工艺角，1.05V以及25℃，系统时钟频率为710MHz，即时钟周期约为1.4ns。此时系统时序比较宽松，error_all时序预警信号拉低，因此，系统开启自适应时钟压缩功能，压缩了时序余量。同时，8比特AES密码电路平台产生的flag_out功能信号在完成一次加密后拉高，表明系统功能在结合自适应时钟压缩功能的情况下正确。
图6所示的是常规电压区下系统实现自适应时钟拉伸的波形图。设置系统当前所处PVT环境为TT工艺角，1.05V以及25℃，系统时钟频率为830MHz，即周期约为1.2ns。当系统时序比较紧张时，产生error_all时序预警信号。该信号立即反馈给自适应时钟拉伸电路，并在当周期拉伸时钟至时钟周期为1.275ns，有效缓解了常规电压下系统的时序紧张问题。
图7所示的是低电压区下系统实现自适应时钟拉伸的波形图。设置系统当前所处PVT环境为TT工艺角，0.6V以及25℃，系统时钟频率为100MHz，即周期为10ns。当系统时序比较紧张时，产生error_all时序预警信号。该信号立即反馈给自适应时钟拉伸电路，并在当周期拉伸时钟至时钟周期为10.42ns，有效缓解了低电压下系统的时序紧张问题。
可见，本发明尤其适合用于基于在线时序监测的自适应电压频率调节电路，当电路运行出现时序违约时，则产生控制信号使时钟拉伸，增加电路时序余量，从而避免电路工作出错；当时序余量比较充足时，则使时钟压缩，尽可能降低时序余量，从而提升电路性能，降低功耗。
以上结果显示了本发明能够在当前周期内迅速实现时钟拉伸或压缩的功能，整体系统功能正确，使用的自适应时钟电路结构简单，精度较好，误差较小。

Claims (8)

  1. 一种支持宽频率范围的双向自适应时钟电路，其特征在于，包括：
    相位时钟生成模块，其输入端接系统时钟，产生N个相位互不相同的延时时钟信号，N为大于1的整数，
    自适应时钟拉伸或压缩量调节电路模块，其输入端接收芯片发出的时序预警信号或芯片关键路径的延时信息，并接收相位时钟生产模块输出的N个相位互不相同的延时时钟信号，实时监测芯片的时序余量或时序违约值，根据N个相位互不相同的延时时钟信号对芯片的时序余量展宽后输出拉伸尺度信号，或者，根据N个相位互不相同的延时时钟信号对时序违约值展宽后输出压缩尺度信号，控制模块，其输入端接收自适应时钟拉伸或压缩量调节电路模块输出的拉伸或压缩尺度信号，产生自适应时钟选择控制信号，及，
    相位时钟选择模块，其输入端接收自适应时钟选择控制信号和N个相位互不相同的延时时钟信号，从N个相位互不相同的延时时钟信号中选择目标相位时钟信号输出。
  2. 根据权利要求1所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，所述相位时钟生成模块包括：
    双延迟线结构的相位时钟产生电路，包含一条快速延迟线和一条慢速延迟线，每一条延迟线均由N/2级延时单元串联而成，每一级延时单元后接一级反相器产生反相时钟信号，各条延迟线上同一级延时单元输出信号经反相处理后输入至与门器件经过与运算得到当前一级延时单元产生的时钟信号φ[1]-φ[N/2]，各条延迟线上同一级延时单元输出信号经反相处理后输入至或门器件经过或运算得到当前一级延时单元产生的反向时钟信号φ[N/2+1]-φ[N]，共产生N个相位互不相同的延时时钟信号，两条延迟线的首端均接有以系统时钟信号和电源信号为输入信号的二选一数据选择器，两个二选一数据选择器的地址信号输入端接同一时刻只有一条延迟线工作的配置信号，及，
    时间数字转换器电路，包含M个检测延迟线信息的D触发器，M个D触发器均以系统时钟信号为时钟输入，M个D触发器的输入端分别接同一条延迟线产生的M个时钟信号，在当前系统时钟频率符合快速延迟线要求时向两条延迟线的首端的二选一数据选择器输入快速延迟线工作而慢速延迟线不工作的配置 信号，在当前系统时钟频率符合慢速延迟线要求时向两条延迟线的首端的二选一数据选择器输入慢速延迟线工作而快速延迟线不工作的配置信号，M小于或等于N/2。
  3. 根据权利要求1所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，所述相位时钟选择模块包括：
    相位时钟接收电路，用于正确地接收来自所述控制模块的自适应时钟选择控制信号，包含N个低电平透明的锁存器和N个与门，N个低电平透明的锁存器的数据输入端均接自适应时钟选择控制信号，N个低电平透明的锁存器的时钟输入端分别接相位时钟生成模块产生的一个时钟信号，一个低电平透明的锁存器的时钟输入端接入的时钟信号以及其输出信号为一个与门的输入信号，及，
    N输入或门电路，其输入端接N个与门的输出端，从N个相位互不相同的延时时钟信号中选择目标相位时钟信号输出。
  4. 根据权利要求1所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，所述自适应时钟拉伸或压缩量调节电路模块包括：
    二分频电路，其输入端接时钟信号，对接入的时钟信号进行二分频得到分频时钟信号，
    由多级组合逻辑门串联而成的复制关键路径模块，其输入端接二分频电路的输出端，输出关键路径的延时信息，
    二选一数据选择器电路，其数据输入端接在线时序监测单元提供的时序预警信号以及复制关键路径模块输出的关键路径延时信息，其地址输入端接时钟拉伸或压缩功能选择信号，及，
    监测单元组电路，由N/2个监测单元和N/2个高电平透明的锁存器组成，各监测单元的输入端均接二选一数据选择器电路的输出端，每个监测单元的输出端接一个高电平透明的锁存器的数据输入端，串接在监测单元输出端的高电平透明的锁存器与该监测单元同时接相位时钟生成模块产生的一个延时时钟信号，各高电平透明的锁存器的输出信号构成指导时钟拉伸或压缩量选择的拉伸或压缩尺度信号。
  5. 根据权利要求1所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，所述控制模块包括：
    状态机电路，其输入端接电路当前的时序信息，输出切换系统处于时钟拉伸、保持或压缩状态的控制指令，及，
    译码器电路，其输入端接自适应时钟拉伸或压缩量调节电路模块输出的拉伸或压缩尺度信号，输出自适应时钟选择控制信号。
  6. 根据权利要求4所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，二分频电路输入端接入的时钟信号为相位时钟选择模块输出的目标相位时钟信号。
  7. 根据权利要求2所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于，每条延迟线上延时单元个数的确定原则为：在各PVT条件下进行仿真，单条延迟线的最后一级相位时钟与系统时钟相位差接近π，两条延迟线的频率范围有交集且能够适应宽频率工作。
  8. 根据权利要求4所述的一种支持宽频率范围的双向自适应时钟电路，其特征在于：所述监测单元以时钟高电平为时序监测窗口，在系统关键路径插入并进行时序监测，在系统时序比较紧张时快速产生时序预警信号。
PCT/CN2019/095202 2019-06-14 2019-07-09 一种支持宽频率范围的双向自适应时钟电路 WO2020248318A1 (zh)

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