WO2020239102A1 - 一种接收电路、接收电路的重构方法及电子设备 - Google Patents

一种接收电路、接收电路的重构方法及电子设备 Download PDF

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Publication number
WO2020239102A1
WO2020239102A1 PCT/CN2020/093449 CN2020093449W WO2020239102A1 WO 2020239102 A1 WO2020239102 A1 WO 2020239102A1 CN 2020093449 W CN2020093449 W CN 2020093449W WO 2020239102 A1 WO2020239102 A1 WO 2020239102A1
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Prior art keywords
data
receiving
module
speed data
speed
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PCT/CN2020/093449
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English (en)
French (fr)
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刘应
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深圳市紫光同创电子有限公司
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Priority to KR1020207031572A priority Critical patent/KR102427873B1/ko
Publication of WO2020239102A1 publication Critical patent/WO2020239102A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Definitions

  • This application relates to the technical field of high-speed serial buses, and in particular to a receiving circuit, a method for reconstructing a receiving circuit, and an electronic device.
  • DPHY is one of the MIPI protocols. DPHY provides the definition of DSI (Serial Display Interface) and CSI (Serial Camera Interface) on the physical layer. DPHY describes a source-synchronous, high-speed, and low-power physical layer.
  • DSI Serial Display Interface
  • CSI Serial Camera Interface
  • DPHY describes a source-synchronous, high-speed, and low-power physical layer.
  • Existing MIPI D-PHY circuits are all implemented by ASIC dedicated circuits. As MIPI D-PHY interfaces are more and more widely used in the mobile industry, the existing MIPI D-PHY circuit implementation methods cannot flexibly configure application modes.
  • the dedicated MIPI D-PHY circuit cannot meet the needs of different application scenarios, and has higher requirements for the diversity of MIPI D-PHY support modes; at the same time, because the general MIPI D-PHY circuit and the protocol (CSI2/DSI) circuit are independent, Both MIPI D-PHY and MIPI protocol layers need to receive and unpack the circuit, and there are problems of duplication of some functions and waste of resources.
  • CSI2/DSI protocol
  • MIPI D-PHY circuit that can be flexibly configured to meet the needs of different application scenarios can reduce the duplication of functions and resource waste of MIPI D-PHY and MIPI protocol layers, which is of great significance to MIPI D-PHY circuits.
  • the purpose of the embodiments of this application is to provide a receiving circuit, a method for reconstructing the receiving circuit, and an electronic device, aiming to solve the problem that the existing MIPI D-PHY circuit cannot be flexibly configured, and the MIPI D-PHY and MIPI protocol layers have partial functional duplication The problem with waste of resources.
  • an embodiment of the present application provides a MIPI D-PHY receiving circuit, and the MIPI D-PHY receiving circuit includes:
  • the receiving data module is used to reconstruct the configuration data channel according to the user, and process the received high-speed data or low-speed data to obtain the output data required by the configuration protocol;
  • the receiving clock module is used to recover the high-speed clock and the byte clock when the receiving data module receives high-speed data in the high-speed data receiving mode, so as to realize synchronous sampling and serial-to-parallel conversion of the receiving data module;
  • the mode control module is used to control the receiving data module and the receiving clock module to switch between the high-speed data receiving mode and the low-speed data receiving mode.
  • the receiving data module includes:
  • At least one data channel used to receive high-speed data or low-speed data, and adopt the high-speed data receiving mode or the low-speed data receiving mode according to the data type of the received data;
  • Word alignment circuit module for word alignment of received high-speed data
  • the protocol analysis circuit module is used to configure the protocol analysis mode, and obtain the output data of the corresponding configuration protocol according to the configuration protocol mode.
  • the data channel includes: a data switching detection circuit module and a data receiving mode switching circuit module;
  • the data switching detection circuit module sends a corresponding data switching signal to the mode control module when detecting that the received data is switched from high-speed data to low-speed data, or from low-speed data to high-speed data;
  • the data switching detection circuit module and the data receiving mode switching circuit module both include triggers; the data receiving mode switching circuit module also includes a deserialization module for converting 8-bit or 4-bit parallel data.
  • the data switching detection circuit module includes a buffer
  • the buffer is used to detect the switching of the data state from high speed to low speed or from low speed to high speed.
  • the mode control module After the mode control module receives the switching data signal, it inputs the control signal to the differential signal buffer in the data switching detection circuit module.
  • the output data includes: byte clock, travel synchronization, field synchronization, data, data valid flag, CSI2/DSI data packet header, and packet header valid flag.
  • the MIPI D-PHY receiving circuit further includes a second multiple selection selector, and the second multiple selection selector is provided between the channel alignment circuit module and the protocol analysis circuit module;
  • the second multiple selection selector is used to determine whether to use channel-aligned deserialization high-speed data.
  • the protocol analysis circuit module sets the protocol analysis mode according to a configuration instruction for reconstructing and configuring the protocol analysis mode.
  • the receiving clock module includes: a clock data switching detection circuit module and a data frequency dividing circuit module;
  • the data frequency dividing circuit module switches to the corresponding high-speed data receiving mode or low-speed data receiving mode after receiving the high-speed data receiving mode or low-speed data receiving mode control signal sent by the mode control module.
  • the clock data switching detection circuit module and the data frequency dividing circuit module both include triggers; the data frequency dividing circuit module also includes a frequency dividing circuit module, and the frequency dividing circuit module supports a configurable divide by 4 and Divide 2 mode.
  • each data channel is correspondingly provided with one word alignment circuit module.
  • each data channel is used for reconstruction according to user configuration.
  • the present application also provides a method for reconstructing a MIPI D-PHY receiving circuit, and the method for reconstructing a MIPI D-PHY receiving circuit includes:
  • the receiving data module processes the received high-speed data or low-speed data, obtains output data required by the configuration protocol, and outputs the output data.
  • the reconstruction parameters include: the target data channel in the reconstructed data channel, the deserialization ratio of the deserialization module in the reconstructed target data channel, and the divide by 4 and divide by 2 modes of the frequency divider circuit in the reconstructed receiving clock module And the configuration protocol mode in the reconfiguration protocol analysis circuit module, said obtaining the reconfiguration parameters configured by the user includes:
  • the determining that the target data channel adopts a high-speed data receiving mode or a low-speed data receiving mode according to the data type received by the mode control module includes:
  • the data switching detection circuit module in the target data channel When the received data is high-speed data, the data switching detection circuit module in the target data channel outputs a low level signal to the mode control module, and the mode control module outputs a high level control to the data receiving mode switching circuit module in the target data channel Signal, the data receiving mode switching circuit module receives the high-level control signal to switch the data receiving mode to the high-speed data receiving mode;
  • the data switching detection circuit module in the target data channel When the received data is low-speed data, the data switching detection circuit module in the target data channel outputs a high-level signal to the mode control module, and the mode control module outputs low-level control to the data receiving mode switching circuit module in the target data channel Signal, the data receiving mode switching circuit module receives the low-level control signal to switch the data receiving mode to a low-speed data receiving mode.
  • the output data includes: byte clock, travel synchronization, field synchronization, data, data valid flag, CSI2/DSI data packet header and packet header valid flag, and the receiving data module processes the received high-speed data or low-speed data To obtain the output data required by the configuration protocol, and output the output data, including:
  • the received high-speed data is synchronized, and the synchronized data is analyzed by protocol, and then converted into low-speed parallel data;
  • the received low-speed data is subjected to protocol analysis to obtain the output data required by the configuration protocol, and the output data is output.
  • the receiving data module includes: a data switching detection circuit module and a data receiving mode switching circuit module;
  • the data switching detection circuit module sends a corresponding data switching signal to the mode control module when detecting that the received data is switched from high-speed data to low-speed data, or from low-speed data to high-speed data;
  • this application proposes an electronic device including the aforementioned MIPI D-PHY receiving circuit.
  • the embodiments of the present application provide a receiving circuit, a method for reconstructing the receiving circuit, and an electronic device.
  • the receiving circuit is a MIPI D-PHY receiving circuit, which includes: a receiving data module, configured to reconstruct and configure a data channel according to a user, and Process the received high-speed data or low-speed data to obtain the output data required by the configuration protocol; the receiving clock module is used to restore the high-speed data serial clock and byte clock; the mode control module is used to control the receiving data module and the receiving clock module Switch between high-speed data reception mode and low-speed data reception mode.
  • the receiving data module configures the data channel according to the user's reconstruction configuration, and at the same time performs data processing on the received high-speed data or low-speed data to obtain the output required by the configuration protocol Data, realizes the reconfiguration configuration of MIPI D-PHY receiving circuit and the integration of MIPI D-PHY and MIPI protocol layer, avoiding duplication of functions and waste of resources.
  • FIG. 2 is a schematic diagram of the circuit structure of a data channel (DPHY_IO) provided by another embodiment of the application;
  • FIG. 3 is a schematic diagram of a circuit structure of a receiving clock module (DPHY_CLK) provided by another embodiment of the application;
  • FIG. 4 is a schematic flowchart of a method for reconstructing a MIPI D-PHY receiving circuit according to an embodiment of the application
  • FIG. 5 is a schematic diagram of the working state of the protocol analysis circuit module state machine system provided by an embodiment of the application.
  • Fig. 6 is a structural block diagram of an electronic device provided by an embodiment of the application.
  • the MIPI D-PHY receiving circuit 100 includes: a receiving data module 110 for configuring a data channel according to user reconstruction and The received high-speed data or low-speed data is processed to obtain the output data required by the configuration protocol; the receiving clock module 120 is used for recovering the high-speed clock and byte clock when the receiving data module receives high-speed data in the high-speed data receiving mode The synchronous sampling and serial-parallel conversion of the receiving data module 110; the mode control module 130, which is used to control the receiving data module 110 and the receiving clock module 120 to switch between the high-speed data receiving mode and the low-speed data receiving mode.
  • the above-mentioned receiving data module 110 includes: at least one data channel 111 for receiving high-speed data or low-speed data, and adopting a high-speed data receiving mode or a low-speed data receiving mode according to the data type of the received data; a word alignment circuit module 112, Used for word alignment of the received high-speed data; channel alignment circuit module 113, used for channel alignment of the received high-speed data; protocol analysis circuit module 115, used to configure the protocol analysis mode, and obtain the corresponding configuration protocol according to the configuration protocol mode The output data.
  • the part DPHY_IO to MIPI_decode in Figure 1 corresponds to the receiving data module 110, where DPHY_IO corresponds to the data channel 111 for receiving low-speed (LP) data and high-speed data (HS), and implements Corresponding high-speed data receiving mode and low-speed data receiving mode switching; word_align corresponds to the word alignment circuit module 112, used to implement the word alignment function; lane_align corresponds to the channel alignment circuit module 114, used to implement the channel alignment function to avoid channel skew MIPI_decode corresponds to the protocol analysis circuit module 115, which is used to analyze data according to different protocol analysis modes; DPHY_CLK corresponds to the receiving clock module 120, which is used to recover the high-speed serial clock (hs_clk) and byte clock (byte_clk) ); mode_ctrl corresponds to the mode control module 130, which is used to control the data link to switch between the high-speed data receiving mode and the low-speed data receiving mode
  • the data channel 111 in the data module of the receiving circuit in Fig. 1 is configured with 1-4 data channels.
  • Each data channel 111 (DPHY_IO) corresponds to a word alignment circuit module 112 (word_align).
  • Each data channel 111 can be configured according to the user Configuration reconstruction, after the data channel 111 is determined according to the user configuration reconstruction, high-speed data and low-speed data can be input on the data channel 111.
  • the data channel 111 is input with low-speed data (LP)
  • the data channel 111 adopts low-speed data Receiving mode.
  • the high-speed data (HS) is input on the data channel 111
  • the data channel 111 adopts the high-speed data receiving mode.
  • the data channel 111 changes from high-speed data to low-speed data
  • the receiving mode is switched to the low-speed data receiving mode.
  • the data channel 111 is switched from the low-speed data receiving mode to the high-speed data receiving mode.
  • the high-speed data is sent to the channel alignment circuit module 114 (lane_align) for channel alignment, and finally the high-speed data after word alignment and channel alignment are deserialized to the protocol analysis circuit module 115 (MIPI_decode) for protocol analysis, and the protocol analysis circuit module 115 (MIPI_decode) According to the configured protocol mode, it can analyze travel synchronization (hsync), field synchronization (vsync), data (Data), data valid flag (de), CSI2/DSI data packet header and packet header valid flag. It can be understood that, in this embodiment, the protocol analysis mode adopted by the protocol analysis circuit module 115 (MIPI_decode) can be set according to the user's reconstruction configuration to implement more protocol configuration modes.
  • a first multiple selection selector 113 is provided between the word alignment circuit module 112 (word_align) and the lane alignment circuit module 114 (lane_align).
  • the first multiple selection The converter 113 is used to determine whether to use word-aligned deserialization high-speed data (HS); a second multiple selector 116 (MUX2) is provided between the lane alignment circuit module 114 (lane_align) and the protocol analysis circuit module 115 (MIPI_decode) , The second multiple selection selector 116 is used to determine whether to use channel-aligned deserialization high-speed data (HS).
  • HS word-aligned deserialization high-speed data
  • the data channel 111 includes: a data switching detection circuit module 1115 and a data receiving mode switching circuit module 1114; the data switching detection circuit module 1115 detects that the received data is switched from high-speed data to low-speed data, or When low-speed data is switched to high-speed data, the corresponding data switching signal is sent to the mode control module 130; the data receiving mode switching circuit module 1114 switches after receiving the high-speed data receiving mode or low-speed data receiving mode control signal sent by the mode control module 130 To the corresponding high-speed data receiving mode or low-speed data receiving mode.
  • the data switching detection circuit module 1115 and the data receiving mode switching circuit module 1114 both include triggers, which can be reconfigured by the user; the data receiving mode switching circuit module 1114 also includes a deserialization module for converting 8 bits Or 4-bit parallel data, the deserialization ratio of the deserialization module can be configured by users, and the serial to parallel ratio of the deserialization ratio can be 1:4, or 1:8, etc.
  • FIG. 2 is a schematic diagram of the circuit structure of the data channel 111 (DPHY_IO) provided in this embodiment.
  • the IO interface module 1110 (IOB0) and the IO interface logic module 1111 (IOL0) in the upper half correspond to the above-mentioned data receiving mode switching circuit module 1114
  • the IO interface module 1112 (IOB1) and the IO interface logic module 1113 in the lower half are (IOL1) corresponds to the above-mentioned data switching detection circuit module 1115.
  • the buffer 11122 (LVCOMS12) in the lower half of IOB1 detects the data state switching from high-speed to low-speed or from low-speed to high-speed.
  • the switch data signal is sent to the mode through IOL1
  • the control module 130 wherein the flip-flop 11131 (FF) in IOL1 can be used through the user’s reconstruction configuration.
  • the control signal is input to the differential signal buffer 11121 (SLVS12 ), realize the switch of receiving mode.
  • the specific receiving mode switching control process is as follows: when working in the high-speed data (HS) receiving mode, the output state of the two LP input buffers is 0 level (LP00), and when the work changes from the high-speed data (HS) receiving mode to low-speed When the data (LP) receiving mode is switched, the output signals of the two input buffers are high, and the output of the two low-speed receiving buffers (LVCOMS12) jumps from 0 level to 1 level (LP11); when the mode is controlled
  • the module 130 detects the low-speed data (LP) transition from 0 level to 1 level, the mode control module 130 controls the M signal to transition from 1 level to 0 level, and controls IOB0 and IOB1 to switch to low-speed data (LP) Receive mode.
  • the high-speed receiving mode In the low-speed data (LP) receiving mode, the high-speed receiving mode is closed, the receiving end connection resistance is closed, and the low-speed receiving buffer (LVCOMS12) is opened; when the mode control module 130 receives the low-speed data (LP) signal, it jumps from LP11 to LP01 and then When it jumps to LP00, control the M signal to jump from 0 level to 1 level, switch IOB0 and IOB1 to the high-speed data (HS) receiving mode, and at the same time open the receiving end connection resistance, the high-speed data signal passes through the differential signal buffer (LVDS12) receiving; the received high-speed data signal is sent to the IOL0 module through a multi-selector (MUX), and the deserialization module (ISERDES) in IOL0 performs deserialization, and converts 8-bit or 4-bit parallel data. Among them, the deserialization of ISERDES is more user-configurable and reconfigurable.
  • MUX multi-selector
  • the receiving clock module 120 includes: a clock data switching detection circuit module 123 and a data frequency dividing circuit module 126; the clock data switching detection circuit module 123 detects that the received data is switched from high-speed data to low-speed data, Or when switching from low-speed data to high-speed data, the corresponding data switching signal is sent to the mode control module 130; after receiving the high-speed data receiving mode or low-speed data receiving mode control signal sent by the mode control module 130, the data frequency dividing circuit module 126 Switch to the corresponding high-speed data receiving mode or low-speed data receiving mode.
  • the clock data switching detection circuit module 123 and the data frequency dividing circuit module 126 both include flip-flops, which can be reconfigured by the user; the data frequency dividing circuit module 126 also includes a frequency dividing circuit module, and the frequency dividing circuit module 126 supports Divide 4 and divide 2 modes of configuration, and users can reconfigure the configuration.
  • FIG. 3 is a schematic diagram of the circuit structure of the receiving clock module 120 (DPHY_CLK) provided in this embodiment.
  • the IO interface module 121 (IOB0) and the IO interface logic module 122 (IOL0) in the upper half correspond to the above-mentioned clock data switching detection circuit module 123, and the IO interface module 124 (IOB1) and the IO interface logic module 125 in the lower half are (IOL1) corresponds to the aforementioned data frequency dividing circuit module 126.
  • the receiving clock module 120 (DPHY_CLK) and the data channel 111 (DPHY_IO) have a similar circuit design architecture.
  • the receiving clock module 120 (DPHY_CLK) circuit is also composed of a clock data switching detection circuit module 123 and a data frequency divider circuit module 126.
  • the IOL0 part of the receiving clock module 120 (DPHY_CLK) circuit is designed with a dedicated frequency divider circuit 1221 (DIV).
  • the frequency divider circuit 1221 supports configurable division by 4 and division by 2 modes, and user configurable reconstruction.
  • This embodiment provides a MIPI D-PHY receiving circuit.
  • a reconfigurable configuration design On the basis of the traditional MIPI D-PHY receiving circuit, a reconfigurable configuration design, a channel alignment circuit module, and a channel alignment circuit module are added, and the MIPI D-PHY receiving circuit Data unpacking and CSI2/DSI protocol unpacking are integrated and designed, and the CSI2/DSI protocol layer unpacking function is integrated into the data unpacking circuit of the MIPI D-PHY layer, which can effectively reduce the circuit area and improve the resource utilization rate of the circuit ; It can effectively reduce the receiving delay of the circuit and improve the delay performance of the circuit; the circuit design supports word alignment and channel alignment, which can effectively solve the problem of channel skew in the application; the MIPI D-PHY receiving circuit is a reconfigurable structure, It can meet the requirements of CSI2 and DSI in many different application scenarios.
  • the reconstruction method of the MIPI D-PHY receiving circuit includes: the receiving data module obtains the reconstruction parameters configured by the user According to the reconstruction parameters, determine the target data channel from at least one data channel; the mode control module determines that the target data channel adopts the high-speed data receiving mode or the low-speed data receiving mode according to the received data type; the receiving data module responds to the received high-speed data or low-speed data The data is processed to obtain the output data required by the configuration protocol, and output the output data.
  • FIG. 4 is a schematic flowchart of a method for reconstructing a MIPI D-PHY receiving circuit provided by this embodiment, which specifically includes the following steps:
  • the data receiving module obtains a reconstruction parameter configured by a user, and determines a target data channel from at least one data channel according to the reconstruction parameter.
  • the reconstruction parameters configured by the user may include: reconstructing the target data channel in the data channel, reconstructing the deserialization ratio of the deserialization module in the target data channel, and reconstructing the frequency divider circuit in the receiving clock module Divide by 4 and divide by 2 modes, reconstruct the configuration protocol mode in the protocol analysis circuit module.
  • the mode control module determines that the target data channel adopts the high-speed data receiving mode or the low-speed data receiving mode according to the received data type.
  • the data switching detection circuit module in the target data channel when the received data is high-speed data, the data switching detection circuit module in the target data channel outputs a low level signal to the mode control module, and the mode control module outputs a high level to the data receiving mode switching circuit module in the target data channel. Control signal, the data receiving mode switching circuit module receives a high level control signal to switch the data receiving mode to the high-speed data receiving mode.
  • the data switching detection circuit module in the target data channel outputs a high-level signal to the mode control module, and the mode control module outputs a low-level control signal to the data receiving mode switching circuit module in the target data channel.
  • the data receiving mode switching circuit module receives the low-level control signal to switch the data receiving mode to the low-speed data receiving mode.
  • the receiving data module includes: a data switching detection circuit module and a data receiving mode switching circuit module; when the data switching detection circuit module detects that the received data is switched from high-speed data to low-speed data, or from low-speed data to high-speed data, Send the corresponding data switching signal to the mode control module; the data receiving mode switching circuit module switches to the corresponding high-speed data receiving mode or low-speed data receiving after receiving the high-speed data receiving mode or low-speed data receiving mode control signal sent by the mode control module mode.
  • the output data includes: byte clock, travel synchronization, field synchronization, data, data valid flag, CSI2/DSI data packet header, and packet header valid flag.
  • the above-mentioned high-speed data or low-speed data received by the receiving data module is processed to obtain the configuration
  • the output data required by the protocol and the output data include: when in the high-speed data receiving mode, the received high-speed data is synchronized, and the synchronized data is analyzed by the protocol, and then converted into low-speed parallel data; In the low-speed data receiving mode, the received low-speed data is analyzed by protocol, the output data required by the configuration protocol is obtained, and the output data is output.
  • This embodiment provides a method for reconstructing the MIPI D-PHY receiving circuit.
  • the method for reconstructing the MIPI D-PHY receiving circuit includes: a receiving data module obtains a user-configured reconstruction parameter, and according to the reconstruction parameter from at least one piece of data The target data channel is determined in the channel; the mode control module determines that the target data channel adopts the high-speed data receiving mode or the low-speed data receiving mode according to the received data type; the receiving data module processes the received high-speed data or low-speed data to obtain the configuration protocol required Output data and output output data.
  • the MIPI D-PHY receiving circuit is a reconfigurable structure, which can meet the needs of various application scenarios of CSI2 and DSI.
  • the MIPI D-PHY receiving circuit data unpacking and CSI2/DSI protocol unpacking are integrated and designed, which can Effectively reduce circuit area and improve circuit resource utilization.
  • FIG. 5 shows a schematic diagram of the working state of a protocol analysis circuit module state machine provided in this embodiment.
  • FIG. 6 shows an electronic device 600 provided by an embodiment of the present application.
  • the electronic device includes the MIPI D-PHY receiving circuit 610 in the foregoing embodiment.
  • the electronic device 600 may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a palmtop computer, a personal digital assistant (PDA), and a mobile smart device with a screen projection function.
  • PDA personal digital assistant
  • it can also be, but not limited to, a personal computer (Personal Computer, PC) with a screen projection function, or a stationary smart device of a vehicle-mounted computer.
  • PC Personal Computer

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Abstract

本申请实施例提供了一种接收电路、接收电路的重构方法及电子设备，该接收电路为MIPI D-PHY接收电路，其包括：接收数据模块，用于根据用户重构配置数据通道，并将接收的高速数据或低速数据进行处理得到配置协议所需的输出数据；接收时钟模块，用于恢复高速数据串行时钟与字节时钟；模式控制模块，用于控制接收数据模块和接收时钟模块进行高速数据接收模式和低速数据接收模式的切换。通过接收时钟模块和模式控制模块来控制接收数据模块的数据接收，接收数据模块根据用户的重构配置数据通道，同时将接收的高速数据或低速数据进行数据处理得到配置协议所需的输出数据，实现了MIPI D-PHY接收电路的重构配置和MIPI D-PHY与MIPI协议层的整合，避免功能重复和资源浪费。

Description

一种接收电路、接收电路的重构方法及电子设备
相关申请的交叉引用
本申请要求于2019年5月29日提交的申请号为201910459476.4的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请涉及高速串行总线技术领域，具体的涉及一种接收电路、接收电路的重构方法及电子设备。
背景技术
随着智能设备所继承的功能越来越多，智能设备上所搭载的各种设备的类型也变得越来越多，各个设备由于功能的差异，导致各个设备对应的连接接口类型也变得越来越多，这给智能设备的主板电路设计带来很大的设计和整合难度。MIPI联盟正是在这个背景下产生，其目的是为了将移动智能设备内的各个组件的接口标准化和规范化，从而减少移动智能设备主板电路设计的复杂度和增加设计的灵活性。
DPHY是MIPI协议中的一项，DPHY提供了对DSI(串行显示接口)和CSI(串行摄像头接口)在物理层上的定义DPHY描述了源同步，高速，低功耗的物理层。现有MIPI D-PHY电路都采用ASIC专用电路实现，随着MIPI D-PHY接口在移动行业中的应用越来越广泛，现有的MIPI D-PHY电路实现方式不能对应用模式进行灵活配置，专用MIPI D-PHY电路不能满足不同应用场景的需求，对MIPI D-PHY支持模式的多样性有了更高的要求；同时由于通用MIPI D-PHY电路与协议(CSI2/DSI)电路分别独立，MIPI D-PHY与MIPI协议层都需要对电路进行接收解包处理，存在部分功能重复与资源浪费的问题。
因此，提出一种可以灵活配置的MIPI D-PHY电路以满足不同应用场景的需求，可减少MIPI D-PHY与MIPI协议层的功能重复与资源浪费，对MIPI D-PHY电路十分的有意义。
发明内容
本申请实施例的目的在于提供一种接收电路、接收电路的重构方法及电子设备，旨在解决现有MIPI D-PHY电路无法灵活配置，以及MIPI D-PHY与MIPI协议层存在部分功能重复与资源浪费的问题。
为了实现上述目的，本申请实施例提供了一种MIPI D-PHY接收电路，所述MIPI D-PHY接收电路包括：
接收数据模块，用于根据用户重构配置数据通道，并将接收的高速数据或低速数据进行处理得到配置协议所需的输出数据；
接收时钟模块，用于所述接收数据模块在高速数据接收模式下接收高速数据时，恢复高速时钟与字节时钟，以实现对所述接收数据模块的同步采样以及串并转换；
模式控制模块，用于控制所述接收数据模块和所述接收时钟模块进行高速数据接收模式和低速数据接收模式的切换。
进一步地，所述接收数据模块包括：
至少一条数据通道，用于接收高速数据或低速数据，并根据接收数据的数据类型分别采用高速数据接收模式或低速数据接收模式；
字对齐电路模块，用于将接收的高速数据进行字对齐；
通道对齐电路模块，用于将接收的高速数据进行通道对齐；
协议解析电路模块，用于配置协议解析模式，根据配置协议模式得到对应的配置协议的输出数据。
进一步地，所述数据通道包括：数据切换检测电路模块和数据接收模式切换电路模块；
所述数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，向所述模式控制模块发送对应的数据切换信号；
所述数据接收模式切换电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
进一步地，所述数据切换检测电路模块和数据接收模式切换电路模块中均包括触发器；所述数据接收模式切换电路模块还包括解串模块，用于转换8比特或4比特并行数据。
进一步地，所述数据切换检测电路模块包括缓冲器；
所述缓冲器，用于检测数据状态从高速到低速的切换或从低速到高速的切换。
进一步地，所述缓冲器还用于：当检测到数据切换时，将切换数据信号发送至所述模式控制模块；
在所述模式控制模块接收到所述切换数据信号后，将控制信号输入至所述数据切换检测电路模块中的差分信号缓冲器。
进一步地，所述输出数据包括：字节时钟、出行同步、场同步、数据、数据有效标志、CSI2/DSI数据包头以及包头有效标志。
进一步地，所述MIPI D-PHY接收电路还包括第一多选选择器，所述第一多选选择器设置于所述字对齐电路模块和所述通道对齐电路模块之间；
所述第一多选选择器，用于确定是否使用字对齐的解串高速数据。
进一步地，所述MIPI D-PHY接收电路还包括第二多选选择器，所述第二多选选择器设置于所述通道对齐电路模块和所述协议解析电路模块之间；
所述第二多选选择器，用于确定是否使用通道对齐的解串高速数据。
进一步地，所述协议解析电路模块根据用于对协议解析模式进行重构配置的配置指令，对所述协议解析模式进行设置。
进一步地，所述接收时钟模块包括：时钟数据切换检测电路模块和数据分频电路模块；
所述时钟数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，向所述模式控制模块发送对应的数据切换信号；
所述数据分频电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
进一步地，所述时钟数据切换检测电路模块和数据分频电路模块中均包括触发器；所述数据分频电路模块还包括分频电路模块，所述分频电路模块支持可配置的除4与除2模式。
进一步地，所述数据通道的数量为1-4，每条数据通道对应设置一个所述字对齐电路模块。
进一步地，所述每条数据通道用于根据用户配置进行重构。
进一步地，本申请还提供了一种MIPI D-PHY接收电路的重构方法，所述MIPI D-PHY接收电路的重构方法包括：
接收数据模块获取用户配置的重构参数，根据所述重构参数从至少一条数据通道中确定目标数据通道；
模式控制模块根据接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式；
所述接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出所述输出数据。
进一步地，所述重构参数包括：重构数据通道中的目标数据通道、重构目标数据通道中解串模块的解串比、重构接收时钟模块中分频电路的除4与除2模式以及重构协议解析电路模块中的配置协议模式，所述获取用户配置的重构参数包括：
获取所述目标数据通道、所述解串比、所述分频电路的除4与除2模式以及所述配置协议模式。
进一步地，所述根据模式控制模块接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式，包括：
当接收数据为高速数据时，目标数据通道中的数据切换检测电路模块输出低电平信号给模式控制模块，所述模式控制模块向目标数据通道中的数据接收模式切换电路模块输出高电平控制信号，所述数据接收模式切换电路模块接收所述高电平控制信号将数据接收模式切换为高速数据接收模式；
当接收数据为低速数据时，目标数据通道中的数据切换检测电路模块输出高电平信号给模式控制模块，所述模式控制模块向目标数据通道中的数据 接收模式切换电路模块输出低电平控制信号，所述数据接收模式切换电路模块接收所述低电平控制信号将数据接收模式切换为低速数据接收模式。
进一步地，所述输出数据包括：字节时钟、出行同步、场同步、数据、数据有效标志、CSI2/DSI数据包头以及包头有效标志，所述接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出所述输出数据，包括：
当处于高速数据接收模式时，将接收的高速数据进行同步处理，并将同步后的数据进行协议解析，再转换为低速并行数据；
当处于低速数据接收模式时，将接收的低速数据进行协议解析，获得配置协议所需的输出数据，并将所述输出数据输出。
进一步地，所述接收数据模块包括：数据切换检测电路模块和数据接收模式切换电路模块；
所述模式控制模块根据接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式，包括：
所述数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，发送对应的数据切换信号至所述模式控制模块；
所述数据接收模式切换电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
进一步地，本申请提出了一种电子设备，包括上述的MIPI D-PHY接收电路。
本申请实施例的有益效果是：
本申请实施例提供了一种接收电路、接收电路的重构方法及电子设备，该接收电路为MIPI D-PHY接收电路，其包括：接收数据模块，用于根据用户重构配置数据通道，并将接收的高速数据或低速数据进行处理得到配置协议所需的输出数据；接收时钟模块，用于恢复高速数据串行时钟与字节时钟；模式控制模块，用于控制接收数据模块和接收时钟模块进行高速数据接收模式和低速数据接收模式的切换。通过接收时钟模块和模式控制模块来控制接收数据模块的数据接收，接收数据模块根据用户的重构配置来配置数据通道，同时将接收的高速数据或低速数据进行数据处理得到配置协议所需的输出数据，实现了MIPI D-PHY接收电路的重构配置和MIPI D-PHY与MIPI协议层的整合，避免功能重复和资源浪费。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提 下，还可以根据这些附图获得其他的附图。
图1为本申请一个实施例提供的MIPI D-PHY接收电路的示意图；
图2为本申请另一个实施例提供的数据通道(DPHY_IO)的电路结构示意图；
图3为本申请又一个实施例提供的接收时钟模块(DPHY_CLK)的电路结构示意图；
图4为本申请一个实施例提供的MIPI D-PHY接收电路的重构方法的流程示意图；
图5为本申请一个实施例提供的协议解析电路模块状态机系统的工作状态示意图；
图6为本申请一个实施例提供的电子设备的结构框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例只是本申请中一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其示出了本申请实施例提供的MIPI D-PHY接收电路100，该MIPI D-PHY接收电路100包括：接收数据模块110，用于根据用户重构配置数据通道，并将接收的高速数据或低速数据进行处理得到配置协议所需的输出数据；接收时钟模块120，用于接收数据模块在高速数据接收模式下接收高速数据时，恢复高速时钟与字节时钟，以实现对接收数据模块110的同步采样以及串并转换；模式控制模块130，用于控制接收数据模块110和接收时钟模块120进行高速数据接收模式和低速数据接收模式的切换。
进一步地，上述接收数据模块110包括：至少一条数据通道111，用于接收高速数据或低速数据，并根据接收数据的数据类型分别采用高速数据接收模式或低速数据接收模式；字对齐电路模块112，用于将接收的高速数据进行字对齐；通道对齐电路模块113，用于将接收的高速数据进行通道对齐；协议解析电路模块115，用于配置协议解析模式，根据配置协议模式得到对应的配置协议的输出数据。
具体的，请再次参见图1，图1中的DPHY_IO到MIPI_decode部分对应于接收数据模块110，其中的DPHY_IO对应于数据通道111，用于接收低速(LP)数据与高速数据(HS)，并且实现对应的高速数据接收模式和低速数据接收模式的切换；word_align对应于字对齐电路模块112，用于实现字对齐功能；lane_align对应于通道对齐电路模块114，用于实现通道对齐功能，避免通道偏斜的问题；MIPI_decode对应于协议解析电路模块115，用于根据不同的协议解析模式，对数据进行解析；DPHY_CLK对应于接收时钟模块120，用于恢复高速串行时钟(hs_clk)与字节时钟(byte_clk)；mode_ctrl对应于模式控 制模块130，用于控制数据通进行高速数据接收模式和低速数据接收模式的切换。
图1中接收电路的数据模块中数据通道111配置了1-4数据通道，其中每一条数据通道111(DPHY_IO)对应设置一个字对齐电路模块112(word_align)，每一条数据通道111均可根据用户配置重构，根据用户配置重构确定数据通道111后，可以在该数据通道111上输入高速数据和低速数据，当数据通道111上输入的是低速数据(LP)时，数据通道111采用低速数据接收模式，当数据通道111上输入的是高速数据(HS)时，数据通道111采用高速数据接收模式，当数据通道111上输入的数据由高速数据改变为低速数据时，数据通道111由高速数据接收模式切换为低速数据接收模式，当数据通道111上输入的数据由低数数据改变为高速数据时，数据通道111由低速数据接收模式切换为高速数据接收模式。
需要说明的是，只有当接收的数据为高速数据时，才可以使用字对齐电路模块112(word_align)和通道对齐电路模块114(lane_align)；当数据通道111上输入的是高速数据(HS)时，数据通道111采用高速数据接收模式接收数据，将接收的高速数据(HS)进行解串，将解串后的高速数据送入字对齐电路模块112(word_align)进行字对齐，将字对齐后的高速数据送入通道对齐电路模块114(lane_align)进行通道对齐，最后将进行字对齐和通道对齐的解串后的高速数据送入协议解析电路模块115(MIPI_decode)进行协议解析，协议解析电路模块115(MIPI_decode)根据配置的协议模式，可解析出行同步(hsync)、场同步(vsync)、数据(Data)、数据有效标志(de)、CSI2/DSI数据包头以及包头有效标志。可以理解的是，在本实施例中，协议解析电路模块115(MIPI_decode)所采用的协议解析模式，可以根据用户的重构配置进行设置，以实现更多的协议配置模式。
可以理解的是，在本实施例中，可以选择是否对解串后的高速数据(HS)进行字对齐和/或通道对齐。具体的参见图1，在图1中，字对齐电路模块112(word_align)和通道对齐电路模块114(lane_align)之间设置有一个第一多选选择器113(MUX1)，该第一多选选择器113用于确定是否使用字对齐的解串高速数据(HS)；通道对齐电路模块114(lane_align)和协议解析电路模块115(MIPI_decode)之间设置有一个第二多选选择器116(MUX2)，该第二多选选择器116用于确定是否使用通道对齐的解串高速数据(HS)。
进一步地，在本实施例中数据通道111包括：数据切换检测电路模块1115和数据接收模式切换电路模块1114；数据切换检测电路模块1115在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，向模式控制模块130发送对应的数据切换信号；数据接收模式切换电路模块1114在接收到模式控制模块130发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。并且，其中的数据切换检测电路模块1115和数据接收模式切换电路模块1114中均包括触发器，触发器用户可重构配置；数据接收模式切换电路模块1114 还包括解串模块，用于转换8比特或4比特并行数据，解串模块的解串比用户可重构配置，解串比的串行转并行的比例可以为1:4，或1:8等。
具体的，请参见图2，图2为本实施例中提供的数据通道111(DPHY_IO)的电路结构示意图。其中上半部分的IO接口模块1110(IOB0)和IO接口逻辑模块1111(IOL0)对应于上述的数据接收模式切换电路模块1114，下半部分的IO接口模块1112(IOB1)和IO接口逻辑模块1113(IOL1)对应于上述的数据切换检测电路模块1115。在图2中，下半部分IOB1中的缓冲器11122(LVCOMS12)检测数据状态从高速到低速的切换或从低速到高速的切换，当检测到数据切换时，将切换数据信号通过IOL1发送至模式控制模块130，其中IOL1中的触发器11131(FF)可以通过用户的重构配置进行使用，在模式控制模块130接收到切换数据信号后，将控制信号通过M输入到差分信号缓冲器11121(SLVS12)，实现接收模式的切换。
具体的接收模式的切换控制过程如下：在高速数据(HS)接收模式工作时，两个LP输入缓冲器的输出状态为0电平(LP00)，当工作由高速数据(HS)接收模式进入低速数据(LP)接收模式切换时，输入的两个缓冲器的输出信号高电平，两个低速接收缓冲器(LVCOMS12)的输出由0电平跳变到1电平(LP11)；当模式控制模块130监测到低速数据(LP)从0电平到1电平跳变，模式控制模块130通过控制M信号由1电平跳变为0电平，控制IOB0与IOB1切换到低速数据(LP)接收模式。在低速数据(LP)接收模式时，高速接收模式关闭，接收端连接电阻关闭，低速接收缓冲器(LVCOMS12)打开；当模式控制模块130接收到低速数据(LP)信号由LP11跳变到LP01再跳变到LP00时，则控制M信号由0电平跳变为1电平，将IOB0与IOB1切换到高速数据(HS)接收模式，同时打开接收端连接电阻,高速数据信号通过差分信号缓冲器(LVDS12)接收；接收的高速数据信号通过1个多选选择器(MUX)，将信号送入到IOL0模块，在IOL0中的解串模块(ISERDES)进行解串，转换8比特或者4比特并行数据。其中，ISERDES的解串比用户可配置重构。
进一步地，在本实施例中接收时钟模块120包括：时钟数据切换检测电路模块123和数据分频电路模块126；时钟数据切换检测电路模块123在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，向模式控制模块130发送对应的数据切换信号；数据分频电路模块126在接收到模式控制模块130发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。其中，时钟数据切换检测电路模块123和数据分频电路模块126中均包括触发器，触发器用户可重构配置；数据分频电路模块126还包括分频电路模块，分频电路模块126支持可配置的除4与除2模式，且用户可重构配置。
具体的，请参见图3，图3为本实施例中提供的接收时钟模块120(DPHY_CLK)的电路结构示意图。其中上半部分的IO接口模块121(IOB0)和IO接口逻辑模块122(IOL0)对应于上述的时钟数据切换检测电路模块 123，下半部分的IO接口模块124(IOB1)和IO接口逻辑模块125(IOL1)对应于上述的数据分频电路模块126。接收时钟模块120(DPHY_CLK)与数据通道111(DPHY_IO)电路设计架构类似，接收时钟模块120(DPHY_CLK)电路同样由时钟数据切换检测电路模块123和数据分频电路模块126两部分电路组成。接收时钟模块120(DPHY_CLK)电路中的IOL0部分设计有专用的分频电路1221(DIV)，分频电路1221支持可配置的除4与除2模式，用户可配置重构。
本实施例提供了一种MIPI D-PHY接收电路，在传统MIPI D-PHY接收电路的基础上增加可重构配置设计、通道对齐电路模块和通道对齐电路模块，同时将MIPI D-PHY接收电路数据解包与CSI2/DSI协议解包进行整合设计，将CSI2/DSI协议层解包功能整合到MIPI D-PHY层的数据解包电路中，能够有效的减少电路面积，提高电路的资源使用率；能够有效的减少电路的接收延时，提升电路的延时性能；电路设计支持字对齐、通道对齐，能够有效解决应用中的通道偏斜问题；MIPI D-PHY接收电路为可重构结构，可以满足CSI2与DSI多种不同应用场景需求。
请参阅图4，其示出了本另一个实施例提供的MIPI D-PHY接收电路的重构方法，该MIPI D-PHY接收电路的重构方法包括：接收数据模块获取用户配置的重构参数，根据重构参数从至少一条数据通道中确定目标数据通道；模式控制模块根据接收的数据类型，确定目标数据通道采用高速数据接收模式或低速数据接收模式；接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出输出数据。
具体的，请再次参见图4，图4为本实施例提供的一种MIPI D-PHY接收电路的重构方法的流程示意图，具体包括以下步骤：
S401、接收数据模块获取用户配置的重构参数，根据重构参数从至少一条数据通道中确定目标数据通道。
参照图1、2和3，用户配置的重构参数可以包括：重构数据通道中的目标数据通道，重构目标数据通道中解串模块的解串比，重构接收时钟模块中分频电路的除4与除2模式，重构协议解析电路模块中的配置协议模式。
S402、模式控制模块根据接收的数据类型，确定目标数据通道采用高速数据接收模式或低速数据接收模式。
具体的，当接收数据为高速数据时，目标数据通道中的数据切换检测电路模块输出低电平信号给模式控制模块，模式控制模块向目标数据通道中的数据接收模式切换电路模块输出高电平控制信号，数据接收模式切换电路模块接收高电平控制信号将数据接收模式切换为高速数据接收模式。当接收数据为低速数据时，目标数据通道中的数据切换检测电路模块输出高电平信号给模式控制模块，模式控制模块向目标数据通道中的数据接收模式切换电路模块输出低电平控制信号，数据接收模式切换电路模块接收低电平控制信号将数据接收模式切换为低速数据接收模式。
进一步地，接收数据模块包括：数据切换检测电路模块和数据接收模式切换电路模块；数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，发送对应的数据切换信号至模式控制模块；数据接收模式切换电路模块在接收到模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
S403、接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出输出数据。
具体的，输出数据包括：字节时钟、出行同步、场同步、数据、数据有效标志、CSI2/DSI数据包头以及包头有效标志，上述对接收数据模块接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出输出数据，包括：当处于高速数据接收模式时，将接收的高速数据进行同步处理，并将同步后的数据进行协议解析，再转换为低速并行数据；当处于低速数据接收模式时，将接收的低速数据进行协议解析，获得配置协议所需的输出数据，并将输出数据输出。
本实施例提供了一种MIPI D-PHY接收电路的重构方法，该MIPI D-PHY接收电路的重构方法包括：接收数据模块获取用户配置的重构参数，根据重构参数从至少一条数据通道中确定目标数据通道；模式控制模块根据接收的数据类型，确定目标数据通道采用高速数据接收模式或低速数据接收模式；接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出输出数据。该方法中MIPI D-PHY接收电路为可重构结构，可以满足CSI2与DSI多种不同应用场景需求，同时将MIPI D-PHY接收电路数据解包与CSI2/DSI协议解包进行整合设计，能够有效的减少电路面积，提高电路的资源使用率。
请参阅图5，其示出了本实施例提供的一种协议解析电路模块状态机的工作状态示意图。
系统工作状态如下描述：系统初始化时，进入等待同步状态(ST_SYNC)；
当接收到高速数据的同步信号后，协议包头在通道0上对齐，状态跳转到接收协议包头1状态(ST_LEN1)；
当在ST_LEN1状态，检测到协议包尾，则跳回到等待同步状态(ST_SYNC)；
当在ST_LEN1状态，检测到协议长包(包长度WC>＝1)，则跳转到接收长包状态(ST_LONG)；
当在ST_LEN1状态，检测到协议短包(包长度WC＝0)，则不跳继续留在ST_LEN1状态；
当在ST_LONG状态，检测到协议包接收完成，最后一个字节在通道0上，且检测到短包，则状态跳转到ST_LEN1；
当在ST_LONG状态，检测到协议包接收完成，最后一个字节在通道1上，且检测到短包，则状态跳转到ST_LEN2；
当在ST_LONG状态，检测到协议包接收完成，最后一个字节在通道2上，且检测到短包，则状态跳转到ST_LEN3；
当在ST_LONG状态，检测到协议包接收完成，最后一个字节在通道3上，且检测到短包，则状态跳转到ST_LEN4；
当在ST_LONG状态，检测到协议包接收完成，最后一个字节在通道3上，且检测到长包，则状态留在ST_LONG状态；
当在ST_LONG状态，检测到协议包接收完成，检测到协议包尾，则跳回到等待同步状态(ST_SYNC)；
当在ST_LEN2状态，检测到协议包尾，则跳回到等待同步状态(ST_SYNC)；
当在ST_LEN2状态，检测到协议长包(包长度WC>＝1)，则跳转到接收长包状态(ST_LONG)；
当在ST_LEN2状态，检测到协议短包(包长度WC＝0)，则不跳继续留在ST_LEN2状态；
当在ST_LEN3状态，检测到协议包尾，则跳回到等待同步状态(ST_SYNC)；
当在ST_LEN3状态，检测到协议长包(包长度WC>＝1)，则跳转到接收长包状态(ST_LONG)；
当在ST_LEN3状态，检测到协议短包(包长度WC＝0)，则不跳继续留在ST_LEN3状态；
当在ST_LEN4状态，检测到协议包尾，则跳回到等待同步状态(ST_SYNC)；
当在ST_LEN4状态，检测到协议长包(包长度WC>＝1)，则跳转到接收长包状态(ST_LONG)；
当在ST_LEN4状态，检测到协议短包(包长度WC＝0)，则跳继续留在ST_LEN4状态。
请参阅图6，其示出了本申请实施例提供的一种电子设备600，该电子设备包括上述实施例中的MIPI D-PHY接收电路610。
可选的，该电子设备600可以为但不限于智能手机、平板电脑、笔记本电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)，以及具有投屏功能的移动类智能设备。当然，也可以为但不限于具有投屏功能的个人计算机(Personal Computer，PC)、车载电脑固定类智能设备。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。通过以上的实施例描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情 况下前者是更佳的实施方式。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。

Claims (20)

  1. 一种MIPI D-PHY接收电路，其特征在于，所述MIPI D-PHY接收电路包括：
    接收数据模块，用于根据用户重构配置数据通道，并将接收的高速数据或低速数据进行处理得到配置协议所需的输出数据；
    接收时钟模块，用于所述接收数据模块在高速数据接收模式下接收高速数据时，恢复高速串行时钟与字节时钟，以实现对所述接收数据模块的同步采样以及串并转换；
    模式控制模块，用于控制所述接收数据模块和所述接收时钟模块进行高速数据接收模式和低速数据接收模式的切换。
  2. 如权利要求1所述的MIPI D-PHY接收电路，其特征在于，所述接收数据模块包括：
    至少一条数据通道，用于接收高速数据或低速数据，并根据接收数据的数据类型分别采用高速数据接收模式或低速数据接收模式；
    字对齐电路模块，用于将接收的高速数据进行字对齐；
    通道对齐电路模块，用于将接收的高速数据进行通道对齐；
    协议解析电路模块，用于配置协议解析模式，根据配置协议模式得到对应的配置协议的输出数据。
  3. 如权利要求2所述的MIPI D-PHY接收电路，其特征在于，所述数据通道包括：数据切换检测电路模块和数据接收模式切换电路模块；
    所述数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，向所述模式控制模块发送对应的数据切换信号；
    所述数据接收模式切换电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
  4. 如权利要求3所述的MIPI D-PHY接收电路，其特征在于，所述数据切换检测电路模块和数据接收模式切换电路模块中均包括触发器；所述 数据接收模式切换电路模块还包括解串模块，用于转换8比特或4比特并行数据。
  5. 如权利要求3所述的MIPI D-PHY接收电路，其特征在于，所述数据切换检测电路模块包括缓冲器；
    所述缓冲器，用于检测数据状态从高速到低速的切换或从低速到高速的切换。
  6. 如权利要求5所述的MIPI D-PHY接收电路，其特征在于，所述缓冲器还用于：当检测到数据切换时，将切换数据信号发送至所述模式控制模块；
    在所述模式控制模块接收到所述切换数据信号后，将控制信号输入至所述数据切换检测电路模块中的差分信号缓冲器。
  7. 如权利要求2-6任一项所述的MIPI D-PHY接收电路，其特征在于，所述输出数据包括：字节时钟、出行同步、场同步、数据、数据有效标志、CSI2/DSI数据包头以及包头有效标志。
  8. 如权利要求2-7任一项所述的MIPI D-PHY接收电路，其特征在于，所述MIPI D-PHY接收电路还包括第一多选选择器，所述第一多选选择器设置于所述字对齐电路模块和所述通道对齐电路模块之间；
    所述第一多选选择器，用于确定是否使用字对齐的解串高速数据。
  9. 如权利要求2-8任一项所述的MIPI D-PHY接收电路，其特征在于，所述MIPI D-PHY接收电路还包括第二多选选择器，所述第二多选选择器设置于所述通道对齐电路模块和所述协议解析电路模块之间；
    所述第二多选选择器，用于确定是否使用通道对齐的解串高速数据。
  10. 如权利要求2-9任一项所述的MIPI D-PHY接收电路，其特征在于，所述协议解析电路模块根据用于对协议解析模式进行重构配置的配置指令，对所述协议解析模式进行设置。
  11. 如权利要求1-10任一项所述的MIPI D-PHY接收电路，其特征在于，所述接收时钟模块包括：时钟数据切换检测电路模块和数据分频电路模块；
    所述时钟数据切换检测电路模块在检测到接收的数据由高速数据切换 到低速数据，或由低速数据切换到高速数据时，向所述模式控制模块发送对应的数据切换信号；
    所述数据分频电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
  12. 如权利要求11所述的MIPI D-PHY接收电路，其特征在于，所述时钟数据切换检测电路模块和数据分频电路模块中均包括触发器；所述数据分频电路模块还包括分频电路模块，所述分频电路模块支持可配置的除4与除2模式。
  13. 如权利要求2所述的MIPI D-PHY接收电路，其特征在于，所述数据通道的数量为1-4，每条数据通道对应设置一个所述字对齐电路模块。
  14. 如权利要求13所述的MIPI D-PHY接收电路，其特征在于，所述每条数据通道用于根据用户配置进行重构。
  15. 一种MIPI D-PHY接收电路的重构方法，其特征在于，所述MIPI D-PHY接收电路的重构方法包括：
    接收数据模块获取用户配置的重构参数，根据所述重构参数从至少一条数据通道中确定目标数据通道；
    模式控制模块根据接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式；
    所述接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出所述输出数据。
  16. 如权利要求15所述的MIPI D-PHY接收电路的重构方法，其特征在于，所述重构参数包括：重构数据通道中的目标数据通道、重构目标数据通道中解串模块的解串比、重构接收时钟模块中分频电路的除4与除2模式以及重构协议解析电路模块中的配置协议模式，所述获取接收数据模块的重构参数包括：
    获取所述目标数据通道、所述解串比、所述分频电路的除4与除2模式以及所述配置协议模式。
  17. 如权利要求15-16任一项所述的MIPI D-PHY接收电路的重构方 法，其特征在于，所述根据模式控制模块接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式，包括：
    当接收数据为高速数据时，目标数据通道中的数据切换检测电路模块输出低电平信号给模式控制模块，所述模式控制模块向目标数据通道中的数据接收模式切换电路模块输出高电平控制信号，所述数据接收模式切换电路模块接收所述高电平控制信号将数据接收模式切换为高速数据接收模式；
    当接收数据为低速数据时，目标数据通道中的数据切换检测电路模块输出高电平信号给模式控制模块，所述模式控制模块向目标数据通道中的数据接收模式切换电路模块输出低电平控制信号，所述数据接收模式切换电路模块接收所述低电平控制信号将数据接收模式切换为低速数据接收模式。
  18. 如权利要求15-17任一项所述的MIPI D-PHY接收电路的重构方法，其特征在于，所述输出数据包括：字节时钟、出行同步、场同步、数据、数据有效标志、CSI2/DSI数据包头以及包头有效标志；所述接收数据模块对接收的高速数据或低速数据进行处理，得到配置协议所需的输出数据，并输出所述输出数据，包括：
    当处于高速数据接收模式时，将接收的高速数据进行同步处理，并将同步后的数据进行协议解析，再转换为低速并行数据；
    当处于低速数据接收模式时，将接收的低速数据进行协议解析，获得配置协议所需的输出数据，并将所述输出数据输出。
  19. 如权利要求15-18任一项所述的MIPI D-PHY接收电路的重构方法，其特征在于，所述接收数据模块包括：数据切换检测电路模块和数据接收模式切换电路模块；
    所述模式控制模块根据接收的数据类型，确定所述目标数据通道采用高速数据接收模式或低速数据接收模式，包括：
    所述数据切换检测电路模块在检测到接收的数据由高速数据切换到低速数据，或由低速数据切换到高速数据时，发送对应的数据切换信号至所述模式控制模块；
    所述数据接收模式切换电路模块在接收到所述模式控制模块发送的高速数据接收模式或低速数据接收模式控制信号后，切换到对应的高速数据接收模式或低速数据接收模式。
  20. 一种电子设备，包括权利要求1-14任一项所述的MIPI D-PHY接收电路。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110347630B (zh) * 2019-05-29 2021-05-11 深圳市紫光同创电子有限公司 一种接收电路、接收电路可重构方法及状态机系统
CN112788327B (zh) * 2019-11-08 2024-03-08 京元电子股份有限公司 影像测试系统及其测试组件
KR20210079642A (ko) 2019-12-20 2021-06-30 에스케이하이닉스 주식회사 수신 장치, 이를 포함하는 반도체 장치 및 반도체 시스템
WO2023159415A1 (en) * 2022-02-24 2023-08-31 Qualcomm Incorporated Adaptive low-power signaling to enable link signal error recovery without increased link clock rates
CN114817114B (zh) * 2022-05-13 2023-08-15 广芯微电子(苏州)有限公司 一种mipi接口、及其控制方法、装置及介质
CN116684722B (zh) * 2023-07-27 2023-10-20 武汉精立电子技术有限公司 Mipi c-phy信号接收装置、方法及摄像头模组测试系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105573952A (zh) * 2015-12-31 2016-05-11 西安中颖电子有限公司 一种多通道数据传输的系统
WO2017177362A1 (zh) * 2016-04-11 2017-10-19 武汉芯泰科技有限公司 一种无线可配置闪存
CN108073539A (zh) * 2017-12-27 2018-05-25 上海集成电路研发中心有限公司 一种mipi接口的d-phy电路
CN110347630A (zh) * 2019-05-29 2019-10-18 深圳市紫光同创电子有限公司 一种接收电路、接收电路可重构方法及状态机系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US9606954B2 (en) * 2014-01-10 2017-03-28 Lattice Semiconductor Corporation Communicating with MIPI-compliant devices using non-MIPI interfaces
JP2015177364A (ja) * 2014-03-14 2015-10-05 シナプティクス・ディスプレイ・デバイス合同会社 レシーバ回路、表示パネルドライバ、表示装置及びレシーバ回路の動作方法
CN104795039B (zh) * 2015-04-30 2017-03-22 武汉精测电子技术股份有限公司 基于fpga实现mipi信号传输调整的方法和装置
CN108011694B (zh) * 2017-11-29 2018-11-20 北京航空航天大学 一种基于fc的高效数据交换方法
CN108280039B (zh) * 2018-02-13 2021-02-26 龙迅半导体（合肥）股份有限公司 一种MIPI C-Phy RX端的输入信号解码电路
CN109639457B (zh) * 2018-11-16 2021-08-13 北京时代民芯科技有限公司 一种jesd204b协议高速发送器单粒子错误率的测试系统及方法
CN109582619B (zh) * 2018-12-04 2023-08-18 中国航空工业集团公司西安航空计算技术研究所 一种高速串行总线与低速串行总线数据传输和转换方法
CN109450610B (zh) * 2018-12-26 2020-04-07 成都九芯微科技有限公司 一种通道相位对齐电路及方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105573952A (zh) * 2015-12-31 2016-05-11 西安中颖电子有限公司 一种多通道数据传输的系统
WO2017177362A1 (zh) * 2016-04-11 2017-10-19 武汉芯泰科技有限公司 一种无线可配置闪存
CN108073539A (zh) * 2017-12-27 2018-05-25 上海集成电路研发中心有限公司 一种mipi接口的d-phy电路
CN110347630A (zh) * 2019-05-29 2019-10-18 深圳市紫光同创电子有限公司 一种接收电路、接收电路可重构方法及状态机系统

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
WU, JINXING: "Design and Research of MIPI High Speed Interface Circuit for TFT-LCD Driver Chip", CHINESE MASTER’S THESES FULL-TEXT DATABASE, INFORMATION SCIENCE AND TECHNOLOGY, no. 2, 15 February 2019 (2019-02-15), ISSN: 1674-0246, DOI: 20200714125711X *
WU, JINXING: "Design and Research of MIPI High Speed Interface Circuit for TFT-LCD Driver Chip", CHINESE MASTER’S THESES FULL-TEXT DATABASE, INFORMATION SCIENCE AND TECHNOLOGY, no. 2, 15 February 2019 (2019-02-15), ISSN: 1674-0246, DOI: 20200714125817A *

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