WO2020232801A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2020232801A1
WO2020232801A1 PCT/CN2019/094690 CN2019094690W WO2020232801A1 WO 2020232801 A1 WO2020232801 A1 WO 2020232801A1 CN 2019094690 W CN2019094690 W CN 2019094690W WO 2020232801 A1 WO2020232801 A1 WO 2020232801A1
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WO
WIPO (PCT)
Prior art keywords
layer
gate
insulating layer
array substrate
bending material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/094690
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English (en)
French (fr)
Inventor
白亚梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/623,457 priority Critical patent/US11342363B2/en
Publication of WO2020232801A1 publication Critical patent/WO2020232801A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate.
  • the existing display panel has the technical problem of poor bending performance of the array substrate, which needs to be improved.
  • the present application provides an array substrate to alleviate the technical problem of poor bending performance of the existing array substrate.
  • the application provides an array substrate, including:
  • the driving circuit layer is formed on one side of the flexible substrate
  • At least one layer of bending material is formed in the driving circuit layer.
  • the material of the bending material layer is the same as that of the flexible substrate.
  • the driving circuit layer includes an active layer formed on the side of the flexible substrate, a gate insulating layer formed on the side of the active layer away from the substrate, and The gate insulating layer is far from the active layer side of the gate layer, the interlayer insulating layer is formed on the side of the gate layer far away from the gate insulating layer, and the interlayer insulating layer is formed far from the gate.
  • the source and drain layer on the side of the electrode layer, the planarization layer formed on the side of the source and drain away from the interlayer insulating layer, the active layer, the gate insulating layer, the gate layer, and the A groove is formed in at least one of the interlayer insulating layer, the source and drain layer, and the planarization layer, and the bending material layer is formed in at least one of the film layers in the groove There is a groove, and the bending material layer is formed in the groove.
  • one groove is formed on each film layer.
  • grooves are formed in at least two film layers of the driving circuit layer, and projections of all the grooves on the flexible substrate overlap.
  • grooves are formed in at least two film layers of the driving circuit layer, and the projections of the at least two grooves on the flexible substrate do not overlap.
  • At least one film layer in the film layer formed with grooves, at least one film layer has at least two grooves formed on it.
  • the driving circuit layer includes an active layer formed on the side of the flexible substrate, a gate insulating layer formed on the side of the active layer away from the substrate, and
  • the gate insulating layer is far from the active layer side of the gate layer
  • the interlayer insulating layer is formed on the side of the gate layer far away from the gate insulating layer
  • the interlayer insulating layer is formed far from the gate.
  • the bending material layer is formed between the active layer and the gate insulating layer.
  • the bending material layer is formed between the gate insulating layer and the gate layer.
  • the bending material layer is formed between the gate layer and the interlayer insulating layer.
  • the bending material layer is formed between the interlayer insulating layer and the source drain layer.
  • the bent material layer is formed between the source and drain layer and the planarization layer.
  • the bending material layer is formed between the source and drain layer and the planarization layer.
  • the bending material layer is formed between the gate insulating layer and the gate layer, and between the gate layer and the interlayer insulating layer.
  • the bending material layer is formed between the gate insulating layer and the gate layer, and between the interlayer insulating layer and the source drain layer.
  • the bending material layer is formed between the gate insulating layer and the gate layer, the source drain layer and the planarization layer.
  • the bending material layer is formed between the gate layer and the interlayer insulating layer, and between the interlayer insulating layer and the source drain layer.
  • the bending material layer is formed between the gate layer and the interlayer insulating layer, and between the source and drain layer and the planarization layer.
  • the bending material layer is formed between the interlayer insulating layer and the source/drain layer, the source/drain layer and the planarization layer.
  • the present application provides an array substrate, including a flexible substrate, a driving circuit layer, and at least one layer of bending material.
  • the driving circuit layer is formed on one side of the flexible substrate; at least one layer of bending material is formed on The driving circuit layer.
  • FIG. 1 is a schematic diagram of the first structure of an array substrate provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a second structure of the array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a fourth structure of an array substrate provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a fifth structure of an array substrate provided by an embodiment of the application.
  • the present application provides an array substrate to alleviate the technical problem of poor bending performance of the existing array substrate.
  • FIG. 1 it is a schematic diagram of the first structure of an array substrate provided by an embodiment of this application.
  • the array substrate includes a flexible substrate 10, a driving circuit layer 20 and at least one layer of bending material 30.
  • the material of the flexible substrate 10 may be a flexible material commonly used in the prior art to make a substrate, for example, it may be at least one of polyimide, polycarbonate, and polyethylene terephthalate.
  • Polyimide has excellent mechanical properties, its tensile strength is above 100Mpa, and its impact strength can also reach 200KJ/m2;
  • polycarbonate is a tough thermoplastic resin with high strength, high elasticity and high impact strength ;
  • Polyethylene terephthalate has good mechanical properties, impact strength is 3 to 5 times that of other films, and good folding resistance, so polyimide, polycarbonate and polyethylene terephthalate Any one or a combination of esters can be used as the flexible substrate 10.
  • the flexible substrate 10 is polyimide.
  • the driving circuit layer 20 is formed on one side of the substrate 10 and includes a plurality of thin film transistors.
  • the thin film transistors may be top gate type or bottom gate type. In the embodiment of the present application, they are top gate type thin film transistors.
  • the driving circuit layer 20 includes an active layer 21, a gate insulating layer 22, a gate layer, an interlayer insulating layer 24, a source and drain layer, and a planarization layer 27 that are stacked.
  • the active layer 21 is provided on one side of the substrate 10.
  • the material of the active layer 21 may be an oxide semiconductor, an inorganic semiconductor or an organic semiconductor.
  • it may include zinc oxide (ZnOx), gallium oxide (GaOx), TiOx, oxide Tin (SnOx), indium oxide (InOx), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide ( ZTO), zinc zirconium oxide (ZnZrxOy), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc. At least one of them.
  • the gate insulating layer 22 is formed on a side of the active layer 21 away from the substrate 10, and the gate insulating layer 22 may include an organic material or an inorganic material.
  • the gate layer is formed on the side of the gate insulating layer 22 away from the active layer 21, and the gate 23 is patterned.
  • the material of the gate 23 can be metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. , Such as gold (Au), silver (Ag), aluminum (Al), aluminum alloy, aluminum nitride (AlNx), silver alloy, tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, Nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride At least one of (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), and
  • the interlayer insulating layer 24 is formed on the side of the gate 23 away from the gate insulating layer 22.
  • the material of the interlayer insulating layer 24 can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and carbon oxide. At least one of silicon (SiOxCy), silicon carbonitride (SiCxNy), hafnium oxide (HfOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), titanium oxide (TiOx), and tantalum oxide (TaOx).
  • the source and drain layer is formed on the side of the interlayer insulating layer 24 away from the gate 23, and patterned to form the source 25 and the drain 26.
  • the material of the source 25 and the drain 26 can be metal, alloy, metal nitride, conductive Metal oxides or transparent conductive materials, such as aluminum (Al), aluminum alloy, aluminum nitride (AlNx), silver (Ag), silver alloy, tungsten (W), tungsten nitride (WNx), copper (Cu ), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta ), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), in
  • the active layer 21 includes a source region corresponding to the source 25, a drain region corresponding to the drain 26, and a channel region between the source region and the drain region (none of the drawings).
  • the gate insulating layer 23 and the interlayer insulating layer 24 are formed with a groove, and the source electrode 25 is connected to the active layer 21 through the groove; in the drain region, the gate insulating layer 23 and the interlayer insulating layer 24 is also formed with a groove, and the drain electrode 26 is connected to the active layer 21 through the groove.
  • the planarization layer 27 is formed on the side of the source electrode 25 and the drain electrode 26 away from the interlayer insulating layer 24, and the planarization layer 27 may be an organic or inorganic material.
  • the bending material layer 30 is a material with strong ability to bend, stretch, and deform and recover, such as polyimide, polyurethane, and the like.
  • the material of the bending material layer 30 and the material of the flexible substrate 10 may be the same or different.
  • At least one of the active layer 21, the gate insulating layer 22, the gate layer, the interlayer insulating layer 24, the source and drain layers, and the planarization layer 27 is formed with a groove, and the bending material layer 30 is formed in the groove.
  • the bending material layer 30 is arranged in the driving circuit layer 20 in various ways.
  • the grooves can be formed in only one film layer, that is, the bending material layer 30 can be provided in only one film layer; or the grooves can be formed in several film layers at the same time, that is, the grooves can be provided in several film layers at the same time.
  • the material layer 30 is bent.
  • the number of grooves in each film layer can be one or more.
  • only one film layer in the driving circuit layer 20 is formed with a groove, and in the film layer formed with the groove, a groove is formed on each film layer.
  • a groove is formed in the gate insulating layer 22, no groove is formed in other film layers, and the bending material layer 30 is formed in the groove in the gate insulating layer 22.
  • the depth of the groove may be less than the thickness of the gate insulating layer 22, that is, the groove does not penetrate the gate insulating layer 22, and the bending material layer 30 is formed on the gate insulating layer 22; the depth of the groove may also be equal to the thickness of the gate insulating layer 22, That is, the groove forms a through hole, and the bending material layer 30 is formed on the substrate 10.
  • the present application does not limit the depth of the groove. It can penetrate the entire film layer or not. Those skilled in the art can according to their needs. design.
  • a groove is formed in the active layer 21, and no groove is formed in other film layers, and the bending material layer 30 is formed in the groove of the active layer 21.
  • a groove is formed in the gate layer, and no groove is formed in other film layers, and the bending material layer 30 is formed in the groove of the gate layer.
  • a groove is formed in the interlayer insulating layer 24, and no groove is formed in other film layers, and the bending material layer 30 is formed in the groove of the interlayer insulating layer 24.
  • a groove is formed in the source and drain layer, and no groove is formed in other film layers, and the bending material layer 30 is formed in the groove of the source and drain layer.
  • a groove is formed in the planarization layer 27, and no groove is formed in other film layers, and the bending material layer 30 is formed in the groove of the planarization layer 27.
  • a layer of polyimide emulsion is first coated on the glass substrate and cured to form the flexible substrate 10, and then chemical vapor deposition (CVD) or physical vapor deposition (PVD) is used on the flexible substrate 10.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • Perform subsequent film layer preparation and finally peel off the glass substrate to form an array substrate.
  • the flexible substrate 10 has good flexibility, and the bending performance of other film layers on the flexible substrate 10 is not strong.
  • a groove is formed in one of the film layers of the driving circuit layer 20, and a bending material layer 30 is formed in the groove, so that the proportion of the bendable material in the array substrate increases, and the bending performance of the array substrate is improved.
  • the driving circuit layer 20 further includes a buffer layer, which is disposed between the substrate 10 and the active layer 21.
  • a groove may also be provided in the buffer layer, and a bending material layer 30 is formed in the groove.
  • this application takes a top-gate thin film transistor as an example, but it is not limited to this. It is also applicable to other types of thin film transistors, and the bending material layer 30 can also be formed in a corresponding film layer.
  • the array substrate includes a flexible substrate 10, a driving circuit layer 20, and at least one layer of bending material 30, wherein the driving circuit layer 20 includes an active layer 21, a gate insulating layer 22, a gate layer, and an interlayer insulating layer 24 that are stacked. , The source and drain layers, and the planarization layer 27.
  • At least two film layers in the driving circuit layer 20 are provided with grooves, and in the film layers with grooves, one groove is formed on each film layer.
  • a groove is formed in the gate insulating layer 22, a groove is formed in the interlayer insulating layer 24, and no groove is formed in other film layers.
  • the bending material layer 30 is formed on the gate insulating layer 22 and In the groove in the interlayer insulating layer 24.
  • the projections of the two grooves on the flexible substrate 10 may or may not overlap.
  • the inner array substrate can be bent or folded.
  • the gate insulating layer 22 can be formed first and patterned to form the groove, and then a layer of bending material 30 is formed in the groove.
  • the interlayer insulating layer 24 is patterned to form a groove, and another layer of bending material 30 is formed in the groove; it is also possible to form the gate insulating layer 22 and the interlayer insulating layer 24 first, and then pattern the two layers to form Two grooves, the projections of the two grooves on the flexible substrate 10 overlap, and finally a bending material layer 30 is formed in the two grooves.
  • the projections of the two grooves on the flexible substrate 10 do not overlap, that is, when the bending material layers 30 in the two film layers are formed in different regions, the bending performance of the entire array substrate is enhanced, and the array substrate can be bent over the entire surface.
  • FIG. 2 only shows one case where at least two layers of bending material 30 are formed in the driving circuit layer 20.
  • the bending material layer 30 can be formed in any of the several film layers in the driving circuit layer 20, and these several film layers may or may not be adjacent, and the grooves on the several film layers are on the flexible substrate 10.
  • the projections of, may or may not overlap, and the forming method and forming position are similar to those in the embodiment in FIG. 1 and FIG. 2, and will not be repeated here.
  • the number of layers of the bending material layer 30 is equal to the number of layers of the driving circuit layer 20, and the bending effect is best at this time.
  • grooves are formed in at least two of the active layer 21, the gate insulating layer 22, the gate layer, the interlayer insulating layer 24, the source and drain layers, and the planarization layer 27, and a bent material is formed in the grooves
  • the layer 30 increases the proportion of bendable materials in the array substrate and improves the bending performance of the array substrate.
  • the array substrate includes a flexible substrate 10, a driving circuit layer 20, and at least one layer of bending material 30, wherein the driving circuit layer 20 includes an active layer 21, a gate insulating layer 22, a gate layer, and an interlayer insulating layer 24 that are stacked. , The source and drain layers, and the planarization layer 27.
  • At least one film layer in the driving circuit layer 20 is formed with grooves, and among the film layers formed with the grooves, at least one film layer is formed with at least two grooves.
  • a groove is formed in the gate insulating layer 22
  • a bending material layer 30 is formed in the groove
  • two grooves are formed in the interlayer insulating layer 24.
  • a bending material layer 30 is formed in the two grooves
  • a groove is formed in the planarization layer 27, and a bending material layer 30 is formed in the groove.
  • the groove may be formed in only one film layer of the driving circuit layer 20, and the bending material layer 30 may be arranged in the groove, or the groove may be formed in two film layers, or in three film layers. Grooves are formed in the layers, and in the film layer with grooves, at least one film layer is formed with at least two grooves. At this time, the bending material layer 30 is formed in different areas of the array substrate. The bending performance is enhanced, and the array substrate can be bent over the entire surface.
  • a groove is formed in at least one layer of the driving circuit layer 20, and in the film layer formed with the groove, at least one film layer is formed with at least two grooves, and a bending material layer is formed in the groove 30.
  • the proportion of bendable materials in the array substrate is increased, and the bending performance of the array substrate is improved.
  • a groove is formed in at least one layer of the driving circuit layer 20, and a bending material layer 30 is filled in the groove, thereby improving the bending performance of the array substrate. It is also possible to improve the bending performance of the array substrate by forming a bending material layer 30 between at least two adjacent film layers in the driving circuit layer 20.
  • the array substrate includes a flexible substrate 10, a driving circuit layer 20, and at least one layer of bending material 30, wherein the driving circuit layer 20 includes an active layer 21, a gate insulating layer 22, a gate layer, and an interlayer insulating layer 24 that are stacked. , The source and drain layers, and the planarization layer 27.
  • a layer of bending material 30 is formed in the driving circuit layer 20.
  • a bending material layer 30 is formed between the active layer 21 and the gate insulating layer 22, and a bending material layer 30 is not formed between other film layers.
  • a bending material layer 30 is formed between the gate insulating layer 22 and the gate layer, and no bending material layer 30 is formed between other film layers.
  • a bending material layer 30 is formed between the gate layer and the interlayer insulating layer 24, and no bending material layer 30 is formed between other film layers.
  • a bending material layer 30 is formed between the interlayer insulating layer 24 and the source and drain layers, and no bending material layer 30 is formed between other film layers.
  • a bending material layer 30 is formed between the source and drain layer and the planarization layer 27, and no bending material layer 30 is formed between other film layers.
  • the bending material layer 30 formed between two film layers is provided with via holes
  • the bending material layer 30 also needs to be provided with corresponding via holes in the area where the via holes are located. Ensure that the wiring in the driving circuit layer 20 is normal.
  • a layer of polyimide emulsion is first coated on the glass substrate and cured to form the flexible substrate 10, and then chemical vapor deposition (CVD) or physical vapor deposition (PVD) is used on the flexible substrate 10.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • other methods to form each film layer in the drive circuit layer 20 wherein after a certain layer of the drive circuit layer 20 is prepared, a layer of bending material 30 is coated or evaporated or deposited on the entire surface of the layer, Then the subsequent film layer is prepared, and finally the glass substrate is peeled off to form an array substrate.
  • the bending material layer 30 is formed between any two adjacent film layers of the driving circuit layer 20, that is, the bending material layer 30 is laid on the entire array substrate, so that the bending performance of the entire array substrate is enhanced, and the array substrate The whole surface can be bent.
  • the array substrate includes a flexible substrate 10, a driving circuit layer 20, and at least one layer of bending material 30, wherein the driving circuit layer 20 includes an active layer 21, a gate insulating layer 22, a gate layer, and an interlayer insulating layer 24 that are stacked. , The source and drain layers, and the planarization layer 27.
  • the bending material layer 30 may be disposed between any two adjacent film layers, and more bending material layers 30 may be disposed. Those skilled in the art can set the position of the bending material layer 30 in the driving circuit layer 20 and the number of the bending material layer 30 as required.
  • a bending material layer 30 is provided between the active layer 21 and the gate insulating layer 22, Furthermore, a bending material layer 30 is also provided between the gate insulating layer 22 and the gate layer, and no bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the active layer 21 and the gate insulating layer 22, and a bending material layer 30 is also provided between the gate layer and the interlayer insulating layer 24. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the active layer 21 and the gate insulating layer 22, and a bending material layer 30 is also provided between the interlayer insulating layer 24 and the source and drain layers. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the active layer 21 and the gate insulating layer 22, and a bending material layer 30 is also provided between the source drain layer and the planarization layer 27, No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the gate insulating layer 22 and the gate layer, and a bending material layer 30 is also provided between the gate layer and the interlayer insulating layer 24. No bending material layer 30 is provided between the film layers.
  • a bending material layer 30 is provided between the gate insulating layer 22 and the gate layer, and a bending material layer 30 is also provided between the interlayer insulating layer 24 and the source and drain layers. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the gate insulating layer 22 and the gate layer, and a bending material layer 30 is also provided between the source and drain layer and the planarization layer 27. No bending material layer 30 is provided between the film layers.
  • a bending material layer 30 is provided between the gate layer and the interlayer insulating layer 24, and a bending material layer 30 is also provided between the interlayer insulating layer 24 and the source and drain layers. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the gate layer and the interlayer insulating layer 24, and a bending material layer 30 is also provided between the source and drain layer and the planarization layer 27. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the interlayer insulating layer 24 and the source and drain layers, and a bending material layer 30 is also provided between the source and drain layers and the planarization layer 27, No bending material layer 30 is provided between other film layers.
  • the gate layer A bending material layer 30 is provided between the insulating layer 24 and the interlayer insulating layer 24, and no bending material layer 30 is provided between other film layers.
  • a bending material layer is provided between the active layer 21 and the gate insulating layer 22, between the gate insulating layer 22 and the gate layer, and between the interlayer insulating layer 24 and the source and drain layers. 30. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the active layer 21 and the gate insulating layer 22, between the gate insulating layer 22 and the gate layer, and between the source drain layer and the planarization layer 27. , No bending material layer 30 is provided between other film layers.
  • a bending material is provided between the active layer 21 and the gate insulating layer 22, between the gate layer and the interlayer insulating layer 24, and between the interlayer insulating layer 24 and the source and drain layers.
  • Layer 30, no bending material layer 30 is provided between other film layers.
  • a layer of bending material is provided between the active layer 21 and the gate insulating layer 22, between the gate layer and the interlayer insulating layer 24, and between the source and drain layers and the planarization layer 27. 30. No bending material layer 30 is provided between other film layers.
  • a bending material is provided between the active layer 21 and the gate insulating layer 22, between the interlayer insulating layer 24 and the source and drain layers, and between the source and drain layers and the planarization layer 27.
  • Layer 30, no bending material layer 30 is provided between other film layers.
  • a bending material layer is provided between the gate insulating layer 22 and the gate layer, between the gate layer and the interlayer insulating layer 24, and between the interlayer insulating layer 24 and the source and drain layers. 30. No bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the gate insulating layer 22 and the gate layer, between the gate layer and the interlayer insulating layer 24, and between the source and drain layers and the planarization layer 27. , No bending material layer 30 is provided between other film layers.
  • a bending material layer is provided between the gate layer and the interlayer insulating layer 24, between the interlayer insulating layer 24 and the source and drain layers, and between the source and drain layers and the planarization layer 27. 30. No bending material layer 30 is provided between other film layers.
  • the gate A bending material layer 30 is provided between the layers and the interlayer insulating layer 24, and between the interlayer insulating layer 24 and the source and drain layers, and no bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the layers 27, and no bending material layer 30 is provided between other film layers.
  • a bending material layer 30 is provided between the chemical layers 27, and no bending material layer 30 is provided between other film layers.
  • the bending material layer 30 formed between two film layers is provided with via holes
  • the bending material layer 30 also needs to be provided with corresponding via holes in the area where the via holes are located. Ensure that the wiring in the driving circuit layer 20 is normal.
  • the bending material layer 30 is formed between any two adjacent film layers of the driving circuit layer 20, that is, the bending material layer 30 is laid on the entire array substrate, so that the bending performance of the entire array substrate is enhanced, and the array substrate The whole surface can be bent.
  • the present application provides an array substrate, including a flexible substrate, a driving circuit layer and at least one layer of bending material.
  • the driving circuit layer is formed on one side of the flexible substrate; at least one layer of bending material is formed in the driving circuit layer. .
  • the bending performance of the array substrate is enhanced.

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  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本申请提供一种阵列基板，包括柔性衬底、驱动电路层和至少一层弯折材料层，驱动电路层形成在柔性衬底的一侧；至少一层弯折材料层形成在驱动电路层内。通过在驱动电路层内设置至少一层弯折材料层，增强了阵列基板的弯折性能。

Description

阵列基板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板。
 背景技术
随着显示行业技术的发展，可弯折的显示面板成为未来的发展趋势，为实现弯折，通常都需要阵列基板具有较好的弯折性能，然而现有的阵列基板弯折性能不佳，难以满足现显示面板的弯折需求。
因此，现有的显示面板存在阵列基板弯折性能不佳的技术问题，需要改进。
 技术问题
本申请提供一种阵列基板，以缓解现有的阵列基板弯折性能不佳的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
柔性衬底；
驱动电路层，形成在所述柔性衬底的一侧；
至少一层弯折材料层，形成在所述驱动电路层内。
在本申请的阵列基板中，所述弯折材料层与所述柔性衬底的材料相同。
在本申请的阵列基板中，所述驱动电路层包括形成在所述柔性衬底一侧的有源层、形成在所述有源层远离所述衬底一侧的栅绝缘层、形成在所述栅绝缘层远离所述有源层一侧的栅极层、形成在所述栅极层远离所述栅绝缘层一侧的层间绝缘层、形成在所述层间绝缘层远离所述栅极层一侧的源漏极层、形成在所述源漏极远离所述层间绝缘层一侧的平坦化层，所述有源层、所述栅绝缘层、所述栅极层、所述层间绝缘层、所述源漏极层以及所述平坦化层中的至少一个膜层中形成有凹槽，所述弯折材料层形成在所述凹槽中的至少一个膜层中形成有凹槽，所述弯折材料层形成在所述凹槽中。
在本申请的阵列基板中，形成有凹槽的膜层中，每个膜层上形成有一个凹槽。
在本申请的阵列基板中，所述驱动电路层的至少两个膜层中形成有凹槽，所有凹槽在所述柔性衬底上的投影重合。
在本申请的阵列基板中，所述驱动电路层的至少两个膜层中形成有凹槽，至少两个凹槽在所述柔性衬底上的投影不重合。
在本申请的阵列基板中，形成有凹槽的膜层中，至少有一个膜层上形成有至少两个凹槽。
在本申请的阵列基板中，所述驱动电路层包括形成在所述柔性衬底一侧的有源层、形成在所述有源层远离所述衬底一侧的栅绝缘层、形成在所述栅绝缘层远离所述有源层一侧的栅极层、形成在所述栅极层远离所述栅绝缘层一侧的层间绝缘层、形成在所述层间绝缘层远离所述栅极层一侧的源漏极层、形成在所述源漏极远离所述层间绝缘层一侧的平坦化层，所述驱动电路层中的至少两个相邻膜层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述有源层和所述栅绝缘层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅绝缘层和所述栅极层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅极层和所述层间绝缘层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅绝缘层和所述栅极层之间、所述栅极层和所述层间绝缘层之间、所述层间绝缘层和所述源漏极层之间、所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅绝缘层和所述栅极层之间、所述栅极层和所述层间绝缘层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅绝缘层和所述栅极层之间、所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅绝缘层和所述栅极层之间、所述源漏极层和所述平坦化层形成有所述弯折材料层。
在本申请的阵列基板中，所述栅极层和所述层间绝缘层之间、所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述栅极层和所述层间绝缘层之间、所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
在本申请的阵列基板中，所述层间绝缘层和所述源漏极层之间、所述源漏极层和所述平坦化层形成有所述弯折材料层。
 有益效果
本申请提供一种阵列基板，包括柔性衬底、驱动电路层和至少一层弯折材料层，所述驱动电路层形成在所述柔性衬底的一侧；至少一层弯折材料层形成在所述驱动电路层内。通过在驱动电路层内设置至少一层弯折材料层，增强了阵列基板的弯折性能。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的第一种结构示意图；
图2为本申请实施例提供的阵列基板的第二种结构示意图；
图3为本申请实施例提供的阵列基板的第三种结构示意图；
图4为本申请实施例提供的阵列基板的第四种结构示意图；
图5为本申请实施例提供的阵列基板的第五种结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供一种阵列基板，以缓解现有的阵列基板弯折性能不佳的技术问题。
如图1所示，为本申请实施例提供的阵列基板的第一种结构示意图。阵列基板包括柔性衬底10、驱动电路层20以及至少一层弯折材料层30。
柔性衬底10的材料可以为现有技术中常用于制作衬底的柔性材料，例如可以为聚酰亚胺、聚碳酸酯和聚对苯二甲酸乙二醇酯中的至少一种。聚酰亚胺具有优良的机械性能，其抗张强度在100Mpa以上，冲击强度也能够达到 200KJ/m2；聚碳酸酯是一种强韧的热塑性树脂，具有高强度、高弹性系数和高冲击强度；聚对苯二甲酸乙二醇酯具有良好的力学性能，冲击强度是其他薄膜的3～5倍，耐折性好，因此聚酰亚胺、聚碳酸酯和聚对苯二甲酸乙二醇酯中的任意一种或组合均可以作为柔性衬底10。需要说明的是，本申请不以此为限，还可以是其他材料，例如聚氨酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜和聚萘二甲酸乙二醇酯等，任意一种能够作为柔性衬底的材料均落入本申请的保护范围。在本实施例中，柔性衬底10为聚酰亚胺。
驱动电路层20形成在衬底10的一侧，包括多个薄膜晶体管，薄膜晶体管可以是顶栅型，也可以是底栅型，在本申请实施例中为顶栅型薄膜晶体管。驱动电路层20包括层叠设置的有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27。
有源层21设置在衬底10的一侧，有源层21的材料可以是氧化物半导体、无机半导体或有机半导体等，例如可以包括氧化锌(ZnOx)、氧化镓(GaOx)、TiOx、氧化锡(SnOx)、氧化铟(InOx)、氧化铟镓(IGO)、氧化铟锌(IZO)、氧化铟锡(ITO)、氧化镓锌(GZO)、 氧化锌镁(ZMO)、氧化锌锡(ZTO)、氧化锌锆(ZnZrxOy)、氧化铟镓锌(IGZO)、氧化铟锌锡 (IZTO)、氧化铟镓铪(IGHO)、氧化锡铝锌(TAZO)、氧化铟镓锡(IGTO)等中的至少一种。
栅绝缘层22形成在有源层21远离衬底10的一侧，栅绝缘层22可以包括有机材料或无机材料。
栅极层形成在栅绝缘层22远离有源层21的一侧，图案化形成栅极23，栅极23的材料可以是金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等，例如金(Au)、银(Ag)、铝（Al）、铝合金、氮化铝(AlNx)、银合金、钨(W)、氮化钨(WNx)、铜(Cu)、铜合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、 钼(Mo)、钼合金、钛（Ti）、氮化钛(TiNx)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)等中的至少一种。
层间绝缘层24形成在栅极23远离栅绝缘层22的一侧，层间绝缘层24的材料可以是氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)、碳氧化硅(SiOxCy)、碳氮化硅(SiCxNy)、氧化铪(HfOx)、氧化铝(AlOx)、氧化锆(ZrOx)、氧化钛(TiOx)和氧化钽(TaOx)中的至少一种。
源漏极层形成在层间绝缘层24远离栅极23的一侧，图案化形成源极25和漏极26，源极25和漏极26的材料可以是金属、合金、金属氮化物、导电性金属氧化物或透明导电材料，例如可以包括铝(Al)、铝合金、氮化铝(AlNx)、银(Ag)、银合金、钨(W)、氮化钨(WNx)、铜(Cu)、铜合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼合金、钛(Ti)、氮化钛(TiNx)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、锶钌氧化物(SRO)、氧化锌(ZnOx)、氧化铟锡(ITO)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)和氧化铟锌(IZO)中的至少一种。
有源层21包括对应源极25的源极区、对应漏极26的漏极区、以及位于源极区和漏极区之间的沟道区（图均未示出）。在源极区内，栅绝缘层23和层间绝缘层24形成有凹槽，源极25通过该凹槽与有源层21连接；在漏极区内，栅绝缘层23和层间绝缘层24也形成有凹槽，漏极26通过该凹槽与有源层21连接。
平坦化层27形成在源极25和漏极26远离层间绝缘层24的一侧，平坦化层27可以是有机或无机材料。
在驱动电路层20内，形成有至少一层弯折材料层30。弯折材料层30为可弯曲、拉伸、形变恢复能力较强的材料，例如聚酰亚胺、聚氨酯等。弯折材料层30的材料与柔性衬底10的材料可以相同，也可以不同。
有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27中的至少一个膜层中形成有凹槽，弯折材料层30形成在凹槽中，也即弯折材料层30在驱动电路层20内的设置方式有多种。可以仅在某一个膜层中形成凹槽，即仅在一个膜层中设置弯折材料层30；也可以同时在几个膜层中都形成凹槽，即同时在几个膜层中都设置弯折材料层30。每个膜层中凹槽的数量可以是一个，也可以是多个。
在本实施例中，驱动电路层20中只有一个膜层形成有凹槽，且形成有凹槽的膜层中，每个膜层上形成有一个凹槽。
如图1所示，在栅绝缘层22中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在栅绝缘层22中的凹槽中。凹槽的深度可以小于栅绝缘层22的厚度，即凹槽未贯通栅绝缘层22，弯折材料层30形成在栅绝缘层22上；凹槽的深度也可以等于栅绝缘层22的厚度，即凹槽形成通孔，弯折材料层30形成在衬底10上，本申请对凹槽的深度不做限制，可以是贯通整个膜层，也可以不贯通，本领域的技术人员可根据需要设计。
在一种实施例中，在有源层21中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在有源层21的凹槽中。
在一种实施例中，在栅极层中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在栅极层的凹槽中。
在一种实施例中，在层间绝缘层24中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在层间绝缘层24的凹槽中。
在一种实施例中，在源漏极层中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在源漏极层的凹槽中。
在一种实施例中，在平坦化层27中形成有一个凹槽，在其他膜层中未形成凹槽，弯折材料层30形成在平坦化层27的凹槽中。
在阵列基板的制备过程中，先在玻璃基板上涂布一层聚酰亚胺乳液并固化形成柔性衬底10，再在柔性衬底10上利用化学气相沉积（CVD）或物理气相沉积（PVD）等方式形成驱动电路层20中各膜层并图案化，其中，在需要形成弯折材料层30的膜层中图案化形成凹槽，并在凹槽中涂布或蒸镀弯折材料层30，再进行后续膜层的制备，最后剥离掉玻璃基板，形成阵列基板。
随着显示行业技术的发展，可弯折的显示面板成为未来的发展趋势，为实现弯折，通常都需要阵列基板具有较好的弯折性能，然而现有的阵列基板弯折性能不佳，难以满足现显示面板的弯折需求。
在阵列基板中，柔性衬底10具有良好的柔性，柔性衬底10上的其他膜层弯折性能不强。本申请通过在驱动电路层20的其中一个膜层中形成凹槽，在凹槽中形成弯折材料层30，使得阵列基板中可弯折的材料占比增多，改善了阵列基板的弯折性能。
在一种实施例中，驱动电路层20还包括缓冲层，缓冲层设置在衬底10和有源层21之间，缓冲层中也可以设置凹槽，凹槽中形成弯折材料层30。
需要说明的是，本申请以顶栅型薄膜晶体管为例，但不限于此，对于其他类型的薄膜晶体管也适用，弯折材料层30也可形成在相应的膜层中。
如图2所示，为本申请实施例提供的阵列基板的第二种结构示意图。阵列基板包括柔性衬底10、驱动电路层20以及至少一层弯折材料层30，其中驱动电路层20包括层叠设置的有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27。
在本实施例中，驱动电路层20中有至少两个膜层设置有凹槽，且形成有凹槽的膜层中，每个膜层上形成有一个凹槽。
在图2中，栅绝缘层22中形成有一个凹槽，层间绝缘层24中形成有一个凹槽，且其他膜层中未形成凹槽，弯折材料层30形成在栅绝缘层22和层间绝缘层24中的凹槽内。
两个凹槽在柔性衬底10上的投影可以重合，也可以不重合。
当两个凹槽在柔性衬底10上的投影重合，即两个膜层中弯折材料层30形成在一个区域内时，在该区域内，阵列基板的弯折性能显著增强，在该区域内阵列基板可实现弯曲或折叠。
此时，由于形成凹槽的栅绝缘层22和层间绝缘层24相邻，可以先形成栅绝缘层22并图案化形成凹槽，在凹槽中形成一层弯折材料层30，再形成层间绝缘层24，并图案化形成凹槽，在凹槽中形成另一层弯折材料层30；也可以先形成栅绝缘层22和层间绝缘层24，再图案化这两层，形成两个凹槽，两个凹槽在柔性衬底10上的投影重合，最后再在两个凹槽里形成弯折材料层30。
当两个凹槽在柔性衬底10上的投影不重合，即两个膜层中弯折材料层30形成在不同区域时，整个阵列基板的弯折性能增强，阵列基板可实现整面弯曲。
需要说明的是，图2仅表示驱动电路层20中形成至少两层弯折材料层30的其中一种情况。弯折材料层30可以形成在驱动电路层20中的任意几个膜层中，这几个膜层可以相邻，也可以不相邻，几个膜层上的凹槽在柔性衬底10上的投影可以重合，也可以不重合，形成方式与形成位置与图1和图2中实施例相似，在此不再赘述。
当驱动电路层20的所有的膜层均形成有凹槽时，弯折材料层30的层数与驱动电路层20的层数相等，此时弯折效果最好。
本申请通过在有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层以及平坦化层27中的至少两层形成凹槽，在凹槽中形成弯折材料层30，使得阵列基板中可弯折的材料占比增多，改善了阵列基板的弯折性能。
如图3所示，为本申请实施例提供的阵列基板的第三种结构示意图。阵列基板包括柔性衬底10、驱动电路层20以及至少一层弯折材料层30，其中驱动电路层20包括层叠设置的有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27。
驱动电路层20中的至少一个膜层中形成有凹槽，且形成有凹槽的膜层中，至少有一个膜层上形成有至少两个凹槽。在一种实施例中，如图4所示，栅绝缘层22中形成有一个凹槽，该凹槽内形成有弯折材料层30，层间绝缘层24中形成有两个凹槽，这两个凹槽内形成有弯折材料层30，平坦化层27中形成有一个凹槽，该凹槽内形成有弯折材料层30。
在本实施例中，可以仅在驱动电路层20的一个膜层中形成凹槽，在凹槽内设置弯折材料层30，也可以在两个膜层中形成凹槽，或者在三个膜层中都形成凹槽，形成有凹槽的膜层中，至少有一个膜层上形成有至少两个凹槽，此时弯折材料层30形成在阵列基板的不同区域内，整个阵列基板的弯折性能增强，阵列基板可实现整面弯曲。
本申请通过在驱动电路层20中的至少一层形成凹槽，且形成有凹槽的膜层中，至少有一个膜层上形成有至少两个凹槽，在凹槽中形成弯折材料层30，使得阵列基板中可弯折的材料占比增多，改善了阵列基板的弯折性能。
在图1至图3中，是通过在驱动电路层20中至少一层中形成凹槽，在凹槽中填充弯折材料层30，进而改善阵列基板的弯折性能。还可以通过在驱动电路层20中的至少两个相邻膜层之间形成有弯折材料层30，来改善阵列基板的弯折性能。
如图4所示，为本申请实施例提供的阵列基板的第四种结构示意图。阵列基板包括柔性衬底10、驱动电路层20以及至少一层弯折材料层30，其中驱动电路层20包括层叠设置的有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27。
在本实施例中，驱动电路层20中形成有一层弯折材料层30。
在一种实施例中，如图5所示，有源层21和栅绝缘层22之间形成有弯折材料层30，其他膜层之间未形成弯折材料层30。
在一种实施例中，栅绝缘层22和栅极层之间形成有弯折材料层30，其他膜层之间未形成弯折材料层30。
在一种实施例中，栅极层和层间绝缘层24之间形成有弯折材料层30，其他膜层之间未形成弯折材料层30。
在一种实施例中，层间绝缘层24和源漏极层之间形成有弯折材料层30，其他膜层之间未形成弯折材料层30。
在一种实施例中，源漏极层和平坦化层27之间形成有弯折材料层30，其他膜层之间未形成弯折材料层30。
需要说明的是，形成在两个膜层之间的弯折材料层30，在膜层中设置有过孔时，在过孔所在区域，弯折材料层30也需要设置相应的过孔，以保证驱动电路层20中走线正常。
在阵列基板的制备过程中，先在玻璃基板上涂布一层聚酰亚胺乳液并固化形成柔性衬底10，再在柔性衬底10上利用化学气相沉积（CVD）或物理气相沉积（PVD）等方式形成驱动电路层20中的各膜层，其中，在驱动电路层20的某一层制备完成后，在该层上整面涂布或蒸镀或沉积一层弯折材料层30，再进行后续膜层的制备，最后剥离掉玻璃基板，形成阵列基板。
本申请通过在驱动电路层20的任意两相邻膜层之间形成弯折材料层30，即弯折材料层30在阵列基板中整层铺设，使得整个阵列基板的弯折性能增强，阵列基板可实现整面弯曲。
如图5所示，为本申请实施例提供的阵列基板的第五种结构示意图。阵列基板包括柔性衬底10、驱动电路层20以及至少一层弯折材料层30，其中驱动电路层20包括层叠设置的有源层21、栅绝缘层22、栅极层、层间绝缘层24、源漏极层、以及平坦化层27。
在本实施例中，驱动电路层20中形成有至少两层弯折材料层30。在驱动电路层20中，弯折材料层30可以设置在任意两个相邻的膜层之间，且可以设置更多的弯折材料层30。本领域的技术人员可根据需要设置弯折材料层30在驱动电路层20中的位置，以及弯折材料层30的数量。
当驱动电路层20中形成有两层弯折材料层30时，在一种实施例中，如图5所示，在有源层21和栅绝缘层22之间设置有弯折材料层30，且在栅绝缘层22和栅极层之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间设置有弯折材料层30，且在栅极层和层间绝缘层24之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间设置有弯折材料层30，且在层间绝缘层24和源漏极层之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间设置有弯折材料层30，且在源漏极层和平坦化层27之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间设置有弯折材料层30，且在栅极层和层间绝缘层24之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间设置有弯折材料层30，且在层间绝缘层24和源漏极层之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间设置有弯折材料层30，且在源漏极层和平坦化层27之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅极层和层间绝缘层24之间设置有弯折材料层30，且在层间绝缘层24和源漏极层之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅极层和层间绝缘层24之间设置有弯折材料层30，且在源漏极层和平坦化层27之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在层间绝缘层24和源漏极层之间设置有弯折材料层30，且在源漏极层和平坦化层27之间也设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
当驱动电路层20中形成有三层弯折材料层30时，在一种实施例中，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、层间绝缘层24和源漏极层之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、栅极层和层间绝缘层24之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、层间绝缘层24和源漏极层之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
当驱动电路层20中形成有四层弯折材料层30时，在一种实施例中，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
在一种实施例中，在栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间、源漏极层和平坦化层27之间均设置有弯折材料层30，在其他膜层之间未设置弯折材料层30。
当驱动电路层20中形成有五层弯折材料层30时，在有源层21和栅绝缘层22之间、栅绝缘层22和栅极层之间、栅极层和层间绝缘层24之间、层间绝缘层24和源漏极层之间、源漏极层和平坦化层27之间均设置有弯折材料层30。
需要说明的是，形成在两个膜层之间的弯折材料层30，在膜层中设置有过孔时，在过孔所在区域，弯折材料层30也需要设置相应的过孔，以保证驱动电路层20中走线正常。
本申请通过在驱动电路层20的任意两相邻膜层之间形成弯折材料层30，即弯折材料层30在阵列基板中整层铺设，使得整个阵列基板的弯折性能增强，阵列基板可实现整面弯曲。
根据上述实施例可知：
本申请提供一种阵列基板，包括柔性衬底、驱动电路层和至少一层弯折材料层，驱动电路层形成在柔性衬底的一侧；至少一层弯折材料层形成在驱动电路层内。通过在驱动电路层内设置至少一层弯折材料层，增强了阵列基板的弯折性能。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    柔性衬底；
    驱动电路层，形成在所述柔性衬底的一侧；
    至少一层弯折材料层，形成在所述驱动电路层内。
  2. 如权利要求1所述的阵列基板，其中，所述弯折材料层与所述柔性衬底的材料相同。
  3. 如权利要求1所述的阵列基板，其中，所述驱动电路层包括形成在所述柔性衬底一侧的有源层、形成在所述有源层远离所述衬底一侧的栅绝缘层、形成在所述栅绝缘层远离所述有源层一侧的栅极层、形成在所述栅极层远离所述栅绝缘层一侧的层间绝缘层、形成在所述层间绝缘层远离所述栅极层一侧的源漏极层、形成在所述源漏极远离所述层间绝缘层一侧的平坦化层，所述有源层、所述栅绝缘层、所述栅极层、所述层间绝缘层、所述源漏极层以及所述平坦化层中的至少一个膜层中形成有凹槽，所述弯折材料层形成在所述凹槽中。
  4. 如权利要求3所述的阵列基板，其中，形成有凹槽的膜层中，每个膜层上形成有一个凹槽。
  5. 如权利要求4所述的阵列基板，其中，所述驱动电路层的至少两个膜层中形成有凹槽，所有凹槽在所述柔性衬底上的投影重合。
  6. 如权利要求4所述的阵列基板，其中，所述驱动电路层的至少两个膜层中形成有凹槽，至少两个凹槽在所述柔性衬底上的投影不重合。
  7. 如权利要求3所述的阵列基板，其中，形成有凹槽的膜层中，至少有一个膜层上形成有至少两个凹槽。
  8. 如权利要求1所述的阵列基板，其中，所述驱动电路层包括形成在所述柔性衬底一侧的有源层、形成在所述有源层远离所述衬底一侧的栅绝缘层、形成在所述栅绝缘层远离所述有源层一侧的栅极层、形成在所述栅极层远离所述栅绝缘层一侧的层间绝缘层、形成在所述层间绝缘层远离所述栅极层一侧的源漏极层、形成在所述源漏极远离所述层间绝缘层一侧的平坦化层，所述驱动电路层中的至少两个相邻膜层之间形成有所述弯折材料层。
  9. 如权利要求8所述的阵列基板，其中，所述有源层和所述栅绝缘层之间形成有所述弯折材料层。
  10. 如权利要求8所述的阵列基板，其中，所述栅绝缘层和所述栅极层之间形成有所述弯折材料层。
  11. 如权利要求8所述的阵列基板，其中，所述栅极层和所述层间绝缘层之间形成有所述弯折材料层。
  12. 如权利要求8所述的阵列基板，其中，所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
  13. 如权利要求8所述的阵列基板，其中，所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
  14. 如权利要求8所述的阵列基板，其中，所述栅绝缘层和所述栅极层之间、所述栅极层和所述层间绝缘层之间、所述层间绝缘层和所述源漏极层之间、所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
  15. 如权利要求8所述的阵列基板，其中，所述栅绝缘层和所述栅极层之间、所述栅极层和所述层间绝缘层之间形成有所述弯折材料层。
  16. 如权利要求8所述的阵列基板，其中，所述栅绝缘层和所述栅极层之间、所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
  17. 如权利要求8所述的阵列基板，其中，所述栅绝缘层和所述栅极层之间、所述源漏极层和所述平坦化层形成有所述弯折材料层。
  18. 如权利要求8所述的阵列基板，其中，所述栅极层和所述层间绝缘层之间、所述层间绝缘层和所述源漏极层之间形成有所述弯折材料层。
  19. 如权利要求8所述的阵列基板，其中，所述栅极层和所述层间绝缘层之间、所述源漏极层和所述平坦化层之间形成有所述弯折材料层。
  20. 如权利要求8所述的阵列基板，其中，所述层间绝缘层和所述源漏极层之间、所述源漏极层和所述平坦化层形成有所述弯折材料层。
PCT/CN2019/094690 2019-05-17 2019-07-04 阵列基板 Ceased WO2020232801A1 (zh)

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