WO2020230668A1 - 画像表示装置の製造方法および画像表示装置 - Google Patents

画像表示装置の製造方法および画像表示装置 Download PDF

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Publication number
WO2020230668A1
WO2020230668A1 PCT/JP2020/018398 JP2020018398W WO2020230668A1 WO 2020230668 A1 WO2020230668 A1 WO 2020230668A1 JP 2020018398 W JP2020018398 W JP 2020018398W WO 2020230668 A1 WO2020230668 A1 WO 2020230668A1
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Prior art keywords
layer
light emitting
light
image display
insulating film
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PCT/JP2020/018398
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English (en)
French (fr)
Japanese (ja)
Inventor
秋元　肇
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Nichia Corp
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Nichia Corp
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Priority to JP2021519382A priority Critical patent/JP7432845B2/ja
Priority to CN202080043755.3A priority patent/CN113994486A/zh
Priority to KR1020217034936A priority patent/KR102804328B1/ko
Publication of WO2020230668A1 publication Critical patent/WO2020230668A1/ja
Priority to US17/522,497 priority patent/US12255276B2/en
Anticipated expiration legal-status Critical
Priority to US19/055,986 priority patent/US20250194315A1/en
Ceased legal-status Critical Current

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    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H10H20/841—Reflective coatings, e.g. dielectric Bragg reflectors
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
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    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
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    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
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    • H10H20/01—Manufacture or treatment
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    • H10H20/01—Manufacture or treatment
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    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
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    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout

Definitions

  • An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device.
  • a self-luminous element As a self-luminous element, the appearance of a display device using a micro LED, which is a fine light emitting element, is expected.
  • a method of manufacturing a display device using micro LEDs a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced.
  • the number of micro LED elements increases as the image quality becomes higher, such as full high-definition, 4K, 8K, etc.
  • a large number of micro LEDs may be individually formed and transferred sequentially to a substrate on which a drive circuit or the like is formed.
  • the transfer process requires a huge amount of time. Further, a poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.
  • a technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the electrodes are attached to a circuit board on which a drive circuit is formed (for example, Patent Document 1).
  • One embodiment of the present invention provides a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved.
  • the method for manufacturing an image display device includes a step of preparing a substrate having a semiconductor layer including a light emitting layer on the first substrate and a second substrate on which a circuit including a circuit element is formed.
  • the light-shielding layer is provided between the light emitting element and the circuit element.
  • the light-shielding layer is provided so as to cover the circuit element in a plan view.
  • An image display device includes a circuit element, a first wiring layer electrically connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer.
  • a light emitting element provided on the first insulating film, a light-shielding layer provided between the circuit element and the light emitting element in the first insulating film, and at least a part of the light emitting element. It includes a second insulating film that covers the light emitting element, and a second wiring layer that is electrically connected to the light emitting element and is arranged on the second insulating film.
  • the light emitting element has a first conductive type first semiconductor layer, a light emitting layer provided on the first semiconductor layer, and a second conductive type provided on the light emitting layer and different from the first conductive type. Includes a second semiconductor layer.
  • the light-shielding layer is provided so as to cover the circuit element in a plan view.
  • the image display device includes a plurality of transistors, a first wiring layer electrically connected to the plurality of conductors, the plurality of transistors, and a first insulation covering the first wiring layer.
  • a second insulating film that covers the first insulating film and at least a part of the second semiconductor layer, and the second semiconductor layer that is exposed from the second insulating film according to the plurality of conductors.
  • the second wiring layer connected to the transparent electrodes arranged on the plurality of exposed surfaces of the above, the first insulating film and the second insulating film, and the wiring of the first wiring layer and the second wiring. It includes vias that electrically connect the wiring of the layers.
  • the light-shielding layer is provided between the light emitting element and the plurality of transistors. The light-shielding layer is provided so as to cover the circuit element in a plan view.
  • a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved are realized.
  • FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the embodiment.
  • FIG. 1 schematically shows the configuration of the sub-pixel 20 of the image display device of the present embodiment.
  • the pixel 10 constituting the image displayed on the image display device is composed of a plurality of subpixels 20. In the following, it may be described using the three-dimensional coordinate system of XYZ.
  • the subpixels 20 are arranged on a two-dimensional plane. Let the two-dimensional plane in which the subpixels 20 are arranged be the XY plane.
  • the subpixels 20 are arranged along the X-axis direction and the Y-axis direction.
  • the subpixel 20 has a light emitting surface 153S substantially parallel to the XY plane.
  • the light emitting surface 153S mainly outputs light in the positive direction of the Z axis orthogonal to the XY plane.
  • FIG. 1 schematically shows a cross section when the subpixel 20 is cut along a plane parallel to the XZ plane.
  • the subpixel 20 of the image display device includes a transistor 103, a first wiring layer (first wiring layer) 110, a first interlayer insulating film (first insulating film) 112, and light shielding.
  • a layer 120, a light emitting element 150, a second interlayer insulating film (second insulating film) 156, a second wiring layer (second wiring layer) 160, and a via 161d are provided.
  • the subpixel 20 further includes a color filter 180.
  • the color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin film adhesive layer 188.
  • the surface resin layer 170 is provided on the light emitting element 150, the interlayer insulating film 156, and the wiring layer 160.
  • the transistor 103 is formed on the substrate 102.
  • circuit elements such as other transistors, resistors, and capacitors are formed on the substrate 102, and the circuit 101 is composed of wiring and the like.
  • the transistor 103 corresponds to the drive transistor 26 shown in FIG. 3, which will be described later, and the selection transistor 24, the capacitor 28, and the like are other circuit elements.
  • the circuit 101 includes an element forming region 104 in which a circuit element is formed, an insulating layer 105, a wiring layer 110, a via connecting the wiring layer 110 and the circuit element, and an insulating film 108 that insulates between the circuit elements. ..
  • the circuit board 100 may include other components such as the substrate 102, the circuit 101, and the interlayer insulating film 112. Further, as will be described in detail later, the light-shielding layer 120 is provided in the interlayer insulating film 112, and the circuit board 100 includes the light-shielding layer 120.
  • the transistor 103 includes a p-type semiconductor region 104b, an n-type semiconductor region 104s and 104d, and a gate 107.
  • the gate 107 is provided on the p-type semiconductor region 104b via the insulating layer 105.
  • the insulating layer 105 is provided to insulate the element forming region 104 and the gate 107 and to sufficiently insulate the other adjacent circuit elements. When a voltage is applied to the gate 107, a channel can be formed in the p-type semiconductor region 104b.
  • the transistor 103 is an n-channel transistor, for example, an n-channel MOSFET.
  • the element forming region 104 is provided on the substrate 102.
  • the substrate 102 is, for example, a Si substrate.
  • the element forming region 104 includes a p-type semiconductor region 104b and an n-type semiconductor region 104s and 104d.
  • the p-type semiconductor region 104b is provided near the surface of the substrate 102.
  • the n-type semiconductor regions 104s and 104d are provided in the p-type semiconductor region 104b in the vicinity of the surface of the p-type semiconductor region 104b so as to be separated from each other.
  • An insulating layer 105 is provided on the surface of the substrate 102.
  • the insulating layer 105 also covers the element forming region 104, and also covers the surfaces of the p-type semiconductor region 104b and the n-type semiconductor regions 104s and 104d.
  • the insulating layer 105 is, for example, SiO 2 .
  • the insulating layer 105 may be a multi-layered insulating layer containing SiO 2 or Si 3 N 4 depending on the covering region.
  • the insulating layer 105 may include a layer of an insulating material having a high dielectric constant.
  • a gate 107 is provided on the p-type semiconductor region 104b via the insulating layer 105.
  • the gate 107 is provided between the n-type semiconductor regions 104s and 104d.
  • the gate 107 is, for example, polycrystalline Si.
  • the gate 107 may contain silicide or the like having a resistance lower than that of polycrystalline Si.
  • the gate 107 and the insulating layer 105 are covered with the insulating film 108.
  • the insulating film 108 is, for example, SiO 2 or Si 3 N 4 or the like.
  • an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass) may be further provided.
  • a first wiring layer (first wiring layer) 110 is formed on the insulating film 108.
  • the first wiring layer 110 includes a plurality of wirings having different potentials, and includes wirings 110s and 110d. As described above, in the cross-sectional views after FIG. 1, the wiring layer is assumed to display a code at a position next to one wiring included in the wiring layer.
  • Vias 111s and 111d are provided between the wirings 110s and 110d of the wiring layer 110 and the n-type semiconductor regions 104s and 104d, respectively, and are electrically connected to each other.
  • the wiring layer 110 and the vias 111s and 111d are formed of, for example, a metal such as Al or Cu.
  • the wiring layer 110 and the vias 111s and 111d may contain a refractory metal or the like.
  • a first interlayer insulating film 112 is provided on the insulating film 108 and the wiring layer 110.
  • the first interlayer insulating film 112 also functions as a protective film that protects the surface of the circuit board 100.
  • the first interlayer insulating film 112 includes a plurality of insulating layers.
  • the plurality of insulating layers are the first insulating layer 112a and the second insulating layer 112b.
  • the first insulating layer 112a covers the insulating film 108 and the first wiring layer 110.
  • a light-shielding layer 120 is provided on the first insulating layer 112a.
  • the second insulating layer 112b is provided on the light shielding layer 120.
  • the light-shielding layer 120 is provided between the first insulating layer 112a and the second insulating layer 112b.
  • the first insulating layer 112a and the second insulating layer 112b may be made of the same material or may be made of different materials.
  • the first insulating layer 112a may be formed of PSG, BPSG, or the like
  • the second insulating layer 112b may be formed of SOG (Spin On Glass) or the like.
  • SOG Spin On Glass
  • the second insulating layer 112b insulates the light emitting element 150 provided on the light-shielding layer 120 and the light-shielding layer 120.
  • the second insulating layer 112b has a flattened surface for wafer bonding.
  • the light-shielding layer 120 which is a light-shielding layer, has a plane substantially parallel to the XY plane.
  • the light-shielding layer 120 is provided so as to cover the entire circuit element that malfunctions due to the transistor 103 or the irradiation of light.
  • the light-shielding layer 120 covers at least the entire transistor 103 that drives the light-emitting element 150.
  • the light shielding layer 120 covers the entire subpixel 20, and more preferably the entire circuit board 100.
  • the light-shielding layer 120 suppresses the scattered light emitted from the light-emitting element 150 from reaching a circuit element such as a transistor 103 provided below the light-shielding layer 120 to prevent the circuit element from malfunctioning.
  • the light-shielding layer 120 has light reflectivity. Since the light-shielding layer 120 has light reflectivity, the light emitted downward from the light-emitting element 150 is reflected toward the upper light-emitting surface side, so that the luminous efficiency of the light-emitting element 150 can be improved.
  • the light-shielding layer 120 is formed of a material that blocks scattered light emitted from the light-emitting element 150.
  • the light-shielding layer 120 can have light reflectivity by containing a metal material such as Al or Ag.
  • the light-shielding layer 120 may not be connected to any potential, or may be connected to any appropriate potential.
  • the light-shielding layer 120 may be connected to the potential of the GND line 4 (FIG. 3) or the potential of the power supply line 3 (FIG. 3).
  • the light-shielding layer 120 can also be used as auxiliary wiring for the GND line 4 and the power supply line 3.
  • the voltage value for the GND line which is the reference potential, is not limited to the above, and an appropriate value can be arbitrarily set. Since the light-shielding layer 120 can be provided over all the sub-pixels 20, by applying a voltage having a constant potential with respect to the reference potential to the light-shielding layer 120, the effect of suppressing electromagnetic radiation due to the operation of the circuit element can be obtained. Can be held.
  • the light-shielding layer 120 has a through hole 121.
  • the through hole 121 is provided at a position corresponding to the wiring 110d in the XY plan view.
  • a via 161d is inserted through the through hole 121.
  • the material of the second insulating layer 112b is filled between the through hole 121 and the via 161d, and the via 161d and the light-shielding layer 120 are electrically insulated.
  • the light emitting element 150 includes an n-type semiconductor layer (first semiconductor layer) 151, a light emitting layer 152, and a p-type semiconductor layer (second semiconductor layer) 153.
  • the n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the interlayer insulating film 112 of the circuit board 100 toward the positive direction of the Z axis, that is, toward the light emitting surface 153S. That is, in this example, the n-type semiconductor layer 151 of the light emitting element 150 is provided on the second insulating layer 112b of the interlayer insulating film 112.
  • the light emitting element 150 has, for example, a substantially square or rectangular shape in XY plan view, but the corners may be rounded.
  • the light emitting element 150 may have, for example, an elliptical shape or a circular shape in an XY plan view.
  • the degree of freedom in layout is improved by appropriately selecting the shape and arrangement of the light emitting elements in a plan view.
  • the n-type semiconductor layer 151 has a stepped portion 151a extending on the second insulating layer 112b in the X-axis direction.
  • the light emitting element 150 for example, a nitride semiconductor such as In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) is preferably used.
  • the light emitting element 150 in one embodiment of the present invention is a so-called blue light emitting diode, and the wavelength of the light emitted by the light emitting element 150 is, for example, about 467 nm ⁇ 20 nm.
  • the wavelength of the light emitted by the light emitting element 150 may be bluish purple emission of about 410 nm ⁇ 20 nm.
  • the wavelength of the light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be appropriate.
  • the second interlayer insulating film 156 covers the first interlayer insulating film 112 and the light emitting element 150.
  • the second interlayer insulating film 156 is preferably formed of a white resin.
  • the white resin can be realized, for example, by dispersing scattered particles such as titanium oxide having a fine particle size in an organic material.
  • the light emitting element 150 can reflect the light emitted in the lateral direction or the downward direction, and the brightness of the light emitting element 150 can be substantially improved.
  • the second interlayer insulating film 156 may be a black resin.
  • the interlayer insulating film 156 as a black resin, scattering of light in the subpixels is suppressed, and stray light is suppressed more effectively.
  • An image display device in which stray light is suppressed can display a sharper image.
  • the interlayer insulating film 156 also has a function of protecting the light emitting element 150 and flattening the surface due to the wiring layer 160 formed on the second interlayer insulating film 156.
  • the second interlayer insulating film 156 has an opening 158.
  • the opening 158 is formed by removing a part of the interlayer insulating film 156 above the light emitting element 150.
  • the opening 158 is formed so that the light emitting surface 153S is exposed from the interlayer insulating film 156.
  • the light emitting surface 153S is a surface of the p-type semiconductor layer 153 facing the surface in contact with the light emitting layer 152.
  • the light emitting surface 153S is preferably roughened. When the light emitting surface 153S is a rough surface, the light emitting element 150 can improve the light extraction efficiency.
  • a via 161k is provided so as to penetrate the second interlayer insulating film 156.
  • One end of the via 161k is connected to the step portion 151a.
  • the via 161d is provided so as to penetrate the interlayer insulating films 112 and 156 and the light shielding layer 120. As described above, the via 161d is insulated from the light-shielding layer 120 by the interlayer insulating film 112, and one end of the via 161d is connected to the wiring 110d.
  • the wiring layer 160 is provided on the flattened interlayer insulating film 156.
  • the wiring layer 160 includes wirings 160a and 160k.
  • the wiring 160a is formed by extending to the opening 158, and the tip of the wiring 160a is connected to the light emitting surface 153S. Although not shown in this figure, the wiring 160a is connected to a power line that supplies power to the subpixel 20.
  • the wiring 160k is connected to the other ends of the vias 161k and 161d. Therefore, the n-type semiconductor layer 151 of the light emitting element 150 is electrically connected to the main electrode of the transistor 103 via the vias 161k and 161d and the wirings 160k and 110d.
  • the p-type semiconductor layer 153 of the light emitting element 150 is connected to the power supply line via the wiring 160a.
  • the n-type semiconductor layer 151 of the light emitting element 150 is connected to the drain electrode of the transistor 103 via the via 161k, the wiring 160k, the via 161d, and the wiring 110d.
  • the surface resin layer 170 covers the second interlayer insulating film 156 and the second wiring layer 160.
  • the surface resin layer 170 is a transparent resin and has a flattening surface for protecting the interlayer insulating film 156 and the wiring layer 160 and for adhering the color filter 180.
  • the color filter 180 includes a light-shielding unit 181 and a color conversion unit 182.
  • the color conversion unit 182 is provided directly above the light emitting surface 153S of the light emitting element 150 according to the shape of the light emitting surface 153S.
  • the portion other than the color conversion unit 182 is a light-shielding unit 181.
  • the light-shielding unit 181 is a so-called black matrix, which reduces bleeding due to color mixing of light emitted from the adjacent color conversion unit 182 and makes it possible to display a sharp image.
  • the color conversion unit 182 has one layer or two layers.
  • FIG. 1 shows a two-layer portion. Whether it is one layer or two layers is determined by the color of the light emitted by the subpixel 20, that is, the wavelength.
  • the color conversion unit 182 preferably has two layers.
  • the emission color of the subpixel 20 is blue, it is preferably one layer.
  • the first layer closer to the light emitting element 150 is the color conversion layer 183
  • the second layer is the filter layer 184. That is, the filter layer 184 is laminated on the color conversion layer 183.
  • the color conversion layer 183 is a layer that converts the wavelength of the light emitted by the light emitting element 150 into a desired wavelength.
  • the light having a wavelength of 467 nm ⁇ 20 nm of the light emitting element 150 is converted into light having a wavelength of, for example, about 630 nm ⁇ 20 nm.
  • the light having a wavelength of 467 nm ⁇ 20 nm of the light emitting element 150 is converted into light having a wavelength of, for example, about 532 nm ⁇ 20 nm.
  • the filter layer 184 blocks the wavelength component of blue light emission remaining without color conversion in the color conversion layer 183.
  • the subpixel 20 may output the light through the color conversion layer 183, or outputs the light as it is without passing through the color conversion layer 183. You may do so.
  • the wavelength of the light emitted by the light emitting element 150 is about 467 nm ⁇ 20 nm
  • the subpixel 20 may output the light without passing through the color conversion layer 183.
  • the wavelength of the light emitted by the light emitting element 150 is 410 nm ⁇ 20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ⁇ 20 nm.
  • the subpixel 20 may have a filter layer 184.
  • the filter layer 184 By providing the filter layer 184 on the blue subpixel 20, minute external light reflection generated on the surface of the light emitting element 150 is suppressed.
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating a part of a modification of the image display device of the present embodiment, respectively.
  • the display of the surface resin layer 170 and the color filter 180 is omitted in order to avoid complication.
  • a surface resin layer and a color filter are provided on the second interlayer insulating film and the second wiring layer. The same applies to the cases of other embodiments and modifications thereof described later.
  • the subpixel 20a of the first modification is different from the case of the first embodiment in the connection between the light emitting element 150 and the wiring 160a1.
  • the subpixel 20b of the modification 2 has a different configuration of the interlayer insulating film 156a from the case of the first embodiment, and the connection method of the light emitting element 150 and the wiring 160a2 is different.
  • the other components are the same as those in the first embodiment described above, and the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • the subpixel 20a includes the wiring 160a1 and the wiring 160k, and the transparent electrode 159a and the transparent electrode 159k.
  • the light emitting surface 153S of the light emitting element 150 is preferably roughened as in the case of the first embodiment.
  • the wiring 160a1 is connected to the power supply line 3 shown in FIG. 3, which will be described later.
  • a transparent electrode 159a is provided on the wiring 160a1.
  • the transparent electrode 159a is provided over the entire light emitting surface 153S.
  • the transparent electrode 159a is provided between the wiring 160a1 and the light emitting surface 153S, and the transparent electrode 159a electrically connects the wiring 160a1 and the light emitting surface 153S.
  • the transparent electrode 159k is provided on the wiring 160k.
  • the connection area with the p-type semiconductor layer 153 can be increased, and the luminous efficiency can be improved.
  • the connection area between the light emitting surface 153S and the transparent electrode 159a can be increased, and the contact resistance can be reduced.
  • the second interlayer insulating film 156a is a transparent resin.
  • the light emitting element 150 emits light from the light emitting surface 153S via the transparent interlayer insulating film 156a.
  • the light emitting surface 153S is connected to the wiring 160a2 of the second wiring layer 160 via a contact hole.
  • the light emitting element 150 emits light from the light emitting surface 153S via the interlayer insulating film 156a. Therefore, a step of forming an opening in the interlayer insulating film 156a and a step of roughening the light emitting surface 153S. Can be omitted.
  • any of the configurations of the subpixels 20, 20a, and 20b shown above can be included.
  • FIG. 3 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 1 of the present embodiment includes a display area 2.
  • Subpixels 20 are arranged in the display area 2.
  • the subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.
  • Pixel 10 includes a plurality of subpixels 20 that emit light of different colors.
  • the subpixel 20R emits red light.
  • the subpixel 20G emits green light.
  • the subpixel 20B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by emitting light of the three types of sub-pixels 20R, 20G, and 20B at desired brightness.
  • One pixel 10 includes three sub-pixels 20R, 20G, 20B, and the sub-pixels 20R, 20G, 20B are linearly arranged on the X-axis, for example, as in this example.
  • subpixels of the same color may be arranged in the same column, or subpixels of different colors may be arranged for each column as in this example.
  • the image display device 1 further includes a power supply line 3 and a ground line 4.
  • the power line 3 and the ground line 4 are arranged in a grid pattern along the array of subpixels 20.
  • the power supply line 3 and the ground line 4 are electrically connected to each subpixel 20, and power is supplied to each subpixel 20 from a DC power source connected between the power terminal 3a and the GND terminal 4a.
  • the power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with reference to the GND terminal 4a.
  • the image display device 1 further has a scanning line 6 and a signal line 8.
  • the scanning line 6 is laid out in a direction parallel to the X axis. That is, the scanning lines 6 are laid out along the array in the row direction of the subpixels 20.
  • the signal line 8 is laid out in a direction parallel to the Y axis. That is, the signal line 8 is laid out along the array of the subpixels 20 in the column direction.
  • the image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7.
  • the row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2.
  • the row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2.
  • the row selection circuit 5 is electrically connected to the subpixels 20 of each column via the scanning line 6 to supply a selection signal to each subpixel 20.
  • the signal voltage output circuit 7 is provided along the outer edge of the display area 2.
  • the signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2.
  • the signal voltage output circuit 7 is electrically connected to the subpixel 20 of each line via the signal line 8 to supply a signal voltage to each subpixel 20.
  • the subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28.
  • the selection transistor 24 may be displayed as T1
  • the drive transistor 26 may be displayed as T2
  • the capacitor 28 may be displayed as Cm.
  • the light emitting element 22 is connected in series with the drive transistor 26.
  • the drive transistor 26 is an n-channel MOSFET, and the cathode electrode, which is the n electrode of the light emitting element 22, is connected to the drain electrode, which is the main electrode of the drive transistor 26.
  • the series circuit of the light emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4.
  • the drive transistor 26 corresponds to the transistor 103 in FIG. 1 and the like, and the light emitting element 22 corresponds to the light emitting element 150 in FIG. 1 and the like.
  • the voltage applied between the gate and the source of the drive transistor 26 determines the current flowing through the light emitting element 22, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.
  • the selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode.
  • the gate electrode of the selection transistor 24 is connected to the scanning line 6.
  • a capacitor 28 is connected between the gate electrode of the drive transistor 26 and the ground wire 4.
  • the row selection circuit 5 selects one row from the array of subpixels 20 in the m row and supplies the selection signal to the scanning line 6.
  • the signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value for each subpixel 20 in the selected row.
  • a signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row.
  • the signal voltage is held by the capacitor 28.
  • the drive transistor 26 causes a current corresponding to the signal voltage to flow through the light emitting element 22.
  • the light emitting element 22 emits light with a brightness corresponding to the current flowing through the light emitting element 22.
  • the row selection circuit 5 sequentially switches the rows to be selected and supplies the selection signal. That is, the row selection circuit 5 scans the row in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light emitting element 22 of the subpixel 20 that is sequentially scanned to emit light. Each pixel 10 emits light with an emission color and brightness determined by the emission color and brightness emitted by the sub-pixels 20 of each RGB color, and an image is displayed in the display area 2.
  • FIG. 4A to 7B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • a semiconductor growth substrate 1194 is prepared.
  • the semiconductor growth substrate 1194 has a semiconductor layer 1150 grown on the crystal growth substrate (first substrate) 1001.
  • the crystal growth substrate 1001 is, for example, a Si substrate, a sapphire substrate, or the like.
  • a Si substrate is used.
  • the buffer layer 1140 is formed on one surface of the crystal growth substrate 1001.
  • nitride such as AlN is preferably used.
  • the buffer layer 1140 is used to alleviate the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 when epitaxially growing GaN.
  • the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are laminated on the buffer layer 1140 in this order from the buffer layer 1140 side.
  • a vapor phase growth method (Chemical Vapor Deposition, CVD method) is used, and an organic metal vapor deposition method (Metal Organic Chemical Vapor Deposition, MOCVD method) is preferably used.
  • the semiconductor layer 1150 is, for example, In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) or the like.
  • the semiconductor layer 1150 may be formed on the crystal growth substrate 1001 without passing through the buffer layer 1140.
  • the semiconductor layer 1150 has the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 on the crystal growth substrate 1001 on the side of the crystal growth substrate 1001. They are stacked in this order.
  • the semiconductor growth substrate 1194 when the semiconductor layers 1150 are laminated via the buffer layer 1140 will be described, but the same can be produced even in the case of the semiconductor growth substrate 1194a without the buffer layer 1140.
  • a circuit board (second board) 1100 is prepared.
  • the circuit board 1100 has a circuit 101 whose configuration of the subpixel 20 is described with reference to FIG. 1 and the like.
  • the circuit 101 is covered with the first insulating layer 1112a.
  • the surface of the first insulating layer 1112a is flattened.
  • a light shielding layer 1120 is formed on the first insulating layer 1112a.
  • the light-shielding layer 1120 is made of metal, the light-shielding layer 1120 is formed by sputtering or the like.
  • the light-shielding layer 1120 is formed on the circuit board 1100 in an appropriate manner.
  • the light-shielding layer 1120 is preferably formed over the entire surface of the circuit board 1100.
  • each circuit 101 is formed over the entire surface of the circuit 101.
  • the light-shielding layer 1120 of FIG. 5B is formed with a through hole 121 at an appropriate position in the XY plan view, and is a light-shielding layer 120 having the through hole 121.
  • the position of the through hole 121 is the position through which the via 161d (FIG. 1) is inserted.
  • An appropriate method is selected for forming the through hole 121 depending on the material of the light shielding layer 1120.
  • the light-shielding layer 1120 is made of a metal such as Al or Ag, through holes 121 are formed by dry etching after exposure development.
  • the second insulating layer 112b is formed so as to cover the first insulating layer 112a exposed from the light shielding layer 120 and the through hole 121.
  • the first insulating layer 112a is an insulating layer after the light-shielding layer 120 is formed on the first insulating layer 1112a.
  • the second insulating layer 112b is applied onto the light-shielding layer 120 and the interlayer insulating film 112, and then fired. After that, if further flattening is required, the surface may be further flattened by using CMP (Chemical Mechanical Polishing) or the like. In this way, the circuit board 1100a is prepared.
  • the circuit board 1100a is a substrate on which a light-shielding layer 120 and a second insulating layer 112b are formed on the circuit board 1100.
  • one surface of the circuit board 1100a and the open surface of the n-type semiconductor layer 1151 of the semiconductor layer 1150 are aligned and both are bonded together.
  • the bonded surface of the circuit board 1100a is an exposed surface of the second insulating layer 112b formed on the light-shielding layer 120.
  • a low melting point metal or a low melting point alloy may be used for heat crimping.
  • the low melting point metal is, for example, Sn, In, etc.
  • the low melting point alloy can be, for example, an alloy containing Zn, In, Ga, Sn, Bi, etc. as main components.
  • the bonded surfaces of each substrate are flattened by chemical mechanical polishing (CMP), etc., and then the bonded surfaces are cleaned and adhered in vacuum by plasma treatment. You may let it.
  • CMP chemical mechanical polishing
  • the crystal growth substrate 1001 is removed.
  • a lift-off technique by wet etching or laser irradiation is used.
  • the semiconductor layer 1150 shown in FIG. 6B is formed in the shape of the light emitting element 150.
  • a dry etching process is used, and preferably anisotropic plasma etching (Reactive Ion Etching, RIE) is used.
  • an interlayer insulating film 156 is formed so as to cover the light emitting element 150.
  • An opening 158 is formed in the interlayer insulating film 156 at a position corresponding to the light emitting surface 153S.
  • the light emitting surface 153S exposed from the opening 158 is roughened.
  • Via holes are formed in the interlayer insulating film 156. After that, the via hole is filled with a conductive material. Either wet etching or dry etching can be used to form the via holes.
  • the wiring layer 160 is formed by sputtering or the like. After forming the via hole, the via and the wiring layer 160 may be formed at the same time.
  • the tip of the wiring 160a of the wiring layer 160 is electrically connected to the light emitting surface 153S.
  • the wiring 160k of the wiring layer 160 is electrically connected to the vias 161k and 161d.
  • 8A to 8C are schematic cross-sectional views illustrating a method of manufacturing an image display device according to a modification of the present embodiment.
  • 8A and 8B show a manufacturing process for forming the subpixel 20a.
  • the same steps as in the case of the first embodiment are obtained until the light emitting element 150 is formed and the second interlayer insulating film 156 is formed.
  • FIGS. 8A and 8B are executed after the step of FIG. 7A.
  • a second interlayer insulating film 156 is formed on the second insulating layer 112b and the light emitting element 150, and an opening 158 is formed in the formed interlayer insulating film 112 by etching to form a light emitting surface 153S. Expose. The etching may be wet etching or dry etching.
  • the light emitting surface 153S of the exposed p-type semiconductor layer 153 is roughened in order to improve the luminous efficiency.
  • a transparent conductive film covering these is formed.
  • the transparent conductive film an ITO film, a ZnO film, or the like is preferably used.
  • the transparent electrodes 159a and 159k are formed by photolithography.
  • the transparent electrode 159a is formed across the wiring 160a1, the light emitting surface 153S, and between them.
  • the subpixel 20a of the modified example is formed.
  • FIG. 8C shows a manufacturing process for forming the subpixel 20b.
  • the process is the same as in the case of the above-described modification until the light emitting element 150 is formed.
  • it is assumed that the process of FIG. 8C is executed after the process of FIG. 7A.
  • the second wiring layer 160 is formed without forming an opening.
  • the wiring 160a2 of the wiring layer 160 connected to the power supply line is connected to the light emitting surface 153S via the contact hole of the interlayer insulating film 156a.
  • a part of the circuit other than the subpixels 20, 20a, 20b is formed in the circuit board 100.
  • the row selection circuit 5 (FIG. 3) can be formed in the circuit board 100 together with the drive transistor, the selection transistor, and the like. That is, the row selection circuit 5 may be incorporated at the same time by the manufacturing process described above.
  • the signal voltage output circuit 7 is mounted on another board together with the CPU and other circuit elements, and is mutually connected with the wiring of the circuit board 100, for example, before incorporating the color filter described later or after incorporating the color filter. Connected to.
  • the circuit board 1100a is a wafer containing the circuit 101.
  • a circuit 101 for one or more image display devices is formed on the circuit board 1100a.
  • the circuit 101 for forming one image display device is divided into a plurality of circuit boards 1100a and formed, and all of the divided circuits are combined to form 1 One image display device may be configured.
  • the crystal growth substrate 1001 is a wafer having the same size as the wafer-shaped circuit board 1100a.
  • FIG. 9 is a perspective view illustrating a method of manufacturing the image display device of the present embodiment. As shown in FIG. 9, a plurality of semiconductor growth substrates 1194 may be prepared, and the semiconductor layers 1150 formed on the plurality of crystal growth substrates 1001 may be bonded to one circuit board 1100a.
  • a plurality of circuits 101 are arranged in a grid pattern on the circuit board 1100a, for example.
  • the circuit 101 includes all the subpixels 20 and the like required for one image display device 1.
  • the circuits 101 arranged adjacent to each other are provided with an interval of about the width of the scribe line. No circuit element or the like is arranged at or near the end of the circuit 101.
  • the semiconductor layer 1150 is formed so that its end portion coincides with the end portion of the crystal growth substrate 1001. Therefore, by arranging the end of the semiconductor growth substrate 1194 so as to coincide with the end of the circuit 101 and joining the semiconductor layer 1194, the end of the semiconductor layer 1150 after joining can be matched with the end of the circuit 101. it can.
  • the crystal quality tends to deteriorate at the end of the semiconductor layer 1150 and its vicinity. Therefore, by matching the end portion of the semiconductor layer 1150 with the end portion of the circuit 101, a region in the vicinity of the end portion of the semiconductor layer 1150 on the semiconductor growth substrate 1194 where the crystal quality is likely to deteriorate is a display region of the image display device 1. Can be avoided.
  • a plurality of circuit boards 1100a are prepared so that the plurality of circuit boards 1100 are bonded to the semiconductor layer 1150 formed on the crystal growth substrate 1001 of one semiconductor growth substrate 1194. You may.
  • FIG. 10 is a schematic cross-sectional view illustrating the method for manufacturing the image display device of the present embodiment.
  • the wiring and the like in the circuit board 100 and the interlayer insulating films 112 and 156 are not shown.
  • a part of the color conversion member such as the color filter 180 is displayed.
  • a structure including a buffer layer 140, a light emitting element 150, vias 161k, 161d, a wiring layer 160, an interlayer insulating film 156, and a surface resin layer 170 is referred to as a light emitting circuit unit 172.
  • a structure in which the light emitting circuit unit 172 is provided on the circuit board 100 is referred to as a structure 1192.
  • the color filter 180 is adhered to the structure 1192 on one side.
  • the other surface of the color filter 180 is adhered to the glass substrate 186.
  • a transparent thin film adhesive layer 188 is provided on one surface of the color filter 180, and is adhered to the surface of the structure 1192 on the light emitting circuit portion 172 side via the transparent thin film adhesive layer 188.
  • the color filter 180 has color conversion units arranged in the positive direction of the X-axis in the order of red, green, and blue.
  • a red color conversion layer 183R and a green color conversion layer 183G are provided on the first layer, and a filter layer 184 is provided on the second layer, respectively.
  • a single-layer color conversion layer 183B is provided.
  • a light-shielding unit 181 is provided between the color conversion units.
  • the color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183R, 183G, and 183B of each color with the positions of the light emitting element 150.
  • 11A to 11D are schematic cross-sectional views showing a modified example of the manufacturing method of the image display device of the present embodiment.
  • 11A-11D show a method of forming a color filter by an inkjet.
  • a structure 1192 having a light emitting circuit unit 172 attached to the circuit board 100 is prepared.
  • a light-shielding portion 181 is formed on the structure 1192.
  • the light-shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.
  • the phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form the color conversion layer 183.
  • the phosphor colors the region where the light-shielding portion 181 is not formed.
  • a fluorescent paint using a general phosphor material or a quantum dot phosphor material is used as the phosphor.
  • a quantum dot phosphor material it is preferable because each emission color can be realized, monochromaticity is high, and color reproducibility can be high.
  • a drying process is performed at an appropriate temperature and time. The thickness of the coating film at the time of coloring is set to be thinner than the thickness of the light-shielding portion 181.
  • the blue light emitting subpixel may not form a color conversion part, so that the phosphor is not ejected.
  • the color conversion unit when forming a blue color conversion layer for the blue light emitting subpixel, the color conversion unit may be one layer, so that the thickness of the coating film of the blue phosphor is preferably the light-shielding portion 181. It is about the same as the thickness.
  • the paint for the filter layer 184 is ejected from the inkjet nozzle.
  • the paint is applied over the coating film of the phosphor.
  • the total thickness of the coating film of the phosphor and the paint is about the same as the thickness of the light-shielding portion 181.
  • the image display device 1 can be manufactured.
  • the semiconductor layer 1150 including the light emitting layer 1152 for the light emitting element 150 is attached to the circuit board 1100a including the circuit element such as the transistor 103 for driving the light emitting element 150. After that, the semiconductor layer 1150 is etched to form the light emitting element 150. Therefore, the step of transferring the light emitting element can be remarkably shortened as compared with the case of individually transferring the light emitting element separated into the circuit board 1100a.
  • the number of subpixels exceeds 24 million, and in the case of an 8K image quality image display device, the number of subpixels exceeds 99 million. It takes an enormous amount of time to mount such a large number of light emitting elements individually on a circuit board, and it is difficult to realize an image display device using micro LEDs at a realistic cost. Further, if a large number of light emitting elements are individually mounted, the yield is reduced due to poor connection at the time of mounting, and further cost increase is unavoidable.
  • the entire semiconductor layer 1150 is attached to the circuit board 1100a before the semiconductor layer 1150 is fragmented, so that the transfer step is completed in one time. ..
  • the light emitting element is directly formed on the circuit board by etching or the like, the light emitting element and the circuit element in the circuit board 1100a (100) are electrically connected by via formation, so that a uniform connection structure is realized. It is possible to suppress a decrease in yield.
  • the semiconductor layer 1150 is attached to the circuit board 1100a at the wafer level without being fragmented in advance or forming an electrode at a position corresponding to the circuit element, it is not necessary to perform alignment. Therefore, the pasting process can be easily performed in a short time. Since it is not necessary to align the light emitting element 150 at the time of sticking, the light emitting element 150 can be easily miniaturized, which is suitable for a high-definition display.
  • the subpixel includes a light shielding layer 120 between the circuit element and the light emitting element 150. Since the light-shielding layer 120 can be provided so as to cover all the sub-pixels, the light from the light emitting element 150 is suppressed from reaching the circuit element such as the transistor 103, and the circuit element malfunctions due to the irradiation of the light. Can be prevented.
  • the light-shielding layer 120 can be formed of a conductive material. By forming the light-shielding layer 120 with a conductive material, it is possible to provide light reflectivity, so that the scattering of light on the light-shielding layer 120 side of the light emitting element 150 can be reflected on the light emitting surface 153S side. Therefore, the luminous efficiency of the subpixel can be improved.
  • the second insulating layer 112b is provided between the light shielding layer 120 and the light emitting element 150.
  • the circuit element and the light-emitting element 150 can be insulated by the second insulating layer 112b.
  • An arbitrary constant voltage can be applied to the light-shielding layer 120, and electromagnetic radiation generated by the operation of the circuit element can be suppressed.
  • FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • the configuration of the light emitting element 250 and the configuration of the transistor 203 for driving the light emitting element 250 are different from those of the other embodiments described above.
  • the same components as those in the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 220 of the image display device of the present embodiment includes the transistor 203 and the light emitting element 250.
  • the transistor 203 is formed in the element forming region 204 formed on the substrate 102.
  • the element forming region 204 includes an n-type semiconductor region 204b and a p-type semiconductor region 204s and 204d.
  • the n-type semiconductor region 204b is provided near the surface of the substrate 102.
  • the p-type semiconductor regions 204s and 204d are provided in the n-type semiconductor region 204b in the vicinity of the surface of the n-type semiconductor region 204b so as to be separated from each other.
  • a gate 107 is provided on the n-type semiconductor region 204b via the insulating layer 105.
  • the gate 107 is provided between the p-type semiconductor regions 204s and 204d.
  • the transistor 203 is a p-channel transistor, for example, a p-channel MOSFET.
  • the light emitting element 250 includes a p-type semiconductor layer (first semiconductor layer) 253, a light emitting layer 252, and an n-type semiconductor layer (second semiconductor layer) 251.
  • the p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the first interlayer insulating film 112 of the circuit board 100 toward the light emitting surface 251S.
  • the light emitting element 250 has, for example, a substantially square or rectangular shape in XY plan view, but the corners may be rounded.
  • the light emitting element 250 may have, for example, an elliptical shape or a circular shape in an XY plan view.
  • the degree of freedom in layout is improved by appropriately selecting the shape and arrangement of the light emitting elements in a plan view.
  • the p-type semiconductor layer 253 has a stepped portion 253a extending in the X-axis direction on the first interlayer insulating film 112.
  • the light emitting element 250 may be made of the same material as in the other embodiments described above.
  • the light emitting element 250 emits, for example, blue light having a wavelength of about 467 nm ⁇ 20 nm or bluish purple light having a wavelength of 410 nm ⁇ 20 nm.
  • the second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112 and the light emitting element 250.
  • the second interlayer insulating film 156 has an opening 258.
  • the opening 258 is formed on the light emitting element 250, and the interlayer insulating film 156 is not provided on the light emitting surface 251S of the light emitting element 250.
  • a white resin is preferably used so that the light emitting element 250 reflects the light emitted and is effectively output from the opening 258.
  • the light emitting surface 251S is a surface of the n-type semiconductor layer 251 facing the surface in contact with the light emitting layer 252.
  • the light emitting surface 251S is roughened.
  • a via 261a is provided so as to penetrate the interlayer insulating film 156.
  • One end of the via 261a is connected to the step portion 253a.
  • the via 161d is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the via 161d is connected to the wiring 110d.
  • the wiring layer 260 is provided on the interlayer insulating film 156.
  • the wiring layer 260 includes wirings 260k and 260a.
  • the wiring 260a is connected to the other ends of the vias 261a and 161d. Therefore, the p-type semiconductor layer 253 of the light emitting element 250 is electrically connected to the main electrode of the transistor 203 via the vias 261a and 161d and the wiring 260a.
  • Wiring 260k is not shown, but is connected to the ground wire. Therefore, the n-type semiconductor layer 251 is connected to the ground wire via the wiring 260k.
  • a surface resin layer 170 is provided on the interlayer insulating film 156 and the wiring layer 260.
  • FIG. 13 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 201 of the present embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207.
  • the sub-pixels 220 are arranged in a grid pattern as in the case of the other embodiments described above.
  • the subpixel 220 includes a light emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228.
  • the selection transistor 224 may be displayed as T1
  • the drive transistor 226 may be displayed as T2
  • the capacitor 228 may be displayed as Cm.
  • the light emitting element 222 is provided on the ground wire 4, and the drive transistor 226 connected in series with the light emitting element 222 is provided on the power supply line 3. That is, the drive transistor 226 is connected to the higher potential side than the light emitting element 222.
  • the drive transistor 226 is a p-channel MOSFET.
  • a selection transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208.
  • the capacitor 228 is connected between the gate electrode of the drive transistor 226 and the power supply line 3.
  • the row selection circuit 205 and the signal voltage output circuit 207 supply the scanning line 206 and the signal line 208 with a signal voltage having a polarity different from that of the other embodiments described above in order to drive the drive transistor 226 which is a p-channel MOSFET. ..
  • the row selection circuit 205 supplies a selection signal to the scanning line 206 so as to sequentially select one row from the array of subpixels 220 in the m row.
  • the signal voltage output circuit 207 supplies a signal voltage having the required analog voltage value to each subpixel 220 in the selected row.
  • the drive transistor 226 of the subpixel 220 in the selected row causes a current corresponding to the signal voltage to flow through the light emitting element 222.
  • the light emitting element 222 emits light with a brightness corresponding to the flowing current.
  • a method of manufacturing the image display device 201 of the present embodiment will be described.
  • 14A to 15C are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • the semiconductor growth substrate 1194 already described in FIG. 5A is used.
  • the subsequent steps of preparing the semiconductor growth substrate 1194 having the semiconductor layer 1150 epitaxially grown via the buffer layer 1140 on the crystal growth substrate 1001 will be described.
  • the semiconductor layer 1150 is mounted on the crystal growth substrate 1001 from the side of the crystal growth substrate 1001 via the buffer layer 1140, and the p-type semiconductor layer 1153 and the light emitting layer 1152. And the n-type semiconductor layer 1151 is grown and laminated in this order.
  • the support substrate 1190 is adhered to the open surface of the n-type semiconductor layer 1151.
  • the support substrate 1190 is made of, for example, Si or quartz.
  • the crystal growth substrate 1001 is removed.
  • wet etching or a laser is used for removing the crystal growth substrate 1001, for example, wet etching or a laser is used.
  • the buffer layer 1140 is removed at the time of removing the crystal growth substrate 1001 or after the removal of the crystal growth substrate 1001.
  • a circuit board 1100a having a light-shielding layer 120 formed in the first interlayer insulating film 112 is prepared, and the semiconductor layer 1150 adhered to the support substrate 1190 is bonded to the circuit board 1100a.
  • the circuit board 1100a is prepared by the manufacturing process described above with reference to FIGS. 5A-5D.
  • the bonded surface of the semiconductor layer 1150 is an open surface of the p-type semiconductor layer 1153, and the bonded surface of the circuit board 1100a is a flattened surface of the second insulating layer.
  • the semiconductor growth substrate 1294 may be used instead of the semiconductor growth substrate 1194.
  • the semiconductor growth substrate 1294 is laminated on the crystal growth substrate 1001 via the buffer layer 1140 in the order of the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 from the side of the crystal growth substrate 1001.
  • the exposed surface of the n-type semiconductor layer 1151 of the semiconductor growth substrate 1294 is attached to the surface of the circuit board 1100a as described in the manufacturing method in the first embodiment described above. match.
  • the semiconductor layer 1150 may be grown on the crystal growth substrate 1001 without passing through the buffer layer 1140, as in the case described in the manufacturing method in the first embodiment.
  • the support substrate 1190 is removed after the semiconductor layer 1150 and the circuit board 1100a are bonded together.
  • the semiconductor layer 1150 is formed in the shape of the light emitting element 250.
  • a dry etching process is used, and preferably anisotropic plasma etching (Reactive Ion Etching, RIE) is used.
  • a first interlayer insulating film 112 and a second interlayer insulating film 156 covering the light emitting element 250 are formed.
  • an opening 258 is formed at a position corresponding to the light emitting surface 251S, the light emitting surface 251S is exposed, and the light emitting surface 251S is preferably roughened.
  • Via holes are formed in the interlayer insulating film 156.
  • the via hole is filled with a conductive metal material.
  • the wiring layer 260 is formed by sputtering or the like.
  • the wirings 260k and 260a are formed by photolithography.
  • the wiring 260a is connected to the vias 261a and 161d.
  • the wiring 260k is connected to the ground wire 4 shown in FIG.
  • This embodiment also has the same effect as that of the other embodiments described above. That is, since the semiconductor layer 1150 is bonded to the circuit board 1100a and then the individual light emitting elements 250 are formed by etching, the transfer process of the light emitting elements can be significantly shortened.
  • the n-type semiconductor layer 251 as the light emitting surface 251S, the surface can be roughened more easily, and the wiring 260k1 is connected to the light emitting surface 251S.
  • the wiring 260k1 is connected to the light emitting surface 251S.
  • FIG. 16 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. As shown in FIG. 16, the image display device includes a subpixel group 320.
  • the subpixel group 320 includes transistors 203-1 and 203-2, a first wiring layer 310, a first interlayer insulating film 112, a light shielding layer 120, a semiconductor layer 350, and a second interlayer insulating film 356. And a second wiring layer 360, and vias 361d1, 361d2.
  • the semiconductor layer is injected through the second wiring layer 360. Electrons are injected into 350 to cause the light emitting layer 352 to emit light.
  • the circuit configuration of FIG. 13 is applied to the drive circuit.
  • the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer may be interchanged up and down using the other embodiments described above.
  • the semiconductor layer is driven by n-channel transistors. In that case, the circuit configuration of FIG. 3 is applied to the drive circuit.
  • the semiconductor layer 350 includes two light emitting surfaces 351S1 and 351S2, and the subpixel group 320 substantially includes two subpixels.
  • the display area is formed by arranging the subpixel group 320 including substantially two subpixels in a grid pattern.
  • Transistors 203-1 and 203-2 are formed in the element forming regions 204-1 and 204-2, respectively.
  • the element forming regions 204-1 and 204-2 are n-type semiconductor layers, and p-type semiconductor layers are formed separated from the n-type semiconductor layers.
  • the n-type semiconductor layer includes a channel region, and the p-type semiconductor layer includes a source region and a drain region, respectively.
  • An insulating layer 105 is formed on the element forming regions 204-1 and 204-2, and gates 107-1 and 107-2 are formed via the insulating layer 105, respectively.
  • Gates 107-1 and 107-2 are gates of transistors 203-1 and 203-2.
  • Transistors 203-1 and 203-2 are p-channel transistors, for example, p-channel MOSFETs.
  • the insulating film 108 covers the two transistors 203-1 and 203-2.
  • the wiring layer 310 is formed on the insulating film 108.
  • Vias 111s1 and 111d1 are provided between the p-shaped semiconductor layer of the transistor 203-1 and the wiring layer 310, respectively. Vias 111s2 and 111d2 are provided between the p-shaped semiconductor layer and the wiring layer 310 of the transistor 203-2.
  • the first wiring layer 310 includes wiring 310s, 310d1, 310d2.
  • the wiring 310s is electrically connected to the p-shaped semiconductor layer corresponding to the source electrodes of the transistors 203-1 and 203-2 via the vias 111s1 and 111s2, respectively.
  • Wiring 310s is not shown, but is connected to a power line.
  • the wirings 310d1 and 310d2 are connected to the p-shaped semiconductor layer corresponding to the drain electrodes of the transistors 203-1 and 203-2 via vias 111d1 and 111d2, respectively.
  • the first interlayer insulating film 112 includes a first insulating layer 112a and a second insulating layer 112b.
  • the first insulating layer 112a covers the wiring layer 310 and the insulating film 108.
  • a light-shielding layer 120 is provided on the first insulating layer 112a.
  • the light-shielding layer 120 has through holes 321-1 and 321-2.
  • the second insulating layer 112b covers the light-shielding layer 120 and the first insulating layer 112a exposed from the through holes 321-1 and 321-2.
  • the through holes 321-1 and 321-2 of the light-shielding layer 120 are provided at positions corresponding to the wirings 310d1 and 310d2 connected to the drain electrodes of the transistors 203-1 and 203-2 in XY plan view, respectively. .. Vias 361d1 and 361d2 are inserted into the through holes 321-1 and 321-2, respectively.
  • the material of the second insulating layer 112b is filled between the through hole 321-1 and the via 161d1, and the through hole 321-1 and the via 161d1 are electrically insulated.
  • the material of the second insulating layer 112b is filled between the through hole 321-2 and the via 161d2, and the through hole 321-2 and the via 161d2 are electrically insulated.
  • a semiconductor layer 350 is provided on the light-shielding layer 120 via a second insulating layer 112b.
  • the semiconductor layer 350 includes a p-type semiconductor layer 353, a light emitting layer 352, and an n-type semiconductor layer 351.
  • the semiconductor layer 350 is laminated in the order of the p-type semiconductor layer 353, the light emitting layer 352, and the n-type semiconductor layer 351 from the side of the interlayer insulating film 112 toward the side of the light emitting surfaces 351S1 and 351S2.
  • the configuration and function of the light-shielding layer 120 are the same as those of the other embodiments described above. That is, the light-shielding layer 120 is provided substantially parallel to the XY plane, and is provided so as to cover the entire circuit element including the transistors 203-1 and 203-2. Therefore, the scattered light from the light emitting layer 352 of the semiconductor layer 350 toward the light shielding layer 120 is suppressed from reaching the circuit element by the light shielding layer 120.
  • the light-shielding layer 120 is made of a light-reflecting material such as metal, the scattered light that reaches the light-shielding layer 120 is reflected by the light-shielding layer 120 and heads toward the light emitting surface 251S, so that the semiconductor layer The luminous efficiency of 350 can be improved.
  • the light-shielding layer 120 is insulated from the semiconductor layer 350 by the second insulating layer 112b. Therefore, the light-shielding layer 120 may be formed of a conductive material such as metal, and is connected to a fixed potential such as a ground wire or a power supply line to have an effect of suppressing electromagnetic radiation due to the operation of the circuit element. be able to.
  • the second interlayer insulating film (second insulating film) 356 covers the second insulating layer 112b and the semiconductor layer 350.
  • the interlayer insulating film 356 covers a part of the semiconductor layer 350.
  • the interlayer insulating film 356 covers the surface of the n-type semiconductor layer 551 except for the light emitting surfaces (exposed surfaces) 351S1 and 351S2 of the semiconductor layer 350.
  • the interlayer insulating film 356 covers the side surface of the semiconductor layer 350.
  • the interlayer insulating film 356 is preferably a white resin.
  • Openings 358-1 and 358-2 are formed in the portion of the semiconductor layer 350 that is not covered with the interlayer insulating film 356.
  • the openings 358-1 and 358-2 are formed at positions corresponding to the light emitting surfaces 351S1 and 351S2.
  • the light emitting surfaces 351S1 and 351S2 are formed at distant positions on the n-type semiconductor layer 351.
  • the light emitting surface 351S1 is provided at a position closer to the transistor 203-1 on the n-type semiconductor layer 351.
  • the light emitting surface 351S2 is provided at a position closer to the transistor 203-2 on the n-type semiconductor layer 351.
  • the openings 358-1 and 358-2 are, for example, square or rectangular in XY plan view.
  • the shape is not limited to a square, and may be a polygon such as a circle, an ellipse, or a hexagon.
  • the light emitting surfaces 351S1 and 351S2 are also squares, rectangles, other polygons, circles, etc. in XY plan view.
  • the shapes of the light emitting surfaces 351S1 and 351S2 may be similar to or different from the shapes of the openings 358-1 and 358-2.
  • the second wiring layer 360 is provided on the interlayer insulating film 356.
  • the wiring layer 360 includes wiring 360k.
  • the wiring 360k is provided on the second interlayer insulating film 356 provided on the n-type semiconductor layer 351 between the openings 358-1 and 358-2. Wiring 360k is connected to a ground wire (not shown).
  • the transparent electrodes 359k are provided over the light emitting surfaces 351S1 and 351S2 of the n-type semiconductor layer 351 exposed from the openings 358-1 and 358-2, respectively.
  • the transparent electrode 359k is provided on the wiring 360k.
  • the transparent electrode 359k is provided between the light emitting surface 351S1 and the wiring 360k, and is provided between the light emitting surface 351S2 and the wiring 360k.
  • the transparent electrode 359k electrically connects the light emitting surfaces 351S1 and 351S2 and the wiring 360k.
  • the transparent electrode 359k is connected to the light emitting surfaces 351S1 and 351S2 exposed from the openings 358-1 and 358-2. Therefore, the electrons supplied from the transparent electrode 359k are supplied to the n-type semiconductor layer 351 from the exposed light emitting surfaces 351S1 and 351S2, respectively.
  • holes are supplied to the p-type semiconductor layer 353 via the wiring 310d1, vias 361d1, wirings 360a1 and vias 361a1, or via wirings 310d2, vias 361d2, wirings 360a2 and vias 361a2.
  • Transistors 203-1 and 203-2 are drive transistors of adjacent subpixels, and are driven sequentially. Therefore, holes supplied from either one of the two transistors 203-1 and 203-2 are injected into the light emitting layer 352, electrons supplied from the wiring 360k are injected into the light emitting layer 352, and the light emitting layer 352 becomes It emits light.
  • the opening 358-1 and the light emitting surface 351S1 are provided at positions closer to the transistor 203-1 of the n-type semiconductor layer 351. Therefore, when the transistor 203-1 is turned on, holes are injected through the wiring 310d1, the via 361d1, the wiring 360a1, and the via 361a1, and the light emitting surface 351S1 emits light.
  • the opening 358-2 and the light emitting surface 351S2 are provided at positions closer to the transistor 203-2 of the n-type semiconductor layer 351. Therefore, when the transistor 203-2 is turned on, holes are injected through the wiring 310d2, the via 361d2, the wiring 360a2, and the via 361a2, and the light emitting surface 351S2 emits light.
  • 17A to 18B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment. As shown in FIG. 17A, the semiconductor growth substrate 1294 and the circuit board 3100a are prepared and bonded to each other.
  • the semiconductor growth substrate 1294 includes a crystal growth substrate 1001 in which the semiconductor layer 1150 is epitaxially grown.
  • the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order on the crystal growth substrate 1001 via the buffer layer 1140 from the side of the crystal growth substrate 1001.
  • the light-shielding layer 120 and the second insulating layer 112b are formed on the circuit board 1100 as already described in FIGS. 5A to 5D.
  • the circuit board 3100a has a circuit configuration different from that of the other embodiments described above, but has the same structure as that described in most of the other parts. In the following, only the reference numerals will be replaced and detailed description will be omitted as appropriate.
  • the crystal growth substrate 1001 is removed after the surface of the p-type semiconductor layer 1153 of the semiconductor layer 1150 is bonded to the surface of the second insulating layer 112b of the circuit board 3100a.
  • the semiconductor layer 1150 is etched to form the semiconductor layer 350.
  • the buffer layer 340 may be removed after etching the semiconductor layer 1150, or may be removed before etching the semiconductor layer 1150.
  • an interlayer insulating film 356 covering the second insulating layer 112b and the semiconductor layer 350 is formed.
  • the wiring layer 360 is formed on the interlayer insulating film 356, and the wirings 360a1, 360a2, 360k and the like are formed by etching.
  • openings 358-1 and 358-2 are formed, respectively.
  • the 351S1 and 351S2 exposed by the openings 358-1 and 358-2 are roughened, respectively.
  • the transparent electrodes 359a1,359a2,359k are formed so as to electrically connect the light emitting surfaces 351S1, 351S2 and the wiring 360k.
  • the subpixel group 320 having the semiconductor layer 350 sharing the two light emitting surfaces 351S1 and 351S2 is formed.
  • two light emitting surfaces 351S1 and 351S2 are provided on one semiconductor layer 350, but the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are one semiconductor. It can also be provided on the layer 350. As an example, one row or two rows of subpixels may be realized by a single semiconductor layer 350. As a result, as will be described later, it is possible to reduce the recombination current that does not contribute to light emission per light emitting surface and increase the effect of realizing a finer light emitting element.
  • FIG. 19 is a schematic cross-sectional view illustrating a part of the image display device according to the modified example of the present embodiment.
  • This modification is different from the case of the third embodiment described above in that two n-type semiconductor layers 3351a1 and 3351a2 are provided on the light emitting layer 352.
  • the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • the image display device of this modified example includes a subpixel group 320a.
  • the subpixel group 320a includes a semiconductor layer 350a.
  • the semiconductor layer 350a includes a p-type semiconductor layer 353, a light emitting layer 352, and n-type semiconductor layers 3351a1, 3351a2.
  • the p-type semiconductor layer 353, the light emitting layer 352, and the n-type semiconductor layers 3351a1, 3351a2 are laminated in this order from the interlayer insulating film 356 toward the light emitting surface 3351S1, 3351S2.
  • the n-type semiconductor layers 3351a1 and 3351a2 are arranged on the light emitting layer 352 so as to be separated from each other along the X-axis direction.
  • An interlayer insulating film 356 is provided between the n-type semiconductor layers 3351a1 and 3351a2, and the n-type semiconductor layers 3351a1 and 3351a2 are separated by an interlayer insulating film 356.
  • the n-type semiconductor layers 3351a1 and 3351a2 have substantially the same shape in XY plan view, and the shape is substantially square or rectangular, and may be another polygonal shape, circular shape, or the like.
  • the n-type semiconductor layers 3351a1 and 3351a2 have light emitting surfaces 3351S1 and 3351S2, respectively.
  • the light emitting surfaces 3351S1 and 3351S2 are surfaces of the n-type semiconductor layers 3351a1 and 3351a2 exposed by the openings 358-1 and 358-2, respectively.
  • the shapes of the light emitting surfaces 3351S1 and 3351S2 in the XY plan view have substantially the same shape as the shape of the light emitting surface in the case of the third embodiment, and have a shape such as a square.
  • the shape of the light emitting surfaces 3351S1 and 3351S2 is not limited to the square as in this embodiment, and may be a polygon such as a circle, an ellipse, or a hexagon.
  • the shapes of the light emitting surfaces 3351S1 and 3351S2 may be similar to or different from the shapes of the openings 358-1 and 358-2.
  • Transparent electrodes 359k are provided on the light emitting surfaces 3351S1 and 3351S2, respectively.
  • the transparent electrode 359k is also provided on the wiring 360k.
  • the transparent electrode 359k is provided between the wiring 360k and the light emitting surface 3351S1 and is provided between the wiring 360k and the light emitting surface 3351S2.
  • the transparent electrode 359k electrically connects the wiring 360k and the light emitting surfaces 3351S1 and 3351S2.
  • 20A and 20B are schematic cross-sectional views illustrating a method of manufacturing an image display device of this modified example.
  • the same steps as those described in FIGS. 16A and 16B in the case of the third embodiment are applied until the circuit board 3100a is bonded to the semiconductor layer 1150.
  • the subsequent steps will be described below.
  • the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 in FIG. 17B are etched to form the light emitting layer 352 and the p-type semiconductor layer 353, and then further. Etching is performed to form two n-type semiconductor layers 3351a1 and 3351a2. After that, the buffer layer 340a may be removed, or the buffer layer may be removed before etching the n-type semiconductor layer 1151.
  • the n-type semiconductor layers 3351a1 and 3351a2 may be formed by deeper etching.
  • etching for forming the n-type semiconductor layers 3351a1 and 3351a2 may be performed to a depth that reaches the inside of the light emitting layer 352 and the inside of the p-type semiconductor layer 353.
  • the etching position of the n-type semiconductor layer 1151 be separated from the outer periphery of the light emitting surfaces 3351S1 and 3351S2 of the n-type semiconductor layer described later by 1 ⁇ m or more.
  • an interlayer insulating film 356 covering the second insulating layer 112b and the semiconductor layer 350a is formed.
  • a wiring layer 360 is formed on the interlayer insulating film 356, and wirings 360a1, 360a2, 360k and the like are formed by etching.
  • Openings 358-1 and 358-2 are formed at positions corresponding to the light emitting surfaces 3351S1 and 3351S2 of the interlayer insulating film, respectively.
  • the light emitting surfaces 3351S1 and 3351S2 of the n-type semiconductor layer exposed by the openings 358-1 and 358-2 are roughened, respectively. After that, transparent electrodes 359a and 359k are formed.
  • the subpixel group 320a having two light emitting surfaces 3351S1 and 3351S2 is formed.
  • the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are provided on one semiconductor layer 350a. May be good.
  • FIG. 21 is a graph illustrating the characteristics of the pixel LED element.
  • the vertical axis of FIG. 21 represents the luminous efficiency [%].
  • the horizontal axis represents the current density of the current flowing through the pixel LED element as a relative value.
  • the luminous efficiency of the pixel LED element increases substantially constant or monotonously.
  • the luminous efficiency decreases monotonically. That is, the pixel LED element has an appropriate current density that maximizes the luminous efficiency.
  • the light emitting element is formed by individually separating all the layers of the semiconductor layer 1150 including the light emitting layer by etching or the like. At this time, the joint surface between the light emitting layer and the n-type semiconductor layer is exposed at the end. Similarly, the joint surface between the light emitting layer and the p-type semiconductor layer is exposed at the end.
  • the ends are formed in all directions for each light emitting element, so that recombination may occur at a total of eight ends.
  • the semiconductor layers 350 and 350a having two light emitting surfaces have four ends. Since the region between the openings 358-1 and 358-2 has few electrons and holes injected and hardly contributes to light emission, it can be considered that there are six ends that contribute to light emission. As described above, in the present embodiment, by substantially reducing the number of ends, recombination that does not contribute to light emission can be reduced, and the drive current can be reduced accordingly.
  • the distance between the light emitting surfaces 351S1 and 351S2 in the sub-pixel group 320 of the third embodiment is used. Becomes shorter. In this case, if the n-type semiconductor layer 351 is shared, a part of the electrons injected to the side of the adjacent light emitting surface may be diverted, and the light emitting surface on the non-driven side may emit a small amount of light. .. In the modified example, since the n-type semiconductor layer is separated for each light emitting surface, it is possible to reduce the occurrence of slight light emission on the light emitting surface on the side that is not driven.
  • the semiconductor layer including the light emitting layer is one in which the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer are laminated in this order from the side of the interlayer insulating film, and the exposed surface of the n-type semiconductor layer is roughened. It is preferable from the viewpoint of improving the luminous efficiency.
  • the stacking order of the p-type semiconductor layer and the n-type semiconductor layer may be changed, and the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer may be laminated in this order.
  • the image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.
  • FIG. 22 is a block diagram illustrating an image display device according to the present embodiment.
  • FIG. 22 shows the main parts of the configuration of a computer display.
  • the image display device 401 includes an image display module 402.
  • the image display module 402 is, for example, an image display device having the configuration in the case of the first embodiment described above.
  • the image display module 402 includes a display area 2 in which subpixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.
  • the image display device 401 further includes a controller 470.
  • the controller 470 inputs control signals separated and generated by an interface circuit (not shown) to control the drive and drive order of each subpixel with respect to the row selection circuit 5 and the signal voltage output circuit 7.
  • FIG. 23 is a block diagram illustrating an image display device of this modified example.
  • FIG. 23 shows the configuration of a high-definition flat-screen television.
  • the image display device 501 includes an image display module 502.
  • the image display module 502 is, for example, an image display device 1 having the configuration in the case of the first embodiment described above.
  • the image display device 501 includes a controller 570 and a frame memory 580.
  • the controller 570 controls the drive order of each subpixel in the display area 2 based on the control signal supplied by the bus 540.
  • the frame memory 580 stores display data for one frame and is used for processing such as smooth moving image reproduction.
  • the image display device 501 has an I / O circuit 510.
  • the I / O circuit 510 provides an interface circuit or the like for connecting to an external terminal or device.
  • the I / O circuit 510 includes, for example, a USB interface for connecting an external hard disk device or the like, an audio interface, or the like.
  • the image display device 501 has a receiving unit 520 and a signal processing unit 530.
  • An antenna 522 is connected to the receiving unit 520, and a necessary signal is separated and generated from the radio wave received by the antenna 522.
  • the signal processing unit 530 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 520 is converted into image data, audio data, etc. by the signal processing unit 530. Separated and generated.
  • an image display device provided with an image display module having an appropriate screen size and resolution can be a mobile information terminal such as a smartphone or a car navigation system.
  • the image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, and may be a modified example thereof or the case of another embodiment.
  • FIG. 24 is a perspective view schematically illustrating an image display device of the first to third embodiments and modified examples thereof.
  • a light emitting circuit 172 having a large number of subpixels is provided on the circuit board 100.
  • a color filter 180 is provided on the light emitting circuit unit 172.
  • the structure including the circuit board 100, the light emitting circuit unit 172, and the color filter 180 is referred to as the image display modules 402 and 502, and is incorporated in the image display devices 401 and 501.
  • 1,201,401,501 image display device 2 display area, 3 power supply line, 4 ground line, 5,205 line selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8 signal line, 10 pixels , 20, 20a, 20b, 20c subpixel, 22,222 light emitting element, 24,224 selection transistor, 26,226 drive transistor, 28,228 capacitor, 100 circuit board, 101 circuit, 103,103-1,103-2 Transistor, 104,104-1,104-2 element formation region, 105 insulating layer, 107,107-1,107-2 gate, 108 insulating film, 110,210,310 first wiring layer, 112 first insulating film , 112a 1st insulating layer, 112b 2nd insulating layer, 120 light shielding layer, 121,321-1,321-2 through hole, 150,250 light emitting element, 156,256,356 second insulating film, 160,260,360 Second wiring layer, 161d, 161k, 261a, 361a1,361a2,361d1,361d2 via

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