WO2020228152A1 - 空气隙型半导体器件封装结构及其制作方法 - Google Patents

空气隙型半导体器件封装结构及其制作方法 Download PDF

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Publication number
WO2020228152A1
WO2020228152A1 PCT/CN2019/099557 CN2019099557W WO2020228152A1 WO 2020228152 A1 WO2020228152 A1 WO 2020228152A1 CN 2019099557 W CN2019099557 W CN 2019099557W WO 2020228152 A1 WO2020228152 A1 WO 2020228152A1
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Prior art keywords
adhesive layer
carrier
semiconductor chip
semiconductor device
air gap
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PCT/CN2019/099557
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English (en)
French (fr)
Inventor
狄云翔
刘孟彬
许嗣拓
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中芯集成电路（宁波）有限公司上海分公司
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Application filed by 中芯集成电路（宁波）有限公司上海分公司 filed Critical 中芯集成电路（宁波）有限公司上海分公司
Priority to KR1020217014565A priority Critical patent/KR20210077728A/ko
Priority to JP2021516364A priority patent/JP7297329B2/ja
Priority to US16/686,452 priority patent/US11695387B2/en
Publication of WO2020228152A1 publication Critical patent/WO2020228152A1/zh
Priority to US18/199,655 priority patent/US11979136B2/en

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Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to an air gap type semiconductor device packaging structure and a manufacturing method thereof.
  • some device active regions need to provide a cavity environment to ensure normal operation, and air gaps need to be formed in the device active regions during device preparation or packaging.
  • Such as filters, MEMS devices, etc. take SAW filters as an example.
  • SAW is the abbreviation of Surface Acoustic Wave (Surface Acoustic Wave), which is an elastic wave whose amplitude is generated and propagated on the surface of a piezoelectric solid material and decreases rapidly as the depth of the solid material increases.
  • SAW filter has the function of allowing the signal of a certain frequency to pass smoothly, while the signal of the other part of the frequency is greatly suppressed. It is widely used in TV, satellite communication, optical fiber communication and mobile communication. Base stations, repeaters, mobile phones, GPS, electronic countermeasures and radars. With the increasing development of filter packaging technology, SAW filters are also developing rapidly in the direction of high performance, small size, light weight, and low cost.
  • the electrical input signal is supplied to the inside of the SAW filter via the port (I/O contact) 12, and the electrical input signal is formed by crossing the metal electrodes 13 arranged on the piezoelectric substrate 11.
  • Interdigital Transducers (IDT) 14 are converted into acoustic waves 15, which mainly propagate along the surface of the piezoelectric substrate 11 and the direction in which the interdigital electrodes rise, so they are called surface acoustic waves.
  • the interdigital The area where the converter is located is the active area of the SAW filter chip. During the packaging process of the SAW filter, a cavity needs to be formed around the active area to ensure the generation and propagation of sound waves.
  • the packaging technology of SAW filters is mainly metal packaging, plastic packaging, and surface mount packaging. At least the base and the upper cover are used in the packaging process of the SAW filter, that is, the SAW filter chip is pasted on the base and then sealed with the upper cover.
  • the SAW filter adopting metal packaging and plastic packaging technology has relatively long pins, which causes the volume of the device to be too large.
  • surface mount packaging technology although the application range is wide, the manufacturing process is complicated, and ceramic materials such as HTCC (high temperature co-fired ceramic) and LTCC (low temperature co-fired ceramic) are expensive. Therefore, it is necessary to find a packaging method for a filter with a small package body size, simple manufacture and low price.
  • the invention provides a manufacturing method of an air gap type semiconductor device packaging structure, which aims at reducing the volume of the packaging body, simplifying the manufacturing process, and reducing the production cost.
  • the invention provides a manufacturing method of an air gap type semiconductor device packaging structure, including:
  • Providing a carrier and a semiconductor chip forming an adhesive layer on the carrier, the adhesive layer is formed with a first adhesive layer opening, and the semiconductor chip includes an active area and an input/output electrode area;
  • the semiconductor chip and the carrier form a first cavity at the opening of the first adhesive layer, and the first cavity is at least aligned with the semiconductor chip Part of the active area;
  • An interconnection structure is formed on the side of the carrier other than the adhesive layer formed thereon, and the interconnection structure penetrates the through hole and is electrically connected to the input/output electrodes of the input/output electrode region.
  • the bonding layer is further formed with a second bonding layer opening.
  • the semiconductor chip and the carrier are in the second bonding layer.
  • a second cavity is formed at the opening, and the second cavity is aligned with at least a part of the input/output electrode area.
  • the adhesive layer is a patterned dry film layer.
  • the method for forming the adhesive layer includes:
  • the dry film layer after development is hardened.
  • the opening includes a first adhesive layer opening and a second adhesive layer opening.
  • the opening also exposes an edge area of the semiconductor chip.
  • the adhesive layer also exposes the edge area of the semiconductor chip.
  • the carrier is a wafer.
  • the method further includes performing a thinning process on the side of the carrier different from the bonding layer formed thereon.
  • the interconnection structure further includes:
  • a solder ball bump is formed on the metal layer under the bump.
  • the material of the interconnection structure includes but is not limited to gold, silver, copper, iron, aluminum, nickel, palladium, or tin.
  • the semiconductor chip includes a filter chip, a MEMS chip, an image sensor chip, or a biosensor chip.
  • the adhesive layer is a dry film layer.
  • the plastic packaging process is a hot press injection molding process
  • the plastic packaging material used in the plastic packaging process includes epoxy resin
  • the present invention provides an air gap type semiconductor device packaging structure, including:
  • a semiconductor chip including an active area and an input/output electrode area
  • the adhesive layer is arranged between the carrier and the semiconductor chip, the adhesive layer has a first adhesive layer opening, and the semiconductor chip and the carrier are in the first adhesive layer.
  • a first cavity is formed at the opening of the junction layer, and the first cavity is aligned with at least a part of the active area of the semiconductor chip;
  • the plastic encapsulation layer, the plastic encapsulation layer and the adhesive layer are located on the same side of the carrier, and the plastic encapsulation layer wraps the semiconductor core and the exposed area of the adhesive layer.
  • At least one through hole which penetrates the carrier and exposes at least part of the input/output electrode area
  • An interconnection structure is formed on the side of the carrier that is different from the adhesive layer formed thereon, and the interconnection structure penetrates the through hole and electrically connects the input/output electrodes of the input/output electrode area.
  • the adhesive layer further has a second adhesive layer opening, the semiconductor chip and the carrier form a second cavity at the second adhesive layer opening, and the second cavity is at least opposite to Quasi-part of the input/output electrode area.
  • the adhesive layer also exposes the edge area of the semiconductor chip.
  • the carrier is a wafer.
  • the semiconductor chip includes a filter chip, a MEMS chip, an image sensor chip, or a biosensor chip.
  • the present invention provides a method for manufacturing an air gap type semiconductor device packaging structure.
  • An adhesive layer with a first adhesive layer opening is formed on a carrier, and a semiconductor chip is placed on the adhesive layer.
  • a first cavity is formed at the opening of the first adhesive layer. The first cavity is aligned with the active area of the semiconductor chip to form an air gap to provide a cavity working environment for the active area.
  • the semiconductor chip is plastically sealed on the carrier, and finally, a through hole penetrating the carrier and the adhesive layer is formed at a position aligned with the input/output electrode area of the semiconductor chip, and in the
  • the carrier forms an interconnection structure on a side different from the adhesive layer formed thereon, and the interconnection structure penetrates the through hole and electrically connects the input/output electrodes of the input/output electrode area.
  • Figure 1 is a schematic diagram of the structure of a SAW filter
  • FIG. 2 is a schematic flowchart of a manufacturing method of an air gap type semiconductor device packaging structure provided by an embodiment of the present invention
  • 3 to 6 are structural schematic diagrams of forming different adhesive layers on the carrier in the manufacturing method of the air gap type semiconductor device packaging structure provided by the embodiment of the present invention.
  • FIG. 7A is a top view of a wafer including a plurality of semiconductor chips in a method for manufacturing an air gap semiconductor device packaging structure provided by an embodiment of the present invention
  • FIG. 7B is a schematic diagram of the structure of the semiconductor chip A in FIG. 7A;
  • FIGS. 8A to 11A are top views of the semiconductor chip from the carrier after the semiconductor chip is placed on the adhesive layer of the carrier in the manufacturing method of the air gap type semiconductor device packaging structure provided by the embodiment of the present invention, and FIGS. 8B to 11B are the semiconductor chip placed on the carrier Schematic diagram of the structure behind the adhesive layer;
  • FIG. 12 is a schematic diagram of the structure after forming a plastic encapsulation layer in the manufacturing method of the air gap type semiconductor device packaging structure provided by the embodiment of the present invention.
  • FIG. 13 is a schematic diagram of the structure of the back surface of the carrier after being thinned in the manufacturing method of the air gap semiconductor device packaging structure provided by the embodiment of the present invention
  • FIG. 14 is a schematic diagram of the structure after forming a through hole in the manufacturing method of the air gap type semiconductor device packaging structure provided by the embodiment of the present invention.
  • 15 is a schematic diagram of the structure after forming the interconnection structure in the manufacturing method of the air gap type semiconductor device packaging structure provided by the embodiment of the present invention.
  • 16 is a schematic structural diagram of an air gap type semiconductor device packaging structure provided by an embodiment of the present invention.
  • 200-semiconductor chip 200a-functional surface of semiconductor chip; 200b-non-functional surface of semiconductor chip; 201-active area; 202-input/output electrode area; 300-wafer containing several semiconductor chips.
  • FIG. 2 is a flowchart of a method for manufacturing an air gap semiconductor device packaging structure provided by this embodiment. As shown in FIG. 2, the method for manufacturing an air gap semiconductor device packaging structure provided by this embodiment includes the following steps:
  • S01 providing a carrier and a semiconductor chip, forming an adhesive layer on the carrier, the adhesive layer is formed with a first adhesive layer opening, and the semiconductor chip includes an active area and an input/output electrode area;
  • S02 Place a semiconductor chip on the adhesive layer, the semiconductor chip and the carrier form a first cavity at the opening of the first adhesive layer, and the first cavity is at least aligned with the semiconductor Part of the active area of the chip;
  • S03 Perform a plastic packaging process on the side of the carrier where the semiconductor chip is fixed, so as to plastic-encapsulate the filter chip on the carrier;
  • S05 An interconnection structure is formed on the side of the carrier that is different from the adhesive layer formed thereon, the interconnection structure penetrates the through hole and is electrically connected to the input/output electrode of the input/output electrode area.
  • FIGS. 3 to 16 are structural schematic diagrams corresponding to the corresponding steps of the manufacturing method of an air gap semiconductor device packaging structure provided by this embodiment.
  • the packaging of the air gap semiconductor device in this embodiment is a wafer Level packaging, the method for manufacturing the air gap type semiconductor device packaging structure provided by this embodiment will be described in detail below with reference to FIG. 2 in conjunction with FIGS. 3 to 16.
  • step S01 is performed to provide the carrier 100 and the semiconductor chip 200.
  • the material of the carrier 100 may be silicon, silicon dioxide, ceramics, glass, organic materials and the like.
  • the carrier 100 in this embodiment is a wafer.
  • the substrate material selected for the wafer may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds, the semiconductor substrate may also include a multilayer structure composed of these materials, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator ( S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeO), etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • S-SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium on insulator
  • FIG. 7A is a top view of a wafer 300 including a plurality of semiconductor chips 200
  • FIG. 7B is a schematic cross-sectional structure diagram of the semiconductor chip A in FIG. 7A
  • the semiconductor chip 200 has a functional surface 200a and a non-functional surface 200b disposed oppositely, and the functional surface 200a of the semiconductor chip 200 includes an active zone (Active Zone) 201 and input/output electrodes. (I/O contact) area 202.
  • the semiconductor chip 200 may be a filter chip, a MEMS chip, an image sensor chip, or a biosensor chip.
  • the filter chip may be a surface acoustic wave (Surface Acoustic Wave, SAW) filter chip or a bulk acoustic wave (Bulk Acoustic Wave) filter chip.
  • Acoustic Wave (BAW) filter chip but not limited to this.
  • the packaging of the surface acoustic wave filter chip is taken as an example to introduce the manufacturing method of the air gap semiconductor device packaging structure.
  • Surface acoustic waves are sound waves that propagate within a finite depth on the surface of an object and travel along the solid-air interface. At the same time, surface acoustic waves are elastic waves with energy concentrated on the surface of the medium; bulk acoustic waves use bulk acoustic signals in different media.
  • the semiconductor chip 200 in this embodiment is a SAW filter chip.
  • a cavity needs to be formed above the active zone (Active Zone) 201 of the functional surface 200a of the filter chip to protect the active zone. Confine the sound wave in the piezoelectric oscillation cavity.
  • the active area 201 in this embodiment includes an area where an interdigital transducer (IDT) is provided.
  • the input/output electrode area 202 is formed with input/output electrodes, and the input/output electrodes are electrically connected to the interdigital transducer of the active area 201.
  • the input/output electrode area 202 is, for example, located around the active area 201.
  • the semiconductor chip 200 has a square shape as a whole
  • the active area 201 has a square shape as a whole
  • the input/output electrode area 202 is located at four corners of the active area 201.
  • an adhesive layer 101 is formed on the carrier 100.
  • the adhesive layer 101 formed on the carrier 100 corresponds to the semiconductor chip 200 on the wafer 300 one-to-one.
  • a filter chip on the wafer 300 is taken as an example for discussion.
  • the material of the adhesive layer 101 is a material that can be patterned and has a certain adhesive force.
  • the adhesive layer 101 is a patterned dry film layer.
  • the material of the dry film layer is, for example, a photoresist film with adhesiveness used in semiconductor chip packaging or printed circuit board manufacturing, usually a photosensitive polymer material, which may be polyimide (PI: polyimide), benzocyclobutene (BCB: bis-BenzoCycloButene), poly-p-phenylene benzobisoxazole (PBO: P-phenylene-2, 6-Benzobis Oxazole), etc.
  • PI polyimide
  • BCB bis-BenzoCycloButene
  • PBO P-phenylene-2, 6-Benzobis Oxazole
  • the manufacturing process of the patterned dry film layer includes, for example, attaching a photoresist film to a surface of the carrier 100, and rolling the photoresist film with a roller to make it close to the carrier 100; The photoresist film is baked; next, the photoresist film is exposed and developed to remove the photoresist film in the unexposed area, and an opening is formed on the carrier 100; then, the development The latter photoresist film is hardened to enhance the adhesion between the photoresist film and the carrier 100, and finally a patterned dry film layer is formed on the carrier 100, which is the adhesive layer 101 .
  • the first adhesive layer opening 110' formed in the adhesive layer 101 corresponds to the active region 201 in the semiconductor chip 200, so that after the carrier 100 and the semiconductor chip 200 are aligned A first cavity 110 is formed between the two.
  • the adhesive layer 101 forms a first adhesive layer opening 110 ′ corresponding to the active area 201 of the semiconductor chip 200, and other areas on the carrier 100 may all cover the adhesive layer 101.
  • it can also be specifically designed according to actual process requirements so as to cover only a predetermined area outside the active area 201, for example, a second adhesive layer opening 120' is formed at the area corresponding to the input/output electrode 202 of the semiconductor chip 200 That is, after placing the semiconductor chip 200 on the adhesive layer 101, a second cavity 120 is formed at the area of the input/output electrode 202, as shown in FIGS. 8B and 10B, so as to facilitate subsequent formation of through holes.
  • the carrier 100 and the through hole 103 of the adhesive layer 101 are examples of the adhesive layer 101.
  • the adhesive layer 101 covers a smaller area of the carrier 100, for example, forming a first adhesive layer opening 110' At the same time as the second adhesive layer opening 120', the adhesive layer 101 also exposes the edge area 100a of the carrier 100, as shown in FIG. 3.
  • the first adhesive layer opening 110' is formed, the The junction layer 101 also exposes the edge area 100a of the carrier 100, as shown in FIG. 4.
  • the additional exposure of the edge area 100a of the carrier 100 can facilitate the subsequent formation of a plastic encapsulation layer 102 so that the plastic encapsulation layer 102 covers the exposed carrier 100, the exposed adhesive layer 101 and the semiconductor chip 200, The adhesive layer 101 and the semiconductor chip 200 are wrapped to achieve a better molding effect.
  • the adhesive layer 101 may also be formed on the semiconductor chip 200, and then the semiconductor chip 200 with the adhesive layer 101 formed thereon is combined with the carrier 100.
  • an adhesive layer 101 may be formed on a wafer 300 containing a plurality of semiconductor chips 200, and a first adhesive layer opening 110' is formed in the adhesive layer 101 to expose the material in the filter chip 200 A source region 201 to form a first cavity 110 between the carrier 100 and the semiconductor chip 200 after they are aligned.
  • the second adhesive layer opening 120' may also be formed in the region corresponding to the input/output electrode 202 of the semiconductor chip 200, and after the semiconductor chip 200 is placed on the adhesive layer 101, the input/output electrode A second cavity 120 is formed in the area 202 to facilitate subsequent formation of a through hole 103 penetrating the carrier 100 and the adhesive layer 101.
  • the adhesive layer 101 covers a smaller area of the carrier 100, for example, forming a first adhesive layer opening 110' At the same time as the second adhesive layer opening 120 ′, the adhesive layer 101 also exposes the edge area of the semiconductor chip 200.
  • the adhesive layer 101 exposes the edge area of the semiconductor chip 200.
  • the edge area 100a of the semiconductor chip 200 is additionally exposed, which facilitates the subsequent formation of a plastic encapsulation layer 102, so that the plastic encapsulation layer 102 covers the exposed carrier 100, the exposed adhesive layer 101 and the semiconductor chip 200 , Wrap the adhesive layer 101 and the semiconductor chip 200 to achieve a better molding effect.
  • the thickness of the adhesive layer 101 directly determines the thickness of the first cavity 110 to be formed subsequently, and the thickness of the first cavity 110 is related to the resonant frequency of the filter.
  • the required resonance frequency is used to set the thickness of the adhesive layer 101.
  • the thickness of the adhesive layer 101 may be 2 ⁇ m to 200 ⁇ m, for example, 50 ⁇ m or 80 ⁇ m or 100 ⁇ m.
  • step S02 is performed, the semiconductor chip 200 is placed on the adhesive layer 101, a first cavity 110 is formed at the first adhesive layer opening 110', and the first cavity 110 is aligned The active area 201 of the semiconductor chip 200.
  • the first cavity may be formed only at the first adhesive layer opening 110'.
  • the second adhesive layer opening 120' while forming the first cavity 110 at the first adhesive layer opening 110', it is also formed at the second adhesive layer opening 120'.
  • the second cavity 120 is aligned with the input/output electrode area 202 of the semiconductor chip 200, and in addition, the edge area 100a of the carrier 100 is also exposed. Or, as shown in FIGS.
  • the semiconductor chip 200 is directly mounted on the carrier 100 through the adhesive layer 101.
  • the adhesive layer 101 can prevent the plastic material from entering the active area 201 of the semiconductor chip 200 during the subsequent plastic packaging process, thereby avoiding active Pollution of area 201.
  • the area of the first cavity 110 is equal to the area of the active region 201 of the semiconductor chip 200, and they are completely opposite.
  • the area of the first cavity 110 may not be equal to the area of the active region 201, as long as the first cavity 110 faces the active region 201 of the semiconductor chip 200, and the area of the semiconductor chip 200 It is sufficient that the projection of the active area 201 at least partially falls into the first cavity 110.
  • the area of the second cavity 120 and the area of the input/output electrode region 202 of the semiconductor chip 200 may be equal or unequal.
  • FIG. 12 shows that the area of the input/output electrode region 202 is larger than The area of the second cavity 120.
  • the second cavity 120 faces the input/output electrode area 202, and the projection of the input/output electrode area 202 at least partially falls into the second cavity 120.
  • the second cavity 120 is aligned with the central area of the input/output electrode area 202.
  • this embodiment only uses the adhesive layer 101 shown in FIG. 12 for introduction.
  • the process of the remaining steps is the same. Discuss one by one.
  • step S03 is performed to perform a plastic encapsulation process on the side of the carrier 100 where the semiconductor chip 200 is mounted, so as to plastic encapsulate the semiconductor chip 200 on the carrier 100.
  • the carrier 100 is subjected to an injection molding process, and a plastic encapsulation layer 102 is formed on the side of the carrier 100 where the semiconductor chip 200 is fixed.
  • the plastic encapsulation layer 102 wraps the semiconductor chip 200 and the semiconductor chip 200. Mentioned adhesive layer 101.
  • the plastic sealing layer 102 can be made of any resin material that can be hot melted, for example, it can include polycarbonate (PC), polyethylene terephthalate (PET), polyethersulfone, polyphenylene ether, poly Thermoplastic resin of amide, polyetherimide, methacrylic resin or cyclic polyolefin resin.
  • the molding layer 102 is made of epoxy resin.
  • the plastic encapsulation layer 102 can be formed by a hot-press injection molding process.
  • the hot-press injection molding process has good filling performance, which can make the injection molding agent fill the carrier 100 and wrap the semiconductor chip 200 well, thereby having a good packaging effect. .
  • step S04 is performed to form a through hole 103 penetrating the carrier 100 and the adhesive layer 101 at a position aligned with the input/output electrode region 202 of the semiconductor chip 200, as shown in FIG. 14.
  • the through hole 103 may be formed by etching, laser or mechanical drilling, and the through hole 103 penetrates the carrier 100 and the adhesive layer 101 to the input/output electrode 202 of the semiconductor chip 200.
  • the through hole 103 is cleaned.
  • the through hole 103 can be cleaned by reactive ion etching (RIE) to facilitate subsequent interconnection structures. Formation.
  • RIE reactive ion etching
  • the carrier 100 is first turned upside down, and then the carrier 100 is thinned, for example, by chemical mechanical polishing ( One or more of CMP), wet etching or dry etching is to thin the side of the carrier 100 that is different from the adhesive layer 101 formed thereon, so as to facilitate the formation of the through hole 103 form.
  • chemical mechanical polishing One or more of CMP
  • wet etching or dry etching is to thin the side of the carrier 100 that is different from the adhesive layer 101 formed thereon, so as to facilitate the formation of the through hole 103 form.
  • step S05 is performed.
  • an interconnection structure 104 is formed on the side of the carrier 100 different from the adhesive layer 101 formed thereon, and the interconnection structure 104 penetrates the through hole 103 and is electrically connected.
  • the input/output electrodes of the input/output electrode area 202 are connected.
  • the interconnection structure 104 is formed by a metal plug and a metal wiring, for example, a metal plug is formed in the through hole 103, and the carrier 100 is different from the adhesive layer 101 formed thereon. Perform metal wiring on one side.
  • the interconnection structure 104 can be formed in the following manner: first, a metal layer that fills the through hole 103 and covers the surface of the carrier 100 is formed by metal pressure filling, electroplating, or deposition, and then photolithography, etching, etc. The metal layer is patterned to form the interconnection structure 104, and the input/output electrode 202 is led out.
  • the material of the interconnection structure 104 is, for example, one of gold, silver, copper, iron, aluminum, nickel, palladium, or tin or an alloy thereof.
  • the interconnection structure 104 further includes: forming a passivation layer 105 on the side of the carrier 100 that is different from the adhesive layer 101 formed thereon, and the passivation layer 105 covers the The interconnect structure 104 and the carrier 100 are different from the side where the bonding layer 101 is formed; then, a passivation layer opening is formed in the passivation layer 105 by photolithography and etching processes to expose the interconnect structure 104, and fill the opening of the passivation layer with a metal material to make an under-bump metal layer (UBM) 106; then, reflow the balls on the under-bump metal layer 106 to form solder bumps 107, as shown in FIG. 16 shown.
  • the solder bump 107 is, for example, a metal material, including one of tin, lead, copper, silver, gold and other metals or an alloy thereof.
  • the air gap type semiconductor device packaging structure formed above is cut to form several individual semiconductor devices.
  • a semiconductor chip 200 the semiconductor chip 200 includes an active area 201 and an input/output electrode 202;
  • the adhesive layer 101 is arranged between the carrier 100 and the semiconductor chip 200, the adhesive layer 101 has a first adhesive layer opening 110', the semiconductor chip 200 and the semiconductor chip 200
  • the carrier 100 forms a first cavity 110 at the first adhesive layer opening 110', and the first cavity 110 is aligned with at least a part of the active area 201 of the semiconductor chip;
  • the plastic encapsulation layer 102, the plastic encapsulation layer 102 and the adhesive layer 101 are located on the same side of the carrier 100, and the plastic encapsulation layer 102 covers the semiconductor chip 200 and the exposed area of the adhesive layer 101;
  • At least one through hole 103 which penetrates the carrier 100 and exposes at least a part of the input/output electrode area 202 of the semiconductor chip 200;
  • the interconnection structure 104 is formed on the side of the carrier 100 different from the adhesive layer 101 formed thereon.
  • the interconnection structure 104 penetrates the through hole 103 and is electrically connected to the input/output electrode region 202. Output electrode.
  • the material of the carrier 100 may be silicon, silicon dioxide, ceramics, glass, organic materials and the like.
  • the carrier 100 is a wafer.
  • the material of the adhesive layer 101 is a material that can be patterned and has a certain adhesive force.
  • the semiconductor chip 200 includes a filter chip, a MEMS chip, an image sensor chip, and a biosensor chip.
  • the filter chip may be a SAW filter chip or a BAW filter chip.
  • the adhesive layer 101 is a patterned dry film layer.
  • the material of the dry film layer is, for example, a photoresist film with adhesiveness used in semiconductor chip packaging or printed circuit board manufacturing, and is usually a photosensitive polymer material.
  • the plastic encapsulation layer 102 is made of epoxy resin, and the material of the interconnect structure 104 is, for example, one of gold, silver, copper, iron, aluminum, nickel, palladium, or tin or an alloy thereof.
  • the area of the first cavity 110 is equal to the area of the active region 201 of the semiconductor chip 200, and they are completely opposite. However, in specific implementation, the area of the first cavity 110 may not be equal to the area of the active region 201, as long as the first cavity 110 faces the active region 201 of the semiconductor chip 200, and the area of the semiconductor chip 200 It is sufficient that the projection of the active area 201 at least partially falls into the first cavity 110.
  • the adhesive layer 101 also has a second adhesive layer opening 120', the semiconductor chip and the carrier 100 form a second cavity 120 at the second adhesive layer opening 120', and the second cavity
  • the cavity 120 is aligned with at least a part of the input/output electrode region 202.
  • the second cavity 120 communicates with the through hole 103, and the interconnection structure 104 penetrates the through hole 103 and the second cavity 120 and is connected to the input/output electrode.
  • the adhesive layer 101 does not have the second adhesive layer opening 120', and subsequently the through hole 103 is formed by etching the carrier 100 and the adhesive layer 101 to expose The input/output electrodes of the input/output electrode area 202 are removed, and then metal plugs are formed in the through holes 103, and metal wiring is performed on the side of the carrier 100 different from the adhesive layer 101 to form Interconnect structure 104.
  • a passivation layer 105 is provided on the side of the carrier 100 away from the adhesive layer 101, and the passivation layer 105 covers the interconnection structure 104 and the carrier 100 different from the adhesive layer formed thereon.
  • an under bump metal layer (UBM) 106 is formed on the passivation layer 105, so as to reflow the balls on the under bump metal layer 106 to form a solder bump 107.
  • the solder ball bump 107 is connected to the interconnect structure 104 through an under bump metal layer (UBM) 106, thereby realizing the connection with the input/output electrode 202 of the semiconductor chip 200, and realizing the introduction and extraction of electrical signals .
  • the air gap type semiconductor device packaging structure can be manufactured by wafer-level packaging, and then the air gap type semiconductor device packaging structure is cut into a number of individual semiconductor devices through a cutting process.
  • the present invention provides an air gap type semiconductor device packaging structure and a manufacturing method thereof.
  • An adhesive layer with a first adhesive layer opening is formed on a carrier, and a semiconductor chip is placed on the adhesive layer, A first cavity is formed at the opening of the first adhesive layer, and the first cavity is aligned with at least a part of the active area of the semiconductor chip to form an air gap to provide a cavity working environment for the active area,
  • the semiconductor chip is plastic-encapsulated on the carrier through a plastic encapsulation process, and finally, a through hole penetrating the carrier is formed at a position aligned with the input/output electrode area of the semiconductor chip, and a through hole is formed in the carrier.
  • An interconnection structure is formed on a side different from the adhesive layer, and the interconnection structure penetrates the through hole and electrically connects the input/output electrodes of the input/output electrode area.

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Abstract

一种空气隙型半导体器件封装结构及其制作方法，该制作方法包括：在载体（100）上形成具有第一粘结层开口（110'）的粘结层（101），将半导体芯片（200）置于所述粘结层（101）上，在所述第一粘结层开口（110'）处形成第一空腔（110），所述第一空腔（110）至少对准所述半导体芯片（200）的有源区域（201）的一部分，然后，通过塑封工艺将所述半导体芯片（200）塑封在所述载体（100）上，最后，在与所述半导体芯片（200）的输入/输出电极区域（202）对准的位置处形成贯穿所述载体的通孔（103），所述载体（100）异于形成有粘结层（101）的一面形成互连结构（104），所述互连结构（104）贯穿通孔（103）并电性连接输入/输出电极。该制作方法不需要较长的引脚和上盖密封，减小了封装体积和材料成本。

Description

空气隙型半导体器件封装结构及其制作方法 技术领域
本发明涉及半导体制造领域，特别涉及一种空气隙型半导体器件封装结构及其制作方法。
背景技术
半导体器件中，部分器件有源区域会有需要提供空腔环境以保证正常工作，器件制备或封装中需要在器件有源区形成空气隙。如滤波器、MEMS器件等，以SAW滤波器为例。
SAW是Surface Acoustic Wave(声表面波)的简称，是在压电固体材料表面产生和传播振幅随深入固体材料的深度增加而迅速减小的弹性波。SAW滤波器作为一种常用电子元件，具有允许某一部分频率的信号顺利的通过、另外一部分频率的信号则受到较大的抑制的功能，被广泛应用于电视、卫星通信、光纤通信和移动通信的基站、直放站、手机、GPS、电子对抗和雷达等领域。随着滤波器封装技术的日益发展，SAW滤波器也向着高性能、体积小、重量轻、成本低的方向快速发展。
如图1所示，SAW滤波器10中，电输入信号经由端口(I/O接点)12提供至SAW滤波器内部，其中电输入信号通过在压电基板11上由交叉排列的金属电极13组成的叉指变换器(Interdigital Transducers，IDT)14被转换成声波15，声波15主要沿着压电基板11的表面与叉指电极升起的方向传播，故称为声表面波，其中，叉指变换器所在的区域为SAW滤波器芯片的有源区域。在SAW滤波器的封装过程中需要在有源区域周围形成一空腔，以保证声波的产生与传播。
目前SAW滤波器的封装技术主要是金属封装、塑料封装、表贴封装。上述SAW滤波器的封装过程中至少要用到的底座和上盖，即将SAW滤波器芯片粘贴在底座上再用上盖封住。采用金属封装和塑料封装技术的SAW滤波器具有比较长的引脚，导致器件的体积太大。采用表贴封装技术，虽然应用范围较广，但制作工艺复杂，陶瓷材料诸如HTCC(高温共烧陶瓷) 及LTCC(低温共烧陶瓷)价格昂贵。因此，需要找到一种封装体尺寸小，制作简单，价格低廉的滤波器的封装方法。
发明内容
本发明提供一种空气隙型半导体器件封装结构的制作方法，目的在于缩小封装体的体积，简化制作工艺，降低成产成本。
本发明提供一种空气隙型半导体器件封装结构的制作方法，包括：
提供载体和半导体芯片，在所述载体上形成粘结层，所述粘结层形成有第一粘结层开口，所述半导体芯片包括有源区域和输入/输出电极区域；
将半导体芯片置于所述粘结层上，所述半导体芯片与所述载体在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分；
在所述载体形成有所述粘结层的一面进行塑封工艺，以将所述半导体芯片塑封在所述载体上；
形成贯穿所述载体的通孔，所述通孔至少对准所述输入/输出电极区域的一部分；以及
在所述载体异于形成有所述粘结层的一面形成互连结构，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。
可选的，所述粘结层还形成有第二粘结层开口，将所述半导体芯片置于所述粘结层上后，所述半导体芯片与所述载体在所述第二粘结层开口处形成第二空腔，所述第二空腔至少对准所述输入/输出电极区域的一部分。
可选的，所述粘结层为图案化的干膜层。
可选的，所述粘结层的形成方法包括：
在所述载体上形成干膜层并进行烘烤；
对所述干膜层进行曝光、显影，以在所述载体上形成开口；
对显影后的所述干膜层进行坚膜处理。
可选的，所述开口包括第一粘结层开口和第二粘结层开口。
可选的，所述开口还暴露所述半导体芯片的边缘区域。
可选的，所述粘结层还暴露所述半导体芯片的边缘区域。
可选的，其特征在于，所述载体为晶圆。
可选的，在进行塑封工艺之后，形成贯穿所述载体和所述粘结层的通孔之前，还包括，对所述载体异于形成有所述粘结层的一面进行减薄工艺。
可选的，形成互连结构后还包括：
在所述载体异于形成有所述粘结层的表面形成钝化层，所述钝化层覆盖所述互连结构；
在所述钝化层中形成钝化层开口；
在所述钝化层开口处形成电性连接所述互连结构的凸点下金属层；以及
在所述凸点下金属层上形成焊球凸块。
可选的，所述互连结构的材质包括但不限于金、银、铜、铁、铝、镍、钯或锡。
可选的，所述半导体芯片包括滤波器芯片、MEMS芯片、图像传感器芯片或生物传感器芯片。
可选的，所述粘结层为干膜层。
可选的，所述塑封工艺为热压注塑成型工艺，所述塑封工艺采用的塑封材料包括环氧树脂。
本发明提供一种空气隙型半导体器件的封装结构，包括：
载体；
半导体芯片，所述半导体芯片包括有源区域和输入/输出电极区域；
粘结层，所述粘结层被布置于所述载体和所述半导体芯片之间，所述粘结层具有第一粘结层开口，所述半导体芯片和所述载体在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分；
塑封层，所述塑封层和所述粘结层位于所述载体的同一侧，且所述塑封层包裹所述半导体芯及所述粘结层暴露的区域。
至少一个通孔，所述通孔贯穿所述载体并至少暴露出部分所述输入/输出电极区域；以及，
互连结构，形成在所述载体异于形成有所述粘结层的一面，所述互连 结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。
可选的，所述粘结层还具有第二粘结层开口，所述半导体芯片与所述载体在所述第二粘结层开口处形成第二空腔，所述第二空腔至少对准所述输入/输出电极区域的一部分。
可选的，所述粘结层还暴露所述半导体芯片的边缘区域。
可选的，所述载体为晶圆。
可选的，所述半导体芯片包括滤波器芯片、MEMS芯片、图像传感器芯片或生物传感器芯片。
综上所述，本发明提供一种空气隙型半导体器件封装结构的制作方法，在载体上形成具有第一粘结层开口的粘结层，将半导体芯片置于所述粘结层上，在所述第一粘结层开口处形成第一空腔，所述第一空腔对准所述半导体芯片的有源区域，形成空气隙，为有源区域提供空腔工作环境，然后，通过塑封工艺将所述半导体芯片塑封在所述载体上，最后，在与所述半导体芯片的输入/输出电极区域对准的位置处形成贯穿所述载体和所述粘结层的通孔，在所述载体异于形成有所述粘结层的一面形成互连结构，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。本发明提供的空气隙型半导体器件封装结构的制作方法，不需要较长的引脚，也无需利用上盖密封以提供出有源区域所需空腔环境，有利于简化封装工艺，减小封装体的体积，降低材料成本。
附图说明
图1为一种SAW滤波器的结构示意图；
图2为本发明实施例提供的空气隙型半导体器件封装结构的制作方法的流程示意图；
图3至图6是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中在载体上形成不同粘结层的结构示意图；
图7A是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中一包含有若干半导体芯片的晶圆的俯视图；
图7B为图7A中半导体芯片A的结构示意图；
图8A至11A是本发明实施例提供的空气隙型半导体器件封装结构的 制作方法中半导体芯片置于载体的粘结层上后从载体处看的俯视图，图8B至11B是半导体芯片置于载体的粘结层上后的结构示意图；
图12是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中形成塑封层后的结构示意图；
图13是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中形成载体背面减薄后的结构示意图；
图14是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中形成通孔后的结构示意图；
图15是本发明实施例提供的空气隙型半导体器件封装结构的制作方法中形成互连结构后的结构示意图；
图16是本发明实施例提供的空气隙型半导体器件封装结构的结构示意图。
附图标记说明：
10-SAW滤波器；11-压电基板；12-I/O接点；13-金属电极；14-叉指变换器；15-声波；
100-载体；100a-载体边缘区域；101-粘结层；110′-第一粘结层开口；120′-第二粘结层开口；110-第一空腔；120-第二空腔；102-塑封层；103-通孔；104-互连结构；105-钝化层；106-凸点下金属层；107-焊球凸块；
200-半导体芯片；200a-半导体芯片的功能面；200b-半导体芯片的非功能面；201-有源区域；202-输入/输出电极区域；300-包含若干半导体芯片的晶圆。
具体实施方式
以下结合附图和具体实施例对本发明的空气隙型半导体器件封装结构及其制作方法作进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
在说明书和权利要求书中的术语“第一”、“第二”等用于在类似要素 之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换，例如可使得本文所述的本发明实施例能够以不同于本文所述的或所示的其他顺序来操作。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
图2本实施例提供的一种空气隙型半导体器件封装结构的制作方法的流程图，如图2所示，本实施例提供的空气隙型半导体器件封装结构的制作方法，包括以下步骤：
S01：提供载体和半导体芯片，在所述载体上形成粘结层，所述粘结层形成有第一粘结层开口，所述半导体芯片包括有源区域和输入/输出电极区域；
S02：将半导体芯片置于所述粘结层上，所述半导体芯片与所述载体在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分；
S03：在所述载体固定有所述半导体芯片的一面进行塑封工艺，以将所述滤波器芯片塑封在所述载体上；
S04：形成贯穿所述载体的通孔，所述通孔至少对准所述输入/输出电极区域的一部分；以及
S05：在所述载体异于形成有所述粘结层的一面形成互连结构，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。
图3～图16为本实施例提供的一种空气隙型半导体器件封装结构的制作方法的相应步骤对应的结构示意图，需要说明的是，本实施例中空气隙型半导体器件的封装为晶圆级封装，以下将参考图2并结合图3～图16详细说明本实施例提供的空气隙型半导体器件封装结构的制作方法。
首先，执行步骤S01，提供载体100和半导体芯片200。所述载体100的材料可以是硅、二氧化硅、陶瓷、玻璃、有机材料等。本实施例中所述 载体100为晶圆，示例性地，晶圆所选用的衬底材料可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物，所述半导体衬底还可以包括这些材料构成的多层结构，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeO)等。
图7A为一包含有若干半导体芯片200的晶圆300的俯视图，图7B为图7A中半导体芯片A的剖面结构示意图。如图7A和图7B所示，所述半导体芯片200具有相对设置的功能面200a及非功能面200b，所述半导体芯片200的功能面200a包括有源区域(Active Zone)201和输入/输出电极(I/O接点)区域202。所述半导体芯片200可以是滤波器芯片、MEMS芯片、图像传感器芯片、生物传感器芯片，具体的，所述滤波器芯片可以是声表面波(Surface Acoustic Wave，SAW)滤波器芯片或体声波(Bulk Acoustic Wave，BAW)滤波器芯片，但不以此为限。本实施例中以声表面波滤波器芯片的封装为例介绍空气隙型半导体器件封装结构的制作方法。声表面波是声波在物体表面有限深度内进行传播，沿固体与空气界面传播，同时，声表面波是一种能量集中在介质表面传播的弹性波；体声波利用的是体声波信号在不同介质传播时，在两电极与空气的交界处发生反射，体声波与载体表面形成一个空气腔体，将声波限制在压电振荡腔内。因此，对于声表面波和体声波来说，都需要在与载体的交界面处形成一个密闭的腔体，用于限制声波的传播路径。本实施例中所述半导体芯片200为SAW滤波器芯片，对于SAW滤波器芯片需要在滤波器芯片的功能面200a的有源区域(Active Zone)201的上方形成一空腔以保护该有源区域，将声波限制在压电振荡腔内。本实施例中有源区域201包括设置有叉指变换器(IDT)的区域。所述输入/输出电极区域202形成有输入/输出电极，所述输入/输出电极与有源区域201的叉指变换器电性连接。所述输入/输出电极区域202例如是位于所述有源区域201的周围。具体的，如图7A所示，所述半导体芯片200整体呈方形，所述有源区域201整体亦呈方形，所述输入/输出电极区域202位于所述有源区域201的四个角落处。
然后，如图3至图6所示，在所述载体100上形成粘结层101。所述载 体100上形成的粘结层101与晶圆300上的所述半导体芯片200一一对应，本实施例中，以晶圆300上一滤波器芯片为例进行论述。所述粘结层101的材料为可被图形化且具有一定黏附力的材料。本实施例中，所述粘结层101为图案化的干膜层(Dry film)。所述干膜层的材料例如是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，通常为一种光敏性聚合物材料，可以为聚酰亚胺(PI:polyimide)、苯并环丁烯(BCB:bis-BenzoCycloButene)、聚对亚苯基苯并双恶唑(PBO:P-phenylene-2，6-BenzobisOxazole)等。图案化的干膜层的制造过程例如是包括：将光致抗蚀膜贴在所述载体100的一表面上，并利用滚轮碾压光致抗蚀膜使其紧贴载体100；接着，对光致抗蚀膜进行烘烤；接着，对光致抗蚀膜进行曝光、显影处理，以将未曝光区域的光致抗蚀膜被去除，在所述载体100上形成开口；接着，对显影后的光致抗蚀膜进行坚膜处理，以增强光致抗蚀膜与载体100之间的粘结力，最终在所述载体100上形成图案化的干膜层，即为粘结层101。其中，所述粘结层101中形成的第一粘结层开口110′与所述半导体芯片200中的有源区域201相对应，以便于在所述载体100与所述半导体芯片200对准之后在二者之间形成第一空腔110。
本实施例中，所述粘结层101在对应半导体芯片200的有源区域201处形成第一粘结层开口110′，在所述载体100上的其他区域可都覆盖粘结层101。具体实施时，也可根据实际工艺需要来具体设计从而仅覆盖有源区域201之外的预定区域，例如在对应所述半导体芯片200输入/输出电极202区域处形成第二粘结层开口120′，即，将半导体芯片200置于所述粘结层101上后，在所述输入/输出电极202区域处形成第二空腔120，如图8B和图10B所示，以便于后续形成贯穿所述载体100和所述粘结层101的通孔103。或者，在保证所述载体100与所述半导体芯片200之间粘结力的前提下，所述粘结层101覆盖较小区域的所述载体100，例如，形成第一粘结层开口110′和第二粘结层开口120′的同时，粘结层101还暴露出所述载体100的边缘区域100a，如图3所示，再例如，形成第一粘结层开口110′的同时，粘结层101还暴露出所述载体100的边缘区域100a，如图4所示。额外暴露出所述载体100的边缘区域100a，可便于在后续形成塑封层102，使所 述塑封层102覆盖暴露的所述载体100、暴露的所述粘结层101及所述半导体芯片200，将所述粘结层101和所述半导体芯片200包裹以达到较好的塑封效果。
可以理解的，本发明其他实施例中，所述粘结层101也可以形成在所述半导体芯片200上，然后将形成有粘结层101的半导体芯片200与载体100结合。具体的，可以在包含有若干半导体芯片200的晶圆300上形成粘结层101，所述粘结层101中形成第一粘结层开口110′以暴露出所述滤波器芯片200中的有源区域201，以在所述载体100与所述半导体芯片200对准之后在二者之间形成第一空腔110。当然，也可以在对应所述半导体芯片200输入/输出电极202区域处形成第二粘结层开口120′，在半导体芯片200置于所述粘结层101上后，在所述输入/输出电极202区域处形成第二空腔120，以便于后续形成贯穿所述载体100和所述粘结层101的通孔103。或者，在保证所述载体100与所述半导体芯片200之间粘结力的前提下，所述粘结层101覆盖较小区域的所述载体100，例如，形成第一粘结层开口110′和第二粘结层开口120′的同时，粘结层101还暴露出所述半导体芯片200的边缘区域。再例如，形成第一粘结层开口110′的同时，粘结层101暴露出所述半导体芯片200的边缘区域。额外暴露出所述半导体芯片200的边缘区域100a，可便于在后续形成塑封层102，使所述塑封层102覆盖暴露的所述载体100、暴露的所述粘结层101及所述半导体芯片200，将所述粘结层101和所述半导体芯片200包裹以达到较好的塑封效果。
本实施例中，所述粘结层101的厚度直接决定后续形成的第一空腔110的厚度，所述第一空腔110的厚度与滤波器的谐振频率有关，因此，可以根据滤波器所需要的谐振频率来设定所述粘结层101的厚度。示例性的，所述粘结层101的厚度可以为2μm～200μm，例如50μm或80μm或100μm。
接着，执行步骤S02，将所述半导体芯片200置于所述粘结层101上，在所述第一粘结层开口110′处形成第一空腔110，所述第一空腔110对准所述半导体芯片200的有源区域201。如图11A和图11B所示，可以仅在所述第一粘结层开口110′处形成第一空腔。具体实施时，也可以如图8A和 图8B所示，在所述第一粘结层开口110′处形成第一空腔110的同时，还在所述第二粘结层开口120′处形成第二空腔120，所述第二空腔120与所述半导体芯片200的输入/输出电极区域202对准，此外，所述载体100的边缘区域100a也被暴露出来。或者，如图9A和图9B所示，仅在所述第一粘结层开口110′处形成第一空腔110的同时，与此同时，所述载体100的边缘区域100a也被暴露出来。再或者，如图10A和图10B所示，在所述第一粘结层开口110′处形成第一空腔110的同时，在所述第二粘结层开口120′处形成第二空腔120，且所述载体100的边缘区域100a被粘结层101覆盖。
本实施例中通过粘结层101直接将半导体芯片200贴装在载体100上，所述粘结层101可以阻挡后续的塑封过程中塑封材料进入半导体芯片200的有源区域201，从而避免有源区域201的污染。
本实施例中，所述第一空腔110的面积与半导体芯片200的有源区域201的面积相等，且二者完全正对。但在具体实施时，所述第一空腔110的面积也可以与有源区域201的面积不相等，只要所述第一空腔110面向半导体芯片200的有源区域201，且半导体芯片200的有源区域201的投影至少部分落入在所述第一空腔110内即可。同理，所述第二空腔120的面积与半导体芯片200的所述输入/输出电极区域202的面积可以相等也可以不相等，图12所示出的是输入/输出电极区域202的面积大于第二空腔120的面积的情形。只要所述第二空腔120面向所述输入/输出电极区域202，且所述输入/输出电极区域202的投影至少部分落入在第二空腔120内即可。较佳的，第二空腔120对准所述输入/输出电极区域202的中心区域。
对于空气隙型半导体器件封装结构制作方法余下的步骤，本实施例仅采用图12所示的粘结层101进行介绍，对于其他形状设置的粘结层101，余下步骤的工艺相同，在此不一一论述。
接着，执行步骤S03，在所述载体100贴装有所述半导体芯片200的一面进行塑封工艺，以将所述半导体芯片200塑封在所述载体100上。具体的，如图12所示，对所述载体100进行注塑工艺，在所述载体100固定有所述半导体芯片200的一面形成塑封层102，所述塑封层102包裹所述半导体芯片200和所述粘结层101。所述塑封层102可采用任意能够热熔的树脂 材料进行制作，例如可包括诸如聚碳酸脂(PC)、聚对苯二甲酸乙二醇酯(PET)、聚醚砜、聚苯醚、聚酰胺、聚醚酰亚胺、甲基丙烯酸树脂或环聚烯烃系树脂的热塑性树脂。在本发明实施例中，所述塑封层102由环氧树脂制成。具体地，可以通过热压注塑工艺形成所述塑封层102，热压注塑工艺的填充性能较好，可以使注塑剂较好地填充在载体100上并包裹半导体芯片200，从而具有良好的封装效果。
接着，执行步骤S04，在与所述半导体芯片200的输入/输出电极区域202对准的位置处形成贯穿所述载体100和所述粘结层101的通孔103，如图14所示。所述通孔103可以通过刻蚀、激光或者机械钻的方法来形成，所述通孔103贯穿所述载体100和所述粘结层101至所述半导体芯片200的输入/输出电极202。且在较佳方案中，所述通孔103完成后，对所述通孔103进行清洁，例如可以通过反应离子刻蚀(RIE)对所述通孔103进行清洁处理，以便于后续互连结构的形成。在本发明的另一实施例中，形成所述通孔103之前，如图13所示，先将所述载体100倒置，然后对所述载体100进行减薄工艺，例如可以通过化学机械研磨(CMP)、湿法刻蚀或干法刻蚀方式中的一种或多种对所述载体100的异于形成有所述粘结层101的一面进行减薄，以便于所述通孔103的形成。
接着，执行步骤S05，如图15所示，在所述载体100异于形成有所述粘结层101的一面形成互连结构104，所述互连结构104贯穿所述通孔103并电性连接所述输入/输出电极区域202的输入/输出电极。示例性的，所述互连结构104采用金属插塞加金属布线的方式形成，例如在所述通孔103内形成金属插塞，在所述载体100异于形成有所述粘结层101的一面进行金属布线。所述互连结构104可以如下方式形成：先采用金属压填、电镀或沉积的方式形成填充所述通孔103并覆盖所述载体100表面的金属层，然后采用光刻、刻蚀等工艺对金属层进行图形化，从而形成互连结构104，实现输入/输出电极202引出。所述互连结构104的材料例如为金、银、铜、铁、铝、镍、钯或锡中的一种或其合金。
本实施例中，在形成所述互连结构104之后，还包括：在所述载体100异于形成有所述粘结层101的一面形成钝化层105，所述钝化层105覆盖所 述互连结构104和所述载体100异于形成有所述粘结层101的一面；然后，利用光刻、刻蚀工艺在所述钝化层105中形成钝化层开口以暴露出互连结构104，并在所述钝化层开口处填充金属材料制作凸点下金属层(UBM)106；接着，在所述凸点下金属层106上植球回流，形成焊球凸块107，如图16所示。所述焊球凸块107例如为金属材料，包括锡、铅、铜、银、金等金属中的一种或其合金。
最后，对上述形成的空气隙型半导体器件封装结构进行切割，切割形成若干单个半导体器件。
相应的，本实施例还提供一种空气隙型半导体器件的封装结构，包括：
载体100；
半导体芯片200，所述半导体芯片200包括的有源区域201和输入/输出电极202；
粘结层101，所述粘结层101被布置于所述载体100和所述半导体芯片200之间，所述粘结层101具有第一粘结层开口110′，所述半导体芯片200和所述载体100在所述第一粘结层开口110′处形成第一空腔110，所述第一空腔110至少对准所述半导体芯片的有源区域201的一部分；
塑封层102，所述塑封层102和所述粘结层101位于所述载体100的同一侧，且所述塑封层102包覆所述半导体芯片200及所述粘结层101暴露的区域；
至少一个通孔103，所述通孔103贯穿所述载体100并至少暴露出部分所述半导体芯片200的输入/输出电极区域202；以及
互连结构104，形成在所述载体100异于形成有所述粘结层101一面，所述互连结构104贯穿所述通孔103并电性连接所述输入/输出电极区域202的输入/输出电极。
其中，所述载体100的材料可以是硅、二氧化硅、陶瓷、玻璃、有机材料等。本实施例中所述载体100为晶圆。所述粘结层101的材料为可被图形化且具有一定黏附力的材料。所述半导体芯片200包括滤波器芯片、MEMS芯片、图像传感器芯片、生物传感器芯片，例如所述滤波器芯片可以是SAW滤波器芯片或BAW滤波器芯片。本实施例中，所述粘结层101 为图案化的干膜层(Dry film)。所述干膜层的材料例如是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，通常为一种光敏性聚合物材料。所述塑封层102由环氧树脂制成，所述互连结构104的材料例如为金、银、铜、铁、铝、镍、钯或锡中的一种或其合金。
所述第一空腔110的面积与半导体芯片200的有源区域201的面积相等，且二者完全正对。但在具体实施时，所述第一空腔110的面积也可以与有源区域201的面积不相等，只要所述第一空腔110面向半导体芯片200的有源区域201，且半导体芯片200的有源区域201的投影至少部分落入在所述第一空腔110内即可。
所述粘结层101还具有第二粘结层开口120′，所述半导体芯片与所述载体100在所述第二粘结层开口120′处形成第二空腔120，所述第二空腔120至少对准所述输入/输出电极区域202的一部分。所述第二空腔120与所述通孔103相连通，所述互连结构104贯穿所述通孔103和所述第二空腔120，并与所述输入/输出电极连接。在本发明其他实施例中，所述粘结层101中不具有第二粘结层开口120′，后续通过刻蚀所述载体100和所述粘结层101形成所述通孔103，进而暴露出所述输入/输出电极区域202的输入/输出电极，然后在所述通孔103内形成金属插塞，在所述载体100异于形成有所述粘结层101的一面进行金属布线，构成互连结构104。
进一步的，在所述载体100背离所述粘结层101的一面设置有钝化层105，所述钝化层105覆盖所述互连结构104和所述载体100异于形成有所述粘结层101的一面，所述钝化层105上形成有凸点下金属层(UBM)106，以在所述凸点下金属层106上植球回流，形成焊球凸块107。所述焊球凸块107通过凸点下金属层(UBM)106与所述互连结构104连接，进而实现与所述半导体芯片200的输入/输出电极202的连接，实现电信号的引入和引出。
所述空气隙型半导体器件封装结构可以采用晶圆级封装制作而成，再通过切割工艺将所述空气隙型半导体器件封装结构切割成若干单个半导体器件。
综上所述，本发明提供一种空气隙型半导体器件封装结构及其制作方 法，在载体上形成具有第一粘结层开口的粘结层，将半导体芯片置于所述粘结层上，在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分，形成空气隙，为有源区域提供空腔工作环境，然后，通过塑封工艺将所述半导体芯片塑封在所述载体上，最后，在与所述半导体芯片的输入/输出电极区域对准的位置处形成贯穿所述载体的通孔，并在所述载体异于形成有所述粘结层的一面形成互连结构，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。本发明提供的空气隙型半导体器件封装结构的制作方法，不需要较长的引脚和上盖密封以提供出有源区域所需空腔环境，减小了封装体积和材料成本。
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于结构实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (18)

  1. 一种空气隙型半导体器件封装结构的制作方法，其特征在于，包括：
    提供载体和半导体芯片，在所述载体上形成粘结层，所述粘结层形成有第一粘结层开口，所述半导体芯片包括有源区域和输入/输出电极区域；
    将半导体芯片置于所述粘结层上，所述半导体芯片与所述载体在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分；
    在所述载体形成有所述粘结层的一面进行塑封工艺，以将所述半导体芯片塑封在所述载体上；
    形成贯穿所述载体的通孔，所述通孔至少对准所述输入/输出电极区域的一部分；以及
    在所述载体异于形成有所述粘结层的一面形成互连结构，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。
  2. 根据权利要求1所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述粘结层还形成有第二粘结层开口，将所述半导体芯片置于所述粘结层上后，所述半导体芯片与所述载体在所述第二粘结层开口处形成第二空腔，所述第二空腔至少对准所述输入/输出电极区域的一部分。
  3. 根据权利要求2所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述粘结层为图案化的干膜层。
  4. 根据权利要求3所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述粘结层的形成方法包括：
    在所述载体上形成干膜层并进行烘烤；
    对所述干膜层进行曝光、显影，以在所述载体上形成开口；
    对显影后的所述干膜层进行坚膜处理。
  5. 根据权利要求4所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述开口包括第一粘结层开口和第二粘结层开口。
  6. 根据权利要求4所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述开口还暴露所述半导体芯片的边缘区域。
  7. 根据权利要求1所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述载体为晶圆。
  8. 根据权利要求1所述的空气隙型半导体器件封装结构的制作方法，其特征在于，在进行塑封工艺之后，形成通孔之前，还包括：
    对所述载体异于形成有所述粘结层的一面进行减薄工艺。
  9. 根据权利要求1所述的空气隙型半导体器件封装结构的制作方法，其特征在于，形成互连结构后还包括：
    在所述载体异于形成有所述粘结层的表面形成钝化层，所述钝化层覆盖所述互连结构；
    在所述钝化层中形成钝化层开口；
    在所述钝化层开口处形成电性连接所述互连结构的凸点下金属层；以及
    在所述凸点下金属层上形成焊球凸块。
  10. 根据权利要求1至3中任一项所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述互连结构的材质包括金、银、铜、铁、铝、镍、钯或锡。
  11. 根据权利要求1至3中任一项所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述半导体芯片包括滤波器芯片、MEMS芯片、图像传感器芯片或生物传感器芯片。
  12. 根据权利要求1至3中任一项所述的空气隙型半导体器件封装结构的制作方法，其特征在于，所述塑封工艺为热压注塑成型工艺，所述塑封工艺采用的塑封材料包括环氧树脂。
  13. 一种空气隙型半导体器件的封装结构，其特征在于，包括：
    载体；
    半导体芯片，所述半导体芯片包括有源区域和输入/输出电极区域；
    粘结层，所述粘结层被布置于所述载体和所述半导体芯片之间，所述粘结层具有第一粘结层开口，所述半导体芯片和所述载体在所述第一粘结层开口处形成第一空腔，所述第一空腔至少对准所述半导体芯片的有源区域的一部分；
    塑封层，所述塑封层和所述粘结层位于所述载体的同一侧，且所述塑封层包裹所述半导体芯及所述粘结层暴露的区域。
    至少一个通孔，所述通孔贯穿所述载体并至少暴露出部分所述输入/输出电极区域；以及，
    互连结构，形成在所述载体异于形成有所述粘结层的一面，所述互连结构贯穿所述通孔并电性连接所述输入/输出电极区域的输入/输出电极。
  14. 根据权利要求13所述的空气隙型半导体器件封装结构，其特征在于，所述粘结层还具有第二粘结层开口，所述半导体芯片与所述载体在所述第二粘结层开口处形成第二空腔，所述第二空腔至少对准所述输入/输出电极区域的一部分。
  15. 根据权利要求13所述的空气隙型半导体器件封装结构，其特征在于，所述粘结层还暴露所述半导体芯片的边缘区域。
  16. 根据权利要求13所述的空气隙型半导体器件封装结构，其特征在于，所述载体为晶圆。
  17. 根据权利要求13所述的空气隙型半导体器件封装结构，其特征在于，所述半导体芯片包括滤波器芯片、MEMS芯片、图像传感器芯片或生物传感器芯片。
  18. 一种空气隙型半导体器件，其特征在于，包括权利要求13至17中任一项所述的空气隙型半导体器件封装结构。
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