WO2020220532A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

Info

Publication number
WO2020220532A1
WO2020220532A1 PCT/CN2019/102496 CN2019102496W WO2020220532A1 WO 2020220532 A1 WO2020220532 A1 WO 2020220532A1 CN 2019102496 W CN2019102496 W CN 2019102496W WO 2020220532 A1 WO2020220532 A1 WO 2020220532A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
layer
array substrate
depolarization
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/102496
Other languages
English (en)
French (fr)
Inventor
马远洋
曾燚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2020220532A1 publication Critical patent/WO2020220532A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof.
  • LCD Liquid Crystal Display
  • CRT cathode ray tube
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to pour liquid crystal molecules between the Thin Film Transistor Array Substrate (TFT Array Substrate) and the Color Filter (CF) substrate, and apply driving on the two substrates
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the storage capacitor is usually formed by a common electrode line located on the first metal layer in cooperation with the pixel electrode.
  • the common electrode line often forms a cross structure or crossing point in the light-transmitting area.
  • the polarization direction of the partially polarized light will be deflected to a certain extent, resulting in partial light leakage after the polarized light passes through the vertical direction polarizer filter.
  • non-horizontal or vertical metal corners or metal edges will affect the polarization of horizontally polarized light. A phenomenon similar to diffraction occurs.
  • the polarization direction is partially changed, resulting in light leakage under dark screens.
  • the prior art proposes a solution to cancel the cross structure or cross point, such as directly canceling the metal vertical line, moving the metal horizontal line to below the black gate area outside the sub-pixel display area, and designing the pixel electrode to be horizontal Change the pixel structure in the vertical direction to effectively reduce light leakage and improve contrast; but for some large-scale, high-resolution high-end displays, removing the above-mentioned cross structure or intersection can improve the light leakage phenomenon,
  • the shortage will cause more serious problems such as insufficient charging efficiency of the liquid crystal display panel and insufficient storage capacitance, so this solution cannot be applied to high-end displays.
  • the object of the present invention is to provide an array substrate, which can reduce the light leakage caused by the depolarization of the metal line and improve the display quality without affecting the charging efficiency and the size of the storage capacitor.
  • the object of the present invention is also to provide a manufacturing method of an array substrate, which can reduce light leakage caused by depolarization of metal lines and improve display quality without affecting the charging efficiency and the size of the storage capacitor.
  • the present invention provides an array substrate, which includes a base substrate and a plurality of criss-crossed metal wires arranged on the base substrate, and the sidewalls of the metal wires are covered with an anti-depolarization layer.
  • the material of the metal wire is copper, and the material of the anti-depolarization layer is nickel.
  • the upper surface of the metal wire is also covered with an anti-depolarization layer.
  • the metal wire is a common electrode wire.
  • the present invention also provides a manufacturing method of the array substrate, including the following steps:
  • Step S1 Provide a base substrate, and form a metal film on the base substrate;
  • Step S2 Pattern the metal thin film through a patterning process to form a plurality of crisscross metal lines, and form an anti-depolarization layer covering the sidewalls of the metal lines through an electroplating process.
  • the material of the metal wire is copper, and the material of the anti-depolarization layer is nickel.
  • the step S2 specifically includes:
  • the photoresist layer as a shield to etch the metal film to form a plurality of criss-cross metal lines
  • the step S2 specifically includes:
  • the photoresist layer as a shield to etch the metal film to form a plurality of criss-cross metal lines
  • an anti-depolarization layer is formed on the sidewall and the upper surface of the metal line.
  • the metal wire is a common electrode wire.
  • the current density of the electroplating process in the step S2 is 1 to 3 A/dm 2 , the temperature is 40 to 60° C., and the duration is 20 to 30 min.
  • the present invention provides an array substrate, including a base substrate and a plurality of criss-cross metal wires arranged on the base substrate, the sidewalls of the metal wires are covered with an anti-depolarization layer,
  • the anti-depolarization layer can effectively reduce the depolarization phenomenon of the metal line crossing or bending position, reduce the light leakage of the liquid crystal display panel, improve the contrast of the liquid crystal display panel, and does not affect the charging efficiency of the liquid crystal display panel and the size of the storage capacitor.
  • the present invention also provides a manufacturing method of the array substrate, which can reduce the light leakage caused by the depolarization of the metal line and improve the display quality without affecting the charging efficiency and the size of the storage capacitor.
  • Figure 1 is a top view of the array substrate of the present invention
  • step S1 is a schematic diagram of step S1 of the manufacturing method of the array substrate of the present invention.
  • step S2 of the second embodiment of the manufacturing method of the array substrate of the present invention are schematic diagrams of step S2 of the second embodiment of the manufacturing method of the array substrate of the present invention.
  • the present invention provides an array substrate, including a base substrate 1 and a plurality of criss-cross metal lines 2 arranged on the base substrate 1, the sidewalls of the metal lines 2 are covered with anti-corrosion Partial layer 3.
  • the material of the metal wire 2 is copper, and the material of the anti-depolarization layer 3 is nickel.
  • the multiple criss-crossing metal wires 2 on the base substrate 1 have multiple intersections A.
  • the multiple metal wires 2 intersect perpendicularly at the intersection A, but in actual production, multiple In the case of the metal line 2, the multiple metal lines 2 do not completely intersect vertically at the intersection point A.
  • the edges of the multiple metal lines 2 at the intersection point A actually form an arc.
  • the arc structure will affect the polarization direction of the incident polarized light of the liquid crystal display panel, resulting in light leakage of the liquid crystal display panel.
  • the present invention covers the side wall of the metal wire 2 with an anti-depolarization layer 3.
  • the anti-depolarization layer 3 is made of a large extinction coefficient, for example, made of metal nickel (Ni).
  • the extinction coefficient is a characterization of the material's ability to absorb light. The larger the extinction coefficient, the less light transmission. Therefore, the metal wire 2
  • the sidewalls of the metal wire are covered with an anti-depolarization layer 3 with a high extinction coefficient, which can effectively block the polarized light incident under the metal wire 2 and reduce the contact of the polarized light with the metal wire 2, thereby avoiding polarized light and the sidewall of the metal wire 2
  • Optical coupling causes polarization to disappear, thereby greatly reducing light leakage due to depolarization.
  • the anti-depolarization layer 3 may further cover the upper surface of the metal wire 2. Since the metal nickel used in the anti-depolarization layer 3 also has conductivity, Therefore, the electrical connection of the metal wire 2 will not be affected.
  • the metal line 2 is a common electrode line (A-com) on the array substrate, which is provided on the first metal layer and is connected to the metal line 2 Also provided on the first metal layer, it also includes a plurality of gate lines 91 extending in the horizontal direction and spaced apart from the metal line 2 and a gate 94 electrically connected to the gate line 91.
  • A-com common electrode line
  • the base substrate 1 is covered with a gate insulating layer, a semiconductor layer 97 is provided on the gate insulating layer on the gate 94, and a second metal layer is provided on the gate insulating layer and the semiconductor layer 97.
  • the second metal layer includes a plurality of data lines 92 extending in the vertical direction, a source electrode 93 electrically connected to the data line 92 and in contact with the semiconductor layer 97, and spaced apart from the source electrode 93 and connected to the semiconductor layer. 97.
  • the drain 95 contacted by 97 is covered with a passivation layer on the second metal layer and the gate insulating layer.
  • a pixel electrode 96 is provided on the passivation layer. The pixel electrode 96 passes through the passivation layer.
  • the via 98 is electrically connected to the drain 95.
  • the gate 94, the semiconductor layer 97, the source 93 and the drain 95 form a switching TFT.
  • the material of the pixel electrode 96 is indium tin oxide (ITO).
  • the pixel electrode 96 is a cross-shaped electrode, including a cross-shaped main electrode and branch electrodes connected to the main shaft and extending in four different directions.
  • a metal wire 2 is provided at a position opposite to the main electrode below the main
  • the metal wire 2 opposite to the electrode and the main electrode form a storage capacitor.
  • the metal wire 2 and the pixel electrode 96 have a relatively large relative area, which can ensure sufficient storage capacitor size and ensure the charging efficiency of the liquid crystal display panel.
  • the present invention provides a manufacturing method of an array substrate, including the following steps:
  • Step S1 as shown in FIG. 4, a base substrate 1 is provided, and a metal thin film 20 is formed on the base substrate 1.
  • the material of the metal thin film 20 is copper.
  • Step S2 The metal thin film 20 is patterned through a patterning process to form a plurality of criss-crossed metal lines 2, and an anti-depolarization layer 3 covering the sidewalls of the metal lines 2 is formed through an electroplating process.
  • the material of the anti-depolarization layer 3 is nickel.
  • the step S2 specifically includes:
  • a photoresist film is covered on the metal film 20, and the photoresist film is exposed and developed to form a photoresist layer 21;
  • the metal thin film 20 is etched to form a plurality of crisscross metal lines 2;
  • an anti-depolarization layer 3 is formed on the sidewall of the metal line 2 through an electroplating process; finally, the photoresist layer 21 is removed.
  • the specific operation of the electroplating process is: connecting the circuit, turning on the DC power supply, connecting the anode and cathode electrodes, and immersing them in the nickel plating electrolyte to electroplate nickel;
  • the anode material is pure nickel, and the cathode is copper wire.
  • Nickel plating electrolyte is NiSO 4, NiCl 2 and a mixed aqueous solution of HBO 3, and NiSO 4, NiCl 2 and HBO 3 mass ratio is (6-8) :( 1-2): 1; concentration of nickel sulfate 200 ⁇ 300g/L (the mass of nickel sulfate to the volume ratio of the nickel plating electrolyte), the current density during nickel plating is 1-3A/dm2, the temperature is 40-60°C, and the time is 20-30min.
  • the step S2 specifically includes:
  • a photoresist film is covered on the metal film 20, and the photoresist film is exposed and developed to form a photoresist layer 21;
  • the metal thin film 20 is etched to form a plurality of crisscross metal lines 2; then, the photoresist layer 21 is removed;
  • an anti-depolarization layer 3 is formed on the sidewall and upper surface of the metal wire 2 through an electroplating process.
  • the specific operation of the electroplating process is: connecting the circuit, turning on the DC power supply, connecting the anode and cathode electrodes, and immersing them in the nickel plating electrolyte to electroplate nickel;
  • the anode material is pure nickel, and the cathode is copper wire.
  • Nickel plating electrolyte is NiSO 4, NiCl 2 and a mixed aqueous solution of HBO 3, and NiSO 4, NiCl 2 and HBO 3 mass ratio is (6-8) :( 1-2): 1; concentration of nickel sulfate 200 ⁇ 300g/L (the mass of nickel sulfate to the volume ratio of the nickel plating electrolyte), the current density during nickel plating is 1-3A/dm2, the temperature is 40-60°C, and the time is 20-30min. .
  • the difference between the first embodiment and the second embodiment is whether the photoresist layer 21 is removed before electroplating.
  • the first embodiment does not remove the photoresist layer 21, and the anti-depolarization layer 3 is only formed on the side of the metal line 2.
  • electroplating is performed, and the anti-depolarization layer 3 is formed on the sidewall and upper surface of the metal line 2.
  • the multiple criss-crossing metal wires 2 on the base substrate 1 have multiple intersections A.
  • the multiple metal wires 2 intersect perpendicularly at the intersection A, but in actual production, multiple In the case of the metal line 2, the multiple metal lines 2 do not completely intersect vertically at the intersection point A.
  • the edges of the multiple metal lines 2 at the intersection point A actually form an arc.
  • the arc structure will affect the polarization direction of the incident polarized light of the liquid crystal display panel, resulting in light leakage of the liquid crystal display panel.
  • the present invention covers the side wall of the metal wire 2 with an anti-depolarization layer 3.
  • the anti-depolarization layer 3 is made of a large extinction coefficient, for example, made of metal nickel (Ni).
  • the extinction coefficient is a characterization of the material's ability to absorb light. The larger the extinction coefficient, the less light transmission. Therefore, the metal wire 2
  • the sidewalls of the metal wire are covered with an anti-depolarization layer 3 with a high extinction coefficient, which can effectively block the polarized light incident under the metal wire 2 and reduce the contact of the polarized light with the metal wire 2, thereby avoiding polarized light and the sidewall of the metal wire 2
  • Optical coupling causes polarization to disappear, thereby greatly reducing light leakage due to depolarization.
  • the anti-depolarization layer 3 may further cover the upper surface of the metal wire 2. Since the metal nickel used in the anti-depolarization layer 3 also has conductivity, Therefore, the electrical connection of the metal wire 2 will not be affected.
  • the metal line 2 is a common electrode line (A-com) on the array substrate, which is provided on the first metal layer, and is the same as the metal line 2.
  • the first metal layer also includes a plurality of gate lines 91 extending in the horizontal direction and spaced apart from the metal lines 2 and a gate 94 electrically connected to the gate lines 91.
  • the first metal layer and the substrate 1 is covered with a gate insulating layer, a semiconductor layer 97 is provided on the gate insulating layer on the gate 94, a second metal layer is provided on the gate insulating layer and the semiconductor layer 97, the first The second metal layer includes a plurality of data lines 92 extending in the vertical direction, a source electrode 93 electrically connected to the data line 92 and in contact with the semiconductor layer 97, spaced apart from the source electrode 93 and connected to the semiconductor layer 97
  • the contact drain 95 is covered with a passivation layer on the second metal layer and the gate insulating layer, and a pixel electrode 96 is provided on the passivation layer.
  • the pixel electrode 96 passes through a passivation layer.
  • the via 98 is electrically connected to the drain 95.
  • the gate 94, the semiconductor layer 97, the source 93 and the drain 95 form a switching TFT.
  • the material of the pixel electrode 96 is indium tin oxide (ITO).
  • the pixel electrode 96 is a cross-shaped electrode, including a cross-shaped main electrode and branch electrodes connected to the main shaft and extending in four different directions.
  • a metal wire 2 is provided at a position opposite to the main electrode below the main
  • the metal wire 2 opposite to the electrode and the main electrode form a storage capacitor.
  • the metal wire 2 and the pixel electrode 96 have a relatively large relative area, which can ensure sufficient storage capacitor size and ensure the charging efficiency of the liquid crystal display panel.
  • the present invention provides an array substrate including a base substrate and a plurality of criss-crossed metal lines arranged on the base substrate, the sidewalls of the metal lines are covered with an anti-depolarization layer, so The anti-depolarization layer can effectively reduce the depolarization phenomenon of the metal wire crossing or bending position, reduce the light leakage of the liquid crystal display panel, improve the contrast of the liquid crystal display panel, and does not affect the charging efficiency of the liquid crystal display panel and the size of the storage capacitor.
  • the present invention also provides a manufacturing method of the array substrate, which can reduce the light leakage caused by the depolarization of the metal line and improve the display quality without affecting the charging efficiency and the size of the storage capacitor.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法。阵列基板包括衬底基板(1)及设于衬底基板(1)上的多条纵横交错的金属线(2)，金属线(2)的侧壁覆盖有防消偏层(3)，防消偏层(3)能够有效减少金属线(2)交叉或弯曲位置的消偏现象，降低液晶显示面板的漏光，改善液晶显示面板的对比度，且不影响液晶显示面板的充电效率及存储电容大小。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
 背景技术
随着显示技术的发展，液晶显示器（Liquid Crystal Display，LCD）因具有高画质、省电、机身薄及应用范围广等优点，已经逐步取代阴极射线管（Cathode Ray Tube，CRT）显示屏，被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组（Backlight Module）。液晶显示面板的工作原理是在薄膜晶体管阵列基板（Thin Film Transistor Array Substrate，TFT Array Substrate）与彩色滤光片（Color Filter，CF）基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
现有的液晶显示面板中，存储电容通常由位于第一金属层的公共电极线与像素电极配合形成，为了提高存储电容，在公共电极线往往会在透光区形成十字结构或交叉点。当偏振光在经过该十字结构或交叉点后，部分偏振光的偏振方向会发生一定的偏转，从而导致偏振光在经过垂直方向偏振片滤光后产生部分漏光。对于入射的水平偏振光，非水平或垂直方向的金属拐角或金属边缘会对水平偏振光的偏振产生影响，发生一种类似衍射的现象，同时偏振方向发生部分改变，导致暗画面下发生漏光。
为了避免漏光，现有技术中提出取消十字结构或交叉点的方案，例如将金属竖线直接取消，将金属横向走线移动到子像素显示区域外的黑栅区下方以及将像素电极设计为水平和垂直方向等改变像素结构的方式来有效降低漏光，提高对比度；但是对于一些大尺寸、高分辨率的高阶显示器来，通过移除上述十字结构或交叉点的操作虽然能改善其漏光现象，但缺会引起液晶显示面板充电效率不足和储存电容不足等更严重的问题，因此该方案在高阶显示器无法适用。
 技术问题
本发明的目的在于提供一种阵列基板，能够在不影响充电效率及存储电容大小的前提下，减少因金属线消偏而导致的漏光现象，提升显示品质。
本发明的目的还在于提供一种阵列基板的制作方法，能够在不影响充电效率及存储电容大小的前提下，减少因金属线消偏而导致的漏光，提升显示品质。
 技术解决方案
为实现上述目的，本发明提供了一种阵列基板，包括衬底基板及设于所述衬底基板上的多条纵横交错的金属线，所述金属线的侧壁覆盖有防消偏层。
所述金属线的材料为铜，所述防消偏层的材料为镍。
所述金属线的上表面也覆盖有防消偏层。
所述金属线为公共电极线。
本发明还提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成金属薄膜；
步骤S2、通过一道图案化工艺对所述金属薄膜进行图案化，形成多条纵横交错的金属线，并通过电镀工艺形成覆盖在所述金属线的侧壁的防消偏层。
所述金属线的材料为铜，所述防消偏层的材料为镍。
所述步骤S2具体包括：
在所述金属薄膜上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层；
以所述光阻层为遮挡，对所述金属薄膜进行蚀刻，形成多条纵横交错的金属线；
通过电镀工艺，在所述金属线的侧壁形成防消偏层；
去除所述光阻层。
所述步骤S2具体包括：
在所述金属薄膜上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层；
以所述光阻层为遮挡，对所述金属薄膜进行蚀刻，形成多条纵横交错的金属线；
去除所述光阻层；
通过电镀工艺，在所述金属线的侧壁及上表面均形成防消偏层。
所述金属线为公共电极线。
所述步骤S2中的电镀工艺的电流密度为1～3A/dm 2，温度为40～60℃，时长为20～30min。
有益效果
本发明的有益效果：本发明提供一种阵列基板，包括衬底基板及设于所述衬底基板上的多条纵横交错的金属线，所述金属线的侧壁覆盖有防消偏层，所述防消偏层能够有效减少金属线交叉或弯曲位置的消偏现象，降低液晶显示面板的漏光，改善液晶显示面板的对比度，且不影响液晶显示面板的充电效率及存储电容大小。本发明还提供一种阵列基板的制作方法，能够在不影响充电效率及存储电容大小的前提下，减少因金属线消偏而导致的漏光，提升显示品质。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的阵列基板的俯视图；
图2为本发明的阵列基板的金属线的放大图；
图3为本发明的阵列基板的制作方法的流程图；
图4为本发明的阵列基板的制作方法的步骤S1的示意图；
图5至图7为本发明的阵列基板的制作方法的第一实施例的步骤S2的示意图；
图8至图10为本发明的阵列基板的制作方法的第二实施例的步骤S2的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种阵列基板，包括衬底基板1及设于所述衬底基板1上的多条纵横交错的金属线2，所述金属线2的侧壁覆盖有防消偏层3。
具体地，所述金属线2的材料为铜，所述防消偏层3的材料为镍。
需要说明的是，衬底基板1上的多条纵横交错的金属线2具有多个交点A，设计时，多条金属线2在交点A均是垂直相交的，但实际生产中制作出多条金属线2时，多条金属线2在交点A并非完全的垂直相交，如图2所述，由于曝光工艺制程的原因，多条金属线2在交点A的位置的边缘实际会形成一个弧形结构，该弧形结构会对液晶显示面板的入射偏振光的偏振方向产生影响，导致液晶显示面板发生漏光，为了解决上述问题，本发明在金属线2的侧壁覆盖防消偏层3，所述防消偏层3采用具有较大的消光系数，例如采用金属镍（Ni）制作，消光系数是材料对光吸收能力的表征，消光系数越大，光透过越少，因此在金属线2的侧壁覆盖具有高消光系数的防消偏层3，能够有效遮挡金属线2下方射入的偏振光，减少偏振光同金属线2的接触，进而避免偏振光与金属线2的侧壁产生光耦合导致偏振消失，从而大幅减少因消偏而导致的漏光。进一步地，根据需要，在本发明的一些实施例中，所述防消偏层3可以进一步覆盖所述金属线2的上表面，由于防消偏层3采用的金属镍的也具有导电能力，因此不会影响金属线2的电性连接。
具体地，如图1所示，对应到具体的阵列基板结构中，所述金属线2为阵列基板上的公共电极线（A-com），其设于第一金属层，与该金属线2同样设于第一金属层的还包括多条沿水平方向延伸且与金属线2间隔的栅极线91及与所述栅极线91电性连接的栅极94，在第一金属层及衬底基板1上覆盖一层栅极绝缘层，在栅极94上的栅极绝缘层上设有半导体层97，在所述栅极绝缘层及半导体层97上设有第二金属层，所述第二金属层包括多条沿竖直方向延伸的数据线92、与所述数据线92电性连接且与所述半导体层97接触的源极93、与源极93间隔且与所述半导体层97接触的漏极95，在所述第二金属层及栅极绝缘层上覆盖有钝化层，在钝化层上设有像素电极96，所述像素电极96通过一穿越所述钝化层的过孔98与所述漏极95电性连接。
具体地，所述栅极94、半导体层97、源极93及漏极95形成一开关TFT。
具体地，所述像素电极96的材料为氧化铟锡（ITO）。所述像素电极96为米字形电极，包括十字形的主干电极及与所述主干相连且向四个不同方向延伸的分支电极，在所述主干电极下方相对的位置设有金属线2，与主干电极相对的金属线2与所述主干电极组成一存储电容，所述金属线2与所述像素电极96具有较大的相对面积，可以保证存储电容的大小充足，保证液晶显示面板的充电效率。
请参阅图3，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、如图4所示，提供一衬底基板1，在所述衬底基板1上形成金属薄膜20。
具体地，所述金属薄膜20的材料为铜。
步骤S2、通过一道图案化工艺对所述金属薄膜20进行图案化，形成多条纵横交错的金属线2，并通过电镀工艺形成覆盖在所述金属线2的侧壁的防消偏层3。
具体地，所述防消偏层3的材料为镍。
具体地，如图5至图7所示，在本发明的阵列基板的制作方法的第一实施例中，所述步骤S2具体包括：
如图5所示，首先，在所述金属薄膜20上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层21；
如图6所示，接着，以所述光阻层21为遮挡，对所述金属薄膜20进行蚀刻，形成多条纵横交错的金属线2；
如图7所示，然后通过电镀工艺，在所述金属线2的侧壁形成防消偏层3；最后去除所述光阻层21。
其中，以所述防消偏层3的材料为镍为例，所述电镀工艺的具体操作为：连接电路，打开直流电源，将阴阳电极连接好后浸入镀镍电解液中电镀镍；其中阳极材料为纯镍，阴极为铜导线。镀镍电解液为NiSO 4、NiCl 2和HBO 3的混合水溶液，且NiSO 4、NiCl 2 及HBO 3的质量比为(6～8 ):(1～2):1；硫酸镍的浓度为200～300g/L(硫酸镍的质量与镀镍电解液的体积比)，镀镍时的电流密度为1～3A/dm2，温度为40～60℃，时间为20～30min。
具体地，如图8至图10所示，在本发明的阵列基板的制作方法的第二实施例中，所述步骤S2具体包括：
如图8所示，首先，在所述金属薄膜20上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层21；
如图9所示，接着，以所述光阻层21为遮挡，对所述金属薄膜20进行蚀刻，形成多条纵横交错的金属线2；然后，去除所述光阻层21；
如图10所示，最后，通过电镀工艺，在所述金属线2的侧壁及上表面均形成防消偏层3。
其中，以所述防消偏层3的材料为镍为例，所述电镀工艺的具体操作为：连接电路，打开直流电源，将阴阳电极连接好后浸入镀镍电解液中电镀镍；其中阳极材料为纯镍，阴极为铜导线。镀镍电解液为NiSO 4、NiCl 2和HBO 3的混合水溶液，且NiSO 4、NiCl 2 及HBO 3的质量比为(6～8 ):(1～2):1；硫酸镍的浓度为200～300g/L(硫酸镍的质量与镀镍电解液的体积比)，镀镍时的电流密度为1～3A/dm2，温度为40～60℃，时间为20～30min。。
具体地，所述第一实施例与第二实施例的区别在于电镀之前是否去除光阻层21，第一实施例不去除光阻层21，防消偏层3仅形成在金属线2的侧壁上，而第二实施例去除光阻层21之后在进行电镀，防消偏层3形成在金属线2的侧壁及上表面上。
需要说明的是，衬底基板1上的多条纵横交错的金属线2具有多个交点A，设计时，多条金属线2在交点A均是垂直相交的，但实际生产中制作出多条金属线2时，多条金属线2在交点A并非完全的垂直相交，如图2所述，由于曝光工艺制程的原因，多条金属线2在交点A的位置的边缘实际会形成一个弧形结构，该弧形结构会对液晶显示面板的入射偏振光的偏振方向产生影响，导致液晶显示面板发生漏光，为了解决上述问题，本发明在金属线2的侧壁覆盖防消偏层3，所述防消偏层3采用具有较大的消光系数，例如采用金属镍（Ni）制作，消光系数是材料对光吸收能力的表征，消光系数越大，光透过越少，因此在金属线2的侧壁覆盖具有高消光系数的防消偏层3，能够有效遮挡金属线2下方射入的偏振光，减少偏振光同金属线2的接触，进而避免偏振光与金属线2的侧壁产生光耦合导致偏振消失，从而大幅减少因消偏而导致的漏光。
进一步地，根据需要，在本发明的一些实施例中，所述防消偏层3可以进一步覆盖所述金属线2的上表面，由于防消偏层3采用的金属镍的也具有导电能力，因此不会影响金属线2的电性连接。
具体地，如图1所示，对应到具体的阵列基板中，所述金属线2为阵列基板上的公共电极线（A-com），其设于第一金属层，与该金属线2同样设于第一金属层的还包括多条沿水平方向延伸且与金属线2间隔的栅极线91及与所述栅极线91电性连接的栅极94，在第一金属层及衬底基板1上覆盖一层栅极绝缘层，在栅极94上的栅极绝缘层上设有半导体层97，在所述栅极绝缘层及半导体层97上设有第二金属层，所述第二金属层包括多条沿竖直方向延伸的数据线92、与所述数据线92电性连接且与所述半导体层97接触的源极93、与源极93间隔且与所述半导体层97接触的漏极95，在所述第二金属层及栅极绝缘层上覆盖有钝化层，在钝化层上设有像素电极96，所述像素电极96通过一穿越所述钝化层的过孔98与所述漏极95电性连接。
具体地，所述栅极94、半导体层97、源极93及漏极95形成一开关TFT。
具体地，所述像素电极96的材料为氧化铟锡（ITO）。所述像素电极96为米字形电极，包括十字形的主干电极及与所述主干相连且向四个不同方向延伸的分支电极，在所述主干电极下方相对的位置设有金属线2，与主干电极相对的金属线2与所述主干电极组成一存储电容，所述金属线2与所述像素电极96具有较大的相对面积，可以保证存储电容的大小充足，保证液晶显示面板的充电效率。
综上所述，本发明提供一种阵列基板，包括衬底基板及设于所述衬底基板上的多条纵横交错的金属线，所述金属线的侧壁覆盖有防消偏层，所述防消偏层能够有效减少金属线交叉或弯曲位置的消偏现象，降低液晶显示面板的漏光，改善液晶显示面板的对比度，且不影响液晶显示面板的充电效率及存储电容大小。本发明还提供一种阵列基板的制作方法，能够在不影响充电效率及存储电容大小的前提下，减少因金属线消偏而导致的漏光，提升显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种阵列基板，包括衬底基板及设于所述衬底基板上的多条纵横交错的金属线，所述金属线的侧壁覆盖有防消偏层。
  2. 如权利要求1所述的阵列基板，其中，所述金属线的材料为铜，所述防消偏层的材料为镍。
  3. 如权利要求1所述的阵列基板，其中，所述金属线的上表面也覆盖有防消偏层。
  4. 如权利要求1所述的阵列基板，其中，所述金属线为公共电极线。
  5. 一种阵列基板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成金属薄膜；
    步骤S2、通过一道图案化工艺对所述金属薄膜进行图案化，形成多条纵横交错的金属线，并通过电镀工艺形成覆盖在所述金属线的侧壁的防消偏层。
  6. 如权利要求5所述的阵列基板的制作方法，其中，所述金属线的材料为铜，所述防消偏层的材料为镍。
  7. 如权利要求5所述的阵列基板的制作方法，其中，所述步骤S2具体包括：
    在所述金属薄膜上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层；
    以所述光阻层为遮挡，对所述金属薄膜进行蚀刻，形成多条纵横交错的金属线；
    通过电镀工艺，在所述金属线的侧壁形成防消偏层；
    去除所述光阻层。
  8. 如权利要求5所述的阵列基板的制作方法，其中，所述步骤S2具体包括：
    在所述金属薄膜上覆盖光阻薄膜，并对所述光阻薄膜进行曝光和显影，形成光阻层；
    以所述光阻层为遮挡，对所述金属薄膜进行蚀刻，形成多条纵横交错的金属线；
    去除所述光阻层；
    通过电镀工艺，在所述金属线的侧壁及上表面均形成防消偏层。
  9. 如权利要求5所述的阵列基板的制作方法，其中，所述金属线为公共电极线。
  10. 如权利要求5所述的的阵列基板的制作方法，其中，所述步骤S2中的电镀工艺的电流密度为1～3A/dm 2，温度为40～60℃，时长为20～30min。
PCT/CN2019/102496 2019-04-30 2019-08-26 阵列基板及其制作方法 Ceased WO2020220532A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910364397.5A CN109976060A (zh) 2019-04-30 2019-04-30 阵列基板及其制作方法
CN201910364397.5 2019-04-30

Publications (1)

Publication Number Publication Date
WO2020220532A1 true WO2020220532A1 (zh) 2020-11-05

Family

ID=67087538

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/102496 Ceased WO2020220532A1 (zh) 2019-04-30 2019-08-26 阵列基板及其制作方法

Country Status (2)

Country Link
CN (1) CN109976060A (zh)
WO (1) WO2020220532A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109976060A (zh) * 2019-04-30 2019-07-05 深圳市华星光电技术有限公司 阵列基板及其制作方法
CN110488546A (zh) * 2019-08-21 2019-11-22 深圳市华星光电半导体显示技术有限公司 阵列基板、液晶显示面板及液晶显示器
CN110989218A (zh) * 2019-11-20 2020-04-10 Tcl华星光电技术有限公司 检测金属信号线漏光的装置及方法
CN111025750A (zh) * 2019-12-09 2020-04-17 Tcl华星光电技术有限公司 显示面板以及显示装置
CN112327536B (zh) * 2020-11-03 2023-10-17 Tcl华星光电技术有限公司 显示面板、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000187208A (ja) * 1998-12-22 2000-07-04 Matsushita Electric Ind Co Ltd 反射型液晶表示装置とその製造方法
JP2014089281A (ja) * 2012-10-30 2014-05-15 Sharp Corp 表示装置およびその製造方法、電子機器
CN108594550A (zh) * 2018-04-25 2018-09-28 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN109976060A (zh) * 2019-04-30 2019-07-05 深圳市华星光电技术有限公司 阵列基板及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW589472B (en) * 1995-10-12 2004-06-01 Hitachi Ltd In-plane field type liquid crystal display device comprising a structure preventing electricity
CN101303500B (zh) * 2008-07-08 2010-04-14 友达光电股份有限公司 液晶显示面板及液晶显示面板的制作方法
CN102253533B (zh) * 2011-08-08 2013-04-10 南京中电熊猫液晶显示科技有限公司 多域紫外光配向模式的液晶显示器
CN206020839U (zh) * 2016-04-11 2017-03-15 台谱企业股份有限公司 消光镜片及眼镜
CN107561807B (zh) * 2017-10-16 2020-07-28 深圳市华星光电技术有限公司 阵列基板和液晶显示装置
CN108598132A (zh) * 2018-05-23 2018-09-28 京东方科技集团股份有限公司 显示基板的制作方法、掩膜板的制作方法、显示装置
CN109143774A (zh) * 2018-07-18 2019-01-04 深圳市华星光电半导体显示技术有限公司 掩膜板及金属线的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000187208A (ja) * 1998-12-22 2000-07-04 Matsushita Electric Ind Co Ltd 反射型液晶表示装置とその製造方法
JP2014089281A (ja) * 2012-10-30 2014-05-15 Sharp Corp 表示装置およびその製造方法、電子機器
CN108594550A (zh) * 2018-04-25 2018-09-28 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN109976060A (zh) * 2019-04-30 2019-07-05 深圳市华星光电技术有限公司 阵列基板及其制作方法

Also Published As

Publication number Publication date
CN109976060A (zh) 2019-07-05

Similar Documents

Publication Publication Date Title
WO2020220532A1 (zh) 阵列基板及其制作方法
US7061565B2 (en) Array substrate having double-layered metal patterns and method of fabricating the same
KR100934590B1 (ko) 하프톤 노광법을 사용한 액정표시장치의 제조법
CN202404339U (zh) 阵列基板及包括该阵列基板的显示装置
CN104216183B (zh) 一种阵列基板及其制备方法、显示装置
CN108594550B (zh) 阵列基板及其制作方法
CN103345092B (zh) 阵列基板及其制作方法、显示装置
US8514340B2 (en) Method of fabricating array substrate having double-layered patterns
CN103309105B (zh) 阵列基板及其制备方法、显示装置
CN105448824B (zh) 阵列基板及其制作方法、显示装置
CN103885221B (zh) 大板加电线路及其制造方法
CN106353944A (zh) 阵列基板及其制造方法、显示面板、显示装置
JP2007279683A (ja) 液晶ディスプレイの製造方法
CN104779203B (zh) 一种阵列基板及其制造方法、显示装置
WO2020124896A1 (zh) 液晶显示面板
WO2020093442A1 (zh) 阵列基板的制作方法及阵列基板
US6330042B1 (en) Liquid crystal display and the method of manufacturing the same
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
US10644036B2 (en) VA type TFT array substrate and the manufacturing method thereof
CN107170751A (zh) 阵列基板及其制造方法、显示装置
CN101236953B (zh) 薄膜晶体管阵列基板制造方法
CN222214179U (zh) 一种提高开口率的低寄生电容tft阵列基板
WO2020220529A1 (zh) Tft 阵列基板及其制作方法
US20190157301A1 (en) Ffs type tft array substrate and the manufacturing method thereof
CN203616561U (zh) 一种阵列基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19927322

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19927322

Country of ref document: EP

Kind code of ref document: A1