WO2020215502A1 - 微发光二极管显示面板及制备方法、显示装置 - Google Patents

微发光二极管显示面板及制备方法、显示装置 Download PDF

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Publication number
WO2020215502A1
WO2020215502A1 PCT/CN2019/096460 CN2019096460W WO2020215502A1 WO 2020215502 A1 WO2020215502 A1 WO 2020215502A1 CN 2019096460 W CN2019096460 W CN 2019096460W WO 2020215502 A1 WO2020215502 A1 WO 2020215502A1
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Prior art keywords
emitting diode
passivation layer
layer
pixel electrode
micro
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PCT/CN2019/096460
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English (en)
French (fr)
Inventor
张玮
卢马才
柳铭岗
徐君哲
李佳育
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/615,276 priority Critical patent/US11355478B2/en
Publication of WO2020215502A1 publication Critical patent/WO2020215502A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • This application relates to the field of display technology, and in particular to a micro-light emitting diode display panel, a manufacturing method, and a display device.
  • Micro LED (Micro LED) display panel is a display device that uses high-density and small-size light-emitting diode (LED) arrays integrated on a substrate as display pixels to realize image display. Micro LED display panel Belongs to self-luminous display.
  • the thin film transistor (TFT) in the array substrate will be irradiated by the short-wavelength light emitted by the micro light emitting diode and the threshold value (Vth) will shift, which will cause the light leakage current to increase. Affect the display effect.
  • the existing micro-light-emitting diode display panel has a technical problem that the light-emitting of the micro-light-emitting diode causes the threshold value of the thin film transistor to shift, which needs to be improved.
  • the present application provides a micro-light-emitting diode display panel, a manufacturing method, and a display device, so as to alleviate the technical problem of the thin-film transistor threshold shift caused by the light-emitting of the micro-light-emitting diode in the existing micro-light-emitting diode display panel.
  • the embodiment of the present application provides a method for manufacturing a micro light emitting diode display panel, which includes:
  • first passivation layer Forming a first passivation layer on the substrate, the first passivation layer covering the source and drain electrodes; a first through hole is provided on the first passivation layer;
  • a micro light emitting diode is arranged on the substrate, and the micro light emitting diode is connected to the pixel electrode.
  • the method for manufacturing the micro-light-emitting diode display panel before the step of forming a light shielding layer on the substrate, the method for manufacturing the micro-light-emitting diode display panel further includes:
  • a second passivation layer is formed on the pixel electrode, and the second passivation layer is provided with a second through hole, and the micro light emitting diode is connected to the pixel electrode through the second through hole.
  • the method for manufacturing the micro-light-emitting diode display panel before the step of forming a second passivation layer on the pixel electrode, the method for manufacturing the micro-light-emitting diode display panel further includes:
  • a metal electrode is formed on the pixel electrode, and the micro light-emitting diode is connected to the pixel electrode through the second through hole and the metal electrode.
  • the method for manufacturing the micro-light-emitting diode display panel after the step of forming a light shielding layer on the substrate, the method for manufacturing the micro-light-emitting diode display panel further includes:
  • a third passivation layer is formed on the light shielding layer, and the third passivation layer covers the light shielding layer and part of the second passivation layer.
  • micro light emitting diode display panel which includes:
  • a first passivation layer covering the source electrode and the drain electrode, and a first through hole is provided on the first passivation layer;
  • a pixel electrode, the pixel electrode is connected to the drain or the source through the first through hole
  • the micro light emitting diode is connected to the pixel electrode.
  • the micro light emitting diode display panel further includes: a second passivation layer, the second passivation layer is disposed on the pixel electrode; The layer is provided with a second through hole, and the micro light emitting diode is connected to the pixel electrode through the second through hole.
  • the micro-light-emitting diode display panel further includes: a metal electrode disposed on the pixel electrode; the micro-light-emitting diode passes through the second communication The hole and the metal electrode are connected to the pixel electrode.
  • the micro light emitting diode display panel further includes: a third passivation layer, the third passivation layer is disposed on the light shielding layer; the third passivation layer A chemical layer covers the light shielding layer and a part of the second passivation layer.
  • the projection of the pixel electrode on the substrate overlaps with the projection of the source electrode or the drain electrode on the substrate; the light shielding layer Covering part of the second passivation layer.
  • the material of the light shielding layer is black photoresist.
  • An embodiment of the present application provides a display device, which includes a micro light emitting diode display panel, and the micro light emitting diode display panel includes:
  • a first passivation layer covering the source electrode and the drain electrode, and a first through hole is provided on the first passivation layer;
  • a pixel electrode, the pixel electrode is connected to the drain or the source through the first through hole
  • the micro light emitting diode is connected to the pixel electrode.
  • the micro light emitting diode display panel further includes:
  • a second passivation layer, the second passivation layer is provided on the pixel electrode; the second passivation layer is provided with a second through hole, the micro light emitting diode passes through the second through hole and the Pixel electrode connection.
  • the micro light emitting diode display panel further includes:
  • the metal electrode is arranged on the pixel electrode; the micro light-emitting diode is connected to the pixel electrode through the second through hole and the metal electrode.
  • the micro light emitting diode display panel further includes:
  • a third passivation layer, the third passivation layer is disposed on the light shielding layer; the third passivation layer covers the light shielding layer and part of the second passivation layer.
  • the projection of the pixel electrode on the substrate overlaps with the projection of the source electrode or the drain electrode on the substrate;
  • the second passivation layer
  • the light shielding layer is provided on the first passivation layer; the pixel electrode is provided on the light shielding layer, and the pixel electrode passes through the light shielding layer and the light shielding layer.
  • the through hole of the first passivation layer is connected to the drain or the drain.
  • the light-shielding layer is disposed on the first passivation layer and the second passivation layer; the micro light-emitting diode passes through the light-shielding layer and the second passivation layer.
  • the through hole of the layer is connected to the pixel electrode.
  • the micro-light-emitting diode display panel includes an active layer forming a thin film transistor, a gate insulating layer, a gate, a source and a drain, a pixel electrode, and a micro-luminescence
  • the diode and the light-shielding layer covering the active layer, the gate insulating layer, the gate, the source and the drain, based on the light-shielding layer block the light emitted by the micro-light-emitting diode from irradiating the thin-film transistor, reducing the light-emitting of the micro-light-emitting diode
  • the impact on thin film transistors reduces the threshold Vth drift caused by the micro-light-emitting diode illuminating the thin-film transistor, thereby reducing the light leakage current, and alleviating the technology of the existing micro-light-emitting diode display panel that causes the threshold
  • FIG. 1 is a schematic diagram of the first structure of the micro light emitting diode display panel of this application;
  • FIGS. 2 to 24 are schematic diagrams of the process of the method for manufacturing the micro light emitting diode display panel of this application.
  • FIG. 25 is a schematic diagram of the second structure of the micro light emitting diode display panel of this application.
  • FIG. 26 is a schematic diagram of the third structure of the micro light emitting diode display panel of this application.
  • FIG. 27 is a schematic diagram of the fourth structure of the micro light emitting diode display panel of this application.
  • FIG. 28 is a schematic diagram of the fifth structure of the micro light emitting diode display panel of this application.
  • FIG. 29 is a schematic diagram of the sixth structure of the micro light emitting diode display panel of this application.
  • the embodiment of the present application can alleviate the technical problem that the light emission of the micro light emitting diode in the existing micro light emitting diode display panel causes the threshold value of the thin film transistor to shift.
  • the micro light emitting diode display panel As shown in Fig. 1, the micro light emitting diode display panel provided by the present application includes:
  • the substrate 101 can be glass or a flexible substrate, etc.;
  • the active layer 21, the gate insulating layer 22, the gate 23, the source 24 and the drain 25 are arranged on the substrate 101; the active layer 21, the gate insulating layer 22, the gate 23, the source 24 and the drain 25 forming a thin film transistor;
  • a first passivation layer 108 covering the source electrode 24 and the drain electrode 25, and a first through hole a is provided on the first passivation layer 108;
  • the pixel electrode 31 is connected to the drain 25 or the source 24 through the first through hole; when the thin film transistor is an N-type thin film transistor, the pixel electrode 31 is connected through the first through hole For the drain 25, when the thin film transistor is a P-type thin film transistor, the pixel electrode 31 is connected to the drain 25 through the first through hole;
  • a light shielding layer 112 which covers the active layer 21, the gate insulating layer 22, the gate 23, the source 24 and the drain 25;
  • the micro light emitting diode 4 is connected to the pixel electrode.
  • the micro light emitting diode display panel includes an active layer forming a thin film transistor, a gate insulating layer, a gate, a source and a drain, a pixel electrode, a micro light emitting diode, and a cover
  • the pixel electrode 31 if the potential of the pixel electrode is positive, the pixel electrode 31 is connected to the drain 25 through the first through hole, and if the potential of the pixel electrode is negative, the pixel electrode 31 passes through the first through hole.
  • the source electrode 24 is connected to the through hole.
  • the micro light emitting diode display panel further includes: a second passivation layer 111, the second passivation layer 111 is disposed on the pixel electrode 31;
  • the second passivation layer 111 is provided with a second through hole b, and the micro light emitting diode 4 is connected to the pixel electrode 31 through the second through hole.
  • the micro light emitting diode display panel further includes: a metal electrode 32, the metal electrode 32 is disposed on the pixel electrode 31; the micro light emitting diode 4 passes through the The second through hole b and the metal electrode 32 are connected to the pixel electrode 31.
  • the micro light emitting diode display panel further includes: a third passivation layer 113, the third passivation layer 113 is disposed on the light shielding layer 112;
  • the three passivation layer 113 covers the light shielding layer 112 and part of the second passivation layer 111.
  • the projection of the pixel electrode 31 on the substrate 101 overlaps with the projection of the source electrode or the drain electrode on the substrate; the shading The layer 112 covers a part of the second passivation layer 111.
  • the micro light emitting diode 4 can be divided into a vertical structure micro light emitting diode and a horizontal structure micro light emitting diode.
  • the first electrode and the second electrode of the vertical structure micro light emitting diode are respectively located on the upper and lower sides of the micro light emitting diode.
  • the first electrode and the second electrode of the micro light emitting diode of the structure are both located on the lower side of the micro light emitting diode.
  • the micro light emitting diode 4 is a horizontal structure micro light emitting diode
  • the micro light emitting diode display panel further includes: a connecting electrode 26 for connecting a common voltage, a transparent common electrode 33, and a transparent common electrode 33
  • the connection electrode 26 is connected through the first through hole; the first electrode of the micro light emitting diode 4 is connected to the pixel electrode 31, and the second electrode is connected to the transparent common electrode 33.
  • the second passivation layer 111 is also disposed on the transparent common electrode 33; the second electrode of the micro light emitting diode 4 is connected through the second through hole Transparent common electrode 33.
  • the micro light emitting diode display panel further includes: a metal common electrode 34 disposed on the transparent common electrode 33, and the second electrode of the micro light emitting diode 4 passes through the The two vias and the metal common electrode 34 are connected to the transparent common electrode 33.
  • the micro light emitting diode 4 is a flip-chip horizontal structure micro light emitting diode to improve light extraction efficiency.
  • the micro light emitting diode 4 is a vertical structure micro light emitting diode
  • the micro light emitting diode display panel further includes: a transparent common electrode layer, and the first electrode of the micro light emitting diode 4 is connected to the pixel electrode 31 , The second electrode is connected to the transparent common electrode layer.
  • the thin film transistor includes a driving thin film transistor, a switching thin film transistor, a sensing thin film transistor, etc.;
  • the driving thin film transistor includes a metal oxide semiconductor thin film transistor, and the switching thin film transistor includes a low temperature polysilicon thin film transistor.
  • the micro-light-emitting diode display substrate includes sub-pixel units arranged in an array, and one sub-pixel unit includes one micro-light-emitting diode 4 and at least one driving thin film transistor.
  • the micro-light-emitting diode 4 is driven by the driving thin film transistor. Glow.
  • the material of the pixel electrode 31 and the transparent common electrode 33 may be indium tin oxide, indium zinc oxide, aluminum zinc oxide, or the like.
  • the material of the metal electrode 32 and the metal common electrode 34 may be a copper-molybdenum laminate, a copper-molybdenum-titanium laminate, a copper-titanium laminate, an aluminum-molybdenum laminate, a copper-niobium alloy, a nickel-chromium alloy, and the like.
  • the material of the light shielding layer 112 is black photoresist.
  • the micro light emitting diode display panel further includes: a buffer layer 102 disposed on the substrate 101, the active layer 21, the gate insulating layer 22, and the gate 23 , The source 24 and the drain 25 are arranged on the buffer layer 102.
  • the micro light emitting diode display panel further includes: an intermediate dielectric layer 106, which is arranged on the gate 23, and the source 24 and the drain 25 are arranged on the On the intermediate dielectric layer 106.
  • the micro light emitting diode display panel further includes: an encapsulation film 114, which may be an organic/inorganic alternately deposited water and oxygen barrier and mechanical impact protection film for encapsulating the micro Light-emitting diode 4.
  • an encapsulation film 114 which may be an organic/inorganic alternately deposited water and oxygen barrier and mechanical impact protection film for encapsulating the micro Light-emitting diode 4.
  • an embodiment of the present application also provides a method for preparing a micro-light-emitting diode display panel, which includes the following steps:
  • Step 1 Provide a substrate
  • Step 2 An active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode are sequentially formed on the substrate;
  • Step 3 A first passivation layer is formed on the substrate, the first passivation layer covers the source and drain electrodes; the first passivation layer is provided with a first through hole;
  • Step 4 A pixel electrode and a light shielding layer are formed on the substrate, the pixel electrode is connected to the drain or the source through the first through hole, and the light shielding layer covers the active layer and the gate insulating layer.
  • step 4 includes:
  • Step 41 forming a pixel electrode on the substrate, and the pixel electrode is connected to the drain or the source through the first through hole;
  • Step 42 Form a light-shielding layer on the substrate, the light-shielding layer covering the active layer, the gate insulating layer, the gate, the source and the drain.
  • the manufacturing method of the micro light emitting diode display panel further includes:
  • Step 43 A second passivation layer is formed on the pixel electrode, the second passivation layer is provided with a second through hole, and the micro light emitting diode is connected to the pixel electrode through the second through hole.
  • the manufacturing method of the micro light emitting diode display panel further includes:
  • Step 44 forming a metal electrode on the pixel electrode, and the micro light emitting diode is connected to the pixel electrode through the second through hole and the metal electrode.
  • the method for manufacturing the micro light emitting diode display panel further includes:
  • Step 45 forming a third passivation layer on the light shielding layer, the third passivation layer covering the light shielding layer and part of the second passivation layer.
  • the method for manufacturing a micro-light-emitting diode display panel includes the following steps:
  • a substrate 101 is provided.
  • the substrate 101 may be a glass substrate, a flexible substrate, etc., and is subjected to processing such as cleaning.
  • a buffer layer 102 is deposited on the substrate 101.
  • the material of the buffer layer 102 may be silicon oxide, silicon nitride/silicon oxide stack, aluminum oxide/silicon oxide stack, or the like.
  • a metal oxide semiconductor film layer 103 is deposited on the buffer layer 102.
  • the material of the metal oxide semiconductor film layer 103 may be indium gallium zinc oxide, indium zinc oxide, indium gallium oxide, indium gallium titanium oxide, indium gallium zinc titanium oxide, and the like.
  • the metal oxide semiconductor film layer 103 is processed to form the active layer 21.
  • the active layer 21 includes an N-doped region and a P-doped region, and a channel region located between the N-doped region and the P-doped region.
  • an insulating layer 104 and a metal layer 105 are deposited on the buffer layer 102 and the active layer 21.
  • the insulating layer 104 is patterned to form the gate insulating layer 22, and the metal layer 105 is patterned to form the gate 23.
  • an intermediate dielectric layer 106 is deposited on the buffer layer 102, the active layer 21, the gate insulating layer 22, and the gate 23.
  • the material of the intermediate dielectric layer 106 may be silicon oxide, silicon nitride/silicon oxide stack, or the like.
  • the intermediate dielectric layer 106 is patterned to form openings corresponding to the N-doped region and the P-doped region.
  • a metal layer 107 is on the intermediate dielectric layer 106.
  • the material of the metal layer 107 may be a copper-molybdenum laminate, a copper-molybdenum-titanium laminate, a copper-titanium laminate, an aluminum-molybdenum laminate, a copper-niobium alloy, and the like.
  • the metal layer 107 is patterned to form the source electrode 24, the drain electrode 25 and the connection electrode 26.
  • a first passivation layer 108 is deposited on the intermediate dielectric layer 106, the source electrode 24, the drain electrode 25 and the connection electrode 26.
  • the material of the first passivation layer 108 may be silicon oxide, silicon nitride, or a silicon nitride/silicon oxide stack.
  • the first passivation layer 108 is patterned to form a first through hole a corresponding to the drain 25 and the connection electrode 26.
  • a transparent conductive layer 109 and a metal layer 110 are deposited on the first passivation layer 108.
  • the material of the transparent conductive layer 109 may be indium tin oxide, indium zinc oxide, aluminum zinc oxide, etc.
  • the material of the metal layer 110 may be copper molybdenum laminate, copper molybdenum titanium laminate, copper titanium laminate, aluminum molybdenum laminate, copper Niobium alloy, nickel-chromium alloy, etc.
  • the transparent conductive layer 109 is patterned to form the pixel electrode 31 and the transparent common electrode 33, and the metal layer 110 is patterned to form the metal electrode 32 and the metal common electrode 34.
  • the pixel electrode 31 is connected to the drain 25 through the first through hole a, and the transparent common electrode 33 is connected to the connection electrode 26 through the first through hole a.
  • a second passivation layer 111 is deposited on the first passivation layer 108, the metal electrode 32 and the metal common electrode 34.
  • the material of the second passivation layer 111 may be silicon oxide, silicon nitride, aluminum oxide, silicon oxide/silicon oxide stack, or the like.
  • the second passivation layer 111 is patterned, leaving the area covering the metal electrode 32 and the metal common electrode 34.
  • a light shielding layer 112 is deposited on the first passivation layer 108 and the second passivation layer 111.
  • the material of the light shielding layer 112 may be black photoresist, opaque metal, or the like.
  • the light-shielding layer 112 is patterned, leaving regions covering the active layer 21, the gate insulating layer 22, the gate 23, the source 24 and the drain 25.
  • a third passivation layer 113 is deposited on the first passivation layer 108, the second passivation layer 111, and the light shielding layer 112.
  • the material of the third passivation layer 113 may be silicon oxide, silicon nitride, aluminum oxide, silicon oxide/silicon oxide stack, or the like.
  • the third passivation layer 113 is patterned, leaving the area covering the light shielding layer 112.
  • the second passivation layer 111 is patterned and dug to form a second through hole b corresponding to the metal electrode 32 and the metal common electrode 34.
  • the micro light emitting diode 4 is bound.
  • the first electrode of the micro light emitting diode 4 is connected to the metal electrode 32 through the second through hole b, and the second electrode of the micro light emitting diode 4 is connected to the metal common electrode 32 through the second through hole b.
  • a transparent packaging film 114 is deposited on the first passivation layer 108, the second passivation layer 111, and the micro light emitting diode 4.
  • the encapsulation film 114 may be an organic/inorganic alternately deposited water and oxygen barrier and mechanical collision protection film.
  • the film layers and component names corresponding to the same reference numerals are the same as those of the micro light emitting diode display panel shown in FIG. 25 to FIG. 29, the film layers and component names corresponding to the same reference numerals are the same as those of the micro light emitting diode display panel shown in FIG.
  • the light shielding layer 112 is disposed on the first passivation layer 108; the pixel electrode 31 is disposed on the light shielding layer 112, and the pixel electrode 31 passes through
  • the through hole c passing through the light shielding layer 112 and the first passivation layer 108 is connected to the drain electrode 25; or connected to the source electrode 24 (not shown in FIG. 25).
  • the manufacturing method of the micro light emitting diode display panel provided in the present application includes the following steps:
  • An active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25 are sequentially formed on the substrate 101;
  • first passivation layer 108 Forming a first passivation layer 108 on the substrate 101, the first passivation layer covering the source 24 and the drain 25;
  • a micro light emitting diode is arranged on the substrate, and the micro light emitting diode is connected to the pixel electrode.
  • the micro light emitting diode display panel further includes a third passivation layer 113, the third passivation layer 113 is disposed on the light shielding layer 112; the pixel electrode 31 is on the On the third passivation layer 113, the pixel electrode 31 is connected to the drain 25 through a through hole d that penetrates the third passivation layer 113, the light shielding layer 112 and the first passivation layer 108.
  • the manufacturing method of the micro light emitting diode display panel provided in the present application includes the following steps:
  • An active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25 are sequentially formed on the substrate 101;
  • a micro light emitting diode is arranged on the substrate, and the micro light emitting diode is connected to the pixel electrode.
  • the light-shielding layer 112 is disposed on the first passivation layer 108 and the second passivation layer 111; the micro light-emitting diode 4 passes through the light-shielding layer 112.
  • the fifth through hole e of the second passivation layer 111 is connected to the pixel electrode 31.
  • the manufacturing method of the micro-light-emitting diode display panel provided in the present application includes the following steps:
  • An active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25 are sequentially formed on the substrate 101;
  • a first passivation layer 108 is formed on the substrate 101, and the first passivation layer covers the source electrode 24 and the drain electrode 25; the first passivation layer 108 is formed with a first through hole a;
  • a micro light emitting diode 4 is provided on the light shielding layer 112, and the micro light emitting diode is connected to the pixel electrode 31 through a fifth through hole e.
  • the light-shielding layer 112 is disposed on the first passivation layer 108 and the second passivation layer 111, and the light-shielding layer 112 is on a portion of the pixel electrode 31.
  • a groove is formed in the region; the micro light emitting diode 4 is disposed in the groove, and is connected to the pixel electrode 31 through a fifth through hole e that penetrates the light shielding layer 112 and the second passivation layer 111 .
  • the manufacturing method of the micro light emitting diode display panel provided in the present application includes the following steps:
  • An active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25 are sequentially formed on the substrate 101;
  • first passivation layer 108 Forming a first passivation layer 108 on the substrate 101, the first passivation layer covering the source 24 and the drain 25; the first passivation layer 108 is formed with a first through hole a;
  • a micro light emitting diode 4 is arranged in the groove of the light shielding layer 112, and the micro light emitting diode is connected to the pixel electrode 31 through a fifth through hole e.
  • the micro-light-emitting diode display panel further includes a third passivation layer 113, and the third passivation layer 113 is disposed on the light shielding layer 112;
  • the diode 4 is connected to the pixel electrode 31 through a sixth through hole f that penetrates the third passivation layer 113, the light shielding layer 112, and the second passivation layer 111.
  • the manufacturing method of the micro light emitting diode display panel provided in the present application includes the following steps:
  • An active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25 are sequentially formed on the substrate 101;
  • a first passivation layer 108 is formed on the substrate 101, and the first passivation layer covers the source electrode 24 and the drain electrode 25; the first passivation layer 108 is formed with a first through hole a;
  • a micro light emitting diode 4 is provided on the light shielding layer 112, and the micro light emitting diode is connected to the pixel electrode 31 through a sixth through hole f.
  • the present application also provides a display device, including a micro light emitting diode display panel, the micro light emitting diode display panel including:
  • a first passivation layer covering the source electrode and the drain electrode, and a first through hole is provided on the first passivation layer;
  • a pixel electrode, the pixel electrode is connected to the drain or the source through the first through hole
  • the micro light emitting diode is connected to the pixel electrode.
  • the micro light emitting diode display panel further includes: a second passivation layer, the second passivation layer is disposed on the pixel electrode;
  • the two passivation layers are provided with a second through hole, and the micro light emitting diode is connected to the pixel electrode through the second through hole.
  • the micro light emitting diode display panel further includes: a metal electrode, the metal electrode is disposed on the pixel electrode; the micro light emitting diode passes through the second The two through holes and the metal electrode are connected with the pixel electrode.
  • the micro light emitting diode display panel further includes: a third passivation layer, the third passivation layer is disposed on the light shielding layer; A three passivation layer covers the light shielding layer and part of the second passivation layer.
  • the projection of the pixel electrode on the substrate overlaps with the projection of the source electrode or the drain electrode on the substrate;
  • the light shielding layer covers part of the second passivation layer.
  • the material of the light shielding layer is black photoresist.
  • the light shielding layer is provided on the first passivation layer; the pixel electrode is provided on the light shielding layer, and the pixel electrode The through hole of the light shielding layer and the first passivation layer is connected to the drain or the drain.
  • the light-shielding layer is disposed on the first passivation layer and the second passivation layer; the micro light emitting diode penetrates the light-shielding layer and the The through hole of the second passivation layer is connected to the pixel electrode.
  • the light shielding layer forms a groove in a partial area of the pixel electrode; the micro light emitting diode is arranged in the groove.
  • the micro-light-emitting diode display panel includes an active layer forming a thin film transistor, a gate insulating layer, a gate, a source and a drain, a pixel electrode, and a micro-luminescence
  • the diode and the light-shielding layer covering the active layer, the gate insulating layer, the gate, the source and the drain, based on the light-shielding layer block the light emitted by the micro-light-emitting diode from irradiating the thin-film transistor, reducing the light-emitting of the micro-light-emitting diode
  • the impact on thin film transistors reduces the threshold Vth drift caused by the micro-light-emitting diode illuminating the thin-film transistor, thereby reducing the light leakage current, and alleviating the technology of the existing micro-light-emitting diode display panel that causes the threshold

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Abstract

一种微发光二极管显示面板及制备方法、显示装置，该微发光二极管显示面板包括有源层（21）、栅绝缘层（22）、栅极（23）、源极（24）和漏极（25），像素电极（31）、微发光二极管（4）、以及覆盖有源层（21）、栅绝缘层（22）、栅极（23）、源极（24）和漏极（25）的遮光层（112）；遮光层（112）阻挡了微发光二极管（4）所发出的光线照射到薄膜晶体管，减小了微发光二极管（4）对薄膜晶体管的影响。

Description

微发光二极管显示面板及制备方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种微发光二极管显示面板及制备方法、显示装置。
 背景技术
微发光二极管(Micro LED) 显示面板是一种以在一个基板上集成的高密度微小尺寸的发光二极管（LED）阵列作为显示像素来实现图像显示的显示装置，微发光二极管(Micro LED)显示面板属于自发光显示器。
由于微发光二极管所发的光为全方位的，阵列基板内的薄膜晶体管（TFT）会受到微发光二极管所发出的短波段光照射而产生阈值（Vth）漂移，进而导致光漏电流变大而影响显示效果。
即，现有微发光二极管显示面板存在微发光二极管发光引起薄膜晶体管阈值偏移的技术问题，需要改进。
 技术问题
本申请提供一种微发光二极管显示面板及制备方法、显示装置，以缓解现有微发光二极管显示面板存在微发光二极管发光引起薄膜晶体管阈值偏移的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种微发光二极管显示面板制备方法，其包括：
提供一基板；
在所述基板上依次形成有源层、栅绝缘层、栅极、源极和漏极；
在所述基板上形成第一钝化层，所述第一钝化层覆盖所述源极和漏极；所述第一钝化层上设有第一通孔；
在所述基板上形成像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
在所述基板上形成遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
在所述基板上设置微发光二极管，所述微发光二极管与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板制备方法中，在所述基板上形成遮光层的步骤之前，所述微发光二极管显示面板制备方法还包括：
在所述像素电极上形成第二钝化层，所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板制备方法中，在所述像素电极上形成第二钝化层的步骤之前，所述微发光二极管显示面板制备方法还包括：
在所述像素电极上形成金属电极，所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板制备方法中，在所述基板上形成遮光层的步骤之后，所述微发光二极管显示面板制备方法还包括：
在所述遮光层上形成第三钝化层，所述第三钝化层覆盖所述遮光层和部分第二钝化层。
同时，本申请实施例还提供一种微发光二极管显示面板，其包括：
基板；
设置在所述基板上的有源层、栅绝缘层、栅极、源极和漏极；
覆盖所述源极和所述漏极的第一钝化层，所述第一钝化层上设有第一通孔；
像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
微发光二极管，所述微发光二极管与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板中，所述微发光二极管显示面板还包括：第二钝化层，所述第二钝化层设置在所述像素电极上；所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板中，所述微发光二极管显示面板还包括：金属电极，所述金属电极设置在所述像素电极上；所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
在本申请实施例提供的微发光二极管显示面板中，所述微发光二极管显示面板还包括：第三钝化层，所述第三钝化层设置在所述遮光层上；所述第三钝化层覆盖所述遮光层和部分所述第二钝化层。
在本申请实施例提供的微发光二极管显示面板中：所述像素电极在所述基板上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；所述遮光层覆盖部分所述第二钝化层。
在本申请实施例提供的微发光二极管显示面板中，所述遮光层的材料为黑色光阻。
本申请实施例提供一种显示装置，其包括一微发光二极管显示面板，所述微发光二极管显示面板包括：
基板；
设置在所述基板上的有源层、栅绝缘层、栅极、源极和漏极；
覆盖所述源极和所述漏极的第一钝化层，所述第一钝化层上设有第一通孔；
像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
微发光二极管，所述微发光二极管与所述像素电极连接。
在本申请实施例提供的显示装置中，所述微发光二极管显示面板还包括：
第二钝化层，所述第二钝化层设置在所述像素电极上；所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
在本申请实施例提供的显示装置中，所述微发光二极管显示面板还包括：
金属电极，所述金属电极设置在所述像素电极上；所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
在本申请实施例提供的显示装置中，所述微发光二极管显示面板还包括：
第三钝化层，所述第三钝化层设置在所述遮光层上；所述第三钝化层覆盖所述遮光层和部分所述第二钝化层。
在本申请实施例提供的显示装置中：所述像素电极在所述基板上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；所述遮光层覆盖部分所述第二钝化层。
在本申请实施例提供的显示装置中，所述遮光层设置在所述第一钝化层上；所述像素电极设置在所述遮光层上，所述像素电极通过贯穿所述遮光层和所述第一钝化层的通孔，与所述漏极或者所述漏极连接。
在本申请实施例提供的显示装置中，所述遮光层设置在所述第一钝化层和第二钝化层上；所述微发光二极管通过贯穿所述遮光层和所述第二钝化层的通孔，与所述像素电极连接。
 有益效果
本申请提供一种微发光二极管显示面板及制备方法、显示装置，该微发光二极管显示面板包括形成薄膜晶体管的有源层、栅绝缘层、栅极、源极和漏极，像素电极、微发光二极管、以及覆盖有源层、栅绝缘层、栅极、源极和漏极的遮光层，基于该遮光层，阻挡了微发光二极管所发出的光线照射到薄膜晶体管，减小了微发光二极管发光对薄膜晶体管的影响，降低了微发光二极管照射薄膜晶体管导致的阈值Vth漂移，进而降低了光漏电流，缓解了现有微发光二极管显示面板存在的微发光二极管发光引起薄膜晶体管阈值偏移的技术问题，同时降低非开启时薄膜晶体管的漏电流，提高亮暗态对比度。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请微发光二极管显示面板的第一种结构示意图；
图2至图24为本申请微发光二极管显示面板制备方法的流程示意图；
图25为本申请微发光二极管显示面板的第二种结构示意图；
图26为本申请微发光二极管显示面板的第三种结构示意图；
图27为本申请微发光二极管显示面板的第四种结构示意图；
图28为本申请微发光二极管显示面板的第五种结构示意图；
图29为本申请微发光二极管显示面板的第六种结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有微发光二极管显示面板存在的微发光二极管发光引起薄膜晶体管阈值偏移的技术问题，本申请实施例可以缓解。
如图1所示，本申请提供的微发光二极管显示面板包括：
基板101；基板101可以是玻璃或者柔性衬底等；
设置在所述基板101上的有源层21、栅绝缘层22、栅极23、源极24和漏极25；有源层21、栅绝缘层22、栅极23、源极24和漏极25形成薄膜晶体管；
覆盖所述源极24和所述漏极25的第一钝化层108，所述第一钝化层108上设有第一通孔a；
像素电极31，所述像素电极31通过所述第一通孔连接所述漏极25或者所述源极24；在薄膜晶体管为N型薄膜晶体管时，像素电极31通过所述第一通孔连接所述漏极25，在薄膜晶体管为P型薄膜晶体管时，像素电极31通过所述第一通孔连接所述漏极25；
遮光层112，所述遮光层112覆盖所述有源层21、栅绝缘层22、栅极23、源极24和漏极25；
微发光二极管4，所述微发光二极管与所述像素电极连接。
本实施例提供了一种微发光二极管显示面板，该微发光二极管显示面板包括形成薄膜晶体管的有源层、栅绝缘层、栅极、源极和漏极，像素电极、微发光二极管、以及覆盖有源层、栅绝缘层、栅极、源极和漏极的遮光层；基于该遮光层，阻挡了微发光二极管所发出的光线照射到薄膜晶体管，减小了微发光二极管发光对薄膜晶体管的影响。
在一种实施例中，若像素电极的电位为正时，像素电极31通过所述第一通孔连接所述漏极25，若像素电极的电位为负时，像素电极31通过所述第一通孔连接所述源极24。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：第二钝化层111，所述第二钝化层111设置在所述像素电极31上；所述第二钝化层111设有第二通孔b，所述微发光二极管4通过所述第二通孔与所述像素电极31连接。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：金属电极32，所述金属电极32设置在所述像素电极31上；所述微发光二极管4通过所述第二通孔b、金属电极32与所述像素电极31连接。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：第三钝化层113，所述第三钝化层113设置在所述遮光层112上；所述第三钝化层113覆盖所述遮光层112和部分所述第二钝化层111。
在一种实施例中，如图1所示，所述像素电极31在所述基板101上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；所述遮光层112覆盖部分所述第二钝化层111。
微发光二极管4按照结构不同，可分为垂直结构的微发光二极管和水平结构的微发光二极管，垂直结构的微发光二极管的第一电极和第二电极分别位于微发光二极管的上下两侧，水平的结构的微发光二极管的第一电极和第二电极均位于微发光二极管的下侧。
在一种实施例中，所述微发光二极管4为水平结构的微发光二极管，所述微发光二极管显示面板还包括：用于连接公共电压的连接电极26、透明公共电极33，透明公共电极33通过所述第一通孔连接所述连接电极26；所述微发光二极管4的第一电极连接像素电极31，第二电极连接透明公共电极33。
在一种实施例中，如图1所示，所述第二钝化层111还设置在所述透明公共电极33上；所述微发光二极管4的第二电极通过所述第二通孔连接透明公共电极33。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：金属公共电极34，设置在所述透明公共电极33上，所述微发光二极管4的第二电极通过第二过孔、金属公共电极34连接透明公共电极33。
在一种实施例中，所述微发光二极管4为倒装的水平结构微发光二极管，以提高出光效率。
在一种实施例中，所述微发光二极管4为垂直结构的微发光二极管，所述微发光二极管显示面板还包括：透明公共电极层，所述微发光二极管4的第一电极连接像素电极31，第二电极连接透明公共电极层。
在一种实施例中，薄膜晶体管包括驱动薄膜晶体管、开关薄膜晶体管、感测薄膜晶体管等；驱动薄膜晶体管包括金属氧化物半导体薄膜晶体管等，开关薄膜晶体管包括低温多晶硅薄膜晶体管等。
在一种实施例中，微发光二极管显示基板包括阵列排布的子像素单元，一个子像素单元包括一个微发光二极管4，以及至少一个驱动薄膜晶体管，微发光二极管4在驱动薄膜晶体管的驱动下发光。
在一种实施例中，像素电极31和透明公共电极33的材料可以是氧化铟锡、氧化铟锌、氧化铝锌等。
在一种实施例中，金属电极32和金属公共电极34的材料可以是铜钼叠层、铜钼钛叠层、铜钛叠层，铝钼叠层，铜铌合金、镍铬合金等。
在一种实施例中，所述遮光层112的材料是黑色光阻。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：缓冲层102，设置在所述基板101上，所述有源层21、栅绝缘层22、栅极23、源极24和漏极25设置在所述缓冲层102上。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：中间电介质层106，设置在所述栅极23上，所述源极24和漏极25设置在所述中间电介质层106上。
在一种实施例中，如图1所示，所述微发光二极管显示面板还包括：封装膜114，封装膜可以为有机/无机交替沉积的隔水氧及机械碰撞保护膜，用于封装微发光二极管4。
为了制备得到图1所示的微发光二极管显示面板，本申请实施例也提供了一种微发光二极管显示面板制备方法，其包括以下步骤：
步骤1、提供一基板；
步骤2、在所述基板上依次形成有源层、栅绝缘层、栅极、源极和漏极；
步骤3、在所述基板上形成第一钝化层，所述第一钝化层覆盖所述源极和漏极；所述第一钝化层上设有第一通孔；
步骤4、在所述基板上形成像素电极和遮光层，所述像素电极通过所述第一通孔连接所述漏极或者所述源极，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
步骤5、在所述基板上设置微发光二极管，所述微发光二极管与所述像素电极连接。
在一种实施例中，步骤4包括：
步骤41、在所述基板上形成像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
步骤42、在所述基板上形成遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极。
在一种实施例中，在步骤42之前，所述微发光二极管显示面板制备方法还包括：
步骤43、在所述像素电极上形成第二钝化层，所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
在一种实施例中，在步骤43之前，所述微发光二极管显示面板制备方法还包括：
步骤44、在所述像素电极上形成金属电极，所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
在一种实施例中，在步骤42之后，所述微发光二极管显示面板制备方法还包括：
步骤45、在所述遮光层上形成第三钝化层，所述第三钝化层覆盖所述遮光层和部分第二钝化层。
现以薄膜晶体管为金属氧化物半导体薄膜晶体管、微发光二极管为水平结构的微发光二极管为例，对本申请提供的微发光二极管显示面板制备方法进行描述。
如图2至图24所示，本申请实施例提供的微发光二极管显示面板制备方法包括以下步骤：
如图2所示，提供一基板101。
基板101可以是玻璃基板、柔性基板等，并进行清洗等处理。
如图3所示，在基板101上沉积缓冲层102。
缓冲层102的材料可以为氧化硅、氮化硅/氧化硅叠层，氧化铝/氧化硅叠层等。
如图4所示，在缓冲层102上沉积金属氧化物半导体膜层103。
金属氧化物半导体膜层103的材料可以是氧化铟镓锌、氧化铟锌、氧化铟镓、氧化铟镓钛、氧化铟镓锌钛等。
如图5所示，对金属氧化物半导体膜层103进行处理，形成有源层21。
有源层21包括N掺杂区和P掺杂区、以及位于N掺杂区和P掺杂区之间的沟道区。
如图6所示，在缓冲层102和有源层21上沉积绝缘层104和金属层105。
绝缘层104的材料可以为氧化硅、氮化硅/氧化硅叠层，氧化铝/氧化硅叠层等，第一金属层105的材料可以为铜钼叠层、铜钼钛叠层、铜钛叠层，铝钼叠层，铜铌合金等。
如图7所示，对绝缘层104进行图案化处理，形成栅绝缘层22，对金属层105进行图案化处理，形成栅极23。
如图8所示，在缓冲层102、有源层21、栅绝缘层22、栅极23上沉积中间电介质层106。
中间电介质层106的材料可以为氧化硅、氮化硅/氧化硅叠层等。
如图9所示，对中间电介质层106图案化处理，形成对应N掺杂区和P掺杂区的开孔。
如图10所示，在中间电介质层106上金属层107。
金属层107的材料可以为铜钼叠层、铜钼钛叠层、铜钛叠层，铝钼叠层，铜铌合金等。
如图11所示，对金属层107进行图案化处理，形成源极24、漏极25以及连接电极26。
如图12所示，在中间电介质层106、源极24、漏极25以及连接电极26上沉积第一钝化层108。
第一钝化层108的材料可以为氧化硅、氮化硅、氮化硅/氧化硅叠层。
如图13所示，对第一钝化层108图案化处理，形成对应漏极25以及连接电极26的第一通孔a。
如图14所示，在第一钝化层108上沉积透明导电层109及金属层110。
透明导电层109的材料可以为氧化铟锡、氧化铟锌、氧化铝锌等，金属层110的材料可以是铜钼叠层、铜钼钛叠层、铜钛叠层，铝钼叠层，铜铌合金、镍铬合金等。
如图15所示，对透明导电层109进行图案化处理，形成像素电极31和透明公共电极33，对金属层110进行图案化处理，形成金属电极32和金属公共电极34。
像素电极31通过第一通孔a连接漏极25，透明公共电极33通过第一通孔a与连接电极26连接。
如图16所示，在第一钝化层108、金属电极32和金属公共电极34上沉积第二钝化层111。
第二钝化层111的材料可以为氧化硅、氮化硅、氧化铝、氧化硅/氧化硅叠层等。
如图17所示，对第二钝化层111进行图案化处理，保留覆盖金属电极32和金属公共电极34的区域。
如图18所示，在第一钝化层108、第二钝化层111上沉积遮光层112。
遮光层112的材料可以是黑色光阻、不透明金属等。
如图19所示，对遮光层112进行图案化处理，保留覆盖有源层21、栅绝缘层22、栅极23、源极24和漏极25的区域。
如图20所示，在第一钝化层108、第二钝化层111、遮光层112上沉积第三钝化层113。
第三钝化层113的材料可以为氧化硅、氮化硅、氧化铝、氧化硅/氧化硅叠层等。
如图21所示，对第三钝化层113进行图案化处理，保留覆盖遮光层112的区域。
如图22所示，对第二钝化层111进行图案化挖孔，形成对应金属电极32和金属公共电极34的第二通孔b。
如图23所示，进行微发光二极管4的绑定。
将微发光二极管4的第一电极通过第二通孔b与金属电极32连接，将微发光二极管4的第二电极通过第二通孔b与金属公共电极32连接。
如图24所示，在第一钝化层108、第二钝化层111、微发光二极管4上沉积透明的封装膜114。
封装膜114可以为有机/无机交替沉积的隔水氧及机械碰撞保护膜等。
现结合图25至图29对本申请的其他实现方式进行描述。
在图25至图29所示的微发光二极管显示面板中，相同标号所对应的膜层以及构件名称与图1所示的微发光二极管显示面板一致。
在一种实施例中，如图25所示，所述遮光层112设置在所述第一钝化层108上；所述像素电极31设置在所述遮光层112上 ，所述像素电极31通过贯穿所述遮光层112和所述第一钝化层108的通孔c，与所述漏极25连接；或者与所述源极24连接（图25未示出）。
为了得到图25所示的微发光二极管显示面板，本申请提供的微发光二极管显示面板制备方法包括以下步骤：
提供一基板101；
在所述基板101上依次形成有源层21、栅绝缘层22、栅极23、源极24和漏极25；
在所述基板101上形成第一钝化层108，所述第一钝化层覆盖所述源极24和漏极25；
在所述第一钝化层108上形成遮光层112；
对所述第一钝化层108、以及遮光层112进行处理，形成第三通孔c；
在所述遮光层112形成像素电极31，所述像素电极通过所述第三通孔c（包括第一钝化层108形成的第一通孔）连接所述漏极或者所述源极；
在所述基板上设置微发光二极管，所述微发光二极管与所述像素电极连接。
在一种实施例中，如图26所示，所述微发光二极管显示面板还包括第三钝化层113，第三钝化层113设置在遮光层112上；所述像素电极31在所述第三钝化层113上 ，所述像素电极31通过贯穿所述第三钝化层113、遮光层112和所述第一钝化层108的通孔d，与所述漏极25连接。
为了得到图26所示的微发光二极管显示面板，本申请提供的微发光二极管显示面板制备方法包括以下步骤：
提供一基板101；
在所述基板101上依次形成有源层21、栅绝缘层22、栅极23、源极24和漏极25；
在所述基板101上形成第一钝化层108，所述第一钝化层覆盖所述源极24和漏极25；
在所述第一钝化层108上形成遮光层112；
在所述遮光层112上形成第三钝化层113；
对所述第一钝化层108、第三钝化层113以及遮光层112进行处理，形成第四通孔d；
在所述遮光层112形成像素电极31，所述像素电极通过所述第四通孔d（包括第一钝化层108形成的第一通孔）连接所述漏极或者所述源极；
在所述基板上设置微发光二极管，所述微发光二极管与所述像素电极连接。
在一种实施例中，如图27所示，所述遮光层112设置在所述第一钝化层108和第二钝化层111上；所述微发光二极管4通过贯穿所述遮光层112和所述第二钝化层111的第五通孔e，与所述像素电极31连接。
为了得到图27所示的微发光二极管显示面板，本申请提供的微发光二极管显示面板制备方法包括以下步骤：
提供一基板101；
在所述基板101上依次形成有源层21、栅绝缘层22、栅极23、源极24和漏极25；
在所述基板101上形成第一钝化层108，所述第一钝化层覆盖所述源极24和漏极25；第一钝化层108形成有第一通孔a；
在所述第一钝化层108上形成像素电极31；
在所述像素电极31上形成遮光层112；
对所述遮光层112进行处理，形成第五通孔e；
在所述遮光层112上设置微发光二极管4，所述微发光二极管通过第五通孔e与所述像素电极31连接。
在一种实施例中，如图28所示，所述遮光层112设置在所述第一钝化层108和第二钝化层111上，所述遮光层112在所述像素电极31的部分区域内形成凹槽；所述微发光二极管4设置在所述凹槽内，通过贯穿所述遮光层112和所述第二钝化层111的第五通孔e，与所述像素电极31连接。
为了得到图28所示的微发光二极管显示面板，本申请提供的微发光二极管显示面板制备方法包括以下步骤：
提供一基板101；
在所述基板101上依次形成有源层21、栅绝缘层22、栅极23、源极24和漏极25；
在所述基板101上形成第一钝化层108，所述第一钝化层覆盖所述源极24和漏极25；第一钝化层108形成有第一通孔a；
在所述第一钝化层108上形成像素电极31；
在所述像素电极31上形成遮光层112；
对所述遮光层112进行处理，形成凹槽以及第五通孔e；
在所述遮光层112的凹槽内设置微发光二极管4，所述微发光二极管通过第五通孔e与所述像素电极31连接。
在一种实施例中，如图29所示，所述微发光二极管显示面板还包括第三钝化层113，所述第三钝化层113设置在所述遮光层112上；所述微发光二极管4通过贯穿所述第三钝化层113、所述遮光层112和所述第二钝化层111的第六通孔f，与所述像素电极31连接。
为了得到图29所示的微发光二极管显示面板，本申请提供的微发光二极管显示面板制备方法包括以下步骤：
提供一基板101；
在所述基板101上依次形成有源层21、栅绝缘层22、栅极23、源极24和漏极25；
在所述基板101上形成第一钝化层108，所述第一钝化层覆盖所述源极24和漏极25；第一钝化层108形成有第一通孔a；
在所述第一钝化层108上形成像素电极31；
在所述像素电极31上形成遮光层112；
在所述遮光层112上形成第三钝化层113；
对所述遮光层112以及所述第三钝化层113进行处理，形成第六通孔f；
在所述遮光层112上设置微发光二极管4，所述微发光二极管通过第六通孔f与所述像素电极31连接。
同时，本申请还提供一种显示装置，包括一微发光二极管显示面板，该微发光二极管显示面板包括：
基板；
设置在所述基板上的有源层、栅绝缘层、栅极、源极和漏极；
覆盖所述源极和所述漏极的第一钝化层，所述第一钝化层上设有第一通孔；
像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
微发光二极管，所述微发光二极管与所述像素电极连接。
在一种实施例中，在本申请提供的显示装置中，所述微发光二极管显示面板还包括：第二钝化层，所述第二钝化层设置在所述像素电极上；所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
在一种实施例中，在本申请提供的显示装置中，所述微发光二极管显示面板还包括：金属电极，所述金属电极设置在所述像素电极上；所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
在一种实施例中，在本申请提供的显示装置中，所述微发光二极管显示面板还包括：第三钝化层，所述第三钝化层设置在所述遮光层上；所述第三钝化层覆盖所述遮光层和部分所述第二钝化层。
在一种实施例中，在本申请提供的显示装置中：所述像素电极在所述基板上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；所述遮光层覆盖部分所述第二钝化层。
在一种实施例中，在本申请提供的显示装置中，所述遮光层的材料为黑色光阻。
在一种实施例中，在本申请提供的显示装置中，所述遮光层设置在所述第一钝化层上；所述像素电极设置在所述遮光层上，所述像素电极通过贯穿所述遮光层和所述第一钝化层的通孔，与所述漏极或者所述漏极连接。
在一种实施例中，在本申请提供的显示装置中，所述遮光层设置在所述第一钝化层和第二钝化层上；所述微发光二极管通过贯穿所述遮光层和所述第二钝化层的通孔，与所述像素电极连接。
在一种实施例中，在本申请提供的显示装置中，所述遮光层在所述像素电极的部分区域内形成凹槽；所述微发光二极管设置在所述凹槽内。
根据上述实施例可知：
本申请提供一种微发光二极管显示面板及制备方法、显示装置，该微发光二极管显示面板包括形成薄膜晶体管的有源层、栅绝缘层、栅极、源极和漏极，像素电极、微发光二极管、以及覆盖有源层、栅绝缘层、栅极、源极和漏极的遮光层，基于该遮光层，阻挡了微发光二极管所发出的光线照射到薄膜晶体管，减小了微发光二极管发光对薄膜晶体管的影响，降低了微发光二极管照射薄膜晶体管导致的阈值Vth漂移，进而降低了光漏电流，缓解了现有微发光二极管显示面板存在的微发光二极管发光引起薄膜晶体管阈值偏移的技术问题，同时降低非开启时薄膜晶体管的漏电流，提高亮暗态对比度。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种微发光二极管显示面板制备方法，其包括：
    提供一基板；
    在所述基板上依次形成有源层、栅绝缘层、栅极、源极和漏极；
    在所述基板上形成第一钝化层，所述第一钝化层覆盖所述源极和漏极；所述第一钝化层上设有第一通孔；
    在所述基板上形成像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
    在所述基板上形成遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
    在所述基板上设置微发光二极管，所述微发光二极管与所述像素电极连接。
  2. 根据权利要求1所述的微发光二极管显示面板制备方法，其中，在所述基板上形成遮光层的步骤之前，所述微发光二极管显示面板制备方法还包括：
    在所述像素电极上形成第二钝化层，所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
  3. 根据权利要求2所述的微发光二极管显示面板制备方法，其中，在所述像素电极上形成第二钝化层的步骤之前，所述微发光二极管显示面板制备方法还包括：
    在所述像素电极上形成金属电极，所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
  4. 根据权利要求2所述的微发光二极管显示面板制备方法，其中，在所述基板上形成遮光层的步骤之后，所述微发光二极管显示面板制备方法还包括：
    在所述遮光层上形成第三钝化层，所述第三钝化层覆盖所述遮光层和部分第二钝化层。
  5. 一种微发光二极管显示面板，其包括：
    基板；
    设置在所述基板上的有源层、栅绝缘层、栅极、源极和漏极；
    覆盖所述源极和所述漏极的第一钝化层，所述第一钝化层上设有第一通孔；
    像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
    遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
    微发光二极管，所述微发光二极管与所述像素电极连接。
  6. 根据权利要求5所述的微发光二极管显示面板，其中，所述微发光二极管显示面板还包括：
    第二钝化层，所述第二钝化层设置在所述像素电极上；所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
  7. 根据权利要求6所述的微发光二极管显示面板，其中，所述微发光二极管显示面板还包括：
    金属电极，所述金属电极设置在所述像素电极上；所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
  8. 根据权利要求6所述的微发光二极管显示面板，其中，所述微发光二极管显示面板还包括：
    第三钝化层，所述第三钝化层设置在所述遮光层上；所述第三钝化层覆盖所述遮光层和部分所述第二钝化层。
  9. 根据权利要求6所述的微发光二极管显示面板，其中：
    所述像素电极在所述基板上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；
    所述遮光层覆盖部分所述第二钝化层。
  10. 根据权利要求5所述的微发光二极管显示面板，其中，所述遮光层的材料为黑色光阻。
  11. 根据权利要求5所述的微发光二极管显示面板，其中，所述遮光层设置在所述第一钝化层上；所述像素电极设置在所述遮光层上，所述像素电极通过贯穿所述遮光层和所述第一钝化层的通孔，与所述漏极或者所述漏极连接。
  12. 根据权利要求6所述的微发光二极管显示面板，其中，所述遮光层设置在所述第一钝化层和第二钝化层上；所述微发光二极管通过贯穿所述遮光层和所述第二钝化层的通孔，与所述像素电极连接。
  13. 根据权利要求12所述的微发光二极管显示面板，其中，所述遮光层在所述像素电极的部分区域内形成凹槽；所述微发光二极管设置在所述凹槽内。
  14. 一种显示装置，其包括一微发光二极管显示面板，所述微发光二极管显示面板包括：
    基板；
    设置在所述基板上的有源层、栅绝缘层、栅极、源极和漏极；
    覆盖所述源极和所述漏极的第一钝化层，所述第一钝化层上设有第一通孔；
    像素电极，所述像素电极通过所述第一通孔连接所述漏极或者所述源极；
    遮光层，所述遮光层覆盖所述有源层、栅绝缘层、栅极、源极和漏极；
    微发光二极管，所述微发光二极管与所述像素电极连接。
  15. 根据权利要求14所述的显示装置，其中，所述微发光二极管显示面板还包括：
    第二钝化层，所述第二钝化层设置在所述像素电极上；所述第二钝化层设有第二通孔，所述微发光二极管通过所述第二通孔与所述像素电极连接。
  16. 根据权利要求15所述的显示装置，其中，所述微发光二极管显示面板还包括：
    金属电极，所述金属电极设置在所述像素电极上；所述微发光二极管通过所述第二通孔、金属电极与所述像素电极连接。
  17. 根据权利要求15所述的显示装置，其中，所述微发光二极管显示面板还包括：
    第三钝化层，所述第三钝化层设置在所述遮光层上；所述第三钝化层覆盖所述遮光层和部分所述第二钝化层。
  18. 根据权利要求15所述的显示装置，其中：
    所述像素电极在所述基板上的投影，与所述源极或者所述漏极在所述基板上的投影部分重合；
    所述遮光层覆盖部分所述第二钝化层。
  19. 根据权利要求14所述的显示装置，其中，所述遮光层设置在所述第一钝化层上；所述像素电极设置在所述遮光层上，所述像素电极通过贯穿所述遮光层和所述第一钝化层的通孔，与所述漏极或者所述漏极连接。
  20. 根据权利要求15所述的显示装置，其中，所述遮光层设置在所述第一钝化层和第二钝化层上；所述微发光二极管通过贯穿所述遮光层和所述第二钝化层的通孔，与所述像素电极连接。
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