WO2024000470A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024000470A1
WO2024000470A1 PCT/CN2022/102983 CN2022102983W WO2024000470A1 WO 2024000470 A1 WO2024000470 A1 WO 2024000470A1 CN 2022102983 W CN2022102983 W CN 2022102983W WO 2024000470 A1 WO2024000470 A1 WO 2024000470A1
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Prior art keywords
layer
area
metal layer
base substrate
display
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PCT/CN2022/102983
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English (en)
French (fr)
Inventor
张家祥
王珂
曹占锋
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京东方科技集团股份有限公司
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Priority to CN202280002072.2A priority Critical patent/CN117642864A/zh
Priority to PCT/CN2022/102983 priority patent/WO2024000470A1/zh
Publication of WO2024000470A1 publication Critical patent/WO2024000470A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • LED Light Emitting Diode
  • Mini LED Small Light Emitting Diode
  • Micro LED micro light emitting diode
  • LED has the advantages of self-illumination, wide viewing angle, fast response, simple structure, long life, etc.
  • Mini LED/Micro LED displays can achieve large-size display through splicing, so they have good market prospects.
  • the structure and manufacturing process of Mini LED/Micro LED display devices are one of the important topics that R&D personnel pay attention to.
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • a display substrate including: a substrate substrate; a metal layer located on the substrate substrate, the metal layer including a copper layer having a first thickness; the metal layer located away from the substrate An anti-oxidation layer on one side of the substrate, the anti-oxidation layer having a second thickness; a light-emitting diode on the side of the anti-oxidation layer away from the substrate, the light-emitting diode including at least one electrode, the light-emitting diode At least one electrode is electrically connected to the metal layer, wherein the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.
  • the anti-oxidation layer includes a nickel-containing alloy.
  • the substrate substrate includes a display area and a marking area
  • the display substrate includes: a first accompanying plating area located in the marking area; and a second accompanying plating area located in the display area. area; the first accompanying plating area and the second accompanying plating area both include a copper layer; the area ratio of the first accompanying plating area to the mark area is greater than that of the second accompanying plating area to the display area area ratio.
  • the display substrate further includes: a mark located in the mark area; and a clear area located in the mark area, the first plating area surrounds the mark, and the clear area A region is located between the mark and the first plating area and surrounds the mark.
  • an orthographic projection of the first plating area on the base substrate is an annular area surrounding the mark.
  • the anti-oxidation layer surrounds the metal layer, and at least one electrode of the light-emitting diode is electrically connected to the metal layer through the anti-oxidation layer.
  • the display substrate further includes: a passivation layer located on the anti-oxidation layer away from the base substrate; and a first via hole located in the passivation layer; the first The via hole exposes at least a portion of the anti-oxidation layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the first via hole.
  • the anti-oxidation layer surrounds the metal layer.
  • the display substrate further includes: a passivation layer located on the anti-oxidation layer away from the base substrate; and a third via hole located in the passivation layer; the third The via hole is located at the pad position of the display area, the third via hole exposes at least a part of the metal layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the third via hole.
  • the display substrate further includes: a fourth via hole located in the passivation layer; the fourth via hole is located at a binding position, and the fourth via hole exposes the anti-oxidation At least a portion of the layer, at least one electrode of the light-emitting diode is electrically connected to the metal layer through an exposed portion of the anti-oxidation layer.
  • the anti-oxidation layer includes an opening that exposes at least a portion of the metal layer, and an orthographic projection of the third via hole on the base substrate is located in the opening. part is within the orthographic projection on the base substrate.
  • a light-emitting diode is installed on the side of the anti-oxidation layer away from the base substrate, wherein the light-emitting diode includes at least one electrode, and at least one electrode of the light-emitting diode is electrically connected to the metal layer,
  • the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.
  • the base substrate includes a display area and a marking area
  • Forming a copper layer on the portion of the copper seed layer not covered by the photoresist pattern through an electroplating process includes:
  • a first plating area is formed
  • first accompanying plating area and the second accompanying plating area respectively include a part of the copper layer
  • the method further includes: forming a mark through an electroplating process in an area surrounded by the first accompanying plating area.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes:
  • first via hole in the passivation layer, the first via hole exposing at least a portion of the metal layer
  • the anti-oxidation layer includes an organic soldering film.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes: forming an anti-oxidation layer surrounding the metal layer on a side of the metal layer away from the base substrate. Nickel alloy layer.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes:
  • a second via hole is formed in the passivation layer, the second via hole exposing at least a portion of the nickel-containing alloy layer.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes:
  • An opening is formed in the nickel-containing alloy layer at a pad position in the display area, and the opening exposes at least a part of the metal layer,
  • a third via hole is formed in the passivation layer at the pad position of the display area, and the third via hole exposes at least a portion of the metal layer,
  • the orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the opening on the base substrate.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate further includes: forming a fourth via hole in the passivation layer at a binding position, and the third via hole is formed in the passivation layer.
  • Four vias expose at least a portion of the nickel-containing alloy layer.
  • a display device including the display substrate as described above.
  • FIG. 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that, for illustration, FIG. 1 shows the unfolded state of the display substrate and another substrate bound thereto.
  • FIG. 2 is a cross-sectional view of the display substrate taken along line AA' in FIG. 1 according to some exemplary embodiments of the present disclosure.
  • FIG. 3 is a flow chart of a method of forming a copper layer using a subtractive method in the related art.
  • FIG. 4 is a flowchart of a method of manufacturing a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 5A is a partial plan view of a display substrate schematically illustrating a display area and a mark area, according to some exemplary embodiments of the present disclosure.
  • Figure 5B is a partial enlarged view of the marked area shown in Figure 5A.
  • FIG. 5C is a partial enlarged view of the display area shown in FIG. 5A.
  • 6A is a schematic diagram of marks formed by a method of manufacturing a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 6B is a schematic diagram of marks formed by a preparation method of a display substrate in the related art.
  • FIG. 7 is a partial cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing the positional relationship between the metal layer and the anti-oxidation layer.
  • Figures 8A and 8B are electron microscopy images of areas I and II in Figure 7, respectively.
  • FIG. 9A is a partial cross-sectional view of a display substrate according to other exemplary embodiments of the present disclosure, schematically showing the positional relationship between the metal layer and the anti-oxidation layer.
  • Figure 9B is an electron microscope image of region III in Figure 9A.
  • 10A and 10B are respectively a partial cross-sectional view and a partial plan view of a display substrate according to further exemplary embodiments of the present disclosure, which schematically illustrate the positional relationship between the metal layer and the anti-oxidation layer.
  • FIG. 11 is a partial cross-sectional view of a display substrate according to other exemplary embodiments of the present disclosure, which schematically shows the positional relationship between the metal layer and the anti-oxidation layer.
  • 12A and 12B are partial cross-sectional views of the display substrate at the first position and the second position respectively according to other exemplary embodiments of the present disclosure, which schematically illustrate the positional relationship between the metal layer and the anti-oxidation layer.
  • FIG. 13 is a schematic diagram of the arrangement of the light emitting units of the display substrate shown in FIG. 1 .
  • FIG. 14 is a schematic diagram of a light-emitting unit in the display substrate shown in FIG. 13 .
  • connection may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader meaning.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or Any combination of two or more of X, Y and Z such as XYZ, XY, YZ and XZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED means inorganic light-emitting elements that are different from OLEDs.
  • inorganic light-emitting elements may include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, English abbreviation: Mini LED) and micro-light emitting diodes (Micro Light Emitting Diode, English abbreviation: Micro LED).
  • micro light-emitting diodes refer to ultra-small light-emitting diodes with a grain size of less than 100 microns
  • sub-millimeter light-emitting diodes refer to small light-emitting diodes with a grain size between Micro LED and traditional LEDs.
  • the grain size of Mini LED can be between 100 and 300 microns
  • the grain size of Micro LED can be between 10 and 100 microns.
  • Wire bonding is a process that uses heat, pressure or ultrasonic energy to tightly bond metal bonding wires to substrate pads.
  • wire bonding can be used to connect the semiconductor chip pad to the I/O bonding wire of the microelectronic package or the metal wiring pad on the substrate with metal filaments.
  • the principle of wire bonding is to use heating, pressure or ultrasonic waves to destroy the oxide layer and pollution on the surface to be welded, and produce plastic deformation, so that the metal bonding wire is in close contact with the surface to be welded, reaching the gravitational range between atoms and causing the interface The atoms diffuse to form a weld.
  • OSP is the abbreviation of Organic Solde-rability Preservatives, which can be called organic solder mask, also known as copper protective agent.
  • OSP chemically grows an organic film on a clean bare copper surface. This film has anti-oxidation, thermal shock resistance, and moisture resistance to protect the copper surface from continuing to rust (oxidation or sulfurization, etc.) in normal environments. This protective film can be easily removed during subsequent welding at high temperatures. The flux is removed quickly, allowing the exposed clean copper surface to be immediately combined with the molten solder to form a strong solder joint in a very short time.
  • Some exemplary embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device including the display substrate.
  • some embodiments of the present disclosure provide a display substrate, including: a substrate substrate; a metal layer located on the substrate substrate, the metal layer including a copper layer having a first thickness; located on the metal layer an anti-oxidation layer on a side away from the base substrate, the anti-oxidation layer having a second thickness; a light-emitting diode on a side of the anti-oxidation layer away from the base substrate, the light-emitting diode including at least one electrode , at least one electrode of the light-emitting diode is electrically connected to the metal layer, wherein the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.
  • a display substrate with a thick copper layer can be realized, and the copper layer can be prevented from being oxidized through the film design of the anti-oxidation layer.
  • FIG. 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that, for illustration, FIG. 1 shows the unfolded state of the display substrate and another substrate bound thereto. 2 is a cross-sectional view of the display substrate taken along line AA' in FIG. 1 according to some exemplary embodiments of the present disclosure.
  • the display substrate 100 may include a base substrate 1 and a plurality of first electrodes 2 and a plurality of first conductive pads 3 provided on the base substrate 1 .
  • a plurality of first conductive pads 3 are located at the edge of the display substrate 100 .
  • a plurality of first conductive pads 3 are located in a fan-out area (ie, fan-out area) of the display substrate 100 for connecting signal lines (for example, schematically shown in FIG. 1 ) located on the display substrate 100 A portion of the signal line 150) is electrically connected to the external driving circuit.
  • the material of the base substrate 1 may include but is not limited to glass, quartz, plastic, silicon, polyimide, etc.
  • the first electrode 2 and the first conductive pad 3 may have a columnar structure.
  • the materials of the first electrode 2 and the first conductive pad 3 may include conductive materials, such as metal materials, etc., specifically, they may be gold, silver, copper, aluminum, molybdenum, gold alloy, silver alloy, copper alloy, aluminum alloy, molybdenum At least one or a combination of at least two selected from alloys, etc., the embodiments of the present disclosure are not limited to this.
  • the display substrate 100 may further include a driving circuit 4 electrically connected to the plurality of first electrodes 2 , and the driving circuit 4 is disposed on the base substrate 1 .
  • the driving circuit 4 can be used to provide electrical signals to the light-emitting diode chips 5 located on the plurality of first electrodes 2 to control their luminous brightness.
  • the driving circuit 4 can be a plurality of pixel driving circuits connected to each light-emitting diode chip in a one-to-one correspondence, or a plurality of micro integrated circuit chips connected to each light-emitting diode chip in a one-to-one correspondence, etc. structure, each light-emitting diode chip can be controlled to emit different brightness gray scales.
  • the specific circuit structure of the driving circuit 4 on the display substrate 100 can be set according to actual needs, and the embodiments of the present disclosure do not limit this.
  • multiple light-emitting diodes 5 can be transferred and bound to the display substrate 100 .
  • the light-emitting diode 5 includes an N electrode 5N and a P electrode 5P.
  • the N electrodes and P electrodes of the light-emitting diode 5 are respectively connected to the corresponding first electrodes 2, and the surfaces of the plurality of first conductive pads 3 are exposed. .
  • a plurality of light emitting diodes are arranged in an array along a first direction X and a second direction Y.
  • the first direction X is the row direction and the second direction Y is the column direction.
  • the first direction and the second direction can be any direction, as long as the first direction and the second direction intersect.
  • the plurality of light-emitting diodes is not limited to being arranged along a straight line, but can also be arranged along a curve, a ring, or any other manner. This can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.
  • a plurality of first conductive pads 3 are arranged at the edge of the display substrate 100 along the first direction X, that is, the plurality of first conductive pads 3 constitute a first conductive pad row.
  • a plurality of first conductive pads 3 are arranged at equal intervals along the first direction X.
  • the light emitting diode may include a micro light emitting diode (Micro-LED) or a sub-millimeter light emitting diode (Mini-LED).
  • Micro-LED micro light emitting diode
  • Mini-LED sub-millimeter light emitting diode
  • the second substrate 200 may be a circuit board, such as PCB (Printed Circuit Board), FPC (Flexible Printed Circuit) or COF (Chip On Film), etc.
  • PCB Printed Circuit Board
  • FPC Flexible Printed Circuit
  • COF Chip On Film
  • the second substrate 200 may include a plurality of second conductive pads 7 .
  • a plurality of second conductive pads 7 may be arranged along the first direction X, that is, the plurality of second conductive pads 7 constitute a second conductive pad row.
  • the plurality of second conductive pads 7 may correspond to the plurality of first conductive pads 3 one-to-one. That is, the arrangement period of the second conductive pads 7 is the same as the arrangement period of the first conductive pads 3 .
  • the bonding wire 9 electrically connects the first conductive pad 3 and the second conductive pad 7 .
  • One end of the bonding wire 9 is connected to the first conductive pad 3 and the other end is connected to the second conductive pad 7 . That is, one end of the bonding wire 9 is welded to the first conductive pad 3 and the other end is welded to the second conductive pad 7 .
  • the solder joint soldered on the first conductive pad 3 is called the first solder joint 911
  • the solder joint soldered on the second conductive pad 7 is called the second solder joint 921 .
  • the bonding wire 9 can be made of metals such as Cu, Al, Au, Ag, or alloys thereof.
  • the second substrate 200 may also include an external driving circuit, such as an integrated circuit chip, but embodiments of the present disclosure are not limited thereto.
  • the display substrate 100 may be a backplane for a light emitting diode display panel.
  • the display substrate 100 includes, but is not limited to, the following backplanes: passively driven backplanes, or active driven backplanes containing thin film transistors, or active driven backplanes driven by micro ICs.
  • the backplane according to the embodiments of the present disclosure may include a backplane known in the art.
  • Driver backplanes of various types and structures may be included in the art.
  • FIG. 13 is a schematic diagram of the arrangement of the light-emitting units of the display substrate shown in FIG. 1
  • FIG. 14 is a schematic diagram of one light-emitting unit in the display substrate shown in FIG. 13
  • the display substrate 100 may include a base substrate 1 and a plurality of light emitting units 140 arranged in an array on the base substrate 1 .
  • the plurality of light-emitting units 140 are arranged in N rows and M columns, N is an integer greater than 0, and M is an integer greater than 0.
  • the number of light-emitting units 140 may be determined according to actual needs, such as the size of the display substrate and the required brightness. Although only three rows and five columns of light-emitting units 140 are shown in FIG. 13 , it should be understood that the number of light-emitting units 140 The number of 140 is not limited to this.
  • each row of light-emitting units 140 is arranged along the first direction X, and each column of light-emitting units 140 is arranged along the second direction Y.
  • Each light-emitting unit 140 includes a driving circuit 4, a plurality of light-emitting diodes 5 and a driving voltage terminal Vled.
  • the driving circuit 4 includes a first input terminal Di, a second input terminal Pwr, an output terminal OT and a common voltage terminal GND.
  • the first input terminal Di receives a first input signal, such as an address signal, for strobing the driving circuit 4 of the corresponding address.
  • the addresses of different driving circuits 4 may be the same or different.
  • the first input signal may be an 8-bit address signal, and the address to be transmitted can be obtained by parsing the address signal.
  • the second input terminal Pwr receives a second input signal, and the second input signal is, for example, a power line carrier communication signal.
  • the second input signal not only provides power to the driving circuit 4, but also transmits communication data to the driving circuit 4.
  • the communication data can be used to control the lighting duration of the corresponding light-emitting unit 140, thereby controlling its visual lighting brightness.
  • the output terminal OT can output different signals in different time periods, such as relay signals and driving signals respectively.
  • the relay signal is an address signal provided to other driving circuits 4 , that is, the first input terminal Di of the other driving circuit 4 receives the relay signal as the first input signal, thereby obtaining the address signal.
  • the driving signal may be a driving current, which is used to drive the light-emitting diode 5 to emit light.
  • the common voltage terminal GND receives a common voltage signal, such as a ground signal.
  • the driving circuit 4 is configured to output a relay signal through the output terminal OT in a first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr, and through the output terminal OT in the second period.
  • the output terminal OT provides driving signals to a plurality of light-emitting diodes 5 connected in series.
  • the output terminal OT outputs a relay signal, and the relay signal is provided to other drive circuits 4 so that other drive circuits 4 obtain address signals.
  • the output terminal OT outputs a driving signal, and the driving signal is provided to a plurality of light-emitting diodes 5 connected in series, so that the light-emitting diodes 5 emit light in the second period.
  • the first time period and the second time period are different time periods, and the first time period may be earlier than the second time period, for example.
  • the first time period can be continuously connected with the second time period, and the end time of the first time period is the start time of the second time period; or, there can be other time periods between the first time period and the second time period, and the other time periods can be used to implement
  • the other time periods may also be used only to separate the first time period and the second time period to avoid signals at the output terminal OT in the first time period and the second time period from interfering with each other.
  • each light-emitting diode 5 includes an anode (+) and a cathode (-) (or it can be called an anode and a cathode, or it can also be called a P electrode and an N electrode).
  • the anodes and cathodes of the plurality of light-emitting diodes 5 are They are connected in series from beginning to end, thereby forming a current path between the driving voltage terminal Vled and the output terminal OT.
  • the driving voltage terminal Vled provides a driving voltage, for example, a high voltage during the period when the light-emitting diode 5 needs to emit light (the second period), and a low voltage during other periods. Therefore, during the second period, the driving signal (for example, the driving current) sequentially flows from the driving voltage terminal Vled through the plurality of light-emitting diodes 5 and then flows into the output terminal OT of the driving circuit 4 .
  • the plurality of light-emitting diodes 5 emit light when the driving current flows through them. By controlling the duration of the driving current, the light-emitting duration of the light-emitting diodes 5 can be controlled, thereby controlling the visual brightness of the light.
  • the number of light-emitting diodes 5 in each light-emitting unit 140 is not limited, and can be any number such as 4, 5, 7, 8, etc., and is not limited to 6. .
  • the plurality of light-emitting diodes 5 can be arranged in any manner, for example, arranged according to a required pattern, and are not limited to a matrix arrangement.
  • the installation position of the driving circuit 4 is not limited and can be installed in any gap between the light-emitting diodes 5. This can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.
  • the driving circuit 4 in each light-emitting unit 140 can be led to the first conductive pad 3 located in the fan-out area through the signal line 150 , and then led to the outside through the bonding wire 9 and the second conductive pad 7 Drive circuit.
  • the driving circuit 4 may include a metal layer, for example, conductive traces may be formed in the metal layer. Since the current load of the display substrate is large, which can reach tens of milliamperes, it requires high resistance performance of the wiring. It is necessary to use metal with smaller resistance. Otherwise, the heat generated by the wiring will cause the temperature to be too high. Copper has superior conductive properties. Therefore, copper is used as the main body of conductive traces. Of course, conductive traces are not limited to copper, but can also be made of other metals, such as silver, aluminum, etc. As shown in FIG. 2 , the conductive traces include a copper layer 32 , and the thickness of the copper layer 32 can be adjusted according to the size of the current load.
  • the thickness of the copper layer 32 may be 1-30 microns, and in some embodiments, may be 2-6 microns, 2 microns, 4 microns, 5 microns, 6 microns, etc.
  • the copper layer 32 can be completed by electroplating.
  • FIG. 3 is a flow chart of a method of forming a copper layer using a subtractive method in the related art.
  • a buffer layer is first formed on the base substrate.
  • the buffer layer may include one or more insulating materials among silicon nitride, silicon oxide, and silicon oxynitride.
  • the stress direction of the formed copper layer is consistent with the On the contrary, this can offset the stress generated when forming the copper layer and avoid the base substrate from being broken.
  • a copper layer is formed using a subtractive method.
  • the so-called subtractive process is a method of selectively removing part of the copper foil on the surface of the copper-clad laminate to obtain a conductive pattern.
  • a thick copper layer can be formed on the buffer layer, and then a patterning process can be used to selectively remove part of the copper to form a wiring pattern.
  • the copper layer is processed through a gold chemical process to form a protective layer.
  • gold chemical process refers to a solderable surface coating process that chemically plating nickel on the bare copper surface and then chemically immerses gold.
  • FIG. 4 is a flowchart of a method of preparing a display substrate according to some exemplary embodiments of the present disclosure.
  • the method may form the metal layer through an additive process, and the method may include steps S410 to S470. It should be noted that some steps of the preparation method described below can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figure.
  • step S410 a copper seed layer is deposited on the base substrate.
  • step S420 a photoresist layer is formed on a side of the copper seed layer away from the base substrate.
  • step S430 the photoresist layer is patterned through a patterning process to form a photoresist pattern.
  • step S440 a copper layer is formed on the portion of the copper seed layer that is not covered by the photoresist pattern through an electroplating process.
  • step S450 portions of the photoresist pattern and the copper seed layer that are not covered by the metal layer are removed to form a metal layer including copper.
  • step S460 an anti-oxidation layer is formed on the side of the metal layer away from the base substrate.
  • a light-emitting diode is installed on the side of the anti-oxidation layer away from the base substrate, wherein the light-emitting diode includes at least one electrode, and at least one electrode of the light-emitting diode is electrically connected to the metal layer.
  • the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.
  • the thickness of the metal layer may be 5-30 microns. In some embodiments, the thickness may be 5-10 microns, 5 microns, 6 microns, 7 microns, 8 microns, etc.
  • a high-thickness metal layer can be formed on the LED display substrate through an additive process, which can save manufacturing costs.
  • FIG. 5A is a partial plan view of a display substrate schematically illustrating a display area and a mark area, according to some exemplary embodiments of the present disclosure.
  • Figure 5B is a partial enlarged view of the marked area shown in Figure 5A.
  • FIG. 5C is a partial enlarged view of the display area shown in FIG. 5A.
  • 6A is a schematic diagram of marks formed by a method of manufacturing a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 6B is a schematic diagram of marks formed by a preparation method of a display substrate in the related art.
  • the base substrate may include a display area AA and a mark area MA.
  • the display area AA may be an area used for display, and for example, the above-mentioned light emitting diodes may be located in the display area AA.
  • the mark area MA may be an area for forming the alignment mark MK.
  • step S440 forming a copper layer on the portion of the copper seed layer not covered by the photoresist pattern through an electroplating process may include: forming a first accompanying plating area 51 in the mark area MA; In the display area AA, a second plating area 81 is formed.
  • the first plating area 51 and the second plating area 81 each include a part of the copper layer.
  • the area ratio of the first accompanying plating area 51 to the mark area MA is greater than the area ratio of the second accompanying plating area 81 to the display area AA.
  • the area ratio of the first plating area 51 to the mark area MA represents the proportion of copper in the mark area MA
  • the area ratio of the second plating area 81 to the display area AA represents the proportion of copper in the display area AA.
  • proportion of copper In embodiments of the present disclosure, the copper proportion in the mark area MA is greater than the copper proportion in the display area AA.
  • the areas of the first and second plating areas 51 and 81 can be characterized by the area of an annular region, a shape enclosed by the outer contour of the first plating area 51 is a square, the shape enclosed by the outer contour of the clearance area 52 is a square, the shape enclosed by the outer contour of the second plating area 81 is a square, and the shape enclosed by the outer contour of the clearance area 82 is a square.
  • the copper proportion M1 in the marked area MA can be expressed by the following formula:
  • the copper proportion M2 in the display area AA can be expressed by the following formula:
  • the concentration of electric field lines may cause the electroplating rate to be faster.
  • the thickness of the metal exceeds the photoresist pattern. thickness, causing the resulting component to deform.
  • the method may further include: forming a mark MK through an electroplating process in an area surrounded by the first accompanying plating area 51 .
  • FIG. 7 is a partial cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing the positional relationship between the metal layer and the anti-oxidation layer.
  • Figures 8A and 8B are electron microscopy images of areas I and II in Figure 7, respectively.
  • FIG. 9A is a partial cross-sectional view of a display substrate according to other exemplary embodiments of the present disclosure, which schematically shows the positional relationship between the metal layer and the anti-oxidation layer.
  • Figure 9B is an electron microscope image of region III in Figure 9A.
  • FIG. 10A and 10B are respectively a partial cross-sectional view and a partial plan view of a display substrate according to further exemplary embodiments of the present disclosure, which schematically illustrate the positional relationship between the metal layer and the anti-oxidation layer.
  • FIG. 11 is a partial cross-sectional view of a display substrate according to other exemplary embodiments of the present disclosure, schematically showing the positional relationship between the metal layer and the anti-oxidation layer.
  • 12A and 12B are partial cross-sectional views of the display substrate at the first position and the second position respectively according to other exemplary embodiments of the present disclosure, which schematically illustrate the positional relationship between the metal layer and the anti-oxidation layer.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate may include: forming an OSP layer 61 on a side of the metal layer 32 away from the base substrate.
  • the metal layer 32 may be a high-thickness copper layer. After the high-thickness copper layer 32 is formed, the surface is pickled so that the surface micro-etching depth of the copper layer 32 is 1 to 2 microns. Then OSP soaking is performed, and OSP reacts with the surface of the copper layer. In this way, the outer surface of the copper layer 32 is covered with a layer of OSP.
  • the middle thickness of the OSP layer 61 is 0.2-0.4 microns, as shown in FIG. 8A.
  • Figure 8B there is a sloped part on the edge after the OSP process, and the OSP layer is thin, between 0 and 0.1 microns.
  • forming an anti-oxidation layer on a side of the metal layer away from the base substrate may include: forming a passivation layer PVX on a side of the metal layer 32 away from the base substrate. ; A first via hole VH1 is formed in the passivation layer, and the first via hole exposes at least a portion of the metal layer; the anti-oxidation layer is formed in the first via hole VH1.
  • the anti-oxidation layer includes an organic soldering film, that is, it is the OSP layer 61 .
  • the metal layer 32 may be a high-thickness copper layer. After the high-thickness copper layer 32 is formed, a passivation layer is coated on the outer surface of the copper layer 32 to achieve good coverage and reliability and meet high temperature and high humidity requirements.
  • the location where the first via VH1 is formed may be a bonding pad and a binding location. Then, the surface is pickled so that the exposed surface of the copper layer 32 is micro-etched to a depth of 1 to 2 microns. Then OSP soaking is performed, and OSP reacts with the surface of the copper layer. In this way, the exposed outer surface of the copper layer 32 is covered with a layer of OSP.
  • a passivation layer is first coated on the outer surface of the metal layer, which can prevent the OSP film layer from being thinner at the sloped edge after the OSP process, and is conducive to uniform coating of the metal layer, as shown in Figure 9B It shows that the middle thickness of the passivation layer PVX is basically equal to the edge thickness, that is, the passivation layer PVX can improve the uniform coating of the metal layer and improve the protection effect.
  • step S460 forming an anti-oxidation layer on a side of the metal layer 32 away from the base substrate may include: forming a layer surrounding the metal on a side of the metal layer 32 away from the base substrate. A nickel-containing alloy layer 71 is formed.
  • the nickel-containing alloy layer 71 has oxidation resistance and good welding performance.
  • the nickel-containing alloy layer 71 can be CuNi, with a Ni mass percentage of 10 to 30%; or, the nickel-containing alloy layer 71 can be NiV, with a Ni mass percentage of 50-97%; alternatively, the nickel-containing alloy layer 71 may be NiW, with the mass percentage of Ni being 50-97%, etc.
  • the thickness of the nickel-containing alloy layer 71 may be 500 to 4000 angstroms.
  • the pattern of the nickel-containing alloy layer 71 may be formed by photolithography.
  • step S460 forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes: forming an anti-oxidation layer on a side of the metal layer 32 away from the base substrate to surround the metal layer.
  • the nickel-containing alloy layer 71 is formed; a passivation layer PVX is formed on the side of the nickel-containing alloy layer 71 away from the base substrate; a second via VH2 is formed in the passivation layer PVX. Hole VH2 exposes at least a portion of the nickel-containing alloy layer 71 .
  • the metal layer 32 may be a high-thickness copper layer. After the high-thickness copper layer 32 is formed, the outer surface of the copper layer 32 is coated with a nickel-containing alloy layer 71 to achieve good coating properties and reliability and meet high temperature and high humidity requirements.
  • the position where the second via hole VH2 is formed may be a bonding pad and a binding position.
  • step S460 forming an anti-oxidation layer on a side of the metal layer 32 away from the base substrate includes: forming an anti-oxidation layer on a side of the metal layer 32 away from the base substrate.
  • Three via holes VH3 expose at least a portion of the metal layer 32 .
  • the orthographic projection of the third via hole VH3 on the base substrate is located within the orthographic projection of the opening 72 on the base substrate.
  • step S460 forming an anti-oxidation layer on the side of the metal layer away from the base substrate also includes: forming a fourth via VH4 in the passivation layer PVX at the binding position.
  • the via VH4 exposes at least a portion of the nickel-containing alloy layer 71 .
  • the pad area located in the display area AA can be well processed.
  • nickel-containing alloys and/or OSP are used as the anti-oxidation layer to solve the anti-oxidation problem of high-thickness copper, and a process route with good effect and low cost is obtained.
  • the gold solution is avoided, which greatly saves the manufacturing cost of the display substrate.
  • the display substrate includes: a base substrate 1; a metal layer located on the base substrate, the metal layer including a copper layer 32 having a first thickness;
  • the anti-oxidation layers 61 and 71 are located on the side of the metal layer 32 away from the base substrate, and the anti-oxidation layer has a second thickness;
  • the light-emitting diode 5 is located on the side of the anti-oxidation layer away from the base substrate.
  • the light-emitting diode 5 includes at least one electrode, and at least one electrode of the light-emitting diode is electrically connected to the metal layer, wherein the first thickness of the metal layer 32 is greater than the second thickness of the anti-oxidation layer 61/71 thickness.
  • the base substrate 1 includes a display area AA and a mark area MA.
  • the display substrate includes: a first plating area 51 located in the mark area MA; and a first plating area 51 located in the display area AA.
  • the first accompanying plating area 51 and the second accompanying plating area both include copper layers.
  • the area ratio of the first accompanying plating area 51 to the mark area MA is greater than the area ratio of the second accompanying plating area to the display area AA.
  • the display substrate further includes: a mark MK located in the marked area; and a clear area 52 located in the marked area.
  • the first accompanying plating area 51 surrounds the mark MK
  • the clear area 52 is located between the mark MK and the first accompanying plating area 51 and surrounds the mark.
  • the clearance area refers to the area set aside to prevent other graphics from affecting the alignment when the exposure machine is aligned. Only the graphics that need alignment can be retained under the alignment lens. This area can only have alignment graphics.
  • the orthographic projection of the first plating area 51 on the base substrate 1 is an annular area surrounding the mark MK.
  • the anti-oxidation layer 71 surrounds the metal layer 32 , and at least one electrode of the light-emitting diode is electrically connected to the metal layer through the anti-oxidation layer.
  • the display substrate further includes: a passivation layer PVX located on the anti-oxidation layer 71 away from the base substrate 1 ; and a first via VH1 located in the passivation layer.
  • the first via hole VH1 exposes at least a portion of the anti-oxidation layer 71 , and at least one electrode of the light emitting diode is electrically connected to the metal layer 32 through the first via hole 71 .
  • the anti-oxidation layer 71 surrounds the metal layer 32 .
  • the display substrate further includes: a passivation layer PVX located on the anti-oxidation layer 71 away from the base substrate; and a third via VH3 located in the passivation layer.
  • the third via hole VH3 is located at the pad position of the display area.
  • the third via hole VH3 exposes at least a part of the metal layer 32 .
  • At least one electrode of the light-emitting diode is connected to the pad through the third via hole.
  • the metal layers are electrically connected.
  • the anti-oxidation layer includes an opening 72 that exposes at least a portion of the metal layer 32 , and the orthographic projection of the third via VH3 on the base substrate is located where the opening 72 is. within the orthographic projection on the substrate.
  • the display substrate further includes: a fourth via hole VH4 located in the passivation layer PVX.
  • the fourth via VH4 is located in a binding position, and the fourth via VH4 exposes at least a portion of the anti-oxidation layer 71 , and at least one electrode of the light-emitting diode is connected to the anti-oxidation layer 71 through the exposed portion.
  • the metal layer is electrically connected.
  • the thickness of the copper layer 32 is greater than the thickness of the passivation layer PVX, and the thickness of the passivation layer PVX is greater than the thickness of the OSP layer 61 and the anti-oxidation layer 71 respectively.
  • the thickness of the oxide layer 71 is substantially the same.
  • the copper layer 32 has a high thickness, for example, it can be 5 to 10 microns; the thickness of the passivation layer PVX can be 3000 to 5000 angstroms. When the thickness of the passivation layer PVX is greater than 5000 angstroms, the stress will be greater.
  • the thickness of the passivation layer PVX is less than 2000 angstroms, the side coverage of the copper layer 32 by the passivation layer PVX will be affected; the thicknesses of the OSP layer 61 and the anti-oxidation layer 71 are basically equal and can be 2000 to 4000 angstroms.
  • Some exemplary embodiments of the present disclosure also provide a display device.
  • 11 and 12 are schematic diagrams of a display device according to some exemplary embodiments of the present disclosure. Referring to FIGS. 11 and 12 , the display device includes at least two display substrates as described above.
  • the display device has all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to the above description of the display substrate and will not be described again here.
  • the terms “substantially,” “approximately,” “approximately,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to explain what would be recognized by one of ordinary skill in the art. Inherent bias in measured or calculated values. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the stated value and means that for this purpose Specific values are within acceptable deviations as determined by one of ordinary skill in the art. For example, "about” may mean within one or more standard deviations, or within ⁇ 10% or ⁇ 5% of the stated value.

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Abstract

一种显示基板（100）及其制备方法和显示装置。显示基板（100）包括：衬底基板（1）；位于衬底基板（1）上的金属层（32），金属层（32）包括具有第一厚度的铜层；位于金属层（32）远离衬底基板（1）一侧的抗氧化层（61/71），抗氧化层（61/71）具有第二厚度；位于抗氧化层（61/71）远离衬底基板（1）一侧的发光二极管（5），发光二极管（5）包括至少一个电极，发光二极管（5）的至少一个电极与金属层（32）电连接，其中，金属层（32）的第一厚度大于抗氧化层（61/71）的第二厚度。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
发光二极管(Light Emitting Diode，英文缩写为LED)技术发展了近三十年，其应用范围不断扩展，例如，其可以应用于显示领域，用作显示装置的背光源或用作LED显示屏。随着技术的发展，次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)显示技术和微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)显示技术逐渐成为显示装置的一个热点。LED具有自发光、广视角、快速响应、结构简单、寿命长等优点，而且，Mini LED/Micro LED显示屏可以通过拼接方式实现大尺寸显示，所以，它们具有较好的市场前景。目前，Mini LED/Micro LED显示装置的结构及其制造工艺，是研发人员关注的重要课题之一。
在本部分中公开的以上信息仅用于对本公开的发明构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
为了解决上述问题的至少一个方面，本公开实施例提供一种显示基板及其制备方法和显示装置。
在一个方面，提供一种显示基板，包括：衬底基板；位于所述衬底基板上的金属层，所述金属层包括具有第一厚度的铜层；位于所述金属层远离所述衬底基板一侧的抗氧化层，所述抗氧化层具有第二厚度；位于所述抗氧化层远离所述衬底基板一侧的发光二极管，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，其中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。
根据一些示例性的实施例，所述抗氧化层包括含镍合金。
根据一些示例性的实施例，所述衬底基板包括显示区域和标记区域，所述显示基板包括：位于所述标记区域的第一陪镀区；和位于所述显示区域中的第二陪镀区；所 述第一陪镀区和所述第二陪镀区均包括铜层；所述第一陪镀区与所述标记区域的面积比大于所述第二陪镀区与所述显示区域的面积比。
根据一些示例性的实施例，所述显示基板还包括：位于所述标记区域中的标记；和位于所述标记区域中的净空区，所述第一陪镀区包围所述标记，所述净空区位于所述标记与所述第一陪镀区之间且包围所述标记。
根据一些示例性的实施例，所述第一陪镀区在所述衬底基板上的正投影为包围所述标记的环形区域。
根据一些示例性的实施例，所述抗氧化层包围所述金属层，所述发光二极管的至少一个电极通过所述抗氧化层与所述金属层电连接。
根据一些示例性的实施例，所述显示基板还包括：位于所述抗氧化层远离所述衬底基板的钝化层；和位于所述钝化层中的第一过孔；所述第一过孔暴露所述抗氧化层的至少一部分，所述发光二极管的至少一个电极通过所述第一过孔与所述金属层电连接。
根据一些示例性的实施例，所述抗氧化层包围所述金属层。
根据一些示例性的实施例，所述显示基板还包括：位于所述抗氧化层远离所述衬底基板的钝化层；和位于所述钝化层中的第三过孔；所述第三过孔位于所述显示区域的焊盘位置，所述第三过孔暴露所述金属层的至少一部分，所述发光二极管的至少一个电极通过所述第三过孔与所述金属层电连接。
根据一些示例性的实施例，所述显示基板还包括：位于所述钝化层中的第四过孔；所述第四过孔位于绑定位置，所述第四过孔暴露所述抗氧化层的至少一部分，所述发光二极管的至少一个电极通过暴露的所述抗氧化层的一部分与所述金属层电连接。
根据一些示例性的实施例，所述抗氧化层包括开口部，所述开口部暴露所述金属层的至少一部分，所述第三过孔在所述衬底基板上的正投影位于所述开口部在所述衬底基板上的正投影内。
在另一方面，提供一种显示基板的制备方法，包括：
在衬底基板上沉积铜种子层；
在所述铜种子层远离所述衬底基板的一侧形成光刻胶层；
通过构图工艺对所述光刻胶层进行构图，形成光刻胶图案；
通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层；
去除所述光刻胶图案和所述铜种子层的未被所述金属层覆盖的部分，以形成包括铜的金属层；
在所述金属层远离所述衬底基板的一侧形成抗氧化层；
在所述抗氧化层远离所述衬底基板一侧安装发光二极管，其中，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，
其中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。
根据一些示例性的实施例，所述衬底基板包括显示区域和标记区域，
所述通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层包括：
在所述标记区域，形成第一陪镀区；
在所述显示区域，形成第二陪镀区；
其中，所述第一陪镀区和所述第二陪镀区分别包括铜层的一部分；
所述第一陪镀区与所述标记区域的面积比大于所述第二陪镀区与所述显示区域的面积比。
根据一些示例性的实施例，所述方法还包括：在所述第一陪镀区包围的区域中，通过电镀工艺形成标记。
根据一些示例性的实施例，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
在所述金属层远离所述衬底基板的一侧形成钝化层；
在所述钝化层中形成第一过孔，所述第一过孔暴露所述金属层的至少一部分；
在所述第一过孔中形成所述抗氧化层，
其中，所述抗氧化层包括有机保焊膜。
根据一些示例性的实施例，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层。
根据一些示例性的实施例，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层；
在所述含镍合金层远离所述衬底基板的一侧形成钝化层；
在所述钝化层中形成第二过孔，所述第二过孔暴露所述含镍合金层的至少一部分。
根据一些示例性的实施例，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层；
在所述显示区域的焊盘位置，在所述含镍合金层中形成开口部，所述开口部暴露所述金属层的至少一部分，
在所述含镍合金层远离所述衬底基板的一侧形成钝化层；
在所述显示区域的焊盘位置，在所述钝化层中形成第三过孔，所述第三过孔暴露所述金属层的至少一部分，
其中，所述第三过孔在所述衬底基板上的正投影位于所述开口部在所述衬底基板上的正投影内。
根据一些示例性的实施例，在所述金属层远离所述衬底基板的一侧形成抗氧化层还包括：在绑定位置，在所述钝化层中形成第四过孔，所述第四过孔暴露所述含镍合金层的至少一部分。
在又一方面，提供一种显示装置，包括如上所述的显示基板。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1是根据本公开的一些示例性实施例的显示基板的平面示意图，需要说明的是，为了说明，图1示出了显示基板和与其绑定的另一基板的展开状态。
图2是根据本公开的一些示例性实施例的显示基板沿图1中的线AA’截取的截面图。
图3是相关技术中利用减成法形成铜层的方法的流程图。
图4是根据本公开的一些示例性实施例的显示基板的制备方法的流程图。
图5A是根据本公开的一些示例性实施例的显示基板的局部平面示意图，其示意性示出了显示区域和标记区域。
图5B是图5A中所示的标记区域的局部放大图。
图5C是图5A中所示的显示区域的局部放大图。
图6A是根据本公开的一些示例性实施例的显示基板的制备方法形成的标记的示意图。
图6B是相关技术中的显示基板的制备方法形成的标记的示意图。
图7是根据本公开的一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。
图8A和图8B分别是图7中的区域I、II的电镜图。
图9A是根据本公开的另一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。
图9B是图9A中的区域III的电镜图。
图10A和图10B分别是根据本公开的又一些示例性实施例的显示基板的部分截面图和部分平面图，其示意性示出了金属层与抗氧化层的位置关系。
图11是根据本公开的另一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。
图12A和图12B分别是根据本公开的另一些示例性实施例的显示基板在第一位置和第二位置处的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。
图13为图1所示的显示基板的发光单元的排列示意图。
图14为图13所示的显示基板中一个发光单元的示意图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
在下面的描述中，出于解释的目的，阐述了许多具体细节以提供对各种示例性实施例的全面的理解。然而，明显的是，在不具有这些具体细节或者具有一个或多个等同布置的情况下，可以实施各种示例性实施例。在其它情况下，以框图形式示出了公知的结构和装置，以避免使各种示例性实施例不必要地模糊。此外，各种示例性实施例可以是不同的，但不必是排他的。例如，在不脱离发明构思的情况下，可以在另一示例性实施例中使用或实施示例性实施例的具体形状、配置和特性。
在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。当可以不同地实施示例性实施例时，可以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者以与描述的顺序相反的顺序执行两个连续描述的工艺。此外，同样的附图标记表示同样的元件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XY、YZ和XZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似地，第二元件可以被命名为第一元件。
在本文中，无机发光二极管是指利用无机材料制成的发光元件，其中，LED表示有别于OLED的无机发光元件。具体地，无机发光元件可以包括次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)和微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)。其中，微型发光二极管(即Micro LED)指的是晶粒尺寸在100微米以下的超小型发光二极管，次毫米发光二极管(即Mini LED)是指晶粒尺寸在Micro LED与传统LED之间的小型发光二极管，例如，Mini LED的晶粒尺寸可以在100～300微米之间，Micro LED的晶粒尺寸可以在10～100微米之间。
引线键合(Wire Bonding)是一种利用热、压力或超声波能量使金属键合引线与基板焊盘紧密焊合的工艺。例如，在IC封装中，可以利用引线键合，将半导体芯片焊区与微电子封装的I/O键合引线或基板上的金属布线焊区用金属细丝连接起来。引线键合的原理是采用加热、加压或超声波等方式破坏被焊表面的氧化层和污染，产生塑性变形，使得金属键合引线与被焊面亲密接触，达到原子间的引力范围并导致界面间原 子扩散而形成焊合点。
OSP是Organic Solde-rability Preservatives的简称，可以称为有机保焊膜，又称护铜剂。OSP是在洁净的裸铜表面上，以化学的方法长出一层有机皮膜。这层膜具有防氧化，耐热冲击，耐湿性，用以保护铜表面于常态环境中不再继续生锈(氧化或硫化等)，在后续的焊接高温中，此种保护膜可以容易地被助焊剂迅速清除，从而可使露出的干净铜表面得以在极短的时间内与熔融焊锡立即结合成为牢固的焊点。
本公开的一些示例性实施例提供了一种显示基板及其制备方法和包括所述显示基板的显示装置。例如，本公开的一些实施例提供了一种显示基板，包括：提衬底基板；位于所述衬底基板上的金属层，所述金属层包括具有第一厚度的铜层；位于所述金属层远离所述衬底基板一侧的抗氧化层，所述抗氧化层具有第二厚度；位于所述抗氧化层远离所述衬底基板一侧的发光二极管，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，其中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。在本公开的实施例中，可以实现具有高厚铜层的显示基板，通过抗氧化层的膜层设计，可以防止铜层被氧化。
图1是根据本公开的一些示例性实施例的显示基板的平面示意图，需要说明的是，为了说明，图1示出了显示基板和与其绑定的另一基板的展开状态。图2是根据本公开的一些示例性实施例的显示基板沿图1中的线AA’截取的截面图。
参照图1和图2，显示基板100可以包括衬底基板1以及设置在衬底基板1上的多个第一电极2和多个第一导电垫3。多个第一导电垫3位于所述显示基板100的边缘位置。例如，多个第一导电垫3位于所述显示基板100的扇出区(即fan-out区)，用于将位于所述显示基板100上的信号线(例如，图1中示意性示出了部分信号线150)电连接至外部驱动电路。
例如，衬底基板1的材料可以包括但不限于玻璃，石英，塑料，硅，聚酰亚胺等。第一电极2和第一导电垫3可以为柱状结构。第一电极2和第一导电垫3的材料可以包括导电材料，例如金属材料等，具体地，可以为金、银、铜、铝、钼、金合金、银合金、铜合金、铝合金、钼合金等中选择的至少一种或者至少两种的组合，本公开的实施例对此不作限制。
例如，所述显示基板100还可以包括与多个第一电极2电连接的驱动电路4，该驱动电路4设置在衬底基板1上。该驱动电路4可以用于向位于多个第一电极2上的 发光二极管芯片5提供电信号，控制其发光亮度。例如，在一些示例中，该驱动电路4可以为与每个发光二极管芯片一一对应连接的多个像素驱动电路，或者是与每个发光二极管芯片一一对应连接的多个微型集成电路芯片等结构，可以控制每个发光二极管芯片发出不同的亮度灰阶。需要说明的是，显示基板100上的驱动电路4的具体电路结构可以根据实际需要进行设置，本公开的实施例对此不作限制。
在具体制备方法中，可以将多个发光二极管5转移并绑定至所述显示基板100上。
参照图1和图2，发光二极管5包括N电极5N和P电极5P，发光二极管5的N电极和P电极分别连接到对应的第一电极2，而多个第一导电垫3的表面裸露在外。
参照图1，多个发光二极管沿第一方向X和第二方向Y成阵列地排列。例如，第一方向X为行方向且第二方向Y为列方向。当然，本公开的实施例不限于此，第一方向和第二方向可以为任意的方向，只需使第一方向和第二方向交叉即可。并且，多个发光二极管也不限于沿直线排列，也可以沿曲线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
多个第一导电垫3沿所述第一方向X排列在所述显示基板100的边缘位置，即多个第一导电垫3构成第一导电垫行。例如，多个第一导电垫3沿所述第一方向X等间距地布置。
例如，所述发光二极管可以包括微型发光二极管(Micro-LED)或次毫米发光二极管(Mini-LED)。
例如，第二基板200可以为电路板，例如，PCB(Printed Circuit Board，即印刷电路板)、FPC(Flexible Printed Circuit，即柔性电路板)或COF(Chip On Film，即膜上芯片)等。
第二基板200可以包括多个第二导电垫7。例如，多个第二导电垫7可以沿第一方向X排列，即，多个第二导电垫7构成第二导电垫行。例如，多个第二导电垫7可以与多个第一导电垫3一一对应。即，第二导电垫7的排列周期与第一导电垫3的排列周期相同。
例如，键合引线9电连接第一导电垫3与第二导电垫7。键合引线9的一端连接第一导电垫3，另一端连接第二导电垫7。即，键合引线9的一端焊接在第一导电垫3上，另一端焊接在第二导电垫7上。焊接在第一导电垫3上的焊点称为第一焊点911，焊接在第二导电垫7上的焊点称为第二焊点921。例如，键合引线9可以采用Cu、Al、 Au、Ag等金属或其合金。
当然，第二基板200还可以包括外部驱动电路，例如，集成电路芯片，但本公开的实施例不局限于此。
所述显示基板100可以为用于发光二极管显示面板的背板。所述显示基板100包括但不限于下面的背板：被动驱动背板，或者包含薄膜晶体管的有源驱动背板，或者由微型IC驱动的有源驱动背板。
下面，将以一个具体的示例来说明所述显示基板100，但是，下面的具体示例不应视为对本公开的实施例的限制，根据本公开实施例的背板可以包括本领域中已知的各种类型和各种结构的驱动背板。
图13为图1所示的显示基板的发光单元的排列示意图，图14为图13所示的显示基板中一个发光单元的示意图。如图1、图13和图14所示，显示基板100可以包括衬底基板1和在衬底基板1上阵列排布的多个发光单元140。例如，多个发光单元140排列为N行M列，N为大于0的整数，M为大于0的整数。例如，发光单元140的数量可以根据实际需求而定，例如根据显示基板的尺寸和所需要的亮度而定，虽然图13中仅示出了3行5列发光单元140，但是应当理解，发光单元140的数量不限于此。
例如，每一行发光单元140沿第一方向X排列，每一列发光单元140沿第二方向Y排列。
每个发光单元140包括驱动电路4、多个发光二极管5和驱动电压端Vled。
驱动电路4包括第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND。第一输入端Di接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动电路4。例如，不同的驱动电路4的地址可以相同或不同。第一输入信号可以为8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入端Pwr接收第二输入信号，第二输入信号例如为电力线载波通信信号。例如，第二输入信号不仅为驱动电路4提供电能，还向驱动电路4传输通信数据，该通信数据可用于控制相应的发光单元140的发光时长，进而控制其视觉上的发光亮度。输出端OT可在不同的时段内分别输出不同的信号，例如分别输出中继信号和驱动信号。例如，中继信号为提供给其他驱动电路4的地址信号，也即是，其他驱动电路4的第一输入端Di接收该中继信号以作为第一输入信号，从而获取地址信号。例如，驱动信号可以为驱动电流，用于驱动发光二极管5发光。公共电压端GND接收公共电压信号，例如接 地信号。
驱动电路4配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT提供驱动信号至依次串联的多个发光二极管5。在第一时段内，输出端OT输出中继信号，该中继信号被提供给其他驱动电路4以使其他驱动电路4获得地址信号。在第二时段内，输出端OT输出驱动信号，该驱动信号被提供给依次串联的多个发光二极管5，使得发光二极管5在第二时段内发光。例如，第一时段与第二时段为不同的时段，第一时段例如可以早于第二时段。第一时段可以与第二时段连续相接，第一时段的结束时刻即为第二时段的开始时刻；或者，第一时段与第二时段中间还可以有其他时段，该其他时段可以用于实现其他需要的功能，该其他时段也可以仅用于使第一时段和第二时段间隔开，以避免输出端OT在第一时段和第二时段的信号彼此干扰。
例如，如图14所示，多个发光二极管5依次串联，并且串联连接在驱动电压端Vled和输出端OT之间。例如，每个发光二极管5包括正极(+)和负极(-)(或者，可称为阳极和阴极，或者，也可称为P电极和N电极)，多个发光二极管5的正极和负极依序首尾串联，从而在驱动电压端Vled和输出端OT之间形成电流路径。驱动电压端Vled提供驱动电压，例如在需要使发光二极管5发光的时段(第二时段)内为高电压，而在其他时段内为低电压。由此，在第二时段内，驱动信号(例如驱动电流)从驱动电压端Vled依次流经多个发光二极管5，然后流入驱动电路4的输出端OT。多个发光二极管5在驱动电流流过时发光，通过控制驱动电流的持续时间，可以控制发光二极管5的发光时长，从而控制视觉上的发光亮度。
需要说明的是，本公开的实施例中，每个发光单元140中的发光二极管5的数量不受限制，可以为4个、5个、7个、8个等任意数量，而不限于6个。多个发光二极管5可以采用任意的排列方式，例如按照所需要的图案排列，而不限于矩阵排列方式。驱动电路4的设置位置不受限制，可以设置在发光二极管5彼此之间的任意空隙中，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，返回参照图1，各个发光单元140中的驱动电路4可以通过信号线150引至位于扇出区的第一导电垫3，然后通过键合引线9、第二导电垫7被引至外部驱动电路。
在本公开的实施例中，所述驱动电路4可以包括金属层，例如，在该金属层中可以形成导电走线。由于显示基板的电流负载大，可以达到几十毫安，对走线的电阻性能要求高，需要采用电阻较小的金属，否则走线发热量大会导致温度过高；而铜的导电性能优越，因此，采用铜来作为导电走线的主体。当然，导电走线并不局限于采用铜，还可以采用其他金属，比如银、铝等。如图2所示，导电走线包括铜层32，根据电流负载的大小可以调节铜层32的厚度，电流负载越大，则铜层32的厚度越大。铜层32的厚度可以为1～30微米，在一些实施例中，具体可以为2～6微米，2微米，4微米，5微米，6微米等。铜层32可以通过电镀方式完成。
在相关技术中，通常采用减成法来形成铜层32。图3是相关技术中利用减成法形成铜层的方法的流程图。在该方法中，首先在衬底基板上形成缓冲层，例如，该缓冲层可以包括氮化硅、氧化硅和氮氧化硅中的一种或多种绝缘材料，与形成的铜层的应力方向相反，这样可以抵消形成铜层时所产生的应力，避免衬底基板破碎。然后，利用减成法形成铜层。所谓减成法工艺，是在覆铜箔层压板表面上，有选择性除去部分铜箔来获得导电图形的方法。例如，可以在缓冲层上形成厚铜层，然后利用构图工艺有选择性除去部分铜以形成走线图案。接着，通过化金工艺处理所述铜层，以形成保护层。所谓化金工艺，是指在裸铜面上化学镀镍，然后化学浸金的一种可焊性表面涂覆工艺。
图4是根据本公开的一些示例性实施例的显示基板的制备方法的流程图。该方法可以通过加成法工艺形成金属层，所述方法可以包括步骤S410～S470。需要说明的是，下面描述的制备方法的一些步骤可以单独执行或组合执行，以及可以并行执行或顺序执行，并不局限于图中所示的具体操作顺序。
在步骤S410中，在衬底基板上沉积铜种子层。
在步骤S420中，在所述铜种子层远离所述衬底基板的一侧形成光刻胶层。
在步骤S430中，通过构图工艺对所述光刻胶层进行构图，形成光刻胶图案。
在步骤S440中，通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层。
在步骤S450中，去除所述光刻胶图案和所述铜种子层的未被所述金属层覆盖的部分，以形成包括铜的金属层。
在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层。
在步骤S470中，在所述抗氧化层远离所述衬底基板一侧安装发光二极管，其中，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接。
在本公开的实施例中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。例如，所述金属层的厚度可以为5～30微米，在一些实施例中，具体可以为5～10微米，5微米，6微米，7微米，8微米等。
在本公开的实施例中，可以通过加成法工在LED显示基板上形成高厚度的金属层，可以节约制造成本。
图5A是根据本公开的一些示例性实施例的显示基板的局部平面示意图，其示意性示出了显示区域和标记区域。图5B是图5A中所示的标记区域的局部放大图。图5C是图5A中所示的显示区域的局部放大图。图6A是根据本公开的一些示例性实施例的显示基板的制备方法形成的标记的示意图。图6B是相关技术中的显示基板的制备方法形成的标记的示意图。
结合参照图1至图5C，所述衬底基板可以包括显示区域AA和标记区域MA。例如，显示区域AA可以是用于显示的区域，例如，上述发光二极管可以位于该显示区域AA中。标记区域MA可以是用于形成对位标记MK的区域。
在步骤S440中，所述通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层可以包括：在所述标记区域MA，形成第一陪镀区51；在所述显示区域AA，形成第二陪镀区81。
在本公开的实施例中，所述第一陪镀区51和所述第二陪镀区81分别包括铜层的一部分。所述第一陪镀区51与所述标记区域MA的面积比大于所述第二陪镀区81与所述显示区域AA的面积比。在本公开的实施例中，通过对显示区域和标记区域进行不同的陪镀区设置，达到很好的电镀均一性效果。
所述第一陪镀区51与所述标记区域MA的面积之比表示标记区域MA中的铜占比，所述第二陪镀区81与所述显示区域AA的面积比表示显示区域AA中的铜占比。在本公开的实施例中，标记区域MA中的铜占比大于显示区域AA中的铜占比。
在图5B和图5C所示的示例性实施例中，第一陪镀区51和第二陪镀区81的面积可以用环形区域的面积表征，第一陪镀区51的外轮廓包围的形状为正方形，净空区52的外轮廓包围的形状为正方形，第二陪镀区81的外轮廓包围的形状为正方形，净 空区82的外轮廓包围的形状为正方形。
相应地，标记区域MA中的铜占比M1可以用下面的公式表示：
，
显示区域AA中的铜占比M2可以用下面的公式表示：
。
本领域技术人员应理解，在电镀工艺中，在无陪镀区设计的情况下，电场线集中可能造成电镀速率较快，结果，在形成所述金属层时，金属的厚度超出光刻胶图案的厚度，从而导致形成的部件变形。
通过图6B可以看出，在标记区域不设置陪镀区的情况下，形成的标记会产生变形，从而对对位精度产生影响；通过图6A可以看出，在标记区域中设置陪镀区的情况下，形成的标记较准确，有利于提高对位精度。
参照图5B和图6A，所述方法还可以包括：在所述第一陪镀区51包围的区域中，通过电镀工艺形成标记MK。
图7是根据本公开的一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。图8A和图8B分别是图7中的区域I、II的电镜图。图9A是根据本公开的另一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。图9B是图9A中的区域III的电镜图。图10A和图10B分别是根据本公开的又一些示例性实施例的显示基板的部分截面图和部分平面图，其示意性示出了金属层与抗氧化层的位置关系。图11是根据本公开的另一些示例性实施例的显示基板的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。图12A和图12B分别是根据本公开的另一些示例性实施例的显示基板在第一位置和第二位置处的部分截面图，其示意性示出了金属层与抗氧化层的位置关系。
参照图7，在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层可以包括：在所述金属层32远离所述衬底基板的一侧形成OSP层61。
例如，所述金属层32可以为高厚度铜层。在形成该高厚度铜层32之后，进行表面酸洗，使得铜层32的表面微蚀深度1～2微米。然后进行OSP浸泡，OSP与铜层表面发生反应。以此方式，在铜层32的外表面包覆一层OSP。例如，OSP层61的中间厚度在0.2～0.4微米，如图8A所示。如图8B所示，在OSP工艺后边缘有坡度部分，OSP层较薄，在0～0.1微米之间。
参照图9A，在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层可以包括：在所述金属层32远离所述衬底基板的一侧形成钝化层PVX；在所述钝化层中形成第一过孔VH1，所述第一过孔暴露所述金属层的至少一部分；在所述第一过孔VH1中形成所述抗氧化层。例如，所述抗氧化层包括有机保焊膜，即它为OSP层61。
例如，所述金属层32可以为高厚度铜层。在形成该高厚度铜层32之后，在铜层32外表面包覆钝化层，以达到良好的包覆性和信赖性，满足高温高湿要求。所述第一过孔VH1形成的位置可以是焊盘和绑定位置。然后，进行表面酸洗，使得铜层32的被暴露出的表面微蚀深度1～2微米。然后进行OSP浸泡，OSP与铜层表面发生反应。以此方式，在铜层32的被暴露出的外表面包覆一层OSP。
在该实施例中，先在金属层的外表面包覆一层钝化层，可以防止OSP工艺后边缘有坡度部分OSP膜层较薄，有利于对金属层的均匀包覆，如图9B所示，钝化层PVX的中间厚度与边缘厚度基本相等，即钝化层PVX可以提高对金属层的均匀包覆，提高保护效果。
参照图10A，在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层可以包括：在所述金属层32远离所述衬底基板的一侧形成包围所述金属层的含镍合金层71。
含镍合金层71具有抗氧化能力和良好的焊接性能，例如，含镍合金层71可以为CuNi，Ni质量百分比为10～30％；或者，含镍合金层71可以为NiV，Ni质量百分比为50～97％；或者，含镍合金层71可以为NiW，Ni质量百分比为50～97％等。
例如，含镍合金层71的厚度可以为500～4000埃。可以通过光刻形成含镍合金层71的图案。
参照图11，在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：在所述金属层32远离所述衬底基板的一侧形成包围所述金属层的含镍合金层71；在所述含镍合金层71远离所述衬底基板的一侧形成钝化层PVX；在所述钝化层PVX中形成第二过孔VH2，所述第二过孔VH2暴露所述含镍合金层71的至少一部分。
例如，所述金属层32可以为高厚度铜层。在形成该高厚度铜层32之后，在铜层32外表面包覆含镍合金层71，以达到良好的包覆性和信赖性，满足高温高湿要求。所述第二过孔VH2形成的位置可以是焊盘和绑定位置。
参照图12A和图12B，在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：在所述金属层32远离所述衬底基板的一侧形成包围所述金属层的含镍合金层71；在所述显示区域AA的焊盘位置，在所述含镍合金层中形成开口部72，所述开口部72暴露所述金属层32的至少一部分；在所述含镍合金层71远离所述衬底基板的一侧形成钝化层PVX；在所述显示区域的焊盘位置，在所述钝化层PVX中形成第三过孔VH3，所述第三过孔VH3暴露所述金属层32的至少一部分。
在该实施例中，所述第三过孔VH3在所述衬底基板上的正投影位于所述开口部72在所述衬底基板上的正投影内。
在步骤S460中，在所述金属层远离所述衬底基板的一侧形成抗氧化层还包括：在绑定位置，在所述钝化层PVX中形成第四过孔VH4，所述第四过孔VH4暴露所述含镍合金层71的至少一部分。
在该实施例中，由于OSP工艺过程中使用的化合物仅与铜发生反应来实现OSP层，不与含镍合金层71发生反应，因此，可以对位于显示区域AA中的焊盘区进行良好的保护。在绑定区域中，不形成有机保护层，防止了绑定区域与外接电路的接触不良或接触电阻变大。
在本公开的实施例中，采用含镍合金和/或OSP作为抗氧化层，解决高厚度铜防氧化问题，得出一种效果好且成本低的工艺路线。通过含镍合金和/或OSP的保护方式，避免了化金方案，极大地节约了显示基板的制造成本。
在本公开实施例提供的上述制备方法的基础上，本公开的一些示例性实施例还提供一种显示基板。结合参照图1、图2、图9A-图12B，所述显示基板包括：衬底基板1；位于所述衬底基板上的金属层，所述金属层包括具有第一厚度的铜层32；位于所述金属层32远离所述衬底基板一侧的抗氧化层61、71，所述抗氧化层具有第二厚度；位于所述抗氧化层远离所述衬底基板一侧的发光二极管5，所述发光二极管5包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，其中，所述金属层32的第一厚度大于所述抗氧化层61/71的第二厚度。
参照图5A、图5B，所述衬底基板1包括显示区域AA和标记区域MA，所述显示基板包括：位于所述标记区域MA的第一陪镀区51；和位于所述显示区域AA中的第二陪镀区。所述第一陪镀区51和所述第二陪镀区均包括铜层。所述第一陪镀区51与所述标记区域MA的面积比大于所述第二陪镀区与所述显示区域AA的面积比。
具体地，所述显示基板还包括：位于所述标记区域中的标记MK；和位于所述标记区域中的净空区52。所述第一陪镀区51包围所述标记MK，所述净空区52位于所述标记MK与所述第一陪镀区51之间且包围所述标记。
需要说明的是，净空区是指在曝光机对位时为防止其他图形对对位影响，在对位镜头下只能保留需要对位图形而留出区域，该区域只能有对位图形。
例如，如图5B所示，所述第一陪镀区51在所述衬底基板1上的正投影为包围所述标记MK的环形区域。
如图10A所示，所述抗氧化层71包围所述金属层32，所述发光二极管的至少一个电极通过所述抗氧化层与所述金属层电连接。
如图11所示，所述显示基板还包括：位于所述抗氧化层71远离所述衬底基板1的钝化层PVX；和位于所述钝化层中的第一过孔VH1。所述第一过孔VH1暴露所述抗氧化层71的至少一部分，所述发光二极管的至少一个电极通过所述第一过孔71与所述金属层32电连接。
例如，所述抗氧化层71包围所述金属层32。
如图12A所示，所述显示基板还包括：位于所述抗氧化层71远离所述衬底基板的钝化层PVX；和位于所述钝化层中的第三过孔VH3。所述第三过孔VH3位于所述显示区域的焊盘位置，所述第三过孔VH3暴露所述金属层32的至少一部分，所述发光二极管的至少一个电极通过所述第三过孔与所述金属层电连接。
所述抗氧化层包括开口部72，所述开口部72暴露所述金属层32的至少一部分，所述第三过孔VH3在所述衬底基板上的正投影位于所述开口部72在所述衬底基板上的正投影内。
如图12B所示，所述显示基板还包括：位于所述钝化层PVX中的第四过孔VH4。所述第四过孔VH4位于绑定位置，所述第四过孔VH4暴露所述抗氧化层71的至少一部分，所述发光二极管的至少一个电极通过暴露的所述抗氧化层的一部分与所述金属层电连接。
需要说明的是，在本公开的实施例中，铜层32的厚度大于钝化层PVX的厚度，钝化层PVX的厚度大于OSP层61和抗氧化层71各自的厚度，OSP层61和抗氧化层71的厚度基本相等。例如，铜层32具有高厚度，例如可以为5～10微米；钝化层PVX的厚度可以为3000～5000埃，当钝化层PVX的厚度大于5000埃时，其应力会较大， 当钝化层PVX的厚度小于2000埃时，钝化层PVX对铜层32的侧面包覆性会受影响；OSP层61和抗氧化层71的厚度基本相等，可以为2000～4000埃。
本公开的一些示例性实施例还提供一种显示装置。图11和图12是根据本公开的一些示例性实施例的显示装置的示意图。参照图11和图12，所述显示装置包括至少2个如上所述的显示基板。
应该理解，根据本公开的一些示例性实施例的显示装置具有上述显示基板的所有特点和优点，这些特点和优点可以参照上文针对显示基板的描述，在此不再赘述。
如这里所使用的，术语“基本上”、“大约”、“近似”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±10％或±5％内。
虽然根据本公开的总体发明构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不远离本公开的总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种显示基板，其特征在于，包括：
    衬底基板；
    位于所述衬底基板上的金属层，所述金属层包括具有第一厚度的铜层；
    位于所述金属层远离所述衬底基板一侧的抗氧化层，所述抗氧化层具有第二厚度；
    位于所述抗氧化层远离所述衬底基板一侧的发光二极管，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，
    其中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。
  2. 根据权利要求1所述的显示基板，其中，所述抗氧化层包括含镍合金。
  3. 根据权利要求1所述的显示基板，其中，所述衬底基板包括显示区域和标记区域，所述显示基板包括：位于所述标记区域的第一陪镀区；和位于所述显示区域中的第二陪镀区；
    所述第一陪镀区和所述第二陪镀区均包括铜层；
    所述第一陪镀区与所述标记区域的面积比大于所述第二陪镀区与所述显示区域的面积比。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括：位于所述标记区域中的标记；和位于所述标记区域中的净空区，
    所述第一陪镀区包围所述标记，所述净空区位于所述标记与所述第一陪镀区之间且包围所述标记。
  5. 根据权利要求4所述的显示基板，其中，所述第一陪镀区在所述衬底基板上的正投影为包围所述标记的环形区域。
  6. 根据权利要求1或2所述的显示基板，其中，所述抗氧化层包围所述金属层，所述发光二极管的至少一个电极通过所述抗氧化层与所述金属层电连接。
  7. 根据权利要求1或2所述的显示基板，其中，所述显示基板还包括：位于所述抗氧化层远离所述衬底基板的钝化层；和位于所述钝化层中的第一过孔；
    所述第一过孔暴露所述抗氧化层的至少一部分，所述发光二极管的至少一个电极通过所述第一过孔与所述金属层电连接。
  8. 根据权利要求1或2所述的显示基板，其中，所述抗氧化层包围所述金属层。
  9. 根据权利要求1或2所述的显示基板，其中，所述显示基板还包括：位于所述抗氧化层远离所述衬底基板的钝化层；和位于所述钝化层中的第三过孔；
    所述第三过孔位于所述显示区域的焊盘位置，所述第三过孔暴露所述金属层的至少一部分，所述发光二极管的至少一个电极通过所述第三过孔与所述金属层电连接。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括：位于所述钝化层中的第四过孔；
    所述第四过孔位于绑定位置，所述第四过孔暴露所述抗氧化层的至少一部分，所述发光二极管的至少一个电极通过暴露的所述抗氧化层的一部分与所述金属层电连接。
  11. 根据权利要求9或10所述的显示基板，其中，所述抗氧化层包括开口部，所述开口部暴露所述金属层的至少一部分，所述第三过孔在所述衬底基板上的正投影位于所述开口部在所述衬底基板上的正投影内。
  12. 一种显示基板的制备方法，其特征在于，包括：
    在衬底基板上沉积铜种子层；
    在所述铜种子层远离所述衬底基板的一侧形成光刻胶层；
    通过构图工艺对所述光刻胶层进行构图，形成光刻胶图案；
    通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层；
    去除所述光刻胶图案和所述铜种子层的未被所述金属层覆盖的部分，以形成包括铜的金属层；
    在所述金属层远离所述衬底基板的一侧形成抗氧化层；
    在所述抗氧化层远离所述衬底基板一侧安装发光二极管，其中，所述发光二极管包括至少一个电极，所述发光二极管的至少一个电极与所述金属层电连接，
    其中，所述金属层的第一厚度大于所述抗氧化层的第二厚度。
  13. 根据权利要求12所述的方法，其中，所述衬底基板包括显示区域和标记区域，
    所述通过电镀工艺在所述铜种子层的未被所述光刻胶图案覆盖的部分上形成铜层包括：
    在所述标记区域，形成第一陪镀区；
    在所述显示区域，形成第二陪镀区；
    其中，所述第一陪镀区和所述第二陪镀区分别包括铜层的一部分；
    所述第一陪镀区与所述标记区域的面积比大于所述第二陪镀区与所述显示区域的面积比。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：在所述第一陪镀区包围的区域中，通过电镀工艺形成标记。
  15. 根据权利要求12所述的方法，其中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
    在所述金属层远离所述衬底基板的一侧形成钝化层；
    在所述钝化层中形成第一过孔，所述第一过孔暴露所述金属层的至少一部分；
    在所述第一过孔中形成所述抗氧化层，
    其中，所述抗氧化层包括有机保焊膜。
  16. 根据权利要求12所述的方法，其中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
    在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层。
  17. 根据权利要求12所述的方法，其中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
    在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层；
    在所述含镍合金层远离所述衬底基板的一侧形成钝化层；
    在所述钝化层中形成第二过孔，所述第二过孔暴露所述含镍合金层的至少一部分。
  18. 根据权利要求12所述的方法，其中，在所述金属层远离所述衬底基板的一侧形成抗氧化层包括：
    在所述金属层远离所述衬底基板的一侧形成包围所述金属层的含镍合金层；
    在所述显示区域的焊盘位置，在所述含镍合金层中形成开口部，所述开口部暴露所述金属层的至少一部分，
    在所述含镍合金层远离所述衬底基板的一侧形成钝化层；
    在所述显示区域的焊盘位置，在所述钝化层中形成第三过孔，所述第三过孔暴露所述金属层的至少一部分，
    其中，所述第三过孔在所述衬底基板上的正投影位于所述开口部在所述衬底基板上的正投影内。
  19. 根据权利要求18所述的方法，其中，在所述金属层远离所述衬底基板的一侧形成抗氧化层还包括：
    在绑定位置，在所述钝化层中形成第四过孔，所述第四过孔暴露所述含镍合金层的至少一部分。
  20. 一种显示装置，包括根据权利要求1-11中任一项所述的显示基板。
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CN110429089A (zh) * 2019-08-15 2019-11-08 京东方科技集团股份有限公司 驱动背板及其制作方法、显示装置
WO2021227717A1 (zh) * 2020-05-11 2021-11-18 京东方科技集团股份有限公司 发光基板及其制造方法、显示装置
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