WO2020211537A1 - Substrat de réseau, panneau d'affichage, son procédé de fabrication, et dispositif d'affichage - Google Patents

Substrat de réseau, panneau d'affichage, son procédé de fabrication, et dispositif d'affichage Download PDF

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Publication number
WO2020211537A1
WO2020211537A1 PCT/CN2020/076641 CN2020076641W WO2020211537A1 WO 2020211537 A1 WO2020211537 A1 WO 2020211537A1 CN 2020076641 W CN2020076641 W CN 2020076641W WO 2020211537 A1 WO2020211537 A1 WO 2020211537A1
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WO
WIPO (PCT)
Prior art keywords
pattern
sub
light
binding
adhesive
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PCT/CN2020/076641
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English (en)
Chinese (zh)
Inventor
董学
袁广才
李海旭
曹占锋
王珂
吕志军
王飞
王慧娟
梁志伟
卢鑫泓
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/959,010 priority Critical patent/US11316003B2/en
Publication of WO2020211537A1 publication Critical patent/WO2020211537A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a manufacturing method thereof, and a display device.
  • a micro light-emitting diode is a light-emitting diode with a size of micrometers. Due to the small size of the Micro LED, it can be used as a pixel on the display panel.
  • the display panel prepared by using Micro LED can be called a Micro LED display panel.
  • Micro LED display panels Compared with Organic Light-Emitting Diode (OLED) display panels, Micro LED display panels have better service life and viewing angles than OLED display panels. Therefore, Micro LED display technology has become the current research focus in the field of display technology.
  • the present disclosure provides an array substrate, a display panel, a manufacturing method thereof, and a display device.
  • the technical solution is as follows:
  • an array substrate including:
  • the planarization pattern has a via hole and a groove, the via hole is provided with a conductive structure, the bonding pattern is connected to the thin film transistor through the conductive structure, and the groove is used to accommodate an adhesive .
  • the planarization pattern includes a first sub-pattern and a second sub-pattern surrounding the first sub-pattern;
  • the groove is located on the side of the first sub-pattern away from the base substrate, the via hole is located in the second sub-pattern, and the binding pattern is located in the first sub-pattern away from the substrate.
  • One side of the bottom substrate One side of the bottom substrate.
  • the thickness of the first sub-pattern is greater than the thickness of the second sub-pattern.
  • the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns
  • the thickness of the second sub-pattern ranges from 0.5 to 1.5 microns
  • the depth of the groove ranges from 0.2 to 0.8 microns.
  • the binding pattern is arranged around the groove.
  • the binding pattern includes a first binding sub-pattern and a second binding sub-graphic that are insulated from each other, and the via includes a first via and a second via;
  • the first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via hole, and the second bonding sub-pattern is connected through the conductive structure in the second via hole.
  • the conductive structure is connected to the second power signal line in the thin film transistor.
  • the bonding pattern and the conductive structure in the via are arranged in the same layer.
  • the thin film transistor is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure.
  • the binding pattern is arranged around the groove, the binding pattern includes a first binding sub-graphic and a second binding sub-graphic that are insulated from each other, and the via includes a first via and a second Two vias;
  • the first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via hole, and the second bonding sub-pattern is connected through the conductive structure in the second via hole.
  • the conductive structure is connected to the second power signal line in the thin film transistor;
  • the bonding pattern and the conductive structure in the via hole are arranged in the same layer.
  • a display panel including: a light-emitting unit and the array substrate according to any one of the aspects;
  • the light-emitting unit is located on a side of the planarization pattern away from the base substrate, and the light-emitting unit is fixedly connected to the binding pattern through the adhesive in the groove of the planarization pattern.
  • the light emitting unit is a micro light emitting diode
  • the micro light emitting diode includes a light emitting body and electrode pins protruding from the light emitting body
  • the light emitting body includes a first electrode and a second electrode
  • the electrode The pins include a first pin connected to the first electrode and a second pin connected to the second electrode;
  • the binding pattern is arranged around the groove, and the binding pattern includes a first binding sub-pattern and a second binding sub-pattern that are insulated from each other, and the via on the planarization pattern includes a first via And a second via, the first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via, and the second bonding sub-pattern passes through the second The conductive structure in the via hole is connected to the second power signal line in the thin film transistor;
  • the end of the first pin away from the light-emitting body is connected to the first binding sub-pattern, and the end of the second pin away from the light-emitting body is connected to the second binding sub-pattern.
  • the side surface of the electrode pin and the side surface of the binding pattern are fixedly connected by an adhesive in the groove.
  • a display device including: the display panel as described in any one of the other aspects.
  • a manufacturing method of an array substrate includes:
  • planarization pattern Forming a planarization pattern on the base substrate on which the thin film transistor is formed, the planarization pattern having a via hole and a groove, and the groove is used for accommodating an adhesive;
  • a bonding pattern is formed on the base substrate on which the planarization pattern is formed, and a conductive structure is formed in the via hole, so that the bonding pattern is connected to the thin film transistor through the conductive structure.
  • the forming a bonding pattern on the base substrate on which the planarization pattern is formed and forming a conductive structure in the via hole includes:
  • the bonding pattern is formed on the base substrate with the planarization pattern formed by a conductive material through a patterning process, and the conductive structure is formed in the via hole.
  • a method for manufacturing a display panel includes:
  • the array substrate including the array substrate according to any one of the aspects
  • An adhesive is arranged in the groove of the flattened pattern, so that the volume of the adhesive in the groove is greater than the volume of the groove;
  • the melted adhesive is cured to fix and connect the light-emitting unit and the binding pattern.
  • the light emitting unit is a micro light emitting diode
  • the micro light emitting diode includes a light emitting body and electrode pins protruding from the light emitting body, and the light emitting unit is arranged on the binding pattern away from the base substrate
  • the side includes:
  • the melting the adhesive so that the melted adhesive contacts the light-emitting unit and the binding pattern includes:
  • the adhesive is melted so that the melted adhesive contacts the side surface of the electrode pin and the side surface of the binding pattern.
  • the adhesive has hot-melt properties
  • the melting treatment of the adhesive includes:
  • the adhesive is melted by heating.
  • the disposing an adhesive in the groove of the planarization pattern includes:
  • the adhesive is coated in the groove by screen printing or photolithography process.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a halftone mask provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a groove provided with an adhesive provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a micro LED provided on the side of the binding pattern away from the base substrate according to an embodiment of the present disclosure.
  • the Micro LED display panel includes an array substrate and a plurality of Micro LED arrays arranged on the array substrate, and each Micro LED can be regarded as a pixel.
  • the Micro LED needs to be welded on the array substrate through a chip-level bonding process to prepare a Micro LED display panel. Since the process of disposing the Micro LED on the array substrate in the related art is relatively complicated, the manufacturing process of the Micro LED display panel is relatively complicated.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate 10 includes a base substrate 101, and a thin film transistor 102, a planarization pattern 103 and a bonding pattern 104 which are stacked on the base substrate 101 in a direction away from the base substrate 101.
  • the planarization pattern 103 has a via W and a groove H.
  • a conductive structure 105 is provided in the via W.
  • the bonding pattern 104 is electrically connected to the thin film transistor 102 through the conductive structure 105.
  • the groove H is used to contain the adhesive.
  • the adhesive in the groove H is used to fix the light-emitting unit and the binding structure 104.
  • the array substrate provided by the embodiment of the present disclosure may be used to prepare a Micro LED display panel.
  • the array substrate provided by the embodiment of the present disclosure has via holes and grooves on the planarization pattern, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.
  • the binding pattern and the conductive structure in the via hole are arranged on the same layer.
  • the material for preparing the binding pattern and the conductive structure includes at least one of aluminum, neodymium and molybdenum.
  • the bonding pattern and the conductive structure in the via hole are arranged in the same layer, that is, the bonding pattern and the conductive structure in the via hole can be formed by one patterning process, which simplifies the manufacturing process of the array substrate.
  • the thin film transistor is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure.
  • the thin film transistor is a thin film transistor with a top gate structure.
  • the thin film transistor 102 includes an active layer pattern 1021, a gate insulating layer 1022, a gate G, a passivation layer 1023, and source and drain patterns stacked in a direction away from the base substrate 101.
  • the source-drain pattern includes a source S and a drain D.
  • the thin film transistor is a thin film transistor with a bottom gate structure.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the thin film transistor 102 includes a gate G, a gate insulating layer 1022, an active layer pattern 1021, and a source/drain pattern stacked in a direction away from the base substrate 101.
  • the source-drain pattern includes a source S and a drain D.
  • the thin film transistor further includes a power signal line
  • the power signal line may be prepared in the same layer as the source electrode and the drain electrode, that is, the source and drain pattern may also include a power signal line.
  • the power signal line includes a Vdd signal line and a Vss signal line.
  • the source-drain pattern includes a source S, a drain D, and a power signal line L (only one power signal line is shown in the figure).
  • the gate of the thin film transistor in the array substrate shown in FIG. 1 and FIG. 2 may also have a two-layer structure, which is not limited by the embodiment of the present disclosure.
  • the drawings provided in the embodiment of the present disclosure are only It is used as an exemplary description and is not used to limit the specific structure of the thin film transistor.
  • the binding pattern 104 is arranged around the groove H on the planarization pattern 103.
  • the groove on the planarization pattern is used to contain the adhesive, if the binding pattern is arranged in the groove, the part of the binding pattern located in the groove cannot be used to connect the light-emitting unit. There is no overlap area between the orthographic projection of the binding pattern on the base substrate and the orthographic projection of the groove on the planarization pattern on the base substrate, that is, no binding pattern is arranged in the groove, which can save preparation materials.
  • the binding pattern 104 includes a first binding sub-graphic 1041 and a second binding sub-graphic 1042 that are insulated from each other.
  • the via W includes a first via and a second via.
  • the first bonding sub-pattern 1041 is connected to the first power signal line in the thin film transistor 102 (the first power signal line is not shown in the figure) through the conductive structure in the first via hole.
  • the second bonding sub-pattern 1042 is connected to the second power signal line L in the thin film transistor 102 through the conductive structure in the second via hole.
  • the first power signal line may be connected to the drain D, or the first power signal line may also be connected to the source S, which is not limited in the embodiment of the present disclosure.
  • the first power signal line is used to provide a high level signal
  • the first power signal line is a Vdd signal line
  • the second power signal line is used to provide a low level signal
  • the second power signal line is a Vss signal line.
  • the preparation material of the gate includes at least one of aluminum (Al), neodymium (Nd), and molybdenum (Mo).
  • the source and drain pattern preparation materials include at least one of aluminum, neodymium, and molybdenum.
  • the preparation materials of the active layer pattern include at least one of Indium Gallium Zinc Oxide (IGZO), Low Temperature Poly-silicon (LTPS) and Low Temperature Polycrystalline Oxide (LTPO) One kind.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly-silicon
  • LTPO Low Temperature Polycrystalline Oxide
  • the structure of the array substrate is further described by taking the thin film transistor in the array substrate as the top gate structure as an example.
  • FIG. 3 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • the planarization pattern 103 includes a first sub-pattern 1031 and a second sub-pattern 1032 surrounding the first sub-pattern 1031.
  • the groove H is arranged on the side of the first sub-pattern 1031 away from the base substrate 101.
  • the via W is located in the second sub-pattern 1032.
  • the binding pattern 104 is located on the side of the first sub-pattern 1031 away from the base substrate 101.
  • the thickness of the first sub-pattern 1031 is greater than the thickness of the second sub-pattern 1032.
  • the planarization pattern includes a first sub-pattern and a second sub-pattern surrounding the first sub-pattern, and the thickness of the first sub-pattern is greater than the thickness of the second sub-pattern, that is, the planarization pattern has a boss structure.
  • the thickness of the source/drain pattern is generally 7500 angstroms, and the thickness of the planarization pattern is greater than the thickness of the source/drain pattern.
  • the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns.
  • the thickness of the second sub-pattern ranges from 0.5 to 1.5 microns.
  • the depth of the grooves ranges from 0.2 to 0.8 microns.
  • the array substrate provided by the embodiment of the present disclosure has via holes and grooves on the planarization pattern, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.
  • FIG. 4 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 4, the method includes the following working processes:
  • step 201 a thin film transistor is formed on a base substrate.
  • the preparation material of the base substrate includes at least one of glass, silicon wafer, quartz and plastic, and the embodiment of the present disclosure does not limit the preparation material of the base substrate.
  • a planarization pattern is formed on the base substrate on which the thin film transistor is formed, and the planarization pattern has a via hole and a groove, and the groove is used for accommodating an adhesive.
  • the planarization pattern 103 includes a first sub-pattern 1031 and a second sub-pattern 1032 surrounding the first sub-pattern 1031.
  • the thickness of the first sub-pattern 1031 is greater than the thickness of the second sub-pattern 1032.
  • the groove H is arranged on the side of the first sub-pattern 1031 away from the base substrate 101.
  • step 203 a bonding pattern is formed on the base substrate with the planarization pattern and a conductive structure is formed in the via hole, so that the bonding pattern is connected to the thin film transistor through the conductive structure.
  • the implementation process of the above step 201 includes the following steps:
  • step 2011a an active layer pattern is formed on the base substrate.
  • the preparation material of the active layer pattern includes at least one of IGZO, LTPS, and LTPO.
  • a patterning process can be used to form the active layer pattern on the base substrate.
  • the patterning process includes: photoresist coating, exposure, development, etching and photoresist stripping.
  • step 2012a a gate insulating layer is formed on the base substrate on which the active layer pattern is formed.
  • the material for preparing the gate insulating layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide.
  • the gate insulating layer can be formed on the base substrate with the active layer pattern formed by deposition.
  • step 2013a a gate is formed on the base substrate on which the gate insulating layer is formed.
  • the preparation material of the grid includes at least one of aluminum, neodymium and molybdenum.
  • a patterning process can be used to form a gate on a base substrate on which a gate insulating layer is formed.
  • step 2014a a passivation layer is formed on the base substrate on which the gate is formed.
  • the preparation material of the passivation layer includes at least one of silicon dioxide, silicon nitride and aluminum oxide.
  • the passivation layer can be formed on the base substrate on which the gate is formed by deposition.
  • step 2015a source and drain patterns are formed on the base substrate on which the passivation layer is formed.
  • the material for preparing the source and drain patterns includes at least one of aluminum, neodymium, and molybdenum.
  • a patterning process can be used to form the source and drain patterns on the base substrate on which the passivation layer is formed.
  • the implementation process of the foregoing step 201 includes the following steps:
  • step 2011b a gate is formed on the base substrate.
  • step 2013a For the material and preparation method of the gate, reference may be made to the above-mentioned step 2013a, which is not repeated in the embodiment of the present disclosure.
  • step 2012b a gate insulating layer is formed on the base substrate on which the gate is formed.
  • step 2013b an active layer pattern is formed on the base substrate on which the gate insulating layer is formed.
  • the material and preparation method of the gate can refer to the above step 2011a, which is not described in detail in the embodiment of the present disclosure.
  • step 2014b source and drain patterns are formed on the base substrate on which the active layer pattern is formed.
  • step 202 includes the following steps:
  • step 2021 a planarization layer is formed on the base substrate on which the thin film transistor is formed.
  • a planarization layer is formed on the base substrate on which the thin film transistor is formed by a coating process.
  • the thickness of the planarization layer is 1.5 to 2.5 microns.
  • the thickness of the planarization layer may be 2 microns.
  • the process for forming a planarization layer with a thickness of 2 microns is relatively mature and stable, and has a better planarization effect on the film, and the uniformity of the obtained film is higher.
  • step 2022 a halftone mask combined with a patterning process is used to pattern the planarization layer to obtain a planarization pattern.
  • the planarization layer may be prepared from a photosensitive resin material.
  • a halftone mask can be used to expose the planarization layer from the side of the planarization layer away from the base substrate.
  • the flattened layer after the exposure treatment is developed to obtain a flattened pattern.
  • FIG. 5 is a schematic structural diagram of a halftone mask provided by an embodiment of the present disclosure.
  • the halftone mask can be used to prepare the planarization pattern in the array substrate as shown in FIG. 3.
  • the halftone mask may include a first light-transmitting area T1, a second light-transmitting area T2, and a third light-transmitting area with successively decreasing light transmittances.
  • the light-shielding area Z is a ring-shaped area
  • the third light-transmitting area T3 is an area enclosed by the light-shielding area Z
  • the second light-transmitting area T2 is located at the periphery of the light-shielding area Z.
  • the gray scale of the halftone mask indicates the degree of light transmittance, and the deeper the gray scale, the smaller the transmittance (black means opaque), that is, the gray scale of the halftone mask
  • the deeper the gray level indicates the weaker the degree of exposure of the planarization layer.
  • the halftone mask shown in FIG. 5 is used to expose the planarization layer, and the exposed planarization layer is developed to obtain the planarization pattern as shown in FIG. 3 .
  • the first light-transmitting area corresponds to the via hole
  • the second light-transmitting area corresponds to the second sub-pattern
  • the third light-transmitting area corresponds to the groove
  • the light-shielding area corresponds to the first sub-pattern.
  • the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns.
  • the thickness of the second sub-pattern ranges from 0.5 to 1.5 microns.
  • the depth of the grooves ranges from 0.2 to 0.8 microns.
  • the binding pattern is provided on the side of the first sub-pattern away from the base substrate. It is convenient for the subsequent positioning of the light-emitting unit, and can improve the installation yield of the light-emitting unit.
  • the implementation process of the above step 203 includes: forming a bonding pattern on the side of the first sub-pattern away from the base substrate through a patterning process using a conductive material, and forming a conductive structure in the via hole.
  • the material for preparing the binding pattern and the conductive structure includes at least one of aluminum, neodymium, and molybdenum.
  • a binding pattern is formed on the side of the first sub-pattern away from the base substrate, and a conductive structure is formed in the via hole, which can simplify the preparation process of the array substrate.
  • the manufacturing method of the array substrate provided by the embodiment of the present disclosure, in the array substrate prepared by the method, the planarization pattern has via holes and grooves, and the binding pattern can pass through the conductive structure and the groove in the via hole. Thin film transistor connection. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.
  • An embodiment of the present disclosure provides a display panel including: a light-emitting unit and an array substrate 10 as shown in any one of FIGS. 1 to 3.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure, and the display panel includes the array substrate as shown in FIG. 3.
  • the light-emitting unit 30 is located on the side of the planarization pattern 103 away from the base substrate 101, and the light-emitting unit 30 is fixedly connected to the binding pattern by the adhesive 40 in the groove of the planarization pattern 103.
  • the display panel provided by the embodiments of the present disclosure includes via holes and grooves on the planarization pattern in the array substrate, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole.
  • the light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarized pattern.
  • the light emitting unit is a micro LED.
  • the micro LED 30 includes a light-emitting body 301 and electrode pins protruding from the light-emitting body 301.
  • the light-emitting body 301 includes a first electrode and a second electrode (the electrode is not shown in the figure).
  • the electrode pins include a first pin 3021 connected to the first electrode and a second pin 3022 connected to the second electrode.
  • the binding pattern 104 includes a first binding sub-pattern 1041 and a second binding sub-pattern 1042 located around the groove and insulated from each other.
  • the via W on the planarization pattern 103 includes a first via and a second via.
  • the first bonding sub-pattern 1041 is connected to the first power signal line in the thin film transistor 102 (the first power signal line is not shown in the figure) through the conductive structure in the first via hole, and the second bonding sub-pattern 1042 passes through the first power signal line.
  • the conductive structure in the two via holes is connected to the second power signal line L in the thin film transistor 102.
  • An end of the first pin 3021 away from the light-emitting body 301 is connected to the first binding sub-pattern 1041.
  • the end of the second pin 3022 away from the light-emitting body 301 is connected to the second binding sub-pattern 1042.
  • the first power signal line is a Vdd signal line for providing a high-level signal
  • the second power signal line is a Vss signal line for providing a low-level signal.
  • the side surface of the electrode pin and the side surface of the binding pattern 104 are fixedly connected by the adhesive 40 in the groove.
  • the end of the electrode pin of the micro LED away from the light-emitting body is in direct contact with the binding pattern, which can eliminate the interference of other film layers, facilitate the overlap between the metals, and ensure the conductivity.
  • the adhesive is an insulating material.
  • the adhesive is one of hot melt adhesive and polyimide adhesive.
  • the display panel provided by the embodiments of the present disclosure includes via holes and grooves on the planarization pattern in the array substrate, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole.
  • the light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarized pattern.
  • FIG. 7 is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure. As shown in Figure 7, the method includes the following working processes:
  • step 501 an array substrate is provided.
  • the array substrate includes the array substrate shown in any one of FIGS. 1 to 3.
  • the manufacturing method of the array substrate and the structure and material of each film layer can refer to the above-mentioned embodiment of the structure and manufacturing method of the array substrate, which is not repeated in the embodiments of the present disclosure.
  • step 502 an adhesive is arranged in the groove of the planarized pattern, so that the volume of the adhesive in the groove is greater than the volume of the groove.
  • FIG. 8 is a schematic structural diagram of a groove provided with an adhesive provided in an embodiment of the present disclosure.
  • an adhesive 40 with a height greater than the depth of the groove H in the groove H, the volume of the adhesive 40 is greater than the volume of the groove H.
  • the adhesive is arranged in the groove of the planarization pattern to fix the position of the adhesive, prevent the adhesive from flowing to the surface of the binding pattern, and affect the contact between the light-emitting unit and the binding pattern.
  • an adhesive is coated in the grooves of the planarization pattern by screen printing or photolithography.
  • the depth of the groove is in the range of 0.2 to 0.8 microns
  • the height of the adhesive can be in the range of 2.5 to 4 microns. It should be noted that by providing an adhesive whose height is greater than the depth of the groove, it is convenient to fix the light-emitting unit later. The adhesive can be accurately set in the groove through the alignment platform.
  • the thickness of the applied adhesive can be controlled by the amount of glue applied by screen printing.
  • the thickness of the applied adhesive can be controlled by the amount of glue dispensed in the photolithography process.
  • the selected adhesive needs to have a certain viscosity to adhere the array substrate and the light-emitting unit, and the adhesive is an insulating material.
  • the binder must have fluidity under certain conditions.
  • the adhesive is in a fluid state after heating.
  • the adhesive is one of hot melt adhesive and polyimide adhesive.
  • step 503 the light emitting unit is arranged on the side of the binding pattern away from the base substrate.
  • the light emitting unit is a micro LED
  • the micro LED includes a light emitting body and electrode pins protruding from the light emitting body.
  • the implementation process of step 503 includes: setting the end of the electrode pin away from the light-emitting body on the side of the binding pattern away from the base substrate. Since the height of the adhesive is greater than the depth of the groove, the micro LED can be arranged on the side of the binding pattern away from the base substrate by pressing and attaching. The precise alignment of the light-emitting unit and the bound graphics can be achieved through the alignment platform.
  • the end of the electrode pin of the micro LED away from the light-emitting body is in direct contact with the binding pattern, which can eliminate the interference of other film layers, facilitate the overlap between the metals, and ensure the conductivity.
  • FIG. 9 is a schematic structural diagram of a micro LED provided on a side of the binding pattern away from the base substrate provided by an embodiment of the present disclosure.
  • the light-emitting body 301 in the micro LED 30 can be preliminarily fixed to the array substrate by the adhesive 40 to avoid misalignment of the electrode pins of the micro LED 30 and the binding pattern 104 in the subsequent process, resulting in poor contact.
  • step 504 the adhesive is melted so that the melted adhesive contacts the light-emitting unit and the binding pattern.
  • the implementation process of step 504 includes: melting the adhesive so that the heated and melted adhesive contacts the side surface of the electrode pin and the side surface of the binding pattern.
  • the adhesive has hot melt properties. The adhesive can be melted by heating.
  • a certain pressure is applied to the micro LED on the side of the binding pattern away from the base substrate to ensure that the electrode pins of the micro LED are in contact with the binding pattern and Counterpoint.
  • the adhesive will collapse after being heated, and the collapsed adhesive will contact the side of the electrode pin and the side of the binding pattern without affecting the contact between the electrode pin and the binding pattern, thereby realizing the effective binding of the micro LED set.
  • step 505 the melted adhesive is cured to fix and connect the light-emitting unit and the binding pattern.
  • the adhesive is cooled and solidified to fix the connection of the light-emitting unit and the binding pattern.
  • the display panel shown in FIG. 6 can be prepared by using the above method.
  • the planarization pattern in the array substrate has via holes and grooves, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole.
  • the light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarization pattern.
  • the light-emitting unit does not need to be welded on the array substrate through a soldering process, thus simplifying the setting process of the light-emitting unit and thus The preparation process of the display panel can be simplified.
  • the cost of the adhesive is low, so the manufacturing cost of the display panel can be saved.
  • micro LEDs can be aligned with the corresponding binding patterns, and the adhesive can be uniformly heated, so that the adhesive is fixedly connected to the corresponding micro LEDs and the binding patterns.
  • the massive transfer of the micro LED can be realized and the transfer efficiency of the micro LED can be improved.
  • the embodiment of the present disclosure also provides a display device, which may include a display panel as shown in FIG. 6.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.
  • plurality refers to two or more, unless specifically defined otherwise.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

La présente invention se rapporte au domaine technique des dispositifs d'affichage, et concerne un substrat de réseau (10), un panneau d'affichage, un procédé de fabrication correspondant, ainsi qu'un dispositif d'affichage. Le substrat de réseau (10) comprend un substrat de base (101), ainsi qu'un transistor en couches minces (102), un motif de planarisation (103) et un motif de liaison (104) stratifiés sur le substrat de base (101) dans une direction opposée à ce dernier. Le motif de planarisation (103) comprend un trou d'interconnexion (W) et un évidement (H), et le trou d'interconnexion (W) contient une structure conductrice (105). Le motif de liaison (104) est électriquement connecté au transistor en couches minces (102) par l'intermédiaire de la structure conductrice (105). L'évidement (H) est destiné à contenir un liant (40). La présente invention simplifie le processus de configuration d'une unité électroluminescente (30), simplifiant ainsi le processus de fabrication d'un panneau d'affichage.
PCT/CN2020/076641 2019-04-17 2020-02-25 Substrat de réseau, panneau d'affichage, son procédé de fabrication, et dispositif d'affichage WO2020211537A1 (fr)

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CN201910308732.XA CN109994533B (zh) 2019-04-17 2019-04-17 阵列基板、显示面板及其制造方法

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CN112542086B (zh) * 2019-09-23 2023-03-31 上海和辉光电股份有限公司 显示面板及显示装置
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US11316003B2 (en) 2020-02-25 2022-04-26 Boe Technology Group Co., Ltd. Array substrate, display device, and method for manufacturing same
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