CN110600497B - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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CN110600497B
CN110600497B CN201911008405.9A CN201911008405A CN110600497B CN 110600497 B CN110600497 B CN 110600497B CN 201911008405 A CN201911008405 A CN 201911008405A CN 110600497 B CN110600497 B CN 110600497B
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film transistor
thin film
conductive connecting
connecting pipe
electrode
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CN110600497A (zh
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袁广才
梁志伟
王珂
曹占锋
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BOE Technology Group Co Ltd
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Priority to PCT/CN2020/121888 priority patent/WO2021078095A1/zh
Priority to US17/418,809 priority patent/US20220068873A1/en
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Abstract

本申请公开了一种阵列基板及其制造方法、显示装置。阵列基板包括衬底基板，所述衬底基板的一侧形成有薄膜晶体管层，所述薄膜晶体管层背向所述衬底基板的一侧形成有多个导电连接管，所述薄膜晶体管层通过所述导电连接管与微发光二极管芯片电连接，所述导电连接管的侧壁靠近所述薄膜晶体管层的一侧形成有至少一个开口。在对导电连接管加热时，导电连接管内部的空气能够从通孔排出，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性。

Description

阵列基板及其制造方法、显示装置
技术领域
本发明一般涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
Micro-LED(微发光二极管)技术是将现有LED(发光二极管)的尺寸微缩至100um以下，尺寸约为现有LED尺寸的1％，再通过巨量转移技术，将微米量级的RGB三色Micro-LED转移到阵列基板上，从而形成各种不同尺寸的Micro-LED显示器。简单来说Micro-LED就是LED的薄膜化、微型化与阵列化，每一个Micro-LED像素可以定址、单独驱动发光，相邻像素间的距离由毫米级降到微米级。Micro-LED具有自发光高亮度、高对比度、超高分辨率与色彩饱和度、长寿命、响应速度快、节能、适应环境宽泛等诸多优点。Micro-LED显示技术可以涵盖从AR/VR等微显示、手机电视等中等尺寸显示到影院大屏幕显示领域。
现有的Micro-LED在生产过程中，需要将阵列基板与Micro-LED芯片通过导电连接管进行bonding(绑定)，而现有的导电连接管都是完整的，在绑定过程中需要对导电连接管加热，导电连接管内的空气会膨胀，导致绑定失效。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供一种提高绑定可靠性的阵列基板及其制造方法、显示装置。
第一方面，本发明的阵列基板，包括衬底基板，所述衬底基板的一侧形成有薄膜晶体管层，所述薄膜晶体管层背向所述衬底基板的一侧形成有多个导电连接管，所述薄膜晶体管层通过所述导电连接管与微发光二极管芯片电连接，所述导电连接管的侧壁靠近所述薄膜晶体管层的一侧形成有至少一个开口。
第二方面，本发明的显示装置，包括阵列基板。
第三方面，本发明的阵列基板的制造方法，包括以下步骤：
在衬底基板的一侧形成薄膜晶体管层；
在所述薄膜晶体管层背向所述衬底基板的一侧形成多个导电连接管，其中，所述导电连接管的侧壁靠近所述薄膜晶体管层的一侧形成有至少一个开口；
将所述导电连接管与微发光二极管芯片电连接。
根据本申请实施例提供的技术方案，通过在导电连接管的侧壁靠近薄膜晶体管层的一侧形成开口，在将薄膜晶体管层与微发光二极管芯片绑定的过程中，在对导电连接管加热时，导电连接管内部的空气能够从开口排出，避免导电连接管内部气压升高，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性，能够解决在绑定过程中，导电连接管内部空气膨胀导致绑定失效的问题。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为本发明的实施例的阵列基板的结构示意图；
图2为本发明的实施例的阵列基板的一种导电连接管的结构示意图；
图3为本发明的实施例的阵列基板的又一种导电连接管的结构示意图；
图4为本发明的实施例的阵列基板的制造方法中在衬底基板上形成薄膜晶体管层的示意图；
图5为本发明的实施例的阵列基板的制造方法中在薄膜晶体管层上形成平坦层和钝化层的示意图；
图6为本发明的实施例的阵列基板的制造方法中在钝化层上涂覆第一光刻胶的示意图；
图7为本发明的实施例的阵列基板的制造方法中刻蚀平坦层和钝化层形成过孔的示意图；
图8为本发明的实施例的阵列基板的制造方法中在钝化层上形成金属层的示意图；
图9为本发明的实施例的阵列基板的制造方法中在金属层上涂覆光刻胶的示意图；
图10为本发明的实施例的阵列基板的制造方法中光刻胶在导电连接管上正投影范围的示意图；
图11为本发明的实施例的阵列基板的制造方法中刻蚀金属层和钝化层的示意图；
图12为本发明的实施例的阵列基板的制造方法中刻蚀光刻胶和平坦层的示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
本发明的其中一个实施例为，请参考图1～3，一种阵列基板，包括衬底基板10，衬底基板10的一侧形成有薄膜晶体管层20，薄膜晶体管层20背向衬底基板10的一侧形成有多个导电连接管40，薄膜晶体管层20通过导电连接管40与微发光二极管芯片50电连接，导电连接管40的侧壁靠近薄膜晶体管层20的一侧形成有至少一个开口41。
在本发明的实施例中，薄膜晶体管层通过导电连接管电连接有微发光二极管芯片，也就是导电连接管与微发光二极管芯片绑定，具体的，将导电连接管背向薄膜晶体管层的一侧与微发光二极管芯片的阴极或者阳极绑定，通过薄膜晶体管层内薄膜晶体管的导通和截止来控制对应微发光二极管的亮和灭。开口沿着导电连接管的径向贯穿导电连接管侧壁，在对导电连接管进行加热时，导电连接管内部的空气会从导电连接管侧壁的开口排出，避免由于导电连接管内部气压升高导致绑定失效，提高了阵列基板的可靠性。
导电连接管设置为中空结构，在将导电连接管刺入微发光二极管芯片的电极时，会有部分电极进入到导电连接管的内腔，提高导电连接管与微发光二极管芯片电极连接的可靠性。导电连接管的侧壁靠近薄膜晶体管层的一侧形成有开口，在将导电连接管与微发光二极管芯片绑定过程中，具体的，将导电连接管背向薄膜晶体管层的一侧与微发光二极管芯片的阴极或者阳极绑定过程中，在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，需要对导电连接管和微发光二极管芯片的阴极或者阳极进行加热，以使导电连接管和微发光二极管芯片的阴极或者阳极相互扩散，从而使两者形成稳定的电连接，理想状态下，微发光二极管芯片的阴极或者阳极能够完全刺入导电连接管的内腔，此时，两者的绑定效果最好。在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，或者是在加热过程中，导电连接管和微发光二极管芯片的阴极或者阳极相互扩散时，开口不会被微发光二极管芯片的阴极或者阳极堵塞，也就是，如果将开口设置在导电连接管侧壁靠近微发光二极管芯片的一侧，则有可能在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，或者是在加热过程中，导电连接管和微发光二极管芯片的阴极或者阳极相互扩散时，微发光二极管芯片的阴极或者阳极会堵住导电连接管上的开口，导致导电连接管内的空气无法从开口排出。导电连接管的侧壁靠近薄膜晶体管层的一侧形成有开口，能够保证在加热导电连接管与微发光二极管芯片的阴极或者阳极，使两者在相互扩散过程中，在导电连接管内腔内的气体能够顺利从开口排出。
导电连接管侧壁上开口的数量为至少一个，可以但不限于，导电连接管侧壁上开口的数量为一个，能够保证导电连接管的强度。可以但不限于导电连接管侧壁上开口的数量为多个，相对于一个开口，多个开口能够避免单个开口被堵住后，导电连接管内部的气体无法排出，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性。
参考图3，进一步的，开口41为沿着导电连接管40的轴向贯穿导电连接管40侧壁的通孔。开口为沿着导电连接管的轴向贯穿导电连接管的侧壁的通孔，便于在导电连接管侧壁形成开口，能够降低工艺难度，提高光刻工艺的加工效率。同时，也能够保证开口的排气效果，避免在加热导电连接管与微发光二极管芯片的阴极或者阳极时，开口被堵住。
进一步的，开口41沿着导电连接管40周向的长度小于或等于导电连接管40周长的六分之一。避免开口沿着导电连接管周向的长度过长，从而减小在导电连接管侧壁设置开口对导电连接管强度的影响，保证了导电连接管的强度，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性，保证了阵列基板的可靠性。
进一步的，导电连接管40侧壁的厚度大于或等于1000A。保证了导电连接管的强度，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性，保证了阵列基板的可靠性。
进一步的，导电连接管40与薄膜晶体管层20连接一侧的厚度大于或等于1000A。也就是导电连接管面向薄膜晶体管层一侧的厚度大于或等于1000A。保证了导电连接管的强度，保证了薄膜晶体管层与微发光二极管芯片绑定的可靠性，保证了阵列基板的可靠性。
进一步的，导电连接管40的材料为钨、铌、钛和钼中任意一种或者多种的组合。
进一步的，薄膜晶体管层20包括多个薄膜晶体管，每个薄膜晶体管包括源极21、漏极22、公共电极23、第一电极31和第二电极32，第一电极31和第二电极32之间相互绝缘，源极21或者漏极22与第一电极31连接，公共电极23与第二电极32连接，导电连接管40包括第一导电连接管42和第二导电连接管43，第一电极31与第一导电连接管42连接，第二电极32与第二导电连接管4连接，
第一导电连接管42与微发光二极管芯片50的阴极连接，第二导电连接管43与微发光二极管芯片50的阳极连接，或者，
第一导电连接管42与微发光二极管芯片50的阳极连接，第二导电连接管43与微发光二极管芯片50的阴极连接。
在本发明的实施例中，薄膜晶体管与导电连接管之间设置有相互绝缘的第一电极和第二电极，第一电极与源极或者漏极电连接，也就是，第一电极将源极或者漏极引出；第二电极与公共电极电连接，也就是，第二电极将公共电极引出。将第一电极和第二电极分别通过导电连接管与微发光二极管芯片的阴极和阳极绑定，具体的，第一电极与第一导电连接管连接，第二电极与第二导电连接管连接，然后将第一导电连接管与微发光二极管芯片的阴极连接，第二导电连接管与微发光二极管芯片的阳极连接，或者，将第一导电连接管与微发光二极管芯片的阳极连接，第二导电连接管与微发光二极管芯片的阴极连接。在对导电连接管进行加热时，导电连接管内部的空气会从导电连接管侧壁的开口排出，避免由于导电连接管内部气压升高导致绑定失效，提高了阵列基板的可靠性。
当薄膜晶体管层内的薄膜晶体管为NMOS(N-channel Metal OxideSemiconductor，N型沟道金属氧化物半导体)管时，第一电极形成于源极表面，也就是第一电极与源极电连接，第一电极引出源极。当薄膜晶体管层内的薄膜晶体管为PMOS(P-channel Metal Oxide Semiconductor，P型沟道金属氧化物半导体)管时，第一电极形成于漏极表面，也就是第一电极与漏极电连接，第一电极引出漏极。公共电极一般为共阴极，也就是公共电极通过第二电极与微发光二极管芯片的阴极电连接。图1所示出的为薄膜晶体管为PMOS管，公共电极为共阴极的情况，其中第一电极分别与漏极以及微发光二极管芯片的阳极电连接，第二电极分别与公共电极以及微发光二极管芯片的阴极电连接。
进一步的，微发光二极管芯片50的阴极51和阳极52的硬度均小于导电连接管40的硬度。便于将导电连接管刺入微发光二极管芯片的阴极和阳极，实现导电连接管与微发光二极管芯片的阴极和阳极的预绑定，起到对导电连接管以及微发光二极管芯片的阴极和阳极的定位。在进行加热时，便于导电连接管与微发光二极管芯片的阴极和阳极相互扩散形成绑定，使得导电连接管与微发光二极管芯片的阴极和阳极之间能够形成可靠的电气连接。
进一步的，微发光二极管芯片50的阴极51和阳极52的材料为铟、铜、银、金和铝中任意一种或者多种的组合。
参考如下表一，表一为导电连接管的多种材料以及微发光二极管芯片的阴极和阳极的多种材料的莫氏硬度和电阻率的具体数值。在选择导电连接管的材料以及微发光二极管芯片的阴极和阳极的材料时，选择硬度差尽量大，电阻率尽量小的材料，这样能够降低二者的绑定难度，保证绑定效果以及导电效果。
表一：
Figure BDA0002243452770000071
本发明的另一个实施例为，一种显示装置，包括阵列基板。
本发明的另一个实施例为，参考图1～3，一种阵列基板的制造方法，包括以下步骤：
在衬底基板10的一侧形成薄膜晶体管层20；
在薄膜晶体管层20背向衬底基板10的一侧形成多个导电连接管40，其中，导电连接管40的侧壁靠近薄膜晶体管层20的一侧形成有至少一个开口41；
将导电连接管40与微发光二极管芯片50电连接。
在本发明的实施例中，在衬底基板的一侧形成薄膜晶体管层，具体的，在衬底基板上依次制作缓冲层、低温多晶硅层、栅绝缘层、栅极层、中间介电层、源极层、漏极层、公共电极层、第一平坦层和第一钝化层。
薄膜晶体管层通过导电连接管绑定有微发光二极管芯片，具体的，将导电连接管背向薄膜晶体管层的一侧与微发光二极管芯片的阴极或者阳极绑定，通过薄膜晶体管层内薄膜晶体管的导通和截止来控制对应微发光二极管的亮和灭。在对导电连接管进行加热时，导电连接管内部的空气会从导电连接管侧壁的开口排出，避免由于导电连接管内部气压升高导致绑定失效，提高了阵列基板的可靠性。
导电连接管的侧壁靠近薄膜晶体管层的一侧形成有开口，在将导电连接管与微发光二极管芯片绑定过程中，具体的，将导电连接管背向薄膜晶体管层的一侧与微发光二极管芯片的阴极或者阳极绑定过程中，在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，需要对导电连接管和微发光二极管芯片的阴极或者阳极进行加热，以使导电连接管和微发光二极管芯片的阴极或者阳极相互扩散，从而形成稳定的电连接，理想状态下，微发光二极管芯片的阴极或者阳极能够完全刺入导电连接管的内腔，此时，两者的绑定效果最好。在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，或者是在加热过程中，导电连接管和微发光二极管芯片的阴极或者阳极相互扩散时，开口不会被微发光二极管芯片的阴极或者阳极堵塞，也就是，如果将开口设置在导电连接管侧壁靠近微发光二极管芯片的一侧，则有可能在将导电连接管刺入微发光二极管芯片的阴极或者阳极后，或者是在加热过程中，导电连接管和微发光二极管芯片的阴极或者阳极相互扩散时，微发光二极管芯片的阴极或者阳极会堵住导电连接管上的开口，导致导电连接管内的空气无法从开口排出。导电连接管的侧壁靠近薄膜晶体管层的一侧形成有开口，能够保证在加热导电连接管与微发光二极管芯片的阴极或者阳极，使其相互扩散过程中，在导电连接管内腔内的气体能够顺利从开口排出。
进一步的，在薄膜晶体管层背向衬底基板的一侧形成多个导电连接管，包括，
在薄膜晶体管背向衬底基板的一侧形成膜层，
在膜层上形成多个过孔，以露出薄膜晶体管层上的电极；
在膜层背向薄膜晶体管层的一侧以及过孔内形成金属层；
刻蚀金属层，形成带有开口的导电连接管。
在本发明的实施例中，膜层可以但不限于包括平坦层60和钝化层70。
参考图5，在薄膜晶体管层20背向衬底基板10的一侧依次形成平坦层60和钝化层70；
参考图7，在平坦层60和钝化层70上形成过孔71，以露出薄膜晶体管层上的第一电极31和第二电极32；
参考图8，在钝化层70背向平坦层60的一侧以及过孔71内形成金属层80；
参考图12，刻蚀金属层80、钝化层70以及平坦层60，形成带有开口41的导电连接管40；
将第一电极31通过第一导电连接管42与微发光二极管芯片50的阴极51绑定，将第二电极32通过第二导电连接管43与微发光二极管芯片50的阳极52绑定，或者，
将第一电极31通过第一导电连接管42与微发光二极管芯片50的阳极52绑定，将第二电极32通过第二导电连接管43与微发光二极管芯片50的阴极51绑定。
在电极层背向薄膜晶体管层的一侧涂覆有机膜形成平坦层，平坦层的厚度为3.0～4.0微米。在平坦层背向电极层的一侧沉积SiO，形成钝化层。
在平坦层和钝化层上形成过孔，以露出第一电极和第二电极，可以但不仅仅为，过孔的侧壁与电极层垂直，能够保证在过孔内形成的导电连接管与电极层垂直，在进行绑定时，使得导电连接管以及电极层能够均匀受力，避免导电连接管以及电极层在绑定过程中受损，降低了绑定难度。在形成金属层时，可以通过sputter(磁控溅射)工艺形成金属层。金属层与第一电极以及第二电极产生电气连接。刻蚀金属层、钝化层以及平坦层，形成带有开口的导电连接管，能够保证导电连接管的精度，并且在第一电极和第二电极上同时形成导电连接管，提高了阵列基板的加工效率。
参考图6，进一步的，刻蚀金属层80，形成带有开口41的导电连接管40，包括，在过孔71内填充光刻胶81，通过构图工艺保留过孔71内部分接触金属层80的光刻胶81；刻蚀未被光刻胶81覆盖的金属层80，形成带有开口41的导电连接管40。在本发明的实施例中，先用干法刻蚀钝化层，在钝化层上形成过孔，将钝化层作为掩模来刻蚀平坦层，从而在平坦层上也形成过孔，加工精度高并且加工效率高。构图工艺可以但不限于包括曝光、显影、刻蚀等步骤。
进一步的，在形成带有开口41的导电连接管40之后，刻蚀余下的膜层以及光刻胶81。
参考图9，进一步的，在金属层80背向薄膜晶体管层20的一侧并且在过孔71在金属层80上的正投影区域内涂覆光刻胶81，并部分露出形成于过孔71侧壁的金属层80，对金属层80和钝化层70进行一次刻蚀，对光刻胶81和平坦层60进行二次刻蚀，形成带有开口41的导电连接管40。
在本发明的实施例中，参考图9，一次刻蚀可以通过光刻工艺刻蚀掉未被光刻胶保护的金属层以及钝化层。参考图11，二次刻蚀可以通过等离子体刻蚀掉光刻胶和平坦层。
参考图10，在图10所示阴影部分为涂覆光刻胶的范围，其中未填充阴影部分为未涂覆光刻胶的范围，通过光刻工艺能够形成图3所示带有开口的导电连接管。
进一步的，将导电连接管40背向薄膜晶体管层20的一侧刺入微发光二极管芯片50的阴极51或者阳极52，加热导电连接管40以及微发光二极管芯片50的阴极51或者阳极52，以使导电连接管40与微发光二极管芯片50的阴极51或者阳极52绑定。
在本发明的实施例中，将导电连接管刺入微发光二极管芯片的阴极或者阳极，并对导电连接管以及微发光二极管芯片的阴极或者阳极进行加热，使得导电连接管与微发光二极管芯片的阴极或者阳极相互扩散，实现绑定，在加热过程中，导电连接管内残留的空气会从开口排出导电连接管，避免由于导电连接管内部气压升高导致绑定失效，提高了阵列基板的可靠性。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (13)

1.一种阵列基板，其特征在于，包括衬底基板，所述衬底基板的一侧形成有薄膜晶体管层，所述薄膜晶体管层背向所述衬底基板的一侧形成有多个导电连接管，所述薄膜晶体管层通过所述导电连接管与微发光二极管芯片电连接，所述导电连接管的侧壁靠近所述薄膜晶体管层的一侧形成有至少一个开口。
2.根据权利要求1所述的阵列基板，其特征在于，所述开口为沿着所述导电连接管的轴向贯穿所述导电连接管侧壁的通孔。
3.根据权利要求1所述的阵列基板，其特征在于，所述开口沿着所述导电连接管周向的长度小于或等于所述导电连接管周长的六分之一。
4.根据权利要求1所述的阵列基板，其特征在于，所述导电连接管侧壁的厚度大于或等于1000A。
5.根据权利要求1所述的阵列基板，其特征在于，所述导电连接管与所述薄膜晶体管层连接一侧的厚度大于或等于1000A。
6.根据权利要求1所述的阵列基板，其特征在于，所述导电连接管的材料为钨、铌、钛和钼中任意一种或者多种的组合。
7.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管层包括多个薄膜晶体管，每个所述薄膜晶体管包括源极、漏极、公共电极、第一电极和第二电极，所述第一电极和所述第二电极之间相互绝缘，所述源极或者所述漏极与所述第一电极连接，所述公共电极与所述第二电极连接，所述导电连接管包括第一导电连接管和第二导电连接管，所述第一电极与所述第一导电连接管连接，所述第二电极与所述第二导电连接管连接，
所述第一导电连接管与所述微发光二极管芯片的阴极连接，所述第二导电连接管与所述微发光二极管芯片的阳极连接，或者，
所述第一导电连接管与所述微发光二极管芯片的阳极连接，所述第二导电连接管与所述微发光二极管芯片的阴极连接。
8.根据权利要求7所述的阵列基板，其特征在于，所述微发光二极管芯片的阴极和阳极的硬度均小于所述导电连接管的硬度。
9.根据权利要求7所述的阵列基板，其特征在于，所述微发光二极管芯片的阴极和阳极的材料为铟、铜、银、金和铝中任意一种或者多种的组合。
10.一种显示装置，其特征在于，包括权利要求1～9任一项所述的阵列基板。
11.一种阵列基板的制造方法，其特征在于，包括以下步骤：
在衬底基板的一侧形成薄膜晶体管层；
在所述薄膜晶体管层背向所述衬底基板的一侧形成多个导电连接管，其中，所述导电连接管的侧壁靠近所述薄膜晶体管层的一侧形成有至少一个开口；
将所述导电连接管与微发光二极管芯片电连接。
12.根据权利要求11所述的阵列基板的制造方法，其特征在于，在所述薄膜晶体管层背向所述衬底基板的一侧形成多个导电连接管，包括，
在所述薄膜晶体管背向所述衬底基板的一侧形成膜层，
在所述膜层上形成多个过孔，以露出所述薄膜晶体管层上的电极；
在所述膜层背向所述薄膜晶体管层的一侧以及所述过孔内形成金属层；
刻蚀所述金属层，形成带有所述开口的所述导电连接管。
13.根据权利要求12所述的阵列基板的制造方法，其特征在于，刻蚀所述金属层，形成带有所述开口的所述导电连接管，包括，
在所述过孔内填充光刻胶，通过构图工艺保留所述过孔内部分接触所述金属层的所述光刻胶；
刻蚀未被所述光刻胶覆盖的所述金属层，形成带有所述开口的所述导电连接管。
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