WO2020199567A1 - 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法 - Google Patents

用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法 Download PDF

Info

Publication number
WO2020199567A1
WO2020199567A1 PCT/CN2019/113503 CN2019113503W WO2020199567A1 WO 2020199567 A1 WO2020199567 A1 WO 2020199567A1 CN 2019113503 W CN2019113503 W CN 2019113503W WO 2020199567 A1 WO2020199567 A1 WO 2020199567A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching
coupled plasma
inductively coupled
plasma etching
cavity
Prior art date
Application number
PCT/CN2019/113503
Other languages
English (en)
French (fr)
Inventor
李国强
孙佩椰
刘智崑
万利军
陈丁波
阙显沣
姚书南
李润泽
Original Assignee
华南理工大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华南理工大学 filed Critical 华南理工大学
Priority to JP2021557435A priority Critical patent/JP7318988B2/ja
Priority to US17/598,891 priority patent/US20220157609A1/en
Publication of WO2020199567A1 publication Critical patent/WO2020199567A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H01J37/3211—Antennas, e.g. particular shapes of coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/245—Detection characterised by the variable being measured
    • H01J2237/24564—Measurements of electric or magnetic variables, e.g. voltage, current, frequency
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the invention relates to the field of dry etching, in particular to a precise etching device and an etching method for preparing a grooved gate enhanced device.
  • GaN HEMT devices are considered to be one of the most ideal materials for next-generation power devices due to their high breakdown voltage, high electron mobility, and high saturation rate. They have been favored by researchers in recent years. Due to the strong spontaneous polarization and piezoelectric polarization effects, most conventional HEMT devices are depletion-type devices. In order to improve the safety and working efficiency of the circuit while saving design costs, it is of great significance to realize enhanced HEMT devices.
  • Cascode cascade technology is one of the earliest commercial enhancement-mode HEMT technologies.
  • the enhancement-mode silicon-based MOSFET is connected in series with a depletion-mode AlGaN/GaN HEMT device, and the HEMT device gate is connected to the source of the MOSFET to keep the HEMT channel open State, through the gate of the enhancement mode MOSFET to control the on-off of the overall channel, to achieve a high withstand voltage enhancement mode HEMT device.
  • the switching speed of this type of enhanced device is mainly determined by the silicon device, which greatly reduces the signal output frequency, limits the play of the advantages of GaN materials, and is difficult to package.
  • the F ion implantation technology introduces fluorine ions into the AlGaN barrier layer under the gate by ion implantation to increase the conduction band height of the AlGaN layer under the gate. When it rises above the Fermi level, the channel under the gate can be exhausted. The two-dimensional electron gas to realize enhanced devices.
  • F ion implantation will cause damage to the device, and due to the poor stability of F, it will cause problems such as poor device reliability and unstable threshold voltage.
  • the p-type gate structure is to introduce a layer of p-type doped GaN or AlGaN epitaxy between the un-doped AlGaN barrier layer and the gate metal to raise the conduction band of the entire heterojunction to deplete the channel under the gate
  • the 2DEG makes the device change from depletion type to enhanced type.
  • the selective growth and activation process of p-type GaN is very difficult, and such chips are extremely expensive. Therefore, it is difficult to realize the industrialization of enhanced HEMT devices with enhanced devices prepared by using Cascode cascade technology, F ion implantation technology and p-type gate structure.
  • the recessed gate structure is an AlGaN barrier layer with a certain thickness in the area below the etched gate to move the threshold voltage of the device in the positive direction, while reducing the distance between the gate and the two-dimensional electron gas channel layer to improve the control of the gate Ability to effectively reduce the short channel effect of the device, improve the transconductance of the device, and have excellent high-frequency characteristics. Therefore, the grooved gate structure is also the current enhancement mode AlGaN/GaN The research hotspot of HEMT device structure.
  • the use of grooved gate structure to prepare enhanced devices requires etching a certain depth of barrier layer. Because of the stable chemical properties of AlGaN, it is difficult to achieve through wet etching, and dry etching is usually used. However, in dry etching, it is difficult to control the etching depth, and different etching depths have a greater impact on the device characteristics, so precise control of the etching depth is required. At the same time, the plasma generated during the etching process has a high etching rate. If the process control is unreasonable or there are slight changes in the gas flow, temperature, and gas return in the reaction chamber, it will cause excessive etching and damage the next layer. The material affects the stability of the device and even causes the device to fail. Therefore, the design of a device and an etching method that can achieve precise etching is of positive significance for realizing the industrialization of the recessed gate enhanced HEMT device.
  • optical spectral emission method uses the intensity change of the wavelength light emitted by the plasma reactant or product to judge. At the end of the etching, the light intensity of the reactant becomes stronger, and the light intensity of the product weakens.
  • the etching rate is very slow or the etching area is small, the received light intensity signal is very weak and cannot be accurately detected.
  • Laser interferometry uses a laser light source to detect changes in film thickness to monitor the etching depth, but this method requires that the sample to be etched has good light transmittance, the laser must be focused on the etched area, and the temperature of the focused area Increase, affect the etching rate.
  • the purpose of the present invention is to provide a precise etching device and an etching method for preparing grooved gate enhanced devices.
  • the existing dry etching process has the disadvantages that it is difficult to control the etching depth and easily cause damage to the device.
  • the present invention provides a precise etching device for preparing grooved gate enhanced devices and its application in etching.
  • the erosion method can overcome the shortcomings of the existing technology.
  • the technical solution provided by the present invention is that the electrode of the penetrating plate in the plasma etching chamber is connected to the external current detection device, and the electrode is connected to the source and drain of the GaN HEMT device to form a current loop. Monitor the etching depth.
  • the barrier layer is continuously thinning, the two-dimensional electron gas concentration is reduced, and the current is reduced.
  • the enhancement mode is realized, and the etching is terminated, effectively avoiding excessive etching to cause the gate Leakage and damage the two-dimensional electron gas channel to achieve precise etching.
  • the invention provides a precise etching device for preparing groove grid enhanced devices, which includes an inductively coupled plasma etching chamber, a current detection device, an inductor coil, a radio frequency source, a mechanical pump, and a molecular pump; the current detection The device is connected to the inductively coupled plasma etching chamber through a wire; the inductive coil is connected to the inductively coupled plasma etching chamber; the radio frequency source is connected to the inductive coil; the mechanical pump and molecular pump are connected to the side of the inductively coupled plasma connection.
  • the inductively coupled plasma etching chamber includes a cavity, a base, a radio frequency bias power source, a penetrating electrode, a probe, a ceramic sleeve, and a gas valve.
  • two penetrating electrodes are arranged on the cavity side wall of the inductively coupled plasma etching cavity, the electrodes in the cavity are connected with probes to the source and drain of the HEMT device, and the electrodes outside the cavity are connected with the current detection device , Forming a current loop.
  • a susceptor is provided at the bottom (inside) of the cavity of the inductively coupled plasma etching chamber, and the lower part of the susceptor is connected to a radio frequency bias power source, which can increase the energy of plasma bombardment.
  • the cavity of the inductively coupled plasma etching chamber is provided with a susceptor for supporting the substrate to be etched, and a radio frequency bias power source is connected below the susceptor to increase the plasma bombardment energy.
  • the side wall of the inductively coupled plasma etching chamber is provided with penetration electrodes (two); one end of the penetration electrode is connected with the probe, and the other end of the penetration electrode is connected with the current detection device.
  • the probe is connected with the source and drain of the HEMT device; the ceramic sleeve is arranged on the upper part of the cavity of the inductively coupled plasma etching cavity, and the ceramic sleeve is connected to the cavity of the inductively coupled plasma etching cavity Connected, the ceramic sleeve is connected with the inductive coil; a ceramic sleeve communicating with the inductively coupled plasma etching chamber is arranged on the upper part of the inductively coupled plasma etching chamber, and the inductive coupling coil is wound on the outside of the sleeve, and the inductively coupled coil is connected Radio frequency source; the radio frequency current is passed into the inductively coupled coil, which can generate an alternating magnetic field and excite the process gas into a high-density plasma.
  • a gas valve is provided on the top of the ceramic sleeve, and the gas valve is communicated with the process gas pipeline.
  • the cavity bottom of the inductively coupled plasma etching chamber is provided with two valves connected to a mechanical pump and a molecular pump respectively, so that the mechanical pump and the molecular pump can vacuum the inductively coupled plasma etching chamber, and During the etching process, the reaction gas is timely removed.
  • the cavity side wall of the inductively coupled plasma etching cavity is provided with two through-plate electrodes, and in the cavity of the inductively coupled plasma etching cavity, the two through-plate electrodes are both connected to the to-be-etched through connecting probes.
  • the source and drain are connected; outside the cavity of the inductively coupled plasma etching chamber, two penetrating electrodes are connected with the current detection device to form a closed current loop.
  • the inductive coil is an inductively coupled coil, wound on a ceramic sleeve, the inductive coil is fed with a radio frequency current, which can generate an alternating magnetic field and excite the process gas into a high-density plasma.
  • the cavity of the inductively coupled plasma etching cavity is made of high-pressure resistant alloy steel.
  • the probe is a beryllium copper gold-plated probe.
  • the present invention provides an etching method for preparing a recessed gate enhanced HEMT device using the above-mentioned precise etching device, including the following steps:
  • the barrier layer of the HEMT device is continuously thinning, the two-dimensional electron gas concentration decreases, and the output current will also change accordingly.
  • the etching depth can be monitored in real time by observing the current, and the current will be reached when the current shows zero. Realize enhanced etching depth and finish etching;
  • the radio frequency source and the bias power source are turned off, and the etched substrate is sent out to obtain the grooved gate enhanced HEMT device.
  • step (6) using the relationship between the output current and the etching depth, the lead electrode in the etching cavity is connected to the external current detection device to form a closed current loop.
  • the present invention has the following advantages and beneficial effects:
  • the present invention cleverly uses the relationship between the thickness of the barrier layer and the two-dimensional electron gas concentration in the GaN HMET device, cleverly converted into the relationship between the etching depth and the current, and directly monitors the etching depth by observing the current change , Etching can be finished when the current is zero, intuitive, high precision and strong operability.
  • FIG. 1 is a schematic structural diagram of a precise etching device used to prepare a grooved gate enhanced device in an embodiment
  • FIG. 2 is a front view of the connection between the through-plate electrode and the inductively coupled plasma etching chamber in the precision etching device for preparing the groove-gated enhanced device in the embodiment;
  • FIG. 1 The structure diagram of the precise etching device of the present invention is shown in FIG. 1, and it includes an inductively coupled plasma etching chamber 1, a current detection device 6, an induction coil 8, a radio frequency source 10, a mechanical pump 11 and a molecular pump 12.
  • a pedestal 2 is provided at the center of the cavity bottom of the inductively coupled plasma etching cavity 1 for placing the substrate to be etched.
  • the pedestal 2 is connected to a radio frequency bias power source 3, and the radio frequency bias Power source 3 provides energy for ion bombardment;
  • Two through-plate electrodes 4 are provided in the middle of the cavity side wall of the inductively coupled plasma etching chamber 1.
  • the internal structure of the through-plate electrodes and the connection with the inductively coupled plasma etching chamber are shown in Figure 2.
  • the through-plate electrodes include The thick lead pipe 101, the thin lead pipe 102 and the lead, wherein the thick lead pipe is connected to the cavity side wall 103 of the inductively coupled plasma etching chamber, the thick lead pipe and the thin lead pipe are screwed together, and the thin lead hole is Consists of continuous leads; in the cavity of the inductively coupled plasma etching chamber 1, two through-plate electrodes 4 are respectively connected to two probes 5, and the two probes 5 are respectively the source and drain of the same unit on the substrate to be etched Connected; outside the cavity of the inductively coupled plasma etching chamber 1, the two through-plate electrodes 4 are both connected to the current detection device 6 to form a closed loop;
  • a ceramic sleeve 7 is arranged on the upper part of the cavity of the inductively coupled plasma etching chamber 1, an induction coil 8 is wound on the outside of the ceramic sleeve 7, and a gas valve 9 is arranged on the top; the induction coil 8 is connected to the radio frequency source 10 to generate The inductive alternating magnetic field excites the process gas discharged from the gas valve 9 into plasma;
  • Valves connected to the mechanical pump 11 and the molecular pump 12 are respectively provided at the bottom of the cavity of the inductively coupled plasma etching chamber 1, so that the mechanical pump 11 and the molecular pump 12 can vacuum the cavity 1 of the inductively coupled plasma etching chamber. , And take away the reactive gas in time during the etching process.
  • the etching method for preparing a recessed gate enhanced HEMT device by using the precise etching device includes the following steps:
  • the substrate to be etched is fed into the cavity of the inductively coupled plasma etching chamber 1, and the substrate to be etched is placed on the base 2;
  • the inductance coil 8 connected to the radio frequency source is supplied with radio frequency current, so that an alternating magnetic field 7 is generated in the ceramic sleeve wound by the inductance coil, and the Cl 2 and BCl 3 mixed gas Excited into plasma;
  • the etched substrate is sent out to obtain the grooved gate enhanced HEMT device.
  • This embodiment cleverly uses the relationship between the thickness of the barrier layer and the two-dimensional electron gas concentration in the GaN HMET device, and cleverly converts it into the relationship between the etching depth and the current.
  • the etching depth is directly monitored by observing the current change. Etching can be ended when it is zero, which is intuitive, high precision and strong operability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Analytical Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明公开了用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法。本发明提供的装置包括电感耦合等离子体刻蚀腔、电流检测装置、电感线圈、射频源、机械泵及分子泵；电流检测装置与电感耦合等离子体刻蚀腔连接；电感线圈与电感耦合等离子体刻蚀腔连接；射频源与电感线圈连接；机械泵和分子泵与电感耦合等离子体刻蚀腔连接。该装置在制备HEMT器件的过程中，当显示电流为零时，二维电子气沟道被关断，达到刻蚀终点，避免过度刻蚀造成栅极漏电及损伤二维电子气沟道，实现精准刻蚀。本发明仅额外接一个电流检测装置，无需增添额外的操作步骤，即可实现精确刻蚀，操作简便，有利于提高增强型HEMT器件产品良率，具有很高的实用价值。

Description

用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法 技术领域
本发明涉及干法刻蚀领域，具体涉及一种用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法。
 背景技术
GaN HEMT器件由于具有击穿电压大、电子迁移率高、饱和速率大等优点，被认为是下一代功率器件最理想的材料之一，近年来备受研究者青睐。由于较强的自发极化和压电极化效应，常规的HEMT器件大多为耗尽型器件。为了能够在节约设计成本的同时提高电路的安全性与工作效率，实现增强型HEMT器件具有重大意义。
为了实现增强型HEMT器件，常用的方法有Cascode级联技术、F离子注入技术、p型栅结构、凹槽栅结构。
Cascode级联技术是商用增强型HEMT最早采用的一种技术，将增强型硅基MOSFET与耗尽型的AlGaN/GaN HEMT器件串联，HEMT器件栅极连接MOSFET的源极使HEMT沟道保持常开状态，通过增强型MOSFET的栅极来控制整体沟道的通断，实现高耐压增强型HEMT器件。但这类增强型器件的开关速度主要由硅器件决定，大幅降低信号输出频率，限制GaN材料优势的发挥，且封装难度大。F离子注入技术通过离子注入的方式在栅下AlGaN势垒层中引入氟离子，提升栅下AlGaN层导带高度，当使其上升到了费米能级以上时即可耗尽了栅下沟道的二维电子气，实现增强型器件。但Ｆ离子注入会给器件带来损伤，且由于F稳定性差，会带来器件可靠性较差、阈值电压不稳定等问题。p型栅结构是在未人为掺杂的AlGaN势垒层和栅极金属之间引入一层p型掺杂的GaN或AlGaN外延，抬升整个异质结的导带从而耗尽栅极下方沟道中的2DEG，使器件由耗尽型转变到增强型。但p型GaN选择性生长和激活工艺难度都很大，此类芯片价格极为昂贵。因此，采用Cascode级联技术、F离子注入技术及p型栅结构制备的增强型器件均难以实现增强型HEMT器件产业化。
目前实现增强型HEMT器件较有前景的工艺技术是凹槽栅结构。凹槽栅结构是在刻蚀栅极下方区域一定厚度的AlGaN势垒层，使器件的阈值电压正向移动，同时减小栅极与二维电子气沟道层的间距,提高栅极的控制能力，有效降低器件的短沟道效应，提高器件跨导，具有优异的高频特性，因此凹槽栅结构也是目前增强型AlGaN/GaN HEMT器件结构的研究热点。
采用凹槽栅结构制备增强型器件，需要刻蚀一定深度的势垒层,由于AlGaN的化学性质稳定，因此难以通过湿法刻蚀实现，通常都采用干法刻蚀。但在干法刻蚀中，难以把控刻蚀深度，不同的刻蚀深度对器件特性具有较大影响，因此需要精准掌控刻蚀深度。同时，刻蚀过程中产生的等离子体具有较高的刻蚀速率，如果工艺控制不合理或反应腔室内气体流量、温度、气体回流等状态出现细微变化，都会造成过度刻蚀，损伤下一层材料，影响器件稳定性，甚至造成器件失效。因此，设计一种能够实现精准刻蚀的装置和刻蚀方法，对实现凹槽栅增强型HEMT器件产业化具有积极意义。
为准确控制刻蚀深度，业界内普遍使用的是光学光谱发射法和激光干涉法。光学光谱发射法是利用等离子体反应物或生成物所发射波长光的强度变化来判断，在刻蚀终点时反应物光强变强，生成物光强减弱。但该方法在刻蚀速率很慢或刻蚀面积很小时，所接收到的光强信号很弱，无法准确检测。激光干涉法是通过激光光源检测薄膜厚度的变化以实现监控刻蚀深度，但该方法要求被刻蚀样品的透光性好，激光必须聚焦在被刻蚀区域，且被激光聚焦的区域温度会升高，影响刻蚀速率。
以上的刻蚀方法均有其局限性，仍未能简便有效地实现精准刻蚀，还需配备专门的光学终点检测仪或激光装置，增加控制难度，提高成本。
 技术问题
为了克服现有技术存在的不足，本发明的目的是提供一种用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法。
目前现有的干法刻蚀工艺存在刻蚀深度难以控制、容易对器件造成损伤的不足，本发明提供的一种用于制备凹槽栅增强型器件的精准刻蚀装置和及其应用于刻蚀的方法，能够克服现有技术存在的不足。
 技术解决方案
为了实现上述目的，本发明提供的技术方案是在等离子体刻蚀腔内引穿板电极与外部电流检测装置导通，电极连接GaN HEMT器件的源漏极构成电流回路，通过观察电流变化，实时监控刻蚀深度。在刻蚀凹槽栅过程中，势垒层不断减薄，二维电子气浓度降低，电流减小，当电流为零时，即实现增强型，刻蚀终止，有效避免过度刻蚀造成栅极漏电及损伤二维电子气沟道，实现精准刻蚀。
本发明的目的至少通过如下技术方案之一实现。
本发明提供的一种用于制备凹槽栅增强型器件的精准刻蚀装置，包括电感耦合等离子体刻蚀腔、电流检测装置、电感线圈、射频源、机械泵及分子泵；所述电流检测装置通过导线与电感耦合等离子体刻蚀腔连接；所述电感线圈与电感耦合等离子体刻蚀腔连接；所述射频源与电感线圈连接；所述机械泵和分子泵与电感耦合等离子体的侧面连接。
进一步地，所述电感耦合等离子体刻蚀腔包括腔体、基座、射频偏置功率源、穿板电极、探针、陶瓷套筒以及气体阀门。
进一步地，所述电感耦合等离子体刻蚀腔的腔体侧壁上设置了两个穿板电极，在腔体内电极接探针与HEMT器件源漏极相连，在腔体外电极与电流检测装置相连，构成电流回路。
进一步地，所述电感耦合等离子体刻蚀腔的腔体底部（内部）设置基座，所述基座下部与射频偏置功率源连接，射频偏置功率源能够增加等离子体轰击的能量。
进一步地，所述电感耦合等离子体刻蚀腔的腔体内部设有承载待刻蚀基片的基座，基座下方连接射频偏置功率源，以便增加等离子体轰击能量。
进一步地，所述电感耦合等离子体刻蚀腔的腔体侧壁设置穿板电极（两个）；所述穿板电极一端与探针连接，穿板电极的另一端与电流检测装置连接。
进一步地，所述探针与HEMT器件源漏极连接；所述陶瓷套筒设置在电感耦合等离子体刻蚀腔的腔体上部，所述陶瓷套筒与电感耦合等离子体刻蚀腔的腔体连通，陶瓷套筒与电感线圈连接；在电感耦合等离子体刻蚀腔的腔体上部设置与电感耦合等离子体刻蚀腔相通的陶瓷套筒，套筒外侧有电感耦合线圈缠绕，电感耦合线圈连接射频源；在所述电感耦合线圈中通入射频电流，能够产生交变磁场，将工艺气体激发为高密度等离子体。
进一步地，所述陶瓷套筒的顶部设置气体阀门，通过气体阀门与工艺气体管道连通。
进一步地，所述电感耦合等离子体刻蚀腔的腔体底部设有分别与机械泵和分子泵连接的两个阀门，以便机械泵和分子泵对电感耦合等离子体刻蚀腔抽真空，以及在刻蚀过程中及时抽走反应气体。
进一步地，所述电感耦合等离子体刻蚀腔的腔体侧壁设置两个穿板电极，在电感耦合等离子体刻蚀腔的腔体内，两个穿板电极均通过连接探针与待刻蚀基片上（HEMT器件）源漏极相连；在电感耦合等离子体刻蚀腔的腔体外，两个穿板电极均与电流检测装置连接，构成电流闭合回路。
进一步地，所述电感线圈为电感耦合线圈，缠绕在陶瓷套筒上，电感线圈通入射频电流，能够产生交变磁场，将工艺气体激发为高密度等离子体。
进一步地，所述电感耦合等离子体刻蚀腔的腔体材质为耐高压合金钢。
进一步地，所述探针为铍铜镀金探针。
本发明提供的一种采用上述的精准刻蚀装置制备凹槽栅增强型HEMT器件的刻蚀方法，包括以下步骤：
（1）将待刻蚀基片送入电感耦合等离子体刻蚀腔的腔体内，放置在基座上；
（2）分别将探针、电流检测装置与穿板电极连接；
（3）分别将探针与器件同一单元的源漏极相接，构成闭合电流回路；
（4）打开机械泵和分子泵连接的阀门，使用机械泵和分子泵对电感耦合等离子体刻蚀腔的腔室抽真空，通入刻蚀气体；
（5）开启射频源及射频偏置功率源，对基片进行刻蚀；
（6）刻蚀过程中，HEMT器件的势垒层不断减薄，二维电子气浓度降低，输出电流也会随之变化，通过观察电流实时监控刻蚀深度，电流显示为零时即达到了实现增强型的刻蚀深度，结束刻蚀；
（7）关闭射频源及偏置功率源，将刻蚀后的基片送出，得到所述凹槽栅增强型HEMT器件。
进一步地，步骤（6）利用输出电流与刻蚀深度的关系，在刻蚀腔内引电极与外部电流检测装置导通构成电流闭合回路。
 有益效果
与现有技术相比，本发明具有如下优点和有益效果：
（1）本发明巧妙地运用了GaN HMET器件中势垒层厚度与二维电子气浓度间的关系特性，巧妙地转化为刻蚀深度与电流大小的关系，直接通过观察电流变化监控刻蚀深度，电流为零时即可结束刻蚀，直观，精度高，可操作性强。
（2）现有用于干法刻蚀中控制刻蚀深度的工艺大多是刻蚀终点检测和自停止刻蚀工艺，步骤复杂，精度有限；而本发明的刻蚀装置只需外接一个简易的电流检测装置，结构简单，结果直观，易控制，不增添额外的工艺步骤，有利于产业化。
（3）在刻蚀过程中，刻蚀工艺控制不合理或反应腔室内气体流量、温度、气体回流等状态出现细微变化，都会造成刻蚀异常，这些异常可通过电流变化异常反映出来，本发明提供的装置有利于及时发现处理，避免造成产品报废。
 附图说明
图1为实施例中用于制备凹槽栅增强型器件的精准刻蚀装置的结构示意图；
图2为实施例中用于制备凹槽栅增强型器件的精准刻蚀装置中穿板电极与电感耦合等离子体刻蚀腔的连接主视图；
其中，1. 电感耦合等离子体刻蚀腔；2. 基座；3. 射频偏置功率源；4. 穿板电极；5. 探针；6. 电流检测装置；7. 陶瓷套筒；8. 电感线圈；9. 气体阀门；10. 射频源；11. 机械泵；12. 分子泵。
 本发明的实施方式
以下结合附图和实例对本发明的具体实施作进一步说明，但本发明的实施和保护不限于此。需指出的是，以下若有未特别详细说明之过程，均是本领域技术人员可参照现有技术实现或理解的。
实施例1
本发明的精准刻蚀装置结构示意图如图1所示，包括电感耦合等离子体刻蚀腔1、电流检测装置6、电感线圈8、射频源10、机械泵11以及分子泵12。
在电感耦合等离子体刻蚀腔1的腔体底部中心位置设有一个基座2，用于放置待刻蚀基片，所述基座2与射频偏置功率源3相连，所述射频偏置功率源3提供离子轰击的能量；
在电感耦合等离子体刻蚀腔1的腔体侧壁中部设有两个穿板电极4，穿板电极的内部结构以及与电感耦合等离子体刻蚀腔连接如图2所示，穿板电极包括粗引线管101、细引线管102以及引线，其中粗引线管与电感耦合等离子体刻蚀腔的腔体侧壁103连接，所述粗引线管与细引线管间以螺纹连接，细引线孔中包含连续的引线；在电感耦合等离子体刻蚀腔1的腔体内，两个穿板电极4分别连接两根探针5，两根探针5分别与待刻蚀基片上同一单元的源漏极相连；在电感耦合等离子体刻蚀腔1的腔体外部，两个穿板电极4均与电流检测装置6相连，构成一个闭合回路；
在电感耦合等离子体刻蚀腔1的腔体上部设有一个陶瓷套筒7，陶瓷套筒7外侧缠绕有电感线圈8，顶部设有气体阀9；电感线圈8与射频源10相连，能够产生电感交变磁场，将从气体阀9排入的工艺气体激发为等离子体；
在电感耦合等离子体刻蚀腔1的腔体底部分别设有与机械泵11、分子泵12相连的阀门，以便机械泵11和分子泵12对电感耦合等离子体刻蚀腔的腔体1抽真空，及在刻蚀过程中及时抽走反应气体。
实施例2
以实施例2为例说明本发明的刻蚀方法，采用所述精准刻蚀装置制备凹槽栅增强型HEMT器件的刻蚀方法，包括如下的步骤：
（1）将待刻蚀的基片送入电感耦合等离子体刻蚀腔1的腔体内中，所述待刻蚀的基片放置于基座2上；
（2）将电流检测装置6与两个穿板电极4连接；
（3）将两个探针5分别与两个穿板电极4连接，调整探针5，使探针5分别与待刻蚀的基片器件中同一单元内的源漏极连接，构成闭合回路；
（4）开启机械泵11，对电感耦合等离子体刻蚀腔1的腔体抽真空；
（5）当真空度抽到150mTorr时，开启分子泵12，进一步抽真空至腔体内部压强为5mT；
（6）通过气体阀门9通入Cl 2和BCl 3混合气体；
（7）开启射频源10，功率参数设置为250W，与射频源连接的电感线圈8通入射频电流，使得电感线圈缠绕的陶瓷套筒内7产生交变磁场，将Cl 2和BCl 3混合气体激发为等离子体；
（8）开启射频偏置功率源3，功率参数设置为30W，增大离子轰击能量；
（9）刻蚀过程中，通过电流检测装置6观察电流变化，当电流显示为零时，达到刻蚀终点，关闭射频源10和射频偏置功率源3；
（10）刻蚀结束，将刻蚀后的基片送出，得到所述凹槽栅增强型HEMT器件。
本实施例巧妙地运用了GaN HMET器件中势垒层厚度与二维电子气浓度间的关系特性，巧妙地转化为刻蚀深度与电流大小的关系，直接通过观察电流变化监控刻蚀深度，电流为零时即可结束刻蚀，直观，精度高，可操作性强。
以上所述仅是本申请的具体实施方式，应当指出，对于本领域的技术人员，在不脱离本申请原理的前提下，可根据以上描述的技术方案以及构思，做出其它各种相应的改变以及变形，而所有的这些改变以及变形都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，包括电感耦合等离子体刻蚀腔、电流检测装置、电感线圈、射频源、机械泵及分子泵；所述电流检测装置通过导线与电感耦合等离子体刻蚀腔连接；所述电感线圈与电感耦合等离子体刻蚀腔连接；所述射频源与电感线圈连接；所述机械泵和分子泵与电感耦合等离子体刻蚀腔连接。
  2. 根据权利要求1所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感耦合等离子体刻蚀腔包括腔体、基座、射频偏置功率源、穿板电极、探针、陶瓷套筒以及气体阀门。
  3. 根据权利要求2所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感耦合等离子体刻蚀腔的腔体底部设置基座，所述基座下部与射频偏置功率源连接，所述射频偏置功率源能够增加等离子体轰击能量；所述电感耦合等离子体刻蚀腔的腔体侧壁设置穿板电极；所述穿板电极一端与探针连接，穿板电极的另一端与电流检测装置连接。
  4. 根据权利要求2所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述探针与待刻蚀基片上源漏极连接；所述陶瓷套筒设置在电感耦合等离子体刻蚀腔的腔体上部，陶瓷套筒与电感线圈连接；所述陶瓷套筒的顶部设置气体阀门，通过气体阀门与工艺气体管道连通。
  5. 根据权利要求2所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感耦合等离子体刻蚀腔的腔体底部设有分别与机械泵和分子泵连接的两个阀门，机械泵和分子泵能够通过阀门对电感耦合等离子体刻蚀腔的腔体内部抽真空以及在刻蚀过程中抽走反应气体。
  6. 根据权利要求1所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感耦合等离子体刻蚀腔的腔体侧壁设置两个穿板电极，在电感耦合等离子体刻蚀腔的腔体内，两个穿板电极分别连接两个探针，所述两个探针与待刻蚀基片上同一单元的源漏极相连；在电感耦合等离子体刻蚀腔的腔体外，两个穿板电极均与电流检测装置连接，构成电流闭合回路。
  7. 根据权利要求1所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感线圈为电感耦合线圈，缠绕在陶瓷套筒上，电感线圈通入射频电流，能够产生交变磁场，将工艺气体激发为高密度等离子体。
  8. 根据权利要求1所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述电感耦合等离子体刻蚀腔的腔体材质为耐高压合金钢。
  9. 根据权利要求1所述的用于制备凹槽栅增强型器件的精准刻蚀装置，其特征在于，所述探针为铍铜镀金探针。
  10. 一种采用权利要求1-9任一项所述的精准刻蚀装置制备凹槽栅增强型HEMT器件的刻蚀方法，其特征在于，包括以下步骤：
    （1）将待刻蚀基片送入电感耦合等离子体刻蚀腔的腔体内，所述待刻蚀基片放置在基座上；
    （2）分别将探针、电流检测装置与穿板电极连接；
    （3）分别将探针与待刻蚀基片上同一单元的源漏极相接，构成闭合电流回路；
    （4）打开机械泵和分子泵连接的阀门，使用机械泵和分子泵对电感耦合等离子体刻蚀腔的腔体内抽真空，通入刻蚀气体；
    （5）开启射频源及射频偏置功率源，对基片进行刻蚀；
    （6）刻蚀过程中，HEMT器件的势垒层不断减薄，二维电子气浓度降低，输出电流也会随之变化，通过观察电流实时监控刻蚀深度，电流显示为零时即达到了实现增强型的刻蚀深度，结束刻蚀；
    （7）关闭射频源及偏置功率源，将刻蚀后的基片送出，得到所述凹槽栅增强型HEMT器件。
PCT/CN2019/113503 2019-03-29 2019-10-27 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法 WO2020199567A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021557435A JP7318988B2 (ja) 2019-03-29 2019-10-27 リセスゲートエンハンスメントデバイスを製造するための高精度エッチング装置、及びそれを用いたエッチング方法
US17/598,891 US20220157609A1 (en) 2019-03-29 2019-10-27 Precise etching apparatus for preparing recessed-gate enhancement device and etching method for the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910252334.0A CN109887872A (zh) 2019-03-29 2019-03-29 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法
CN201910252334.0 2019-03-29

Publications (1)

Publication Number Publication Date
WO2020199567A1 true WO2020199567A1 (zh) 2020-10-08

Family

ID=66935294

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/113503 WO2020199567A1 (zh) 2019-03-29 2019-10-27 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法

Country Status (4)

Country Link
US (1) US20220157609A1 (zh)
JP (1) JP7318988B2 (zh)
CN (1) CN109887872A (zh)
WO (1) WO2020199567A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887872A (zh) * 2019-03-29 2019-06-14 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法
CN111081545A (zh) * 2019-12-18 2020-04-28 华南理工大学 一种实现p型栅增强型HEMT器件的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070231459A1 (en) * 2006-03-30 2007-10-04 Tokyo Electron Limited Change rate prediction method, storage medium, and substrate processing system
CN103745944A (zh) * 2014-02-10 2014-04-23 中国科学院微电子研究所 一种监控AlGaN/GaN HEMT凹栅槽刻蚀的方法
CN105870012A (zh) * 2016-04-21 2016-08-17 苏州能屋电子科技有限公司 通过原位刻蚀监控制备凹栅增强型hemt器件的方法及系统
CN105895519A (zh) * 2015-02-16 2016-08-24 朗姆研究公司 用于在狭小空间各向同性蚀刻硅的无残留的系统和方法
CN109887872A (zh) * 2019-03-29 2019-06-14 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58147123A (ja) * 1982-02-26 1983-09-01 Fujitsu Ltd 半導体層のエツチング処理方法
JP3127448B2 (ja) * 1990-05-22 2001-01-22 住友電気工業株式会社 エッチング制御方法
JP3144664B2 (ja) * 1992-08-29 2001-03-12 東京エレクトロン株式会社 処理装置及び処理方法
JPH11354509A (ja) * 1998-04-07 1999-12-24 Seiko Epson Corp プラズマエッチングの終点検出方法及びプラズマエッチング装置
JP2002294470A (ja) 2001-04-02 2002-10-09 Sony Corp エッチング方法
JP4657620B2 (ja) 2004-04-13 2011-03-23 株式会社日立ハイテクノロジーズ プラズマ処理装置
JP2008288437A (ja) 2007-05-18 2008-11-27 Toshiba Corp プラズマ処理装置及びプラズマ処理方法
CN101640230A (zh) * 2009-09-04 2010-02-03 中国电子科技集团公司第十一研究所 一种用于双色碲镉汞器件的干法刻蚀方法及刻蚀装置
KR101952176B1 (ko) * 2012-07-30 2019-02-26 엘지전자 주식회사 인헨스먼트 질화물 반도체 소자 및 이의 제조 방법
JP2016218029A (ja) 2015-05-18 2016-12-22 インクス株式会社 積層型のコンタクトプローブ
CN106048531A (zh) * 2016-07-28 2016-10-26 苏州大学 ICP增强多靶磁控溅射装置及使用该装置制备TiO2薄膜的方法
CN107768248A (zh) * 2016-08-19 2018-03-06 中国科学院苏州纳米技术与纳米仿生研究所 GaN基增强型HEMT器件的制备方法
KR101826883B1 (ko) 2016-11-03 2018-02-08 인투코어테크놀로지 주식회사 유도 코일 구조체 및 유도 결합 플라즈마 발생 장치
CN209929264U (zh) * 2019-03-29 2020-01-10 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070231459A1 (en) * 2006-03-30 2007-10-04 Tokyo Electron Limited Change rate prediction method, storage medium, and substrate processing system
CN103745944A (zh) * 2014-02-10 2014-04-23 中国科学院微电子研究所 一种监控AlGaN/GaN HEMT凹栅槽刻蚀的方法
CN105895519A (zh) * 2015-02-16 2016-08-24 朗姆研究公司 用于在狭小空间各向同性蚀刻硅的无残留的系统和方法
CN105870012A (zh) * 2016-04-21 2016-08-17 苏州能屋电子科技有限公司 通过原位刻蚀监控制备凹栅增强型hemt器件的方法及系统
CN109887872A (zh) * 2019-03-29 2019-06-14 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法

Also Published As

Publication number Publication date
CN109887872A (zh) 2019-06-14
JP7318988B2 (ja) 2023-08-01
US20220157609A1 (en) 2022-05-19
JP2022528648A (ja) 2022-06-15

Similar Documents

Publication Publication Date Title
US10811296B2 (en) Substrate support with dual embedded electrodes
CN104143513B (zh) 纳米真空场效应电子管及其形成方法
WO2020199567A1 (zh) 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法
TWI555080B (zh) Dry etching method
TWI603368B (zh) Plasma processing apparatus and plasma processing method
CN110729362B (zh) 基于低功函数阳极金属的低开启电压GaN微波二极管及制备方法
US9786471B2 (en) Plasma etcher design with effective no-damage in-situ ash
JP2018037656A (ja) セルフアライン式マルチパターニングのためのその場スペーサ再整形方法及びシステム
WO2023024966A1 (zh) 一种具有新型源漏场板结构的hemt器件及制备方法
CN209929264U (zh) 用于制备凹槽栅增强型器件的精准刻蚀装置
CN105870012B (zh) 通过原位刻蚀监控制备凹栅增强型hemt器件的方法及系统
CN110707158B (zh) 阳极边缘浮空的GaN微波二极管及制备方法
CN110047748A (zh) 一种低损伤AlGaN/GaNHEMT栅槽刻蚀方法
CN107195525B (zh) 一种电感耦合等离子体刻蚀设备
CN105810607A (zh) 通过原位刻蚀监控实现p型氮化物增强型hemt的方法及系统
WO2018233455A1 (zh) 偏压调制方法、偏压调制系统和等离子体处理设备
CN107342221B (zh) 一种SiC基GaN晶体的深孔刻蚀方法
CN104733275A (zh) 等离子体工艺设备
CN108962741A (zh) 一种刻蚀方法
CN103247526A (zh) 一种适合于亚微米栅长半导体器件制造的栅介质刻蚀方法
CN113555283A (zh) 一种刻蚀GaN基高电子迁移率晶体管异质结的方法
CN113314416B (zh) 一种GaN-HEMT器件上倾角结构的制备方法
CN113764509B (zh) 一种增强型电容耦合GaN毫米波开关器件及其制造方法
KR20140145468A (ko) 자성체를 이용한 플라즈마 식각장치
US12009220B2 (en) Method for processing workpiece, plasma processing apparatus and semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19922372

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021557435

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19922372

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21.01.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 19922372

Country of ref document: EP

Kind code of ref document: A1