WO2020199540A1 - 阵列基板及其测试方法、制造方法和测试装置以及显示面板制造方法 - Google Patents

阵列基板及其测试方法、制造方法和测试装置以及显示面板制造方法 Download PDF

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WO2020199540A1
WO2020199540A1 PCT/CN2019/108643 CN2019108643W WO2020199540A1 WO 2020199540 A1 WO2020199540 A1 WO 2020199540A1 CN 2019108643 W CN2019108643 W CN 2019108643W WO 2020199540 A1 WO2020199540 A1 WO 2020199540A1
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Prior art keywords
test
array substrate
driving
pixel circuit
substrate according
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PCT/CN2019/108643
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English (en)
French (fr)
Inventor
白国晓
关江兵
谢乐
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云谷（固安）科技有限公司
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Publication of WO2020199540A1 publication Critical patent/WO2020199540A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and its testing method, manufacturing method, testing device, and display panel manufacturing method.
  • organic electroluminescent displays have a series of advantages such as autonomous light emission, low-voltage DC drive, all-solid-state, wide viewing angle, and rich colors.
  • organic electroluminescent displays do not require a backlight, have a large viewing angle, and Low, its response speed can reach 1000 times that of liquid crystal displays. Therefore, organic electroluminescent displays have broad application prospects and are regarded as one of the most competitive future flat panel display technologies.
  • the organic electroluminescent display achieves light emission through multiple sub-pixels with different colors of light emitted, and each sub-pixel needs to be driven by a corresponding pixel circuit to achieve light emission. Therefore, an organic electroluminescent display will have tens of thousands or even With millions of pixel circuits, how to effectively test these pixel circuits is a big project, and the current testing technology is not convenient enough.
  • the purpose of the present application is to provide an array substrate, a testing method, a manufacturing method, a testing device, and a display panel manufacturing method that can implement convenient electrical testing.
  • an embodiment of the present application provides an array substrate, including a substrate, a plurality of pixel circuits on the substrate, and a plurality of test patterns corresponding to the plurality of pixel circuits, the pixel circuit including a driving unit ,
  • the test pattern is electrically connected to the driving unit, and the test pattern is used to obtain the test signal output by the driving unit.
  • an embodiment of the present invention is a testing device for testing the above-mentioned array substrate, which includes a connection unit and a processing unit; the connection unit is electrically connected to the processing unit;
  • connection unit is electrically connected to the test pattern, and outputs a test signal to the processing unit;
  • the processing unit is used for judging whether the array substrate has defects according to the test signal.
  • a plurality of the pixel circuits form a driving area; the test pattern is located in the driving area;
  • the connecting unit is a connecting terminal, and the connecting terminal is located outside the driving area;
  • the test signal can be obtained by the test pattern provided on the array substrate.
  • the test signal can be used to detect whether the pixel circuit has defects, and the detection process is simple and convenient.
  • FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an array substrate with a testing device according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 4 is a cross-sectional view of an array substrate according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a testing method of an array substrate according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of timing control of a pixel circuit according to an embodiment of the present application.
  • FIG. 7 is a structural block diagram of a testing device according to an embodiment of the present application.
  • FIG. 11 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the present application.
  • FIG. 12 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present application.
  • FIG. 13 is a partial structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 14 is a cross-sectional view of a display panel according to an embodiment of the present application.
  • FIG. 15 is a flowchart of a manufacturing method of a display panel according to another embodiment of the present application.
  • an embodiment of the present application provides a display panel 100.
  • the display panel 100 may be an organic electroluminescence display panel.
  • the display panel 100 includes an array substrate 10 and a plurality of sub-pixels 20 arranged on the array substrate 10 and arranged in an array.
  • the plurality of sub-pixels 20 may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light, but it is not limited to this, and may also include sub-pixels emitting light of other colors. A variety of colors of emitted light can be realized.
  • the array substrate 10 includes a substrate 11, a plurality of pixel circuits 12 on the substrate 11 and a plurality of test patterns A corresponding to the plurality of pixel circuits 12.
  • each pixel circuit 12 is used to drive a corresponding sub-pixel 20, so as to realize the sub-pixel 20 to emit light.
  • FIG. 3 is a schematic diagram of the pixel circuit 12 of this embodiment.
  • the dotted frame in FIG. 3 shows the light-emitting diode 21 subsequently manufactured in the pixel circuit 12.
  • the array substrate 10 of this embodiment does not include the light-emitting diode 21 itself.
  • the sub-pixel 20 includes a light emitting diode 21.
  • the light emitting diode 21 may be an organic light emitting diode.
  • the pixel circuit 12 is actually used to drive the light emitting diode 21 to emit light.
  • the array substrate 10 includes row control lines extending along the row direction X and column direction control lines extending along the column direction Y.
  • the horizontal control line may be a scan line that issues scan signals Scan1, Scan2, Scan3, etc., a control line that issues a control signal EM, and so on.
  • the column control line may be a data line that outputs a data voltage Vdata, etc.
  • the data voltage Vdata output by the data line is used to provide image data for the sub-pixel 20 corresponding to the column, for example, includes red data for carrying the red data signal to the red sub-pixel Line, a green data line for carrying the green data signal to the green sub-pixel, and a blue data line for carrying the blue data signal to the blue sub-pixel.
  • Each control line can be controlled by integrated circuits.
  • the horizontal control line can be controlled by a GIP (Gate in Panel) circuit 13.
  • the horizontal control line can also be controlled by a GOA (Gate Driver on Array) circuit.
  • the array substrate 10 In the actual manufacturing process of the display panel, in order to ensure that the array substrate 10 can drive several sub-pixels 20 normally, after the array substrate 10 is fabricated and before the sub-pixels 20 are fabricated, the pixel circuits 12 on the array substrate 10 need to be electrically performed. In this way, it is possible to avoid defects such as uneven display in the subsequently manufactured display panel 100 due to defects of the array substrate 10.
  • the pixel circuit 12 includes a driving unit 121, the test pattern A is electrically connected to the driving unit 121, and the test pattern A is used to obtain the test signal S TEST output by the driving unit 121.
  • This embodiment can be A test pattern on the array substrate 10 by providing the test signal to obtain S TEST, the test signal S TEST circuit 12 may be used to detect the presence or absence of the pixel defect detection process is simple and convenient.
  • the driving unit 121 includes a driving transistor T1, and the test pattern A is electrically connected to the drain D of the driving transistor T1.
  • the test pattern A can be made of a metal material, and can be a metal conductive layer, such as a metal conductive film.
  • the pixel circuit 12 also includes an energy storage unit 122, charging channels L1, L2, and a test channel L3.
  • the energy storage unit 122 is connected to the driving transistor T1, and the energy storage unit 122 may include a capacitor C1.
  • the charging channels L1 and L2 are connected to the energy storage unit 122, and the charging channels L1 and L2 are used to charge the capacitor C1 and turn on the driving transistor T1.
  • the capacitor C1 may be connected to the gate of the driving transistor T1, and the charging channels L1 and L2 may be connected respectively.
  • the test channel L3 is connected to the power supply voltage VDD and the driving transistor T1.
  • the test channel L3 is used to load the power supply voltage VDD to the driving transistor T1, and the power supply voltage VDD is used to generate the test signal S TEST .
  • the power supply voltage VDD may be electrically connected to the source of the driving transistor T1.
  • the driving unit 121 may also have other structures.
  • test The pattern A is electrically connected to the drain D of the driving transistor T1 may mean that the test pattern A is directly connected to the drain D of the driving transistor T1, or there are other structures such as a switch between the test pattern A and the drain D of the driving transistor T1 Transistor, when the switching transistor is turned on, the drain D of the driving transistor T1 is indirectly connected to the test pattern A.
  • test The pattern A is electrically connected to the drain D of the driving transistor T1
  • test pattern A is directly connected to the drain D of the driving transistor T1
  • there are other structures such as a switch between the test pattern A and the drain D of the driving transistor T1 Transistor, when the switching transistor is turned on, the drain D of the driving transistor T1 is indirectly connected to the test pattern A.
  • other parts please refer to the description here.
  • first component is described as connecting the second component, that is, the first component is directly connected to the second component, and there are no other components between the first component and the second component, and the description of other parts can be referred to here.
  • the drain D of the driving transistor T1 needs to be electrically connected to the light emitting diode 21 to form the display panel 100, and the drain D of the driving transistor T1 is electrically connected to the light emitting diode
  • the first electrode 211 (generally an anode) of 21, that is, the test signal S TEST simulates the actual signal that finally flows into the light emitting diode 21 through the first electrode 211.
  • the array substrate 10 of this embodiment includes a test pattern A electrically connected to the drain D of the driving transistor T1.
  • the pixel circuit 12 keeps the driving transistor T1 in an on state through the charging process of the energy storage unit 122, and applies the power supply voltage VDD to the driving
  • the transistor T1 obtains the test signal S TEST output by the driving transistor T1 through the test pattern A.
  • the test signal S TEST is used to perform an electrical test of the pixel circuit 12.
  • the test signal S TEST is actually a signal that subsequently flows into or is applied to the light emitting diode 21 through the first electrode 211, that is, this embodiment simulates the display process of the display panel 100 ( That is, the pixel circuit 12 is charged to turn on the driving transistor T1, and then the power supply voltage VDD is applied to the driving transistor T1 to drive the connected light-emitting diode 21 to emit light) to perform an electrical test of the pixel circuit 12, so that all parts of the pixel circuit 12 are tested
  • the defect detection rate of the pixel circuit 12 is high, and the reliability of defect detection is high, which can greatly improve the timeliness of process management and control, and because the test process simulates the display process of the display panel 100, the array can be greatly improved.
  • test patterns A are connected to each other to form a test pattern string B.
  • test patterns A located in the same column are connected to each other to form a long test pattern string B.
  • test signals A of all pixel circuits 12 in the column can be transmitted through the test pattern string B, which greatly simplifies the test Process and test device.
  • a pixel circuit 12 including 7 TFTs and 1 storage capacitor is taken as an example for description.
  • the pixel circuit 12 includes a capacitor C1, a driving transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6 (that is, a control signal input terminal transistor), and a Seven switch transistors T7, and the pixel circuit 12 is used to receive the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, the data voltage Vdata, the control signal EM, the power supply voltage VDD, the reference voltage Vref (or the initial voltage Vinit ).
  • the connection relationship between the various elements in the pixel circuit 12 is as shown in FIG. 3, and the test method of the array substrate 10 will be described in detail.
  • all the transistors in this embodiment are PMOS transistors.
  • the drive signal including the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3 and the control signal EM
  • the corresponding transistor Will be turned on
  • the data voltage Vdata and the power supply voltage VDD are positive voltages
  • the reference voltage Vref is negative voltages.
  • an insulating layer 124 is provided between the metal layer 123 connected to the drain D of the driving transistor T1 and the test pattern A, that is, the metal layer 123 and the test pattern A are located in different layers, and the test The pattern A penetrates a part of the insulating layer 124 to conduct the metal layer 123, that is, the test pattern A is electrically connected to the drain D of the driving transistor T1 at this time.
  • pixel circuits 12 jointly form a driving area P (refer to FIG. 2 ), and the driving area P corresponds to the display area of the display panel 100.
  • the test pattern A is located in the driving area P, that is, the formation area of the test pattern A does not exceed the display area of the display panel 100.
  • the testing method of the array substrate 10 of this embodiment includes the following steps Step1 to Step4:
  • Step1 Provide the above-mentioned array substrate 10.
  • the array substrate 10 includes a test pattern A electrically connected to the drain D of the driving transistor T1.
  • the test pattern A is actually connected to the drain D of the sixth switch transistor T6 (control signal input transistor) and the seventh switch
  • the drain of the transistor T7, that is, the test pattern A and the drain D of the driving transistor T1 are electrically connected indirectly.
  • the sub-pixel 20 has not yet been formed on the array substrate 10.
  • Step2 Control the driving unit 121 in the pixel circuit 12 to output the test signal S TEST .
  • the driving unit 121 takes the driving transistor T1 as an example.
  • step Step2 is: turn on the charging channels L1 and L2 to charge the capacitor C1 to turn on the driving transistor T1; turn on the test channel L3 so that the power supply voltage VDD is applied to the driving transistor T1.
  • the charging channel includes a first charging channel L1 and a second charging channel L2.
  • the first charging channel L1 is a channel from the reference voltage Vref to the capacitor C1, and may include a fourth switching transistor T4.
  • the source of the fourth switching transistor T4 is connected to the reference voltage Vref
  • the drain of the fourth switching transistor T4 is connected to the capacitor C1 and the gate of the driving transistor T1, respectively
  • the gate of the fourth switching transistor T4 is electrically connected to the first A scan signal Scan1.
  • the second charging channel L2 is a channel from the data voltage Vdata to the capacitor C1, and may include a second switching transistor T2, a driving transistor T1, and a third switching transistor T3 connected in series in sequence.
  • the source of the second switching transistor T2 is connected to the data voltage Vdata
  • the drain of the second switching transistor T2 is connected to the source of the driving transistor T1 and the drain of the fifth transistor T5, and the gate of the second switching transistor T2
  • the electrode is electrically connected to the second scan signal Scan2 and the gate of the third transistor T3; the drain of the first transistor T1 is connected to the source of the third transistor T3, and the gate of the first transistor T1 is connected to the drain of the third transistor T3.
  • Connected to the first end of the capacitor C1; the second end of the capacitor C1 is connected to the power supply voltage VDD.
  • the test channel L3 is a channel from the power supply voltage VDD to the sixth transistor T6, and may include a fifth switching transistor T5, a driving transistor T1, and a sixth switching transistor T6 connected in series in sequence.
  • the source of the fifth switching transistor T5 is connected to the power supply voltage VDD
  • the drain of the fifth switching transistor T5 is connected to the source of the driving transistor T1
  • the drain of the driving transistor T1 is electrically connected to the source of the sixth switching transistor T6
  • the gate of the sixth switching transistor T6 is connected to the control signal EN, and the drain of the sixth switching transistor T6 is connected to the test pattern A.
  • Step 2 includes: turning on the first charging channel L1 so that the reference voltage Vref charges the capacitor C1, the driving transistor T1 is turned on, and then turning on the second charging channel L2 so that the data voltage Vdata charges the capacitor C1.
  • the fourth switch The transistor T4 is turned on, and the reference voltage Vref charges the capacitor C1 through the fourth switching transistor T4 (that is, the first charging channel L1 is turned on). At this time, the reference voltage Vref can also be transmitted to the gate G of the driving transistor T1. T1 is turned on.
  • the second scan signal Scan2 and the third scan signal Scan3 are at a low level
  • the first scan signal Scan1 and the control signal EM are both at a high level
  • the second switching transistor T2 and the first The three switching transistor T3 and the seventh switching transistor T7 are turned on, and the data voltage Vdata sequentially passes through the second switching transistor T2, the driving transistor T1, and the third switching transistor T3 to charge the capacitor C1 twice (that is, the second charging channel L2 is turned on) .
  • the data voltage Vdata charges the capacitor C1, so that there is enough power in the capacitor C1, so that the driving transistor T1 connected to the capacitor C1 can be kept in an on state.
  • the reference voltage Vref is transmitted through the seventh switching transistor T7 to the drain D of the sixth switching transistor T6 (that is, the position subsequently electrically connected to the first electrode 211 of the light-emitting diode 21) for initializing the first electrode 211 of the light-emitting diode 21 An electrode 211.
  • the reference voltage Vref applied to the seventh switching transistor T7 can be obtained through the test pattern A. If the reference voltage Vref showing a negative voltage is obtained, the seventh switching transistor T7 has no defect; otherwise, the first The seven-switch transistor T7 has defects.
  • the third scan signal Scan3 can also be turned on during the first charging phase M1, that is, during the first charging phase M1, the reference voltage Vref is transmitted to the drain D of the sixth switching transistor T6 through the seventh switching transistor T7. Realize initialization.
  • the control signal EM is at a low level
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all at a high level
  • the fifth switch transistor T5 is turned on
  • the power supply voltage VDD sequentially passes through the fifth switching transistor T5, the driving transistor T1, and the sixth switching transistor T6 to be transferred to the test pattern A.
  • Step3 The test pattern A acquires the test signal S TEST .
  • test signal S TEST is preferably a test current, but not limited to this, and the test signal S TEST finally obtained may also be a test voltage or the like.
  • Step4 Determine whether the pixel circuit 12 is defective according to the test signal S TEST .
  • Step 4 may specifically be: judging whether the value of the test signal S TEST is within the threshold range, if so, the pixel circuit 12 has no defect, if not, the pixel circuit 12 has a defect.
  • the value of the threshold range is related to the power supply voltage VDD. According to different power supply voltages VDD, different threshold ranges can be set. Of course, as the test environment, pixel circuit 12, etc. change, the threshold range can also be changed accordingly , The details can be determined according to the actual situation.
  • the test method of the array substrate 10 of this embodiment performs the electrical test of the pixel circuit 12 through the test signal S TEST output by the driving transistor T1.
  • the test signal S TEST is actually the subsequent signal that flows into the light emitting diode 21 through the first electrode 211, that is, this
  • the electrical test of the pixel circuit 12 is performed by simulating the display process of the display panel 100, so that all parts of the pixel circuit 12 are tested, the defect detection rate of the pixel circuit 12 is high, and the defect detection is reliable Therefore, the timeliness of process control can be greatly improved, and since the test process simulates the display process of the display panel 100, the matching of defect detection between the test phase of the array substrate 10 and the subsequent light-emitting diode 21 lighting test phase can be greatly improved.
  • the pixel circuit 12 of this embodiment charges the capacitor C1 twice, so that enough power is stored in the capacitor C1, so as to ensure that the driving transistor T1 connected to the capacitor C1 remains in the fully-on state during the test phase M3, and the power supply voltage VDD can be It is applied to the driving transistor T1 unimpededly, so that the obtained test signal S TEST is more accurate and reliable.
  • test method of this embodiment is not only applicable to the aforementioned pixel circuit 12, but also applicable to other pixel circuits.
  • this embodiment also provides a test device 30 for the array substrate 10.
  • the test device 30 includes a connecting unit 31 and a processing unit 32 connected to each other.
  • the connecting unit 31 is used to electrically connect the test pattern A and output the test signal S TEST .
  • the processing unit 32 is used to determine whether the array substrate 10 has a defect according to the test signal S TEST .
  • the connecting unit 31 is a connecting terminal, and the connecting unit 31 is located outside the driving area P (for example, corresponding to the non-display area of the display panel 100).
  • the testing device 30 further includes a pin assembly 33, which may include a pin 331 and a lead 332 connected to each other (refer to FIG. 2), and the pin 331 contacts and connects to the connecting unit 31 to obtain a test signal.
  • the lead 332 connects the pin 331 and the processing unit 32 to transmit the test signal S TEST to the processing unit 32.
  • the processing unit 32 is, for example, an external terminal device.
  • the processing unit 32 compares the value of the test signal S TEST with a threshold range to determine whether the corresponding pixel circuit 12 has a defect.
  • test patterns A in the same column are connected to each other to form a long test pattern string B, and a long test pattern string B is connected to a connecting unit 31.
  • the All test signals S TEST output by the column pixel circuit 12 can be sequentially transmitted to the processing unit 32 through the test pattern string B and the corresponding connection unit 31.
  • the lead structure of the test signal S TEST can be greatly simplified, that is, this At this time, only one row of connecting units 31 is needed to realize the transmission of the test signal S TEST of all the pixel circuits 12.
  • test pattern string B is not limited to extending along the column direction Y, and the test pattern string B can also take other forms.
  • testing device 30 may also include a data output unit 34, which can be used to provide input signals for data lines, scan lines, etc., for example, the data output unit 34 is used to connect to the GIP circuit 13 to provide scan signals Scan1, Scan2, Scan3, control signal EM, etc.
  • a data output unit 34 which can be used to provide input signals for data lines, scan lines, etc.
  • the data output unit 34 is used to connect to the GIP circuit 13 to provide scan signals Scan1, Scan2, Scan3, control signal EM, etc.
  • a first signal terminal 341 (refer to FIG. 2) may be provided on the side of the GIP circuit 13 away from the pixel circuit 12, and the data output unit 34 inputs relevant data to the GIP circuit 13 through the first signal terminal 341.
  • a second signal terminal 342 may also be provided on the side of the data line away from the pixel circuit 12, and the data output unit 34 inputs relevant data to the data line through the second signal terminal 342.
  • first signal terminal 341 or second signal terminal 342 it is impossible to connect a signal terminal (first signal terminal 341 or second signal terminal 342) to a line (wire or data line in GIP circuit 13).
  • a demultiplexer 343 or a selection switch or the like can be arranged between the signal terminal and the corresponding line. In this way, the random selection of each line can be realized.
  • the first signal terminal 341, the second signal terminal 342 and other structures can be removed, but it is not limited to this.
  • test results of the test signal S TEST indicated by the processing unit 32 are shown.
  • the column of pixel circuits 12 Take the leftmost column of pixel circuits 12 as an example for description.
  • the column of pixel circuits 12 are defined as pixel circuits X1Y1 from top to bottom.
  • the test signal output by the pixel circuit X1Y4 is S4, the test signal output by the pixel circuit X1Y5 is S5, and the test signal output by the pixel circuit X1Y6 is S6.
  • the waveforms of the test signals S1 to S6 are normal, it means that the column of pixel circuits 12 is free of defects; referring to Fig. 9, if the waveform of the test signal S4 is abnormal, and the waveforms of other test signals are normal, it means this When the pixel circuit X1Y4 has a defect, the other pixel circuits 12 have no defects; referring to FIG. 10, if the waveforms of the test signals S1 to S6 are abnormal, it means that the data line corresponding to the pixel circuit 12 is very likely to be abnormal.
  • test signals S in the same row are all abnormal, it means that it is most likely that the scan line (or control line) of the pixel circuit 12 of the row is abnormal.
  • the condition of the pixel circuit 12 can be accurately obtained according to the waveform of the test signal S output by the processing unit 32, the defect detection rate of the pixel circuit 12 is high, and the reliability of the defect detection is high, which can greatly improve the process control. Timeliness.
  • An embodiment of the present application also provides a method for manufacturing the array substrate 10.
  • the method for manufacturing the array substrate 10 includes steps Step11 to Step13:
  • Step11 provide a substrate 10
  • Step 12 a number of pixel circuits 12 are formed on the substrate 10, and the pixel circuits 12 include a driving unit 121.
  • the pixel circuit 12 includes a driving transistor T1.
  • the pixel circuit 12 also includes a capacitor C1, charging channels L1, L2 for charging the capacitor C1 and turning on the driving transistor T1, and a power supply voltage VDD applied to the driving transistor T1.
  • Test channel L3 is a power supply voltage applied to the driving transistor T1.
  • Step 13 forming a test pattern A electrically connected to the driving unit 121.
  • test pattern A electrically connected to the drain D of the driving transistor T1 is formed.
  • an insulating layer 124 and a test pattern A electrically connected to the metal layer 123 are sequentially formed on the side of the metal layer 123 away from the substrate 11.
  • the metal layer 123 is connected to the drain D of the driving transistor T1, and the test patterns A are located in several pixel circuits. 12 formed in the drive area P.
  • the array substrate 10 obtained by the manufacturing method of this embodiment includes a test pattern A electrically connected to the drain D of the driving transistor T1.
  • the pixel circuit 12 keeps the driving transistor T1 in an on state through the charging process, and applies the power supply voltage VDD to the driving transistor.
  • T1 the test signal S output by the driving transistor T1 is obtained through the test pattern A.
  • the test signal S is used to perform an electrical test of the pixel circuit 12.
  • the test signal S is actually a signal that subsequently flows into the light emitting diode 21 through the first electrode 211, namely
  • the electrical test of the pixel circuit 12 is performed by simulating the display process of the display panel 100, so that all parts of the pixel circuit 12 are tested, the defect detection rate of the pixel circuit 12 is high, and the defect detection can be The reliability is high, which can greatly improve the timeliness of process management and control, and since the test process simulates the display process of the display panel 100, the defect detection matching degree of the array substrate 10 test stage and the subsequent LED 21 lighting test stage can be greatly improved.
  • An embodiment of the present application also provides a manufacturing method of the display panel 100.
  • the manufacturing method of the display panel 100 includes the steps:
  • the test pattern A is etched to form the first electrode 211;
  • a light-emitting function layer 212 and a second electrode 213 are formed on the side of the first electrode 211 away from the substrate 11.
  • the first electrode 211, the light-emitting function layer 212, and the second electrode 213 cooperate to form the light-emitting diode 21.
  • the light-emitting functional layer 212 may include a cave injection layer, an organic emitter, an electron transport layer, etc., and electrons and holes are respectively injected from the cathode and the anode into the light-emitting functional layer 212, and are combined in the light-emitting functional layer 212 An excited state is formed, and then the excited state decays to realize light emission.
  • the manufacturing method of the display panel 100 may also include forming other structures, such as an encapsulation layer, an insulating layer, and so on.
  • the test pattern A can be further manipulated by the exposure, development and etching process to form the first electrode 211.
  • the test pattern A can not only be used as the output carrier of the test signal S TEST , but also can be further manufactured as the first electrode during the manufacturing stage of the display panel 100.
  • the electrode 211 improves the utilization of the test pattern A.
  • the step of etching the test pattern A to form the first electrode 211 specifically includes:
  • the test pattern string B is etched so that the connected test patterns A are disconnected and the first electrode 211 is formed.
  • the test pattern string B is electrically connected to the drain D of the driving transistor T1, and then when the display panel 100 is manufactured, the test pattern string B can be obtained by disconnecting the test pattern string B.
  • the pixel circuit 12 corresponds to the test pattern A one-to-one, and the pixel pattern layer A at this time can be used as the first electrode 211.
  • the manufacturing method of the display panel 100 includes the steps:
  • a light-emitting function layer 212 and a second electrode 213 are formed on the side of the first electrode 211 away from the substrate 11.
  • the test pattern A cannot be directly used as the metal layer forming the first electrode 211. Therefore, after the electrical test of the array substrate 10 is completed, the test pattern A needs to be removed first, and then the array of the test pattern A is removed.
  • the first electrode 211, the light-emitting function layer 212, and the second electrode 213 are sequentially fabricated on the basis of the substrate 10. In this way, the display panel 100 can be fabricated by a conventional process.
  • the array substrate 10 of this embodiment includes the test pattern A electrically connected to the drain D of the driving transistor T1.
  • the pixel circuit 12 keeps the driving transistor T1 in an on state through the charging process, and loads the power supply voltage VDD to the driving transistor T1. , And then obtain the test signal S output by the driving transistor T1 through the test pattern A.
  • the test signal S TEST is used to perform the electrical test of the pixel circuit 12.
  • the test signal S TEST is actually the subsequent signal flowing into the light emitting diode 21 through the first electrode 211, That is, in this embodiment, the electrical test of the pixel circuit 12 is performed by simulating the display process of the display panel 100, so that all parts of the pixel circuit 12 are tested.
  • the defect detection rate of the pixel circuit 12 is high, and the defect detection rate is high. High reliability, which can greatly improve the timeliness of process control, and because the test process simulates the display process of the display panel 100, it can greatly improve the defect detection match between the array substrate 10 test phase and the subsequent light-emitting diode 21 lighting test phase degree.
  • the pixel circuit 12 of this embodiment charges the capacitor C1 twice, so that enough power is stored in the capacitor C1, so as to ensure that the driving transistor T1 connected to the capacitor C1 remains in the fully-on state during the test phase M3, and the power supply voltage VDD can be Load the driving transistor T1 unimpededly, so that the obtained test signal S is more accurate and reliable.

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Abstract

一种阵列基板（10）及其测试方法、制造方法和测试装置以及显示面板（100）制造方法，阵列基板（10）包括基板（11）、位于基板（11）上的若干像素电路（12）及对应若干像素电路（12）的若干测试图案（A），像素电路（12）包括驱动单元（121），测试图案（A）电连接至驱动单元（121），测试图案（A）用于获取驱动单元（121）输出的测试信号（A）。通过设置于阵列基板（10）上的测试图案（A）来获取测试信号（A），测试信号（A）可用于检测像素电路（12）是否存在缺陷，检测过程简单便捷。

Description

阵列基板及其测试方法、制造方法和测试装置以及显示面板制造方法
相关申请的交叉引用
本申请要求于2019年3月29日提交中国专利局，申请号为201910252458.9，申请名称为“阵列基板及测试、成型方法、装置以及显示面板成型方法”的中国专利申请的优先权。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其测试方法、制造方法和测试装置以及显示面板制造方法。
背景技术
当今，随着多媒体技术的发展和信息社会的来临，对电子设备例如显示设备、通信设备等等的要求越来越高。
以显示设备为例，近年来，新出现了三种显示技术：等离子显示、场发射显示和有机电致发光显示，均在一定程度上弥补了阴极射线管和液晶显示的不足。
其中，有机电致发光显示器具有自主发光、低电压直流驱动、全固态、视角宽、颜色丰富等一系列的优点，与液晶显示器相比，有机电致发光显示器不需要背光源，视角大，功率低，其响应速度可达液晶显示器的1000倍。因此，有机电致发光显示器具有广阔的应用前景，被看作极赋竞争力的未来平板显示技术之一。
有机电致发光显示器通过具有不同颜色出射光的多个子像素来实现发光，而每个子像素均需要通过对应的像素电路来驱动以实现发光，因此，一个有机电致发光显示器会有数以万计甚至百万计的像素电路，如何有效测试这些像素电路便是一个很大的工程，而目前的测试技术不够便捷。
发明内容
本申请的目的在于提供一种能够实现便捷电学测试的阵列基板及其测试方法、制造方法和测试装置以及显示面板制造方法。
为实现上述申请目的之一，本申请一实施方式提供一种阵列基板，包括基板、位于所述基板上的若干像素电路及对应若干所述像素电路的若干测试图案，所述像素电路包括驱动单 元，所述测试图案电连接至所述驱动单元，所述测试图案用于获取所述驱动单元输出的测试信号。
为实现上述发明目的之一，本发明一实施方式一种用于测试上述的阵列基板的测试装置，包括连接单元及处理单元；所述连接单元与所述处理单元电连接；
所述连接单元与所述测试图案电连接，并向所述处理单元输出测试信号；
所述处理单元用于根据所述测试信号判断所述阵列基板是否存在缺陷。
在其中一实施例中，若干所述像素电路形成驱动区域；所述测试图案位于所述驱动区域内；
所述连接单元为连接端子，所述连接端子位于所述驱动区域的外部；
本申请实施方式可以通过设置于阵列基板上的测试图案来获取测试信号，测试信号可用于检测像素电路是否存在缺陷，检测过程简单便捷。
附图说明
图1是本申请一实施方式的显示面板的示意图；
图2是本申请一实施方式的阵列基板配合测试装置的示意图；
图3是本申请一实施方式的像素电路的示意图；
图4是本申请一实施方式的阵列基板的剖视图；
图5是本申请一实施方式的阵列基板的测试方法流程图；
图6是本申请一实施方式的像素电路时序控制示意图；
图7是本申请一实施方式的测试装置的结构框图；
图8至图10是本申请一实施方式的测试结果示意图；
图11是本申请一实施方式的阵列基板的制造方法流程图；
图12是本申请一实施方式的显示面板的制造方法流程图；
图13是本申请一实施方式的显示面板部分结构示意图；
图14是本申请一实施方式的显示面板剖视图；
图15是本申请另一实施方式的显示面板的制造方法流程图。
具体实施方式
以下将结合附图所示的具体实施方式对本申请进行详细描述。但这些实施方式并不限制本申请，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本申请的保护范围内。
在本申请的各个图示中，为了便于图示，结构或部分的某些尺寸会相对于其它结构或部分夸大，因此，仅用于图示本申请的主题的基本结构。
参见图1，本申请一实施方式提供一种显示面板100。
显示面板100可以是有机电致发光显示面板。
显示面板100包括阵列基板10及设置于阵列基板10上且呈阵列排布的若干子像素20。
若干子像素20可以包括发出红光的红色子像素、发出绿光的绿色子像素及发出蓝光的蓝色子像素，但不以此为限，也可包含发出其他颜色光的子像素，如此，便可实现各种颜色的出射光。
结合图2至图3，阵列基板10包括基板11、位于基板11上的若干像素电路12及对应若干像素电路12的若干测试图案A。
若干像素电路12对应若干子像素20设置，也就是说，每一个像素电路12用于驱动一个对应的子像素20，以实现子像素20的发光。
参见图3，为本实施方式的像素电路12的示意图，图3虚线框中显示的是后续于像素电路12中制造的发光二极管21，本实施方式的阵列基板10本身不包括发光二极管21。
子像素20包括发光二极管21，这里，发光二极管21可为有机发光二极管，当阵列基板10进一步制造为显示面板100时，像素电路12实际用于驱动发光二极管21发光。
阵列基板10包括沿行方向X延伸的行控制线及沿列向Y延伸的列向控制线。
水平控制线可以是发出扫描信号Scan1、Scan2、Scan3等的扫描线、发出控制信号EM的控制线等。
列控制线可以是输出数据电压Vdata的数据线等，数据线输出的数据电压Vdata用于为该列对应的子像素20提供图像数据，例如包括用于携带给红色子像素红色数据信号的红色数据线、用于携带给绿色子像素绿色数据信号的绿色数据线以及用于携带给蓝色子像素蓝色数据信号的蓝色数据线。
各个控制线可由集成电路控制。在一实施例中，水平控制线可由GIP(Gate in Panel，门面板)电路13控制。在另一实施例中，水平控制线也可由GOA(Gate Driver on Array)电路控制。
在显示面板的实际制备过程中，为了保证阵列基板10可以正常驱动若干子像素20，在制作完成阵列基板10之后，且在制备子像素20之前，需要对阵列基板10上的像素电路12进行电学测试，如此，可以避免因为阵列基板10的缺陷而导致后续制造的显 示面板100出现显示不均等缺陷。
在本实施方式中，像素电路12包括驱动单元121，测试图案A电连接至驱动单元121，测试图案A用于获取驱动单元121输出的测试信号S TEST。
本实施方式可以通过设置于阵列基板10上的测试图案A来获取测试信号S TEST，测试信号S TEST可用于检测像素电路12是否存在缺陷，检测过程简单便捷。
结合图3，在一具体示例中，驱动单元121包括驱动晶体管T1，测试图案A电连接至驱动晶体管T1的漏极D。测试图案A可为金属材料制成，可以为金属导电层，例如金属导电薄膜。像素电路12还包括储能单元122、充电通道L1、L2及测试通道L3。储能单元122连接驱动晶体管T1，储能单元122可包括电容C1。充电通道L1、L2连接储能单元122，充电通道L1、L2用于对电容C1充电并开启驱动晶体管T1。在一实施例中，电容C1可与驱动晶体管T1的栅极连接、充电通道L1和L2分别连接。测试通道L3连接电源电压VDD及驱动晶体管T1，测试通道L3用于使电源电压VDD加载到驱动晶体管T1，电源电压VDD用于生成测试信号S TEST。在一实施例中，电源电压VDD可电连接至驱动晶体管T1的源极。
需要说明的是，在其他实施例中，驱动单元121也可为其他结构。
另外，当第一部件描述为电连接至第二部件时，第一部件可以直接连接至第二部件，或者，第一部件经过一个或多个其他部件间接连接至第二部件，例如，“测试图案A电连接至驱动晶体管T1的漏极D”可以是指测试图案A直接连接驱动晶体管T1的漏极D，或者，测试图案A与驱动晶体管T1的漏极D之间还有其他结构例如开关晶体管，当该开关晶体管开启时，驱动晶体管T1的漏极D与测试图案A之间间接连通，其他部分的说明可以参考此处说明。
相对的，当第一部件描述为连接第二部件时，即第一部件直接连接第二部件，第一部件与第二部件之间没有其他部件，其他部分的说明可以参考此处说明。
在制作完成阵列基板10之后并在制作子像素20的过程中，需要将驱动晶体管T1的漏极D电连接至发光二极管21而形成显示面板100，驱动晶体管T1的漏极D电连接至发光二极管21的第一电极211(一般为阳极)，也就是说，测试信号S TEST模拟的实际为最终通过第一电极211流入发光二极管21的信号。
本实施方式的阵列基板10包括电连接至驱动晶体管T1的漏极D的测试图案A，像素电路12通过储能单元122的充电过程保持驱动晶体管T1处于开启状态，并使电源电压VDD施加到驱动晶体管T1，再通过测试图案A获取驱动晶体管T1输出的测试信号S TEST。该测试信号S TEST用于进行像素电路12的电学测试，测试信号S TEST实际为后续 通过第一电极211流入或施加到发光二极管21的信号，即本实施方式通过模拟显示面板100的显示过程(即像素电路12充电开启驱动晶体管T1，而后电源电压VDD施加到驱动晶体管T1驱动连接的发光二极管21发光的过程)来进行像素电路12的电学测试，从而使得像素电路12中的所有部分均被测试到，像素电路12的缺陷检出率高，且缺陷检出的可信度高，从而可大大提高工艺管控的时效性，且由于测试过程模拟的是显示面板100的显示过程，可大大提高阵列基板10测试阶段与后续发光二极管21点灯测试阶段的缺陷检测匹配度。
在本实施方式中，至少部分测试图案A之间相互连接而形成测试图形串B。
在一实施例中，位于同一列的测试图案A相互连接成一长条测试图形串B，如此，该列所有像素电路12的测试信号A均可通过该测试图形串B传递，大大简化了了测试流程及测试装置。
在本实施方式中，结合图3，以包括7个TFT和1个存储电容的像素电路12为例做说明。
像素电路12包括电容C1、驱动晶体管T1、第二开关晶体管T2、第三开关晶体管T3、第四开关晶体管T4、第五开关晶体管T5、第六开关晶体管T6(即控制信号输入端晶体管)及第七开关晶体管T7，且像素电路12用于接收第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3、数据电压Vdata、控制信号EM、电源电压VDD、参考电压Vref(或初始电压Vinit)。像素电路12中各元件之间的连接关系如图3所述，并将结合阵列基板10的测试方法具体描述。
需要说明的是，本实施方式的所有晶体管为PMOS晶体管，当驱动信号(包括第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3及控制信号EM)为低电平时，对应的晶体管将被开启，数据电压Vdata及电源电压VDD为正电压，参考电压Vref为负电压。
结合图4，在本实施方式中，连接驱动晶体管T1的漏极D的金属层123与测试图案A之间具有绝缘层124，也就是说，金属层123与测试图案A位于不同的层，测试图案A贯穿部分绝缘层124而导通金属层123，即此时测试图案A电连接至驱动晶体管T1的漏极D。
另外，若干像素电路12共同形成驱动区域P(参考图2)，驱动区域P对应显示面板100的显示区域。
测试图案A位于驱动区域P内，也就是说，该些测试图案A的形成区域未超出显示面板100的显示区域。
下面，将结合图5及图6详细介绍本实施方式的阵列基板10的测试方法。
本实施方式的阵列基板10的测试方法包括如下步骤Step1至Step4：
Step1：提供上述阵列基板10。
这里，阵列基板10包括电连接至驱动晶体管T1的漏极D的测试图案A，具体的，测试图案A实际连接的是第六开关晶体管T6(控制信号输入晶体管)的漏极D及第七开关晶体管T7的漏极，即测试图案A与驱动晶体管T1的漏极D间接电连接。阵列基板10上还未形成子像素20。
Step2：控制所述像素电路12中的所述驱动单元121输出所述测试信号S TEST。
这里，驱动单元121以驱动晶体管T1为例。
具体的，步骤Step2为：开启充电通道L1、L2从而对电容C1充电从而开启驱动晶体管T1；开启测试通道L3使得电源电压VDD加载到驱动晶体管T1。
这里，充电通道包括第一充电通道L1及第二充电通道L2。第一充电通道L1为从参考电压Vref至电容C1之间的通道，可包括第四开关晶体管T4。具体的，第四开关晶体管T4的源极连接至参考电压Vref，第四开关晶体管T4的漏极分别连接至电容C1和驱动晶体管T1的栅极，第四开关晶体管T4的栅极电连接至第一扫描信号Scan1。第二充电通道L2为从数据电压Vdata至电容C1之间的通道，可包括依次串联的第二开关晶体管T2、驱动晶体管T1和第三开关晶体管T3。具体的，第二开关晶体管T2的源极连接至数据电压Vdata，第二开关晶体管T2的漏极分别连接至驱动晶体管T1的源极和第五晶体管T5的漏极，第二开关晶体管T2的栅极电连接至第二扫描信号Scan2和第三晶体管T3的栅极；第一晶体管T1的漏极连接第三晶体管T3的源极，第一晶体管T1的栅极连接第三晶体管T3的漏极并连接到电容C1的第一端；电容C1的第二端连接电源电压VDD。测试通道L3为从电源电压VDD至第六晶体管T6的通道，可包括依次串联的第五开关晶体管T5、驱动晶体管T1和第六开关晶体管T6。具体的，第五开关晶体管T5的源极连接至电源电压VDD，第五开关晶体管T5的漏极连接驱动晶体管T1的源极，驱动晶体管T1的漏极电连接至第六开关晶体管T6的源极；第六开关晶体管T6的栅极连接控制信号EN，第六开关晶体管T6的漏极连接测试图案A。
步骤Step2包括：开启第一充电通道L1而使得参考电压Vref对电容C1充电，驱动晶体管T1被开启，而后开启第二充电通道L2使得数据电压Vdata对电容C1充电。
也就是说，当阵列基板10处于第一充电阶段M1时，第一扫描信号Scan1为低电平、第二扫描信号Scan2、第三扫描信号Scan3及控制信号EM均为高电平，第四开关晶体管T4被开启，参考电压Vref通过第四开关晶体管T4而对电容C1进行充电(即第一充电通道L1开启)，此时，参考电压Vref也可传输至驱动晶体管T1的栅极G，驱动晶体管T1被开启。
当阵列基板10处于第二充电阶段M2时，第二扫描信号Scan2、第三扫描信号Scan3为低电平，第一扫描信号Scan1及控制信号EM均为高电平，第二开关晶体管T2、第三开关晶体管T3及第七开关晶体管T7被开启，数据电压Vdata依次经过第二开关晶体管T2、驱动晶体管T1及第三开关晶体管T3而对电容C1进行二次充电(即第二充电通道L2开启)。
需要说明的是，此时数据电压Vdata对电容C1充电，使得电容C1中有足够多的电量，进而可以使得连接电容C1的驱动晶体管T1保持在开启状态。
此时，参考电压Vref通过第七开关晶体管T7传输至第六开关晶体管T6的漏极D(亦即后续与发光二极管21的第一电极211电连接的位置)，用于初始化发光二极管21的第一电极211，这里，可以通过测试图案A来获取施加到第七开关晶体管T7的参考电压Vref，若获取到显示为负电压的参考电压Vref，则第七开关晶体管T7不存在缺陷，否则，第七开关晶体管T7存在缺陷。
可以理解的，第三扫描信号Scan3也可在第一充电阶段M1时开启，即在第一充电阶段M1时，参考电压Vref通过第七开关晶体管T7传输至第六开关晶体管T6的漏极D而实现初始化。
另外，当阵列基板10处于测试阶段M3时，控制信号EM为低电平，第一扫描信号Scan1、第二扫描信号Scan2及第三扫描信号Scan3均为高电平，第五开关晶体管T5被开启，电源电压VDD依次经过第五开关晶体管T5、驱动晶体管T1及第六开关晶体管T6而传递至测试图案A。
Step3：所述测试图案A获取所述测试信号S TEST。
这里，测试信号S TEST较佳为测试电流，但不以此为限，最终获取的测试信号S TEST也可为测试电压等。
Step4：根据测试信号S TEST判断像素电路12是否存在缺陷。
步骤Step4具体可为：判断测试信号S TEST的值是否处于阈值范围内，若是，则像素电路12不存在缺陷，若否，则像素电路12存在缺陷。
需要说明的是，阈值范围的值与电源电压VDD有关，根据不同的电源电压VDD，可设置不同的阈值范围，当然，随着测试环境、像素电路12等的变化，阈值范围也可做相应变化，具体可根据实际情况而定。
本实施方式的阵列基板10的测试方法通过驱动晶体管T1输出的测试信号S TEST来进行像素电路12的电学测试，测试信号S TEST实际为后续通过第一电极211流入发光二极管21的信号，即本实施方式通过模拟显示面板100的显示过程来进行像素电路12的电学测试，从而使得像素电路12中的所有部分均被测试到，像素电路12的缺陷检出率高，且缺陷检出的可信 度高，从而可大大提高工艺管控的时效性，且由于测试过程模拟的是显示面板100的显示过程，可大大提高阵列基板10测试阶段与后续发光二极管21点亮测试阶段的缺陷检测匹配度。
另外，本实施方式的像素电路12对电容C1进行两次充电，使得电容C1中存储足够多的电量，进而保证连接电容C1的驱动晶体管T1在测试阶段M3保持在完全开启状态，电源电压VDD可以畅通无阻地施加到驱动晶体管T1，如此，获取的测试信号S TEST更加准确可靠。
可以理解的，本实施方式的测试方法不仅适用于上述像素电路12，也可使用于其他像素电路。
结合图7，本实施方式还提供一种阵列基板10的测试装置30，测试装置30包括相连的连接单元31及处理单元32，连接单元31用于电连接测试图案A并输出测试信号S TEST，处理单元32用于根据测试信号S TEST判断阵列基板10是否存在缺陷。
具体的，连接单元31为连接端子，连接单元31位于驱动区域P的外部(例如对应显示面板100的非显示区)。
在一实施例中，测试装置30还包括插针组件33，插针组件33可以包括相连的插针331及引线332(参考图2)，插针331接触连接所述连接单元31而获取测试信号S TEST，引线332连接所述插针331及处理单元32而将测试信号S TEST传递至处理单元32。
处理单元32例如为外接的终端设备，处理单元32将测试信号S TEST的值与阈值范围作比较以判断对应的像素电路12是否存在缺陷。
本实施方式中位于同一列的测试图案A相互连接成一长条测试图形串B，一长条测试图形串B连接一个连接单元31，当该列的像素电路12依次被扫描信号扫描开启后，该列像素电路12输出的所有测试信号S TEST可通过该测试图形串B及对应的连接单元31依次传输至处理单元32中，如此，可大大简化测试信号S TEST的引出结构，也就是说，此时仅需设置一排连接单元31便可实现所有像素电路12的测试信号S TEST的传递。
当然，测试图形串B并不以沿列向Y延伸为限，测试图形串B也可为其他形式。
另外，测试装置30还可以包括数据输出单元34，数据输出单元34可用于为数据线、扫描线等提供输入信号，例如，数据输出单元34用于连接GIP电路13而提供扫描信号Scan1、Scan2、Scan3、控制信号EM等。
这里，可以在GIP电路13远离像素电路12的一侧设置第一信号端子341(参考图2)，数据输出单元34通过第一信号端子341将相关数据输入至GIP电路13。
同样的，数据线远离像素电路12的一侧也可设置第二信号端子342，数据输出单元34通过第二信号端子342将相关数据输入至数据线。
实际情况中，由于线与线之间的间距较小，无法实现一个信号端子(第一信号端子341 或第二信号端子342)连接一根线路(GIP电路13中的电线或数据线)，此时，可以在信号端子与对应的线路之间设置多路分配器343或选择开关等，如此，便可实现各条线路的随机选择。
可以理解的，在测试结束之后，可将第一信号端子341、第二信号端子342等结构去除，但不以此为限。
结合图8至图10，为处理单元32示意的测试信号S TEST的测试结果。
以最左侧的一列像素电路12为例做说明，为方便说明，根据像素电路12于行方向X及列方向Y处的位置，该列像素电路12由上向下依次定义为像素电路X1Y1、像素电路X1Y2、像素电路X1Y3、像素电路X1Y4、像素电路X1Y5及像素电路X1Y6，且像素电路X1Y1输出的测试信号为S1，像素电路X1Y2输出的测试信号为S2，像素电路X1Y3输出的测试信号为S3，像素电路X1Y4输出的测试信号为S4，像素电路X1Y5输出的测试信号为S5，像素电路X1Y6输出的测试信号为S6。
参见图8，若测试信号S1至S6的波形均正常，则说明该列像素电路12均无缺陷；参图9，若测试信号S4的波形出现异常，而其他测试信号的波形正常，则说明此时像素电路X1Y4存在缺陷，其他像素电路12均无缺陷；参图10，若测试信号S1至S6的波形均出现异常，则说明极有可能是对应该列像素电路12的数据线存在异常。
同样的，当同一行的测试信号S均出现异常时，则说明极有可能是对应该行像素电路12的扫描线(或控制线)存在异常。
如此，便可根据处理单元32输出的测试信号S的波形准确获取像素电路12的情况，像素电路12的缺陷检出率高，且缺陷检出的可信度高，从而可大大提高工艺管控的时效性。
本申请一实施方式还提供一种阵列基板10的制造方法，结合前述阵列基板10的说明及图11，阵列基板10的制造方法包括步骤Step11至Step13：
Step11，提供一基板10；
Step12，于基板10上形成若干像素电路12，像素电路12包括驱动单元121。
这里，像素电路12包括驱动晶体管T1，另外，像素电路12还包括电容C1、用于对电容C1充电并开启驱动晶体管T1的充电通道L1、L2以及用于使电源电压VDD加载到驱动晶体管T1的测试通道L3。
Step13，形成电连接至驱动单元121的测试图案A。
具体的，形成电连接至驱动晶体管T1的漏极D的测试图案A。
实际操作中，在金属层123远离基板11的一侧依次形成绝缘层124及电连接至金属层123的测试图案A，金属层123连接驱动晶体管T1的漏极D，测试图案A位于若干像素电路 12形成的驱动区域P内。
本实施方式的制造方法获取的阵列基板10包括电连接至驱动晶体管T1的漏极D的测试图案A，像素电路12通过充电过程保持驱动晶体管T1处于开启状态，并使电源电压VDD施加到驱动晶体管T1，再通过测试图案A获取驱动晶体管T1输出的测试信号S，该测试信号S用于进行像素电路12的电学测试，测试信号S实际为后续通过第一电极211流入发光二极管21的信号，即本实施方式通过模拟显示面板100的显示过程来进行像素电路12的电学测试，从而使得像素电路12中的所有部分均被测试到，像素电路12的缺陷检出率高，且缺陷检出的可信度高，从而可大大提高工艺管控的时效性，且由于测试过程模拟的是显示面板100的显示过程，可大大提高阵列基板10测试阶段与后续发光二极管21点灯测试阶段的缺陷检测匹配度。
阵列基板10的制造方法的其他说明可以参考前述阵列基板10、阵列基板10的测试方法、阵列基板10的测试装置30的说明，在此不再赘述。
本申请一实施方式还提供一种显示面板100的制造方法，结合前述阵列基板10及显示面板100的说明以及图12至图14，显示面板100的制造方法包括步骤：
提供阵列基板10；
蚀刻测试图案A而形成第一电极211；
于第一电极211远离基板11的一侧形成发光功能层212及第二电极213(一般为阴极)。
此时，第一电极211、发光功能层212及第二电极213配合形成发光二极管21。
需要说明的是，发光功能层212可以包括洞穴注射层、有机发射器、电子传送层等等，电子和空穴分别从阴极和阳极注射入发光功能层212中，并在发光功能层212中复合形成激发态，而后激发态衰减而实现发光。
当然，显示面板100的制造方法还可包括形成其他结构，例如封装层、绝缘层等等。
本实施方式可以通过曝光显影蚀刻工艺对测试图案A进行进一步操作而形成第一电极211，测试图案A不仅可以作为测试信号S TEST的输出载体，还可在显示面板100制造阶段进一步制造为第一电极211，提高了测试图案A的利用率。
在本实施方式中，当至少部分测试图案A之间相互连接而形成测试图形串B时，所述蚀刻测试图案A而形成第一电极211的步骤具体包括：
蚀刻测试图形串B而使得相连的测试图案A之间断开并形成第一电极211。
也就是说，在阵列基板10电学测试阶段，电连接至驱动晶体管T1漏极D的是测试图形串B，而后进入显示面板100制造阶段时，仅需将测试图形串B断开便可获取与像素电路12一一对应的测试图案A，此时的像素图形层A可以作为第一电极211。
在另一实施方式中，结合图15，显示面板100的制造方法包括步骤：
提供阵列基板10；
去除测试图案A；
形成电连接至驱动晶体管T1的漏极D的第一电极211；
于第一电极211远离基板11的一侧形成发光功能层212及第二电极213。
在本实施方式中，测试图案A并不能直接作为形成第一电极211的金属层，因此，在阵列基板10电学测试完成之后，需要先将测试图案A去除，而后再在去除测试图案A的阵列基板10的基础上依次制造第一电极211、发光功能层212及第二电极213，如此，显示面板100可以通过常规工艺制造。
综上，本实施方式的阵列基板10包括电连接至驱动晶体管T1的漏极D的测试图案A，像素电路12通过充电过程保持驱动晶体管T1处于开启状态，并使电源电压VDD加载到驱动晶体管T1，再通过测试图案A获取驱动晶体管T1输出的测试信号S，该测试信号S TEST用于进行像素电路12的电学测试，测试信号S TEST实际为后续通过第一电极211流入发光二极管21的信号，即本实施方式通过模拟显示面板100的显示过程来进行像素电路12的电学测试，从而使得像素电路12中的所有部分均被测试到，像素电路12的缺陷检出率高，且缺陷检出的可信度高，从而可大大提高工艺管控的时效性，且由于测试过程模拟的是显示面板100的显示过程，可大大提高阵列基板10测试阶段与后续发光二极管21点亮测试阶段的缺陷检测匹配度。
另外，本实施方式的像素电路12对电容C1进行两次充电，使得电容C1中存储足够多的电量，进而保证连接电容C1的驱动晶体管T1在测试阶段M3保持在完全开启状态，电源电压VDD可以畅通无阻地加载到驱动晶体管T1，如此，获取的测试信号S更加准确可靠。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请的保护范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种阵列基板，包括：
    基板；
    位于所述基板上的若干像素电路，所述像素电路包括驱动单元；
    及对应所述若干像素电路的若干测试图案，所述测试图案电连接至所述驱动单元，所述测试图案用于获取所述驱动单元输出的测试信号。
  2. 根据权利要求1所述的阵列基板，其中，
    至少部分所述测试图案之间相互连接而形成测试图形串。
  3. 根据权利要求1所述的阵列基板，其中,
    所述若干像素电路形成驱动区域；所述测试图案位于所述驱动区域内。
  4. 根据权利要求2所述的阵列基板，其中,
    位于同一列的所述测试图案相互连接成一长条测试图形串。
  5. 根据权利要求1所述的阵列基板，其中，
    所述驱动单元包括驱动晶体管，所述测试图案电连接至所述驱动晶体管的漏极。
  6. 根据权利要求5所述的阵列基板，其中，
    连接所述驱动晶体管的漏极与所述测试图案之间具有绝缘层；
    所述测试图案贯穿部分所述绝缘层而导通所述漏极。
  7. 根据权利要求1所述的阵列基板，其中，
    所述像素电路进一步包括控制信号输入晶体管；
    所述驱动单元包括驱动晶体管；
    所述控制信号输入晶体管的源极直接电连接至所述驱动晶体管的漏极；
    所述测试图案直接电连接至所述控制信号输入晶体管的漏极。
  8. 根据权利要求5所述的阵列基板，其中，
    所述像素电路还包括储能单元、充电通道及测试通道；
    所述储能单元连接所述驱动晶体管；
    所述充电通道连接所述储能单元；
    所述测试通道连接电源电压及所述驱动晶体管，所述电源电压用于生成测试信号。
  9. 根据权利要求8所述的阵列基板，其中，所述储能单元包括电容。
  10. 一种阵列基板的测试方法，包括步骤：
    提供权利要求1所述的阵列基板；
    控制所述像素电路中的所述驱动单元输出所述测试信号；
    所述测试图案获取所述测试信号；
    根据所述测试信号判断所述像素电路是否存在缺陷。
  11. 根据权利要求10所述的阵列基板的测试方法，其中，
    至少部分测试图案之间相互连接而形成测试图形串。
  12. 根据权利要求10所述的阵列基板的测试方法，其中，
    所述像素电路形成驱动区域，所述测试图案位于所述驱动区域内。
  13. 根据权利要求10所述的阵列基板的测试方法，其中，
    所述驱动单元包括驱动晶体管，所述像素电路还包括储能单元、充电通道及测试通道。
  14. 根据权利要求13所述的阵列基板的测试方法，其中，
    所述储能单元包括电容；
    所述控制所述像素电路中的所述驱动单元输出所述测试信号的步骤具体包括：
    开启充电通道从而对所述电容充电从而开启所述驱动晶体管；
    开启测试通道，使得电源电压施加到所述驱动晶体管。
  15. 根据权利要求14所述的阵列基板的测试方法，其中，
    所述充电通道包括第一充电通道及第二充电通道；
    所述开启充电通道从而对所述电容充电从而开启所述驱动晶体管的步骤具体包括：
    开启所述第一充电通道从而使得参考电压对所述电容充电，所述驱动晶体管被开启；
    开启所述第二充电通道从而使得数据电压对所述电容充电。
  16. 根据权利要求13所述的阵列基板的测试方法，其中，
    所述根据所述测试信号判断所述像素电路是否存在缺陷的步骤具体包括：
    判断所述测试信号的值是否处于阈值范围内，若是，则所述像素电路不存在缺陷，
    若否，则所述像素电路存在缺陷。
  17. 根据权利要求10所述的阵列基板的测试方法，其中，
    所述测试信号为电流信号或电压信号。
  18. 一种用于测试如权利要求1中所述的阵列基板的测试装置，
    包括连接单元及处理单元；
    所述连接单元与所述处理单元电连接；
    所述连接单元与所述测试图案电连接，并向所述处理单元输出测试信号；
    所述处理单元用于根据所述测试信号判断所述阵列基板是否存在缺陷。
  19. 根据权利要求18所述的阵列基板的测试装置，其中，
    若干所述像素电路形成驱动区域；所述测试图案位于所述驱动区域内；
    所述连接单元为连接端子，所述连接端子位于所述驱动区域的外部；
    所述处理单元为外接的终端设备。
  20. 根据权利要求18所述的阵列基板的测试装置，还包括插针组件:
    所述插针组件包括相连的插针及引线；
    所述插针接触连接所述连接单元；
    所述引线连接所述插针及所述处理单元。
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