WO2021227713A1 - 阵列基板、其检测方法及拼接显示面板 - Google Patents

阵列基板、其检测方法及拼接显示面板 Download PDF

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Publication number
WO2021227713A1
WO2021227713A1 PCT/CN2021/085957 CN2021085957W WO2021227713A1 WO 2021227713 A1 WO2021227713 A1 WO 2021227713A1 CN 2021085957 W CN2021085957 W CN 2021085957W WO 2021227713 A1 WO2021227713 A1 WO 2021227713A1
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Prior art keywords
signal
area
wiring
lines
line
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PCT/CN2021/085957
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English (en)
French (fr)
Inventor
陈昊
张振宇
赵蛟
肖丽
刘冬妮
郑皓亮
陈亮
玄明花
杨明
卢鑫泓
齐琪
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/642,025 priority Critical patent/US12002410B2/en
Priority to KR1020227017342A priority patent/KR20230009867A/ko
Priority to JP2022528657A priority patent/JP2023524191A/ja
Priority to EP21803664.8A priority patent/EP4033477A4/en
Publication of WO2021227713A1 publication Critical patent/WO2021227713A1/zh
Priority to US18/664,242 priority patent/US20240304136A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a detection method thereof, and a spliced display panel.
  • sub-millimeter or even micron-level light-emitting diodes based on the principle of inorganic light-emitting diodes are self-luminous devices like OLEDs, and like OLEDs, they have high brightness and ultra-low delay. , Large viewing angle and a series of advantages.
  • inorganic light-emitting diodes emit light based on metal semiconductors (rather than organics) with more stable properties and lower resistance, they also have lower power consumption, higher resistance to high and low temperatures, and longer service life than OLEDs.
  • metal semiconductors rather than organics
  • the embodiments of the present disclosure provide an array substrate, a detection method thereof, and a spliced display panel.
  • the specific solutions are as follows:
  • an array substrate provided by an embodiment of the present disclosure, wherein:
  • the array substrate includes a display area and a frame area; the display area has a plurality of pixels, a plurality of scan lines, a plurality of data lines, a plurality of positive signal lines, and a plurality of reference signal lines arranged in a matrix;
  • Each pixel of the plurality of pixels includes: sub-pixels of at least three colors and a pixel driving chip that drives each of the sub-pixels to emit light;
  • Each of the sub-pixels includes at least one inorganic light-emitting diode
  • the pixel driving chip is used to write the signal of the data signal line into sub-pixels of different colors in a time-sharing manner under the control of the scan line, wherein the reference signal line is used to transmit the signal to the pixel driving chip.
  • a negative signal is provided to form a current path between the inorganic light emitting diode and the pixel driving chip.
  • the plurality of pixels includes N pixel rows arranged in a first direction and M pixel columns arranged in a second direction; N and M are both integers greater than 1;
  • the multiple scan lines extend along the first direction and are arranged along the second direction
  • the multiple data signal lines extend along the second direction and are arranged along the first direction
  • the multiple Positive signal lines extend along the second direction and are arranged along the first direction
  • the plurality of reference signal lines extend along the second direction and are arranged along the first direction;
  • the first direction and the second direction are not the same.
  • Each of the pixel rows corresponds to one of the plurality of scan lines
  • each column of the pixel column corresponds to one of the plurality of data lines, and one of the plurality of reference signal lines.
  • the pixels include: first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels;
  • Each of the pixel rows corresponds to one of the plurality of scan lines, and each of the pixel columns corresponds to one of the plurality of data lines, and one of the plurality of reference signal lines.
  • One of the two positive signal lines is connected to the anode of the inorganic light emitting diode in the first color sub-pixel, and the other positive signal line is connected to the third color sub-pixel and the second color The anode of the inorganic light emitting diode in the sub-pixel is connected.
  • the display area further includes scan signal wiring lines connected to each scan line of the plurality of scan lines in a one-to-one correspondence, and the scan signal wiring lines extend along the second direction.
  • N M
  • one side of each pixel column corresponds to one scanning signal wiring, and only one scanning signal wiring is provided between two adjacent pixel columns.
  • At least one scan signal wiring is provided on both sides of at least one pixel column;
  • At least one scan signal wiring is arranged between at least part of two adjacent pixel columns, and there are no more than two scan signal wiring between two adjacent pixel columns.
  • the scan line is located in the first metal layer; the scan signal wiring, the data signal line, the reference signal line and the positive signal line are located in the second metal layer.
  • the frame area at one end of the data signal line includes a bending area, a wiring area, and a binding area that are sequentially away from the display area;
  • the bonding area is provided with at least one first chip and at least one second chip;
  • the scan signal wiring and the data signal wiring are sequentially bonded and connected to the first chip through the wiring located in the bending area and the wiring area;
  • the reference signal line and the positive signal line are sequentially bonded and connected to the second chip through wires located in the bending area and the wiring area.
  • the bonding area is provided with a plurality of the first chips and a plurality of the second chips;
  • the first chip and the second chip are spaced apart in the bonding area.
  • the traces of the bending area are all located on the second metal layer.
  • the wires connected to the scan signal wires and the wires connected to the data signal wires are located on the first metal layer;
  • the wiring connected to the reference signal line and the wiring connected to the positive signal line are both located on the second metal layer.
  • the wires connected to the scan signal wires and the wires connected to the data signal wires are both located on the second metal layer;
  • the wiring connected to the reference signal and the wiring connected to the positive signal line are both located on the first metal layer.
  • the scan signal wiring, the data signal line, the reference signal line and the positive signal line are all vertical signal lines;
  • the frame area further includes: a first signal input area located at a side of the bonding area away from the wiring area, and a second signal input area located at an end of the data signal line away from the bending area;
  • the first signal input area is provided with first input electrodes corresponding to each of the vertical signal lines one-to-one, and each of the vertical signal lines in the display area sequentially passes through the bending area and the wiring The wiring of the area is connected to the corresponding first input electrode;
  • the second signal input area is provided with second input electrodes connected to each of the vertical signal lines in a one-to-one correspondence.
  • the frame area at one end of the scan line includes a third signal input area
  • the frame area at the other end of the scan line includes a fourth signal input area
  • the third signal input area is provided with third input electrodes connected to each of the scan lines in a one-to-one correspondence;
  • the fourth signal input area is provided with fourth input electrodes connected to each of the scan lines in a one-to-one correspondence.
  • the embodiments of the present disclosure also provide a spliced display panel, which includes a plurality of any of the above-mentioned array substrates provided in the embodiments of the present disclosure.
  • the embodiments of the present disclosure also provide a detection method of any of the above-mentioned array substrates, wherein it is specified that the vertical signal lines and the scan lines in the display area are lines to be detected, and Detection methods include:
  • test signal For each line to be tested, input a test signal to one of the input electrodes connected to the line to be tested;
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the structure of a pixel in an array substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel in another array substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of an array layout structure corresponding to a pixel in an array substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of another array layout structure corresponding to one pixel in the array substrate provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a partial cross-sectional structure of a wiring area in an array substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a cross-sectional structure of a scan signal wiring in an array substrate provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a cross-sectional structure of a reference signal line in an array substrate provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.
  • FIG. 14 is a flowchart of a method for detecting an array substrate provided by an embodiment of the disclosure.
  • sub-millimeter light-emitting diodes and miniature light-emitting diodes have problems such as poor brightness uniformity at low current densities. Therefore, sub-millimeter light-emitting diodes and miniature light-emitting diodes must use high current density to drive light.
  • the current density of micro-inorganic light-emitting diodes is at least two orders of magnitude higher than that of organic light-emitting diodes. Therefore, micro-inorganic light-emitting diodes cannot be driven by pixel circuits formed by thin film transistors like organic light-emitting diodes. If pixel circuits are formed by thin film transistors For driving, the size of thin film transistors needs to be made larger to generate high current density. The large size of thin film transistors leads to poor uniformity and high power consumption. In addition, the pixel circuits in the existing organic light emitting diodes cannot be directly applied to micro Inorganic light-emitting diodes.
  • the embodiments of the present disclosure provide an array substrate, a detection method thereof, and a spliced display panel.
  • the array substrate includes a display area A1 and a frame area A2;
  • the display area A1 has a plurality of pixels arranged in a matrix, a plurality of scan lines Sn, and Data lines Dm, multiple positive signal lines Hm, and multiple reference signal lines Vm;
  • each pixel 1 in the plurality of pixels includes: sub-pixels 01 of at least three colors and a pixel driving chip 02 that drives each sub-pixel 01 to emit light;
  • Each sub-pixel 01 includes at least one inorganic light emitting diode
  • the pixel driving chip 2 is used to write the signal of the data signal line Dm into the sub-pixels 01 of different colors in time-sharing under the control of the scan line Sn, wherein the reference signal line Vm is used to provide a negative signal to the pixel driving chip 2, So that a current path is formed between the pixel driving chip 2 and the inorganic light emitting diode.
  • the pixels include: sub-pixels of at least three colors and a pixel driving chip that drives each sub-pixel to emit light; each sub-pixel includes at least one inorganic light-emitting diode; the display area further includes: and inorganic light-emitting diode
  • Sub-pixel that is, in the embodiments of the present disclosure, the pixel driving chip is used to directly drive each pixel to achieve display. In addition, since the pixel drive chip is used to directly drive each pixel, it is possible to provide a large current density to the micro-inorganic light-emitting diode.
  • the inorganic light emitting diode may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, English abbreviation Mini LED) or a micro light emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED), there is no limitation here.
  • each sub-pixel includes at least one inorganic light-emitting diode, for example, each sub-image includes one inorganic light-emitting diode, two inorganic light-emitting diodes, and three inorganic light-emitting diodes.
  • the diode or multiple inorganic light emitting diodes are not limited here.
  • each sub-image includes two inorganic light-emitting diodes as an example for illustration.
  • the display area A1 includes N pixel rows arranged in the first direction X and M pixel columns arranged in the second direction. ; N and M are both integers greater than 1;
  • the multiple scan lines Sn extend along the first direction X and are arranged along the second direction Y
  • the multiple data signal lines Dm extend along the second direction Y and are arranged along the first direction X
  • the multiple positive signal lines Hm are arranged along the second direction.
  • the direction Y extends and is arranged along the first direction X
  • the multiple reference signal lines Vm extend along the second direction Y and are arranged along the first direction X;
  • the first direction X and the second direction Y are different.
  • the column corresponds to one data signal line Dm among the plurality of data lines, one reference signal line Vm among the plurality of reference signal lines, and one positive signal line Hm among the plurality of positive signal lines.
  • the difference in current conversion efficiency between the first color inorganic light emitting diode and the second color inorganic light emitting diode is relatively small, while the current conversion efficiency of the first color inorganic light emitting diode and the second color inorganic light emitting diode is the same as that of the third color.
  • the current conversion efficiency of inorganic light-emitting diodes is quite different. Therefore, the electrical signal that the anode of the first-color inorganic light-emitting diode needs to receive is different from the magnitude of the electrical signal that the anode of the second-color inorganic light-emitting diode and the anode of the third-color inorganic light-emitting diode need to receive. Larger.
  • the pixel 1 includes: a first color sub-pixel 01 (R), a second color sub-pixel 01 (B), and a third Color sub-pixel 01 (G);
  • Each pixel row corresponds to one scan line Sn of the plurality of scan lines
  • each pixel column corresponds to one data signal line Dm among the plurality of data lines, one reference signal line Vm among the plurality of reference signal lines, and a plurality of positive electrodes.
  • One of the two positive signal lines Hm1 and Hm2 is connected to the anode of the inorganic light emitting diode in the first color sub-pixel 01 (R), and the other positive signal line Hm2 is connected to the third color sub-pixel 01 ( G) is connected to the anode of the inorganic light emitting diode in the second color sub-pixel 01 (B).
  • the signals received by the anodes of the inorganic light-emitting diodes in the third color sub-pixel 01 (G) and the second color sub-pixel 01 (B) can be the same, while the inorganic light-emitting diodes in the first color sub-pixel 01 (R)
  • the signal received by the anode of the diode has a larger amplitude than the signal received by the sub-pixels of the other two colors, which can prevent the anodes of the three-color sub-pixels from receiving the signal with the largest amplitude among the three-color sub-pixels. Signal, which can reduce power consumption.
  • the first color, the second color, and the third color may be one of red, blue, and green, respectively, for example, the first color is red, the second color is blue, and the third color is green.
  • the display area A1 further includes a scan signal wiring Cn connected in a one-to-one correspondence with each scan line Sn of the plurality of scan lines, and The scan signal wiring Cn extends along the second direction Y.
  • the scan signal can be provided to the corresponding scan line Sn through the scan signal wiring Cn, so that the signal source for providing the scan signal can be set at both ends of the scan signal wiring Cn, avoiding the provision of A chip that provides scanning signals.
  • each pixel column is correspondingly provided with a scanning signal wiring Cn, and only one scanning signal wiring Cn is provided between two adjacent pixel columns.
  • At least one scan signal wiring Cn is provided on both sides of at least one pixel column (for example, in the second pixel column in FIG. 6, a scan signal wiring C1 is provided on the left side, and two scan signal wiring is provided on the right side. Lines C2 and C3); at least one scan signal wiring Cn is provided between at least part of two adjacent pixel columns.
  • each adjacent K columns of pixel columns is a set of repeating units.
  • at least one scan signal wiring is provided on both sides of one of the pixel columns, for example, one side is provided with There are two scan signal traces, and one scan signal trace is provided on the other side; while the other K-1 column pixel columns are provided with at most one scan signal trace on both sides, for example, one of which is provided with one scan signal trace
  • On the other side there is no scan signal wiring (for example, the pixel column is located at the outermost side of the display panel) or only one scan signal wiring is provided (for example, the pixel column is located at the non-outermost side of the display panel).
  • K (min[N,M])/
  • the scan line Sn is provided in the same layer on the first metal layer; the scan signal wiring Cn, the data signal line Dm, and the reference signal line Vm and the positive signal lines Hm1 and Hm2 are arranged in the same layer on the second metal layer.
  • the two structures are "arranged in the same layer” or “located in the same layer”, which may mean that the two structures are formed in the same film forming process, or they are formed in the same patterning process, or they are formed in the same patterning process.
  • the stacking relationship is in the same layer, which can also mean that the distance between them and the substrate is equal.
  • the first metal layer may be located on the side of the second gold layer away from the base substrate 100, or the second metal layer may be located at the side of the first metal layer away from the base substrate 100.
  • One side is not limited here.
  • the pixel driving chip (not shown in FIGS. 7 and 8) has a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, and a fourth signal terminal. O4, the fifth signal terminal O5 and the sixth signal terminal O6.
  • the first signal terminal O1 is connected to the cathode R- of the first color inorganic light-emitting diode
  • the second signal terminal O2 of the pixel drive chip is connected to the cathode G- of the third color inorganic light-emitting diode
  • the third signal terminal of the pixel drive chip O3 is connected to the cathode B- of the second color inorganic light-emitting diode
  • the fourth signal terminal O4 of the pixel drive chip is connected to the scan line Sn
  • the signal terminal of the pixel drive chip is connected to the data signal line Dn through the via hole P1
  • the sixth signal terminal O6 of the driving chip is connected to the reference signal line Vm through the via hole P2
  • the anode R+ of the first color inorganic light emitting diode is connected to the anode signal line Hm1 through the via hole P5, and the anode G+ of the third color inorganic light emitting diode passes through
  • FIG. 7 is a schematic structural diagram of a column of pixels with only one scan signal wiring Cn provided on both sides of the row direction.
  • the scan signal wiring Cn is connected to the scan line Sn through a via P3.
  • FIG. 8 is a schematic structural diagram of a column of pixels having scan signal traces (Cn and C n+1 ) on both sides of the row direction.
  • the scan signal trace Cn is connected to the scan line Sn through a via P3 .
  • the scan signal wiring C n+1 is connected to other scan lines (not shown in FIG. 8).
  • the frame area A2 at one end of the data signal line Dm includes a bending area A21, a wiring area A22, and a bonding area that are sequentially away from the display area A1.
  • the binding area 23 is provided with at least one first chip IC1 and at least one second chip IC2;
  • the scan signal wiring Cn and the data signal line Dm are sequentially bonded and connected to the first chip IC1 through the wiring located in the bending area A21 and the wiring area A22;
  • the reference signal line Vm and the positive signal line Hm are sequentially bonded and connected to the second chip IC2 through wires located in the bending area A21 and the wiring area A22.
  • the bonding area may be provided with only one first chip and one second chip. This can reduce the number of chips.
  • first chip IC1 and one second chip IC2 are provided in the binding area A23.
  • the first chip IC1 is on the left and the second chip IC2 is on the right.
  • the traces on the left side of the wiring area A22 are closer to the first chip IC1 and farther from the second chip IC2, and the wiring area A22
  • the trace on the right is farther from the first chip IC1 and closer to the second chip IC2, that is, the distance between the left and right traces of the wiring area A22 from the same chip is not the same, resulting in a difference in the length of the wiring in the wiring area Larger, that is, the loading of the wiring is inconsistent, resulting in uneven display.
  • the scan signal wiring provides a digital voltage signal, which is used to control when the signal on the data signal line is written into the pixel driving chip. Therefore, the scan signal trace and the data signal line conduction current is small, and it is not sensitive to the IR drop generated by the wiring in the wiring area. Therefore, in the wiring area, the corresponding trace width can be set relatively narrower and/or the length can be set Is relatively long.
  • the signals on the reference signal line and the positive signal line are all fixed voltage signals, but because they are connected in series in the current path of the inorganic light-emitting diode, and the current path will flow through the current of the order of mA, the wiring area is generated by the wiring. IR drop will affect the signal of the current path. Therefore, the width and length of the wiring in the wiring area are required to be high, and it is necessary to increase the line width and/or shorten the line length as much as possible.
  • the bonding area A23 is provided with a plurality of first chips IC1 and a plurality of second chips IC2;
  • the fixed area A23 is distributed at intervals to reduce the length difference of the wiring in the wiring area.
  • the first driver chip can be arranged at a position close to the center of the bonding area, and the second chip can be arranged at a position close to both sides of the bonding area, so that the length of the wiring connected to the first chip can be set It is relatively long, and the length of the trace connected to the second chip is set to be relatively short.
  • the The pin distribution of the chip can also be set by referring to the above rules. For example, the pins that provide signals to the scan signal traces and data signal lines are set in the middle area of the chip, and the pins that provide signals to the reference signal line and the positive signal line are set. Set at both ends of the chip.
  • the traces 03 of the bending area A21 are all located in the second metal layer.
  • the wiring 041 connected with the scan signal wiring Cn and the wiring connected with the data signal line Dm 042 are all located on the first metal layer;
  • the wiring 051 connected to the reference signal line Vm and the wiring 052 connected to the positive signal line Hm are both located in the second metal layer.
  • the second metal layer is located between the first metal layer and the base substrate 100 as an example.
  • a planarization layer 101 is further provided between the first metal layer and the second metal layer, and a protective layer 102 is further provided above the first metal layer.
  • the material of the planarization layer may be an electrodeless material such as silicon oxide or silicon nitride, or an organic material such as resin, which is not limited herein.
  • the material of the protective layer may be an electrodeless material such as silicon oxide or silicon nitride, or an organic material such as resin, which is not limited herein.
  • the wiring connected to the scan signal wiring and the wiring connected to the data signal line are located on the second metal layer;
  • the traces connected to the reference signal and the traces connected to the positive signal line are located on the first metal layer.
  • the wiring in the wiring area, is arranged in two metal layers, which can solve the problem of limited space in the wiring area.
  • the wiring area and the bonding area are bent to the back of the display panel through the bending area, so that the frame of the display panel can be reduced.
  • the scan signal wiring Cn, the data signal line Dm, the reference signal line Vm, and the positive signal line Hm are all vertical signal lines;
  • the frame area A2 further includes: a first signal input area A24 located at the side of the bonding area A23 away from the wiring area A22, and a second signal input area A25 located at an end of the data signal line Dm away from the bending area A21;
  • the first signal input area A24 is provided with a first input electrode Tp1 corresponding to each vertical signal line one-to-one, and each vertical signal line in the display area A1 passes through the wires located in the bending area A21 and the wiring area A22 and the corresponding The first input electrode Tp1 is connected;
  • the second signal input area A25 is provided with second input electrodes Tp2 connected to each vertical signal line in a one-to-one correspondence.
  • the wiring 041 connected to the scanning signal wiring Cn and the wiring 042 connected to the data signal line Dm are all located in the first metal layer; in the wiring area A22, the wiring 051 connected to the reference signal line Vm And the wiring 052 connected to the positive signal line Hm is located in the second metal layer as an example.
  • the scan signal trace Cn located in the second metal layer sequentially passes through the trace 03 located in the bending area A21 and located in the second metal layer, and the trace located in the wiring area A22 and located in the first metal layer.
  • the wire 041 is bound to the first chip IC1 in the binding area A23 through the transparent conductive layer 103, and is connected to the first input electrode Tp1 of the first signal input area A24.
  • the film layer relationship of the data signal line is the same as that of the scan signal line, and will not be repeated here.
  • the reference signal line Vm located in the second metal layer sequentially passes through the wiring 03 located in the bending area A21 and located in the second metal layer, and the wiring located in the wiring area A22 and located in the second metal layer.
  • 051 and the second chip IC2 in the bonding area A23 are bonded through the first metal layer and the transparent conductive layer 103, and are connected to the first input electrode Tp1 of the first signal input area A24.
  • the film layer relationship of the positive signal line is the same as that of the reference signal line, and will not be repeated here.
  • the frame area A2 at one end of the scan line Sn includes a third signal input area A26; the frame area at the other end of the scan line Sn includes The fourth signal input area A27; the third signal input area A26 is provided with a third input electrode Tp3 connected in a one-to-one correspondence with each scan line Sn; the fourth signal input area A27 is provided with a first input electrode Tp3 connected in a one-to-one correspondence with each scan line Sn Four input electrodes Tp4.
  • each vertical signal line on the array substrate is normal by inputting a signal to the input electrode and detecting other input electrode signals. After the inspection is completed and confirmed as a good product, the signal input area can be cut off without affecting the subsequent use of the panel.
  • the embodiments of the present disclosure also provide a detection method for any of the array substrates provided by the embodiments of the present disclosure, and it is specified that the vertical signal lines and scanning lines in the display area are all lines to be tested, as shown in FIG. 14 As shown, the detection method includes:
  • S102 Detect whether another input electrode connected to the line to be detected has a signal output, and if there is no signal output, it is determined that the line to be detected is disconnected.
  • the detection method by inputting a signal to the input electrode, the method of detecting other input electrode signals can detect whether the line to be detected has a short circuit or an open circuit, and the detection method is simple. Moreover, applying the detection method to the preparation process of the array substrate can reduce the cost.
  • step S102 and step S103 are not limited. Step S102 may be performed first, and then step S103; or step S103 may be performed first, and then step S102 may be performed, which is not limited here.
  • the positive signal line for the reference signal line and the positive signal line, the first input electrode of the first signal input area and the second input electrode of the second signal input area can be used in conjunction with each other to detect the reference signal line and the positive signal line.
  • the positive signal line is normal, for example: input a test signal to the first input electrode of the reference signal line, detect whether there is a signal output on the second input electrode connected to the reference signal line, if so, determine that the reference signal line is normal, If not, it is determined that the reference signal line is disconnected, and the reference signal line is repaired.
  • the planarization layer is continuously deposited, and via holes are formed in the planarization layer. At this time, the reference signal line and the positive signal line are repeatedly tested. After the test result is normal, continue to deposit the second metal layer to form the scan line in the second metal layer, and complete the data signal line and the scan signal wiring and the second metal layer. A connection between the signals of the output electrodes.
  • the fourth input electrode of the fourth signal input area Used in conjunction with each other to detect whether all signal lines on the array substrate are normal. If a short circuit or open circuit occurs, repair it until all the signal lines are normal and continue the subsequent process. This avoids the subsequent scrapping of the array substrate due to abnormal signal lines, thereby reducing production costs.
  • embodiments of the present disclosure also provide a spliced display panel, including a plurality of array substrates provided in the embodiments of the present disclosure. Since the problem-solving principle of the spliced display panel is similar to that of the aforementioned array substrate, the implementation of the spliced display panel can refer to the implementation of the aforementioned array substrate, and the repetition will not be repeated.
  • the second signal input area, the third signal input area, and the fourth signal input area in the array substrate can be cut after the array substrate manufacturing process is completed. Affect the subsequent splicing process; the wiring area and the bonding area are bent to the back of the display panel through the bending area, so that the width of the display panel frame can be reduced.
  • the wiring area and the binding area are bent to the back of the display panel through the bending area through a plurality of array substrates.
  • the pixels in the array substrate include: at least three color sub-pixels and a pixel driving chip that drives each sub-pixel to emit light; each sub-pixel includes at least one Inorganic light-emitting diodes; the display area also includes: an anode signal line connected to the anode of the inorganic light-emitting diode, data signal lines, scan lines and reference signal lines connected to the pixel drive chip; the pixel drive chip is used under the control of the scan line, The signal of the data signal line is written into the sub-pixels of different colors in a time-sharing manner.
  • the pixel driving chip is used to directly drive each pixel to achieve display.
  • the pixel drive chip is used to directly drive each pixel, it is possible to provide a large current density to the micro-inorganic light-emitting diode.

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Abstract

一种阵列基板、阵列基板的检测方法及拼接显示面板，在阵列基板中像素（1）包括：至少三种颜色的子像素（01）和驱动各子像素（01）发光的像素驱动芯片（02）；每一子像素（01）包括至少一个无机发光二极管；显示区域（A1）还包括：与无机发光二极管的正极连接的正极信号线（Hm），与像素驱动芯片（02）连接的数据信号线（Dm）、扫描线（Sn）以及参考信号线（Vm）；像素驱动芯片（02）用于在扫描线（Sn）的控制下，将数据信号线（Dm）的信号分时写入不同颜色的子像素（01）中。

Description

阵列基板、其检测方法及拼接显示面板
相关申请的交叉引用
本申请要求在2020年05月13日提交中国专利局、申请号为202010404359.0、申请名称为“阵列基板、其检测方法及拼接显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤指一种阵列基板、其检测方法及拼接显示面板。
背景技术
相比于有机发光二极管(OLED)来说，基于无机发光二极管原理的亚毫米量级甚至微米量级的发光二极管和OLED一样属于自发光器件，而且也和OLED一样，有着高亮度、超低延迟、超大可视角度等一系列优势。而且由于无机发光二极管发光是基于性质更加稳定和电阻更低的金属半导体(而不是有机物)的，因此它相比OLED来说还有着功耗更低、更耐高温和低温、使用寿命更长的优势。
发明内容
本公开实施例提供一种阵列基板、其检测方法及拼接显示面板，具体方案如下：
第一方面，本公开实施例提供的一种阵列基板，其中：
所述阵列基板包括显示区域和边框区域；所述显示区域具有矩阵排列的多个像素、多条扫描线、多条数据线、多条正极信号线和多条参考信号线；
所述多个像素中的每一个像素包括：至少三种颜色的子像素和驱动各所述子像素发光的像素驱动芯片；
每一所述子像素包括至少一个无机发光二极管；
所述像素驱动芯片和与其驱动的每一所述子像素中的所述无机发光二极管的正极、所述多条数据线中的至少一条数据信号线、所述多条扫描线中的至少一条扫描线以及所述多条参考信号线中的至少一条参考信号线连接；
所述像素驱动芯片用于在所述扫描线的控制下，将所述数据信号线的信号分时写入不同颜色的子像素中，其中，所述参考信号线用于向所述像素驱动芯片提供负极信号以使所述无机发光二极管与所述像素驱动芯片之间形成电流通路。
可选地，在本公开实施例提供的阵列基板中，
所述多个像素包括N个沿第一方向排列的像素行和M个沿第二方向排列的像素列；N和M均为大于1的整数；
多条所述扫描线沿所述第一方向延伸且沿所述第二方向排布，所述多条数据信号线沿所述第二方向延伸且沿所述第一方向排布，所述多条正极信号线沿所述第二方向延伸且沿所述第一方向排布，所述多条参考信号线沿所述第二方向延伸且沿所述第一方向排布；
所述第一方向和所述第二方向不相同。
可选地，在本公开实施例提供的阵列基板中，
每一所述像素行对应所述多条扫描线中的一条扫描线，每一列所述像素列对应所述多条数据线中的一条数据信号线、所述多条参考信号线中的一条参考信号线和所述多条正极信号线中的一条正极信号线。
可选地，在本公开实施例提供的阵列基板中，
所述像素包括：第一颜色子像素、第二颜色子像素和第三颜色子像素；
每一所述像素行对应所述多条扫描线中的一条扫描线，每一所述像素列对应所述多条数据线中的一条数据信号线、所述多条参考信号线中的一条参考信号线和所述多条正极信号线中的两条正极信号线；
所述两条正极信号线中的其中一条正极信号线与所述第一颜色子像素中的无机发光二极管的正极连接，另一条正极信号线与所述第三颜色子像素和 所述第二颜色子像素中的无机发光二极管的正极连接。
可选地，在本公开实施例提供的阵列基板中，
所述显示区域还包括与多条所述扫描线中的每一条扫描线一一对应连接的扫描信号走线，且所述扫描信号走线沿所述第二方向延伸。
可选地，在本公开实施例提供的阵列基板中，
N＝M，每一所述像素列的一侧对应设置一条所述扫描信号走线，且相邻两列像素列之间仅设置一条所述扫描信号走线。
可选地，在本公开实施例提供的阵列基板中，
N>M，至少一个像素列的两侧分别至少设置一条所述扫描信号走线；
至少部分相邻两列像素列之间设置有至少一条所述扫描信号走线，且相邻两列像素列之间的所述扫描信号走线不超过两条。
可选地，在本公开实施例提供的阵列基板中，
所述扫描线位于第一金属层；所述扫描信号走线、所述数据信号线、所述参考信号线和所述正极信号线位于第二金属层。
可选地，在本公开实施例提供的阵列基板中，
位于所述数据信号线一端的所述边框区域包括依次远离所述显示区域的弯折区、布线区域和绑定区；
所述绑定区设置有至少一个第一芯片和至少一个第二芯片；
所述扫描信号走线和所述数据信号线依次通过位于所述弯折区和所述布线区的走线与所述第一芯片绑定连接；
所述参考信号线和所述正极信号线依次通过位于所述弯折区和所述布线区的走线与所述第二芯片绑定连接。
可选地，在本公开实施例提供的阵列基板中，
所述绑定区设置有多个所述第一芯片和多个所述第二芯片；
所述第一芯片和所述第二芯片在所述绑定区间隔分布。
可选地，在本公开实施例提供的阵列基板中，
所述弯折区的走线均位于所述第二金属层。
可选地，在本公开实施例提供的阵列基板中，
在所述布线区，与所述扫描信号走线连接的走线以及与所述数据信号线连接的走线均位于所述第一金属层；
在所述布线区，与所述参考信号线连接的走线以及与所述正极信号线连接的走线均位于所述第二金属层。
可选地，在本公开实施例提供的阵列基板中，
在所述布线区，与所述扫描信号走线连接的走线以及与所述数据信号线连接的走线均位于所述第二金属层；
在所述布线区，与所述参考信号连接的走线以及与所述正极信号线连接的走线均位于所述第一金属层。
可选地，在本公开实施例提供的阵列基板中，
规定所述扫描信号走线、所述数据信号线、所述参考信号线和所述正极信号线均为纵向信号线；
所述边框区域还包括：位于所述绑定区远离所述布线区一侧的第一信号输入区，位于所述数据信号线远离所述弯折区一端的第二信号输入区；
所述第一信号输入区设置有与各所述纵向信号线一一对应的第一输入电极，且所述显示区域内的各所述纵向信号线依次通过位于所述弯折区和所述布线区的走线与对应的所述第一输入电极连接；
所述第二信号输入区设置有与各所述纵向信号线一一对应连接的第二输入电极。
可选地，在本公开实施例提供的阵列基板中，
位于所述扫描线一端的所述边框区域包括第三信号输入区；
位于所述扫描线另一端的所述边框区域包括第四信号输入区；
所述第三信号输入区设置有与各所述扫描线一一对应连接的第三输入电极；
所述第四信号输入区设置有与各所述扫描线一一对应连接的第四输入电极。
第二方面，本公开实施例还提供了一种拼接显示面板，其中，包括多个本公开实施例提供的上述任一种阵列基板。
第三方面，本公开实施例还提供了一种上述任一种阵列基板的检测方法，其中，规定所述显示区域内的所述纵向信号线与所述扫描线均为待检测线，所述检测方法包括：
针对各所述待检测线，向与所述待检测线连接的其中一个输入电极输入测试信号；
检测与所述待检测线连接的另一输入电极是否有信号输出，如果没有，则确定所述待检测线发生断路；
检测与除输入有所述测试信号的所述待检测线之外的其它待检测线的输入电极是否有信号输出，如果有，则确定输入有所述测试信号的所述待检测线与输入电极有信号输出的其它所述待检测线之间发生短路。
附图说明
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的另一种阵列基板的结构示意图；
图3为本公开实施例提供的一种阵列基板中像素的结构示意图；
图4为本公开实施例提供的另一种阵列基板中像素的结构示意图；
图5为本公开实施例提供的又一种阵列基板的结构示意图；
图6为本公开实施例提供的又一种阵列基板的结构示意图；
图7为本公开实施例提供的阵列基板中一个像素对应的一种阵列布局结构示意图；
图8为本公开实施例提供的阵列基板中一个像素对应的另一种阵列布局结构示意图；
图9为本公开实施例提供的又一种阵列基板的结构示意图；
图10为本公开实施例提供的阵列基板中布线区的局部剖面结构示意图；
图11为本公开实施例提供的阵列基板中扫描信号走线的剖面结构示意图；
图12为本公开实施例提供的阵列基板中参考信号线的剖面结构示意图；
图13为本公开实施例提供的又一种阵列基板的结构示意图；
图14为本公开实施例提供的阵列基板的检测方法的流程图。
具体实施方式
发明人发现，次毫米发光二极管和微型发光二极管存在低电流密度下亮度均一性差等问题，因此次毫米发光二极管和微型发光二极管必须采用大电流密度驱动发光。微型无机发光二极管的电流密度比有机发光二极管的电流密度大至少两个数量级，因此微型无机发光二极管不能像有机发光二极管一样，采用由薄膜晶体管形成像素电路进行驱动，如若采用由薄膜晶体管形成像素电路进行驱动，需要将薄膜晶体管的尺寸做的较大才能产生大电流密度，薄膜晶体管尺寸大会导致均一性差，且功耗比较大，并且现有的有机发光二极管中的像素电路也不能直接应用于微型无机发光二极管。
有鉴于此，本公开实施例提供了一种阵列基板、其检测方法及拼接显示面板。
为使本公开的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本公开做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本公开中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本公开保护范围内。本公开的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本公开。但是本公开能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本公开内涵的情况下做类似推广。因此本公开不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然所 述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
下面结合附图，对本公开实施例提供的阵列基板、其检测方法及拼接显示面板进行具体说明。
本公开实施例提供的一种阵列基板，如图1和图2所示，阵列基板包括显示区域A1和边框区域A2；显示区域A1具有矩阵排列的多个像素1、多条扫描线Sn、多条数据线Dm、多条正极信号线Hm和多条参考信号线Vm；
如图3所示，多个像素中的每一像素1包括：至少三种颜色的子像素01和驱动各子像素01发光的像素驱动芯片02；
每一子像素01包括至少一个无机发光二极管；
像素驱动芯片2和与其驱动的每一子像素01中的无机发光二极管的正极、该多条数据线中的至少一条数据信号线Dm、该多条扫描线中的至少一条扫描线Sn以及该多条参考信号线中的至少一条参考信号线Vm连接；
像素驱动芯片2用于在扫描线Sn的控制下，将数据信号线Dm的信号分时写入不同颜色的子像素01中，其中，参考信号线Vm用于向像素驱动芯片2提供负极信号，以使像素驱动芯片2和无机发光二极管之间形成电流通路。
本公开实施例提供的阵列基板，像素包括：至少三种颜色的子像素和驱动各子像素发光的像素驱动芯片；每一子像素包括至少一个无机发光二极管；显示区域还包括：与无机发光二极管的正极连接的正极信号线，与像素驱动芯片连接的数据信号线、扫描线以及参考信号线；像素驱动芯片用于在扫描线的控制下，将数据信号线的信号分时写入不同颜色的子像素中。即在本公开实施例中，利用像素驱动芯片直接驱动各像素实现显示。并且，由于利用像素驱动芯片直接驱动各像素，因此可以向微型无机发光二极管提供大电流密度。
在具体实施时，在本公开实施例提供的阵列基板中，无机发光二极管可以为次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)或微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)，在 此不作限定。
在具体实施时，在本公开实施例提供的阵列基板中，每一子像素中包括至少一个无机发光二极管，例如每一子像中包括一个无机发光二极管、两个无机发光二极管、三个无机发光二极管或者多个无机发光二极管，在此不作限定。说明书附图中以每一子像中包括两个无机发光二极管为例进行示意。
可选地，在本公开实施例提供的阵列基板中，如图1和图3所示，显示区域A1包括N个沿第一方向X排列的像素行和M个沿第二方向排列的像素列；N和M均为大于1的整数；
多条扫描线Sn沿第一方向X延伸且沿第二方向Y排布，多条数据信号线Dm沿第二方向Y延伸且沿第一方向X排布，多条正极信号线Hm沿第二方向Y延伸且沿第一方向X排布，多条参考信号线Vm沿第二方向Y延伸且沿第一方向X排布；
第一方向X和第二方向Y不相同。可选地，为了减少显示区域布线，在本公开实施例提供的阵列基板中，如图1和图3所示，每一像素行对应连接多条扫描线中的一条扫描线Sn，每一像素列对应多条数据线中的一条数据信号线Dm、多条参考信号线中的一条参考信号线Vm和多条正极信号线中的一条正极信号线Hm。
在具体实施时，第一颜色无机发光二极管与第二颜色无机发光二极管的电流转换效率差异较小，而第一颜色无机发光二极管与第二颜色无机发光二极管两者的电流转换效率和第三颜色无机发光二极管的电流转换效率相差较大，因此，第一颜色无机发光二极管的正极需要接收的电信号与第二颜色无机发光二极管和第三颜色无机发光二极管的正极需要接收的电信号的大小差异较大。当同一像素中不同颜色的子像素对应同一条正极信号线时，需要正极信号线提供的信号能够让第一颜色无机发光二极管、第二颜色无机发光二极管和第三颜色无机发光二极管发出最大亮度，从而导致功耗增加。可选地，在本公开实施例提供的阵列基板中，如图2和图4所示，像素1包括：第一颜色子像素01(R)、第二颜色子像素01(B)和第三颜色子像素01(G)；
每一像素行对应连接多条扫描线中的一条扫描线Sn，每一像素列对应多条数据线中的一条数据信号线Dm、多条参考信号线中的一条参考信号线Vm和多条正极信号线中的两条正极信号线Hm1和Hm2；
该两条正极信号线Hm1和Hm2中的其中一条正极信号线Hm1与第一颜色子像素01(R)中的无机发光二极管的正极连接，另一条正极信号线Hm2与第三颜色子像素01(G)和第二颜色子像素01(B)中的无机发光二极管的正极连接。这样，可以使第三颜色子像素01(G)和第二颜色子像素01(B)中的无机发光二极管的正极收到的信号相同，而第一颜色子像素01(R)中的无机发光二极管的正极收到的信号相对于其他两个颜色的子像素收到的信号幅值较大，从而能够避免三种颜色的子像素的正极均接收三个颜色子像素中需要信号幅值最大者的信号，从而可以降低功耗。
在具体实施时，第一颜色、第二颜色和第三颜色可以分别为红色、蓝色和绿色中的一种，例如第一颜色为红色，第二颜色为蓝色、第三颜色为绿色，在此不作限定。可选地，在本公开实施例提供的阵列基板中，如图5所示，显示区域A1还包括与多条扫描线中的每一条扫描线Sn一一对应连接的扫描信号走线Cn，且扫描信号走线Cn沿第二方向Y延伸。这样可以通过扫描信号走线Cn向对应的扫描线Sn提供扫描信号，从而可以将用于提供扫描信号的信号源设置在扫描信号走线Cn的两端，避免在扫描线Sn两端设置用于提供扫描信号的芯片。
可选地，在本公开实施例提供的阵列基板中，如图5所示，当显示区域A1中像素行的个数N和像素列的个数M相同时，即N＝M时；
每一像素列的一侧对应设置一条扫描信号走线Cn，且相邻两列像素列之间仅设置一条扫描信号走线Cn。
可选地，在本公开实施例提供的阵列基板中，如图6所示，当显示区域A1中像素行的个数N大于像素列的个数M时，即N>M时；
至少一个像素列的两侧分别至少设置一条扫描信号走线Cn(例如图6中的第2列像素列，其左侧设置有一条扫描信号走线C1，其右侧设置有两条扫 描信号走线C2和C3)；至少部分相邻两列像素列之间均设置有至少一条扫描信号走线Cn。
在具体实施时，以每相邻的K列像素列为一组重复单元，在每组重复单元中，其中一列像素列的两侧分别至少设置有一条扫描信号走线，例如其中一侧设置有两条扫描信号走线，另一侧设置有一条扫描信号走线；而其余K-1列像素列的两侧分别最多设置有一条扫描信号走线，例如其中一侧设置有一条扫描信号走线，另一侧没有扫描信号走线(例如该像素列位于显示面板最外侧)或者仅设置有一条扫描信号走线(例如该像素列位于显示面板的非最外侧)。其中，K＝(min[N,M])/|N-M|。
以N＝135，M＝120为例，需要有15列像素列的两侧分别对应设置有两条扫描信号走线，要使该15列像素列在120列像素列中均匀分布，那么每8列像素列中需要有一列像素列的两侧分别至少设置有一条扫描信号走线。以每相邻的8列像素列为一组重复单元，总共有15组重复单元，在每组重复单元中选择其中一列像素列的两侧分别至少设置有一条扫描信号走线，其余7列像素列的两侧分别最多设置有一条扫描信号走线。
可选地，在本公开实施例提供的阵列基板中，如图7和图8所示，扫描线Sn同层设置于第一金属层；扫描信号走线Cn、数据信号线Dm、参考信号线Vm和正极信号线Hm1和Hm2同层设置于第二金属层。
在本公开实施例中，两结构“同层设置”或者“位于同一层”，可以指二者是在同一次成膜工艺形成的，或者二者是在同一次构图工艺中形成，或者它们在层叠关系上处于相同层中，也可以代表它们与基底间的距离相等。
具体地，在本公开实施例提供的阵列基板中，第一金属层可以位于第二金层远离衬底基板100的一侧，或者，第二金属层位于第一金属层远离衬底基板100的一侧，在此不作限定。
在具体实施时，如图7和图8所示，像素驱动芯片(图7和图8未视出)具有第一信号端O1、第二信号端O2、第三信号端O3、第四信号端O4、第五信号端O5和第六信号端O6。其中，第一信号端O1与第一颜色无机发光二 极管的负极R-连接，像素驱动芯片的第二信号端O2与第三颜色无机发光二极管的负极G-连接，像素驱动芯片的第三信号端O3与第二颜色无机发光二极管的负极B-连接，像素驱动芯片的第四信号端O4与扫描线Sn连接、像素驱动芯片的信号端第五O5通过过孔P1与数据信号线Dn连接、像素驱动芯片的第六信号端O6通过过孔P2与参考信号线Vm连接，第一颜色无机发光二极管的正极R+通过过孔P5与正极信号线Hm1连接，第三颜色无机发光二极管的正极G+通过过孔P4与正极信号线Hm2连接，第二颜色无机发光二极管的正极B+通过过孔P4与正极信号线Hm2连接。
图7为一列像素在其行方向的两侧只设置有一条扫描信号走线Cn的结构示意图，在图7中，扫描信号走线Cn通过过孔P3与扫描线Sn连接。
图8为一列像素在其行方向的两侧均设置有扫描信号走线(Cn和C n+1)的结构示意图，在图8中，扫描信号走线Cn通过过孔P3与扫描线Sn连接，扫描信号走线C n+1与其它扫描线(图8中未视出)连接。其中，
可选地，在本公开实施例提供的阵列基板中，如图9所示，位于数据信号线Dm一端的边框区域A2包括依次远离显示区域A1的弯折区A21、布线区域A22和绑定区A23；
绑定区23设置有至少一个第一芯片IC1和至少一个第二芯片IC2；
扫描信号走线Cn和数据信号线Dm依次通过位于弯折区A21和布线区A22的走线与第一芯片IC1绑定连接；
参考信号线Vm和正极信号线Hm依次通过位于弯折区A21和布线区A22的走线与第二芯片IC2绑定连接。
在具体实施时，在本公开实施例提供的阵列基板中，绑定区可以仅设置有一个第一芯片和一个第二芯片。这样可以减少芯片的数量。
在具体实施时，当绑定区A23仅设置有一个第一芯片IC1和一个第二芯片IC2时。例如图13所示，第一芯片IC1位于左侧，第二芯片IC2位于右侧，那么布线区A22左侧的走线距离第一芯片IC1较近，距离第二芯片IC2较远，布线区A22右侧的走线距离第一芯片IC1较远，距离第二芯片IC2较近，即 布线区A22左侧走线和右侧走线距离同一芯片的距离不相同，从而导致布线区走线长度差异较大，即走线的负载Loading不一致，从而导致显示不均匀。
在具体实施时，扫描信号走线提供的是数字电压信号，作用是控制数据信号线上的信号何时写入像素驱动芯片。因此扫描信号走和数据信号线上导通电流较小，对布线区走线产生的IR drop不敏感，因此，在走线区，对应走线宽度可以相对设置的窄一些和/或长度可以设置的相对长一些。而参考信号线和正极信号线上的信号均为固定电压信号，但由于串联在无机发光二极管的电流通路中，而该电流通路中会流过mA量级的电流，故布线区走线产生的IR drop会影响电流通路的信号，因此，对布线区域走线的宽度和长度的要求高，需要尽量增加线宽和/或缩短线长。
因此，在本公开实施例提供的阵列基板中，如图9所示，绑定区A23设置有多个第一芯片IC1和多个第二芯片IC2；第一芯片IC1和第二芯片IC2在绑定区A23间隔分布，从而降低布线区走线的长度差异。
进一步地，可以使第一驱动芯片设置在靠近绑定区域中心的位置，将第二芯片设置在靠近绑定区域两侧的位置，这样可以使与第一芯片连接的走线的长度可以设置的相对长一些，与第二芯片连接的走线的长度设置的相对短一些。
进一步，在本公开实施例提供的阵列基板中，由于信号线的功能不同，故需要使用不同的芯片提供信号，但也可以使用单颗芯片能够提供不同种类的信号，在这种情况下，该芯片的引脚分布也可以参考上述规则进行设置，例如将向扫描信号走线和数据信号线提供信号的引脚设置在芯片的中间区域，将向参考信号线和正极信号线提供信号的引脚设置在芯片的两端。可选地，在本公开实施例提供的阵列基板中，如图9所示，弯折区A21的走线03均位于第二金属层。
可选地，在本公开实施例提供的阵列基板中，如图9和图10所示，在布线区A22，与扫描信号走线Cn连接的走线041以及与数据信号线Dm连接的走线042均位于第一金属层；
在布线区A22，与参考信号线Vm连接的走线051以及与正极信号线Hm连接的走线052均位于第二金属层。其中，图10中以第二金属层位于第一金属层与衬底基板100之间为例。具体地，在第一金属层与第二金属层之间还设置有平坦化层101，在第一金属层上方还设置有保护层102。
在具体实施时，平坦化层的材料可以为氧化硅或者氮化硅等无极材料，也可以为树脂等有机材料，在此不作限定。
在具体实施时，保护层的材料可以为氧化硅或者氮化硅等无极材料，也可以为树脂等有机材料，在此不作限定。
或者，可选地，在本公开实施例提供的阵列基板中，在布线区，与扫描信号走线连接的走线以及与数据信号线连接的走线均位于第二金属层；
在布线区，与参考信号连接的走线以及与正极信号线连接的走线均位于第一金属层。
在具体实施时，在本公开实施例提供的阵列基板中，在布线区，将走线设在两层金属层中，这样可以解决布线区空间有限的问题。
在具体实施时，在本公开实施例提供的阵列基板，在阵列基板制程完成后，布线区和绑定区通过弯折区弯折至显示面板背面，从而可以降低显示面板边框。
在具体实施时，在本公开实施例提供的阵列基板中，如图9所示，规定扫描信号走线Cn、数据信号线Dm、参考信号线Vm和正极信号线Hm均为纵向信号线；
边框区域A2还包括：位于绑定区A23远离布线区A22一侧的第一信号输入区A24，位于数据信号线Dm远离弯折区A21一端的第二信号输入区A25；
第一信号输入区A24设置有与各纵向信号线一一对应的第一输入电极Tp1，且显示区域A1内的各纵向信号线依次通过位于弯折区A21和布线区A22的走线与对应的第一输入电极Tp1连接；
第二信号输入区A25设置有与各纵向信号线一一对应连接的第二输入电极Tp2。
以在布线区A22，与扫描信号走线Cn连接的走线041以及与数据信号线Dm连接的走线042均位于第一金属层；在布线区A22，与参考信号线Vm连接的走线051以及与正极信号线Hm连接的走线052均位于第二金属层为例。
具体地，如图11所示，位于第二金属层的扫描信号走线Cn依次通过位于弯折区A21且位于第二金属层的走线03、位于布线区A22且位于第一金属层的走线041与绑定区A23的第一芯片IC1通过透明导电层103绑定，并与第一信号输入区A24的第一输入电极Tp1连接。其中，数据信号线的膜层关系与扫描信号走线相同，在此不再赘述。
具体地，如图12所示，位于第二金属层的参考信号线Vm依次通过位于弯折区A21且位于第二金属层的走线03、位于布线区A22且位于第二金属层的走线051与绑定区A23的第二芯片IC2通过第一金属层以及透明导电层103绑定，并与第一信号输入区A24的第一输入电极Tp1连接。其中正极信号线的膜层关系与参考信号线相同，在此不再赘述。
可选地，在本公开实施例提供的阵列基板中，如图9所示，位于扫描线Sn一端的边框区域A2包括第三信号输入区A26；位于扫描线Sn另一端的所述边框区域包括第四信号输入区A27；第三信号输入区A26设置有与各扫描线Sn一一对应连接的第三输入电极Tp3；第四信号输入区A27设置有与各扫描线Sn一一对应连接的第四输入电极Tp4。
在具体实施时，通过向输入电极输入信号，并检测其它输入电极信号的方式可以检测阵列基板上各纵向信号线是否正常。在检测完毕确认为良品后，可将信号输入区可被切割掉，不会影响面板的后续使用。
基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的任一种阵列基板的检测方法，规定显示区域内的纵向信号线与扫描线均为待检测线，如图14所示，该检测方法包括：
S101、针对各待检测线，向与该待检测线连接的其中一个输入电极输入测试信号。
S102、检测与该待检测线连接的另一输入电极是否有信号输出，如果没 有，则确定该待检测线发生断路。
S103、检测与除了输入有测试信号的该待检测线之外的其它待检测线的输入电极是否有信号输出，如果有，则确定输入有测试信号的该待检测线与输入电极有信号输出的其它待检测线之间发生短路。
本公开实施例提供的检测方法，通过向输入电极输入信号，检测其它输入电极信号的方法可以检测待检测线是否有短路或者断路的发生，检测方法简单。并且，将该检测方法应用于阵列基板的制备过程中可以降低成本。
在具体实施时，在本公开实施例提供的检测方法中，对步骤S102和步骤S103的顺序不作限定。可以先执行步骤S102，后执行步骤S103；也可以先执行步骤S103，后执行步骤S102，在此不作限定。
下面通过实施例说明本公开实施例提供的阵列基板的检测方法的应用。
在具体实施时，以第二金属层位于第一金属层下方为例，在生产中，首先制备第二层金属层，在第二金属层中形成扫描信号走线、数据信号线、参考信号线和正极信号线；针对参考信号线和正极信号线，此时可利用第一信号输入区的第一输入电极与第二信号输入区的第二输入电极之间相互配合使用，检测参考信号线和正极信号线是否正常，例如：向参考信号线的第一输入电极输入测试信号，检测与该参考信号线连接的第二输入电极上是否有信号输出，如果有，则确定该参考信号线正常，如果没有，则确定该参考信号线发生了断路，对该参考信号线进行修复。检测除该参考信号线之外其它信号线连接的第一输入电极或第二输入电极上是否有信号输出，如果没有，则确定该参考信号线与其它信号线之间无短路发生，如果有，则确定该参考信号线与其它信号线发生短路，对发生短路的信号线进行修复。当所有参考信号线和正极信号线均无异常后，则继续沉积平坦化层，并在平坦化层形成过孔。此时重复对参考信号线和正极信号线进行检测，检测结果正常后，再继续沉积第二层金属层，在第二金属层中形成扫描线，并完成数据信号线和扫描信号走线与第一输出电极的信号间连接。此时，可利用第一信号输入区的第一输入电极、第二信号输入区的第二输入电极、第三信号输入区的第三输 入电极以及第四信号输入区的第四输入电极之间相互配合使用，检测阵列基板上所有信号线是否正常，如果有短路或者断路发生，则进行修复，直到所有信号线均正常后继续进行后续制程。从而避免后续由于信号线异常导致阵列基板报废，进而降低生产成本。
基于同一发明构思，本公开实施例还提供了一种拼接显示面板，包括多个本公开实施例提供的阵列基板。由于该拼接显示面板解决问题的原理与前述一种阵列基板相似，因此该拼接显示面板的实施可以参见前述阵列基板的实施，重复之处不再赘述。
在具体实施时，在本公开实施例提供的拼接显示面板中，阵列基板中的第二信号输入区、第三信号输入区和第四信号输入区在阵列基板制程结束后，均可切割，不影响后续拼接制程；布线区和绑定区通过弯折区弯折至显示面板背面，从而可以缩减显示面板边框宽度。
在具体实施时，本公开实施例提供的拼接显示面板，多个阵列基板通过弯折区将布线区和绑定区通过弯折区弯折至显示面板背面，其以构图工艺数量少、无需背面工艺、工艺复杂度低、边框小等优势，具有很高的技术价值。
本公开实施例提供的上述阵列基板、其检测方法及拼接显示面板，在阵列基板中像素包括：至少三种颜色的子像素和驱动各子像素发光的像素驱动芯片；每一子像素包括至少一个无机发光二极管；显示区域还包括：与无机发光二极管的正极连接的正极信号线，与像素驱动芯片连接的数据信号线、扫描线以及参考信号线；像素驱动芯片用于在扫描线的控制下，将数据信号线的信号分时写入不同颜色的子像素中。即在本公开实施例中，利用像素驱动芯片直接驱动各像素实现显示。并且，由于利用像素驱动芯片直接驱动各像素，因此可以向微型无机发光二极管提供大电流密度。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种阵列基板，其中：
    所述阵列基板包括显示区域和边框区域；所述显示区域包括多条扫描线、多条数据线、多条正极信号线和多条参考信号线以及阵列排布的多个像素；
    所述多个像素中的至少一个像素包括：至少三种颜色的子像素和驱动各所述子像素发光的像素驱动芯片；
    每一所述子像素包括至少一个无机发光二极管；
    所述像素驱动芯片和与其驱动的每一所述子像素中的所述无机发光二极管的正极、所述多条数据线中的至少一条数据信号线、所述多条扫描线中的至少一条扫描线以及所述多条参考信号线中的至少一条参考信号线连接；
    所述像素驱动芯片用于在所述扫描线的控制下，将所述数据信号线的信号分时写入不同颜色的子像素中，其中，所述参考信号线用于向所述像素驱动芯片提供负极信号以使所述无机发光二极管与所述像素驱动芯片之间形成电流回路。
  2. 如权利要求1所述的阵列基板，其中，
    所述多个像素包括沿N个第一方向排列的像素行和M个沿第二方向排列的M列像素列；N和M均为大于1的整数；
    多条所述扫描线沿所述第一方向延伸且沿所述第二方向排布，所述多条数据信号线沿所述第二方向延伸且沿所述第一方向排布，所述多条正极信号线沿所述第二方向延伸且沿所述第一方向排布，所述多条参考信号线沿所述第二方向延伸且沿所述第一方向排布；
    所述第一方向和所述第二方向不相同。
  3. 如权利要求2所述的阵列基板，其中，
    每一所述像素行对应所述多条扫描线中的一条扫描线，每一列所述像素列对应所述多条数据线中的一条数据信号线、所述多条参考信号线中的一条参考信号线和所述多条正极信号线中的一条正极信号线。
  4. 如权利要求2所述的阵列基板，其中，
    所述像素包括：第一颜色子像素、第二颜色子像素和第三颜色子像素；
    每一所述像素行对应所述多条扫描线中的一条扫描线，每一所述像素列对应所述多条数据线中的一条数据信号线、所述多条参考信号线中的一条参考信号线和所述多条正极信号线中的两条正极信号线；
    所述两条正极信号线中的其中一条正极信号线与所述第一颜色子像素中的无机发光二极管的正极连接，另一条正极信号线与所述第三颜色子像素和所述第二颜色子像素中的无机发光二极管的正极连接。
  5. 如权利要求3或4所述的阵列基板，其中，
    所述显示区域还包括与多条所述扫描线中的每一条扫描线一一对应连接的扫描信号走线，且所述扫描信号走线沿所述第二方向延伸。
  6. 如权利要求5所述的阵列基板，其中，
    N＝M，每一所述像素列的一侧对应设置一条所述扫描信号走线，且相邻两列像素列之间仅设置一条所述扫描信号走线。
  7. 如权利要求5所述的阵列基板，其中，
    N>M，至少一个像素列的两侧分别至少设置一条所述扫描信号走线；
    至少部分相邻两列像素列之间设置有至少一条所述扫描信号走线，且相邻两列像素列之间的所述扫描信号走线不超过两条。
  8. 如权利要求5所述的阵列基板，其中，
    所述扫描线位于第一金属层；所述扫描信号走线、所述数据信号线、所述参考信号线和所述正极信号线位于第二金属层。
  9. 如权利要求8所述的阵列基板，其中，
    位于所述数据信号线一端的所述边框区域包括依次远离所述显示区域的弯折区、布线区域和绑定区；
    所述绑定区设置有至少一个第一芯片和至少一个第二芯片；
    所述扫描信号走线和所述数据信号线依次通过位于所述弯折区和所述布线区的走线与所述第一芯片绑定连接；
    所述参考信号线和所述正极信号线依次通过位于所述弯折区和所述布线区的走线与所述第二芯片绑定连接。
  10. 如权利要求9所述的阵列基板，其中，
    所述绑定区设置有多个所述第一芯片和多个所述第二芯片；
    所述第一芯片和所述第二芯片在所述绑定区间隔分布。
  11. 如权利要求9所述的阵列基板，其中，
    所述弯折区的走线均位于所述第二金属层。
  12. 如权利要求9所述的阵列基板，其中，
    在所述布线区，与所述扫描信号走线连接的走线以及与所述数据信号线连接的走线均位于所述第一金属层；
    在所述布线区，与所述参考信号线连接的走线以及与所述正极信号线连接的走线均位于所述第二金属层。
  13. 如权利要求9所述的阵列基板，其中，
    在所述布线区，与所述扫描信号走线连接的走线以及与所述数据信号线连接的走线均位于所述第二金属层；
    在所述布线区，与所述参考信号连接的走线以及与所述正极信号线连接的走线均位于所述第一金属层。
  14. 如权利要求9所述的阵列基板，其中，
    规定所述扫描信号走线、所述数据信号线、所述参考信号线和所述正极信号线均为纵向信号线；
    所述边框区域还包括：位于所述绑定区远离所述布线区一侧的第一信号输入区，位于所述数据信号线远离所述弯折区一端的第二信号输入区；
    所述第一信号输入区设置有与各所述纵向信号线一一对应的第一输入电极，且所述显示区域内的各所述纵向信号线依次通过位于所述弯折区和所述布线区的走线与对应的所述第一输入电极连接；
    所述第二信号输入区设置有与各所述纵向信号线一一对应连接的第二输入电极。
  15. 如权利要求14所述的阵列基板，其中，
    位于所述扫描线一端的所述边框区域包括第三信号输入区；
    位于所述扫描线另一端的所述边框区域包括第四信号输入区；
    所述第三信号输入区设置有与各所述扫描线一一对应连接的第三输入电极；
    所述第四信号输入区设置有与各所述扫描线一一对应连接的第四输入电极。
  16. 一种拼接显示面板，其中，包括多个如权利要求1-15任一项所述的阵列基板。
  17. 一种如权利要求14或15所述的阵列基板的检测方法，其中，规定所述显示区域内的所述纵向信号线与所述扫描线均为待检测线，所述检测方法包括：
    针对各所述待检测线，向与所述待检测线连接的其中一个输入电极输入测试信号；
    检测与所述待检测线连接的另一输入电极是否有信号输出，如果没有，则确定所述待检测线发生断路；
    检测与除输入有所述测试信号的所述待检测线之外的其它待检测线的输入电极是否有信号输出，如果有，则确定输入有所述测试信号的所述待检测线与输入电极有信号输出的其它所述待检测线之间发生短路。
PCT/CN2021/085957 2020-05-13 2021-04-08 阵列基板、其检测方法及拼接显示面板 WO2021227713A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114822333A (zh) * 2022-04-20 2022-07-29 重庆翰博显示科技研发中心有限公司 一种Microled或Miniled的异常像素实时检测修复方法及装置
CN117413312A (zh) * 2022-04-24 2024-01-16 京东方科技集团股份有限公司 电子设备及显示驱动方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120127559A1 (en) * 2010-11-16 2012-05-24 Imec Holographic visualization system comprising a high data refresh rate dnd driver array
CN109298801A (zh) * 2018-10-19 2019-02-01 合肥京东方光电科技有限公司 一种触控显示装置及其驱动方法
CN109994071A (zh) * 2017-12-29 2019-07-09 乐金显示有限公司 发光显示装置
CN109994068A (zh) * 2017-12-29 2019-07-09 乐金显示有限公司 显示设备
CN110010093A (zh) * 2017-12-29 2019-07-12 乐金显示有限公司 发光显示装置
CN111103726A (zh) * 2018-10-29 2020-05-05 北京小米移动软件有限公司 背光源、显示装置和背光源控制方法
CN211654192U (zh) * 2020-05-13 2020-10-09 京东方科技集团股份有限公司 阵列基板及拼接显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6496238B1 (en) * 2000-01-21 2002-12-17 Rainbow Displays, Inc. Construction of large, robust, monolithic and monolithic-like, AMLCD displays with wide view angle
KR102144767B1 (ko) * 2014-06-02 2020-08-31 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
JP6966943B2 (ja) 2015-06-10 2021-11-17 アップル インコーポレイテッドApple Inc. ディスプレイパネルの冗長スキーム
WO2017053477A1 (en) * 2015-09-25 2017-03-30 Sxaymiq Technologies Llc Hybrid micro-driver architectures having time multiplexing for driving displays
KR102479508B1 (ko) * 2016-03-31 2022-12-20 삼성디스플레이 주식회사 표시 장치
KR102246926B1 (ko) * 2016-11-09 2021-04-30 삼성전자주식회사 Led 디스플레이 모듈 및 디스플레이 장치
US10522608B2 (en) 2016-12-06 2019-12-31 Samsung Display Co., Ltd. Display device
WO2021167292A1 (en) * 2020-02-20 2021-08-26 Samsung Electronics Co., Ltd. Display apparatus and control method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120127559A1 (en) * 2010-11-16 2012-05-24 Imec Holographic visualization system comprising a high data refresh rate dnd driver array
CN109994071A (zh) * 2017-12-29 2019-07-09 乐金显示有限公司 发光显示装置
CN109994068A (zh) * 2017-12-29 2019-07-09 乐金显示有限公司 显示设备
CN110010093A (zh) * 2017-12-29 2019-07-12 乐金显示有限公司 发光显示装置
CN109298801A (zh) * 2018-10-19 2019-02-01 合肥京东方光电科技有限公司 一种触控显示装置及其驱动方法
CN111103726A (zh) * 2018-10-29 2020-05-05 北京小米移动软件有限公司 背光源、显示装置和背光源控制方法
CN211654192U (zh) * 2020-05-13 2020-10-09 京东方科技集团股份有限公司 阵列基板及拼接显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4033477A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230154385A1 (en) * 2021-03-04 2023-05-18 Boe Technology Group Co., Ltd. Light emitting substrate, display apparatus, and method of driving light emitting substrate
US11694607B2 (en) * 2021-03-04 2023-07-04 Boe Technology Group Co., Ltd. Light emitting substrate, display apparatus, and method of driving light emitting substrate

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CN113689796A (zh) 2021-11-23
US20240304136A1 (en) 2024-09-12
KR20230009867A (ko) 2023-01-17
US20220406245A1 (en) 2022-12-22

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