WO2021102734A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021102734A1
WO2021102734A1 PCT/CN2019/121249 CN2019121249W WO2021102734A1 WO 2021102734 A1 WO2021102734 A1 WO 2021102734A1 CN 2019121249 W CN2019121249 W CN 2019121249W WO 2021102734 A1 WO2021102734 A1 WO 2021102734A1
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WIPO (PCT)
Prior art keywords
data
signal
shift register
signal supply
line
Prior art date
Application number
PCT/CN2019/121249
Other languages
English (en)
French (fr)
Inventor
赵蛟
肖丽
玄明花
郑皓亮
刘冬妮
刘静
齐琪
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/121249 priority Critical patent/WO2021102734A1/zh
Priority to EP19945454.7A priority patent/EP4068262A4/en
Priority to US17/052,526 priority patent/US11854493B2/en
Priority to KR1020217037882A priority patent/KR20220104638A/ko
Priority to JP2021572042A priority patent/JP2023510660A/ja
Priority to CN201980002617.8A priority patent/CN113179662B/zh
Publication of WO2021102734A1 publication Critical patent/WO2021102734A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the invention belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • Miniature inorganic light-emitting diodes are a new generation of display technology, with higher brightness, better luminous efficiency and lower power consumption than existing OLED technology.
  • ESD micro-inorganic light-emitting diode display substrate
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.
  • an embodiment of the present invention provides a display substrate, which includes:
  • a plurality of pixel units arranged in an array, a plurality of signal lines and a signal supply module are arranged on the substrate; wherein,
  • the signal supply module includes: a signal supply circuit and a redundant signal supply circuit;
  • Each of the signal supply modules is electrically connected to at least one of the plurality of pixel units through at least one of the plurality of signal lines.
  • the signal supply circuit and redundant signal supply circuit of each signal supply module are electrically connected to at least one of the plurality of pixel units through at least one of the plurality of signal lines.
  • each pixel unit includes a plurality of sub-pixels;
  • the signal line includes a data line group, and each data line group includes a plurality of data lines;
  • the pixel units located in the same column are connected to the same data line group,
  • the sub-pixels in the same column are connected to the same data line, and the sub-pixels in different columns are connected to different data lines;
  • the signal supply module and the data line group are arranged in a one-to-one correspondence;
  • the signal supply circuit includes: a first data selector; the redundant signal supply circuit includes: a second data selector;
  • the first data selector and the second data selector of each of the signal supply modules are electrically connected to the pixel unit through the corresponding data line group.
  • the display substrate further includes: a data voltage lead-in line, a first electrostatic ring structure, and a second electrostatic ring structure;
  • the data voltage lead-in line is connected to the first data selector through the first electrostatic ring structure; a first protection resistor is connected between the data voltage lead-in line and the first electrostatic ring structure; A second protection resistor is connected between an electrostatic ring and the first data selector;
  • the data voltage lead-in line is connected to the second data selector through the second electrostatic ring structure; a third protection resistor is connected between the data voltage lead-in line and the second electrostatic ring structure; A fourth protection resistor is connected between the second electrostatic ring and the second data selector.
  • first electrostatic ring structure and the second electrostatic ring structure both include a first electrostatic transistor, a second electrostatic transistor, a third electrostatic transistor, and a fourth electrostatic transistor;
  • the first electrode of the first electrostatic transistor is connected to its control electrode and the data voltage lead-in line
  • the second electrode is connected to the first electrode and the control electrode of the second electrostatic transistor
  • the second electrode of the second electrostatic transistor is connected to the working level Signal end
  • the first electrode of the third static transistor is connected to the control electrode and the data voltage lead-in line
  • the second electrode is connected to the first electrode and the control electrode of the fourth electrostatic transistor
  • the second electrode of the fourth electrostatic transistor is connected to the non-operating level signal terminal.
  • the resistance values of the first protection resistor, the second protection resistor, the third protection resistor, and the fourth resistor are all between 400 ⁇ -500 ⁇ .
  • the pixel unit includes three sub-pixels; the data line group includes three data lines.
  • the first data selector and the second data selector are located on the side of the signal input end of the data line of the substrate.
  • the signal line includes a gate line; the pixel units located in the same row are connected to the same gate line; the signal supply circuit of each of the signal supply modules includes: a first shift register, and the redundant signal supply The circuit includes: a second shift register; the first shift register and the second shift register are arranged in a pair and connected to the same gate line;
  • the gate line connects a pair of the first shift register and the second shift register in at least one of the signal supply modules.
  • the gate line is connected to two of the signal supply modules, and the two signal supply modules are respectively connected to two opposite ends of the gate line.
  • a plurality of the first shift registers in the signal supply module are connected in cascade, and a plurality of the second shift registers are connected in cascade; each stage of the first shift register is connected to a different gate line. Connection; the second shift registers of each stage are respectively connected to different gate lines;
  • the signal input terminal of the first shift register of the Nth stage is connected to the signal output terminal of the first shift register of the N-1th stage; the signal output terminal of the first shift register of the Nth stage is connected to the N-1th stage The signal input terminal of the first shift register;
  • the signal input end of the second shift register of the Nth stage is connected to the signal output end of the second shift register of the N-1th stage; the signal output end of the second shift register of the Nth stage is connected to the N+th For the signal input terminal of the second shift register of level 1, where N is an integer greater than one.
  • Only one of the signal supply circuit and the redundant signal supply circuit of each signal supply module is electrically connected to at least one of the plurality of pixel units through at least one of the plurality of signal lines.
  • each pixel unit includes a plurality of sub-pixels;
  • the signal line includes a data line group, and each data line group includes a plurality of data lines;
  • the pixel units located in the same column are connected to the same data line group,
  • the sub-pixels in the same column are connected to the same data line, and the sub-pixels in different columns are connected to different data lines;
  • the signal supply module and the data line group are arranged in a one-to-one correspondence;
  • the signal supply circuit includes: a first data selector; the redundant signal supply circuit includes: a second data selector;
  • Only one of the first data selector and the second data selector of each signal supply module is electrically connected to the pixel unit through the corresponding data line group.
  • the display substrate further includes: a data voltage lead-in line, a first electrostatic ring structure, and a second electrostatic ring structure;
  • the data voltage lead-in line is connected to the first data selector through the first electrostatic ring structure; a first protection resistor is connected between the data voltage lead-in line and the first electrostatic ring structure; A second protection resistor is connected between an electrostatic ring and the first data selector;
  • the data voltage lead-in line is connected to the second data selector through the second electrostatic ring structure; a third protection resistor is connected between the data voltage lead-in line and the second electrostatic ring structure; A fourth protection resistor is connected between the second electrostatic ring and the second data selector.
  • first electrostatic ring structure and the second electrostatic ring structure both include a first electrostatic transistor, a second electrostatic transistor, a third electrostatic transistor, and a fourth electrostatic transistor;
  • the first electrode of the first electrostatic transistor is connected to its control electrode and the data voltage lead-in line
  • the second electrode is connected to the first electrode and the control electrode of the second electrostatic transistor
  • the second electrode of the second electrostatic transistor is connected to the working level Signal end
  • the first electrode of the third static transistor is connected to the control electrode and the data voltage lead-in line
  • the second electrode is connected to the first electrode and the control electrode of the fourth electrostatic transistor
  • the second electrode of the fourth electrostatic transistor is connected to the non-operating level signal terminal.
  • the first data selector and the second data selector are located on the side of the signal input end of the data line of the substrate.
  • the signal line includes a gate line; the pixel units located in the same row are connected to the same gate line; the signal supply circuit of each of the signal supply modules includes: a first shift register, and the redundant signal supply The circuit includes: a second shift register; the first shift register and the second shift register are arranged in pairs and correspond to the same gate line;
  • the gate line is connected to only one of a pair of the first shift register and the second shift register in at least one of the signal supply modules.
  • the gate line is connected to two of the signal supply modules, and the two signal supply modules are respectively connected to two opposite ends of the gate line.
  • a plurality of the first shift registers in the signal supply module are connected in cascade, and the second shift registers are connected in cascade; each stage of the first shift register corresponds to a different gate line; The second shift registers of each stage correspond to different gate lines respectively;
  • the signal input end of the first shift register of the Nth stage is connected to the signal output end of the first shift register of the N-1th stage; the signal output end of the first shift register of the Nth stage is connected to the N+th A signal input terminal of the first shift register of level 1;
  • the signal input end of the second shift register of the Nth stage is connected to the signal output end of the second shift register of the N-1th stage; the signal output end of the second shift register of the Nth stage is connected to the N+th The signal input terminal of the second shift register of level 1.
  • the pixel unit includes a light-emitting device; the light-emitting device includes: a miniature inorganic light-emitting diode.
  • an embodiment of the present invention provides a display panel including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of a conventional display substrate.
  • Fig. 2 is a circuit diagram of a pixel in a sub-pixel.
  • Fig. 3 is a circuit diagram of the first shift register.
  • Fig. 4 is a circuit diagram of the first data selector.
  • FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of the position of the first electrostatic ring structure.
  • FIG. 7 is a schematic diagram of the position of the second electrostatic ring structure.
  • FIG. 8 is a schematic diagram of the structure of the first electrostatic ring structure.
  • FIG. 9 is a schematic diagram of another display substrate in an embodiment of the present invention.
  • each pixel unit may be arranged in an array; wherein, each pixel unit may include three different color sub-pixels; for example, it includes a red sub-pixel R and a green sub-pixel. G.
  • Blue sub-pixel B it needs to be explained here that the color of the sub-pixel in the embodiment of the present invention may be determined according to the color of the light-emitting device in each sub-pixel; for example, the light-emitting device in the sub-pixel emits If the light of each light-emitting device is red light, then the sub-pixel is called the red sub-pixel R; of course, if the light-emitting color of each light-emitting device in the display substrate is the same, for example, the light emitted by each light-emitting device is white light.
  • Time it depends on the color of the color film in the color film substrate disposed opposite to the display substrate in the display panel to which the display substrate is applied; for example: the color of the color film on the color film substrate corresponding to a certain sub-pixel is red , The sub-pixel is called the red sub-pixel R.
  • the display substrate includes multiple columns of data lines Data, multiple rows of gate lines Gate, the gate lines Gate and the data lines Data are intersected and arranged at the intersections.
  • the positions define sub-pixels; among them, the sub-pixels in the same column have the same color, and each three adjacent sub-pixels in the row direction constitute a pixel unit, and the three sub-pixels in each pixel unit are red sub-pixels R, Green sub-pixel G, blue sub-pixel B; each sub-pixel in the same row is connected to the same gate line Gate, and each sub-pixel in the same column is connected to the same data line (wherein, the red sub-pixel R in the same column is connected
  • the data line is Data11, the data line Data12 connected to the green sub-pixel G in the same column, and the data line Data13 connected to the blue sub-pixel B in the same column; the gate scan signal of any row of the gate line Gate consists of one level
  • the first shift register for example
  • each gate line Gate is connected to two first shift registers.
  • the two first shift registers connected to each gate line Gate can be respectively connected to both ends of the gate line Gate (for example, the left and right ends of the first row of gate lines Gate are respectively connected to a GOA1-1);
  • the first shift register can also be connected to the middle position of the gate line Gate, or any other position.
  • the entire signal line of the received signal can be The voltage has good uniformity, and can reduce the voltage difference between the signal received at the end close to the shift register and the signal received at the end far away from the shift register due to the line resistance of the signal line itself.
  • Each column of pixel units is connected to a data line group DATA, each data line group DATA includes three data lines (Data11, Data12, Data12), and each data line group DATA is connected to a first data selector, and each data line group DATA is connected to a first data selector.
  • the data line group DATA is connected to different first data selectors (that is, MUX1-1 to MUX1-4 shown in FIG. 1, wherein the three data lines connected to the three columns of sub-pixels in the first column of pixel units are connected to MUX1- 1.
  • the three data lines connected to the three columns of sub-pixels in the second column of pixel units are connected to MUX1-2).
  • the first data selector can be used to provide data voltage signals for the data lines Data connected thereto.
  • the first shift registers are connected together in a cascade manner; specifically, in addition to the first shift registers of the first stage and the last stage, the signal output terminal Output of the first shift register of the Nth stage is connected to the first shift register of the Nth stage.
  • the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and the drain. .
  • one of the electrodes is called the first electrode, the other is called the second electrode, and the gate is called the control electrode.
  • transistors can be divided into N-type and P-type according to the characteristics of transistors. When P-type transistors are used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and the gate is input low.
  • the source and drain are turned on; when using N-type transistors, the first pole is the source of the N-type transistor and the second pole is the drain of the N-type transistor. When the gate is input high, the source and drain are turned on.
  • the following pixel circuits and transistors in the first data selector are all described using N-type transistors as examples. It is conceivable that the implementation of P-type transistors can be implemented by those skilled in the art without creative work. It is thought that, therefore, it is also within the protection scope of the embodiment of the present invention; the transistors in the first pole register described below are all described by using P-type transistors as examples. It is conceivable that the implementation of N-type transistors is in the art. A technician can think of it without creative work, and therefore it is also within the protection scope of the embodiment of the present invention.
  • the working level signal terminal is the high-level signal terminal VGH; the non-working level signal terminal is the low-level signal terminal VGL; when each transistor uses the P-type transistor, the work The level signal terminal is the low level signal terminal VGL; the non-working level signal terminal is the high level signal terminal VGH.
  • Each sub-pixel includes at least a pixel circuit; as shown in FIG. 2, an exemplary pixel circuit is given, which includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a second transistor.
  • the light emitting device D may be a current type light emitting diode, and further, may be a current type inorganic light emitting diode, such as a micro light emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light emitting diode (Mini Light Emitting Diode, Mini LED), Of course, the light emitting device D in the embodiment of the invention may also be an organic light emitting diode (OLED). One of the first electrode and the second electrode of the light emitting device D is an anode, and the other is a cathode.
  • the channel width of the third transistor is wider than when the light-emitting device adopts an electromechanical light-emitting diode, so as to meet the driving requirement for the miniature inorganic light-emitting diode.
  • an exemplary first shift register which includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, The thirteenth transistor T13, the fourteenth transistor T14, the second storage capacitor C2, and the third storage capacitor C3; wherein the first pole of the eighth transistor T8 is connected to the signal input terminal Input, and the second terminal of the eighth transistor T8 is connected to N1 Node, the control electrode of the eighth transistor T8 is connected to the first clock signal terminal; the first electrode of the ninth transistor T9 is connected to the first clock signal terminal CLK, the second electrode of the ninth transistor T9 is connected to node N2, and the control of the ninth transistor T9 The first electrode of the tenth transistor T10 is connected to the low-level signal terminal VGL, the second electrode of the tenth transistor T10 is connected to the N2 node, and the control electrode of the tenth transistor T10 is connected to the first clock signal terminal CLK; The first electrode of the tenth transistor T
  • the two poles are connected to the first pole of the fourteenth transistor T14, the control pole of the thirteenth transistor T13 is connected to the N2 node; the second pole of the fourteenth transistor T14 is connected to the N1 node, and the control pole of the fourteenth transistor T14 is connected to the second clock Signal terminal; the first pole of the fifteenth transistor T15 is connected to the N1 node, the second pole of the fifteenth transistor T15 is connected to the first end of the second storage capacitor C2, and the control pole of the fifteenth transistor T15 is connected to the low-level terminal VGL.
  • an exemplary first data selector is provided, which is applicable to a display substrate in which one pixel unit includes three sub-pixels of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; this The red sub-pixel in the pixel unit is connected to the data line Data11, the green sub-pixel is connected to the data line Data12, and the blue sub-pixel is connected to the data line Data13; in the corresponding embodiment of the present invention, the first data selector includes: a sixteenth transistor T16, The seventeenth transistor T17 and the eighteenth transistor T18; among them, the first pole of the sixteenth transistor T16, the first pole of the seventeenth transistor T17, and the first pole of the eighteenth transistor T18 are connected together and pass data
  • the voltage lead-in line Data' is connected to the source driver (not shown); the second electrode of the sixteenth transistor T16 is connected to the data line Data11, and the control electrode of the sixteenth transistor T16 is connected to the timing controller (not shown)
  • one of the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 is controlled to be turned on by the timing signal output by the timing controller (not shown in the figure).
  • the timing controller controls the sixteenth transistor
  • the data voltage provided by the source driver is provided to the sixteenth transistor through the data voltage lead-in lines ( Figure 1 shows 4 data lead-in lines, Data1', Data2', Data3', Data4')
  • the timing controller controls the eighteenth transistor T18 to turn on the data voltage provided by the source driver is provided to the data line Data13 connected to the eighteenth transistor T18 through the data voltage lead-in line Data'.
  • the structure of the display substrate with micro-inorganic light-emitting diodes is more complicated. Therefore, the process is compared with that of traditional liquid crystal display substrates and organic electroluminescent diode display substrates.
  • the manufacturing process is complicated, which will lead to the accumulation of electrostatic charges during the manufacturing process, resulting in breakdown of the channel of the transistor in the display substrate. Especially, after the transistor in the pixel circuit is destroyed, it will cause the display of the display panel to appear dots. Bad, bad thread or bad surface.
  • the structure of the signal supply circuit and the redundant signal supply circuit may be the same, or may have different circuit structures that achieve the same function.
  • the redundant signal supply circuit can provide the same signal to the pixel unit in the display substrate, and the signal supply circuit and the redundant signal supply circuit adopt the same structure, which is convenient for the display substrate. preparation.
  • the structure of the signal supply circuit and the redundant signal supply circuit may also be different. In this case, the redundant signal supply circuit and the function of the signal supply circuit are exactly the same.
  • the signal supply circuit and the redundant signal supply circuit adopt the same structure for description.
  • an embodiment of the present invention provides a display substrate, which includes a substrate, a pixel unit, a signal line, and a signal supply module disposed on the substrate; in particular, in the embodiment of the present invention, each signal supply module S includes a signal supply circuit and a redundant signal supply circuit; the signal supply circuit and redundant signal supply circuit of each signal supply module S pass through at least one of the plurality of signal lines and at least one of the plurality of pixel units Electric connection. That is, each signal supply module S is used to provide a signal for the pixel unit connected to the signal line connected to it.
  • the signal supply module S of the display substrate in the embodiment of the present invention is provided with a redundant signal supply circuit, in the manufacturing process of the display panel, even if electrostatic charge accumulation occurs, the signal supply circuit and the corresponding redundant signal supply When one of the circuits is damaged, the other can provide corresponding signals to the signal lines in the display substrate to ensure the normal operation of the display substrate.
  • each signal supply module S can also be provided with one signal supply circuit and multiple redundant signal supply circuits.
  • the signal supply circuit and the redundant signal supply circuit in the signal supply module S are arranged in pairs, that is, it includes a signal supply circuit and a redundant signal supply circuit as an example for description.
  • the circuit structure in each signal supply module S that is faulty needs to be electrically disconnected from other electrical structures in the display substrate through a laser cutting process; specific ones may appear
  • the connection between the output terminal of the faulty circuit structure and the signal line is cut off to avoid the faulty circuit structure from outputting an error signal to the signal line.
  • any one of the signal supply circuit and the redundant signal supply circuit in the signal supply module S will be connected to the display substrate.
  • the other electrical structure of the device is disconnected from the electrical connection to reduce the load on the display substrate.
  • the signal line may be a gate line Gate
  • the signal supply circuit in the signal supply module S may be a first shift register
  • the redundant signal supply circuit can include a second shift register with the same structure as the first shift register.
  • Figure 5 shows six second shift registers, namely GOA2-1 ⁇ GOA2-6 ).
  • the first shift register and the second shift register in each signal supply module S are connected to the same gate line Gate, and are used to provide a gate scan signal for the pixel unit connected to the gate line Gate.
  • the structures of the first shift register and the second shift register are the same as the structure of the above-mentioned first shift register, so the description is not repeated here. It should be understood that the signal input terminal Input, the first clock signal terminal CLK, the second clock signal terminal CLKB, the high-level signal terminal VGH, and the low-level signal terminal VGL connected to the second shift register are respectively connected to The signal input terminal Input, the first clock signal terminal CLK, the second clock signal terminal CLKB, the high-level signal terminal VGH, and the low-level signal terminal VGL of the corresponding first shift register are shared.
  • the display substrate is a double-sided drive type display substrate, that is, a row of pixel units is driven by two first shift registers, and correspondingly, a row of pixel units corresponds to two second shift registers.
  • the row of pixel units is connected to a gate line Gate, and the signal output ends of the two first shift registers are respectively connected to both ends of the gate line Gate.
  • the signal output terminals are also respectively connected to the two ends of the gate line Gate, that is, the first register and the second register are set in one-to-one correspondence.
  • the gate line Gate can be provided with a gate scan signal through the other one.
  • the two first shift registers may also be located in the middle area of the display substrate.
  • the first shift register unit is located between two columns of pixel units, and drives the two first shift registers of the gate lines in the same row.
  • a shift register is located between the pixel units in different columns.
  • the position of the first shift register is not limited in any way.
  • each first bit register connected to the left of the gate line Gate is connected in cascade; each second shift register is connected in cascade connection; similarly connected to each first bit on the right side of the gate line Gate
  • the registers are connected in cascade; each second shift register is connected in cascade; the connection mode of each first-bit register connected to the left side of the Gate and the connection mode of each second shift register are taken as an example for description.
  • the signal output terminal of GOA1-1 is connected to the signal input terminal of GOA1-2; the signal output terminal of GOA1-2 is connected to the signal input terminal of GOA1-3; the signal output terminal of GOA1-3 is connected to the signal input terminal of GOA1-4;
  • the signal output terminal of GOA1-4 is connected to the signal input terminal of GOA1-5; the signal output terminal of GOA1-5 is connected to the signal input terminal of GOA1-6; in the same way, the signal output terminal of GOA2-1 is connected to the signal input terminal of GOA2-2 ;
  • the signal output terminal of GOA2-2 is connected to the signal input terminal of GOA2-3; the signal output terminal of GOA2-3 is connected to the signal input terminal of GOA2-4; the signal output terminal of GOA2-4 is connected to the signal input terminal of GOA2-5;
  • GOA1 The signal output terminal of -5 is connected to the signal input terminal of GOA2-6.
  • the signal line may be a data line group DATA, and each data line group DATA includes multiple data lines (for example: each data line DATA shown in FIG. 5 includes three data lines Data11, Data12, Data13), and correspondingly connect a column of pixel units.
  • the signal supply circuit in each signal supply module S can be the first data selector ( Figure 5 shows four first data selectors MUX1-1 to MUX1-4), and the redundant signal supply circuit can be the first data selector.
  • the second data selector with the same structure ( Figure 5 shows four second data selectors MUX2-1 to MUX2-4), where the first data selector and the second data selector are arranged in pairs, that is, one
  • the signal supply module S includes a first data selector and a second data selector. At this time, each signal supply module S is used to provide data voltage signals for the same column of pixel units.
  • the data line connected to the red sub-pixels located in the same column is called the data line Data11.
  • the data line connected to the green sub-pixels located in the same column is called the data line Data12
  • the data line connected to the blue sub-pixels located in the same column is called the data line Data13.
  • the connection relationship between the data line Data 11, the data line Data 12, the data line Data 13 and the first data selector and the second data selector respectively connected to the three columns of sub-line pixels located in the pixel unit of the first column will be described in detail.
  • each column of pixel units includes three columns of sub-pixels of three different colors, which are a column of red sub-pixels R, a column of green sub-pixels G, and a column of blue sub-pixels B.
  • Each data line group DATA It includes three data lines, namely Data11, Data12, and Data13; take the connection relationship between MUX1-1 and MUX2-1 and the data line group as an example; among them, the input terminals of MUX1-1 and MUX2-1 are connected to the data voltage lead-in line Data', the three output terminals of MUX1-1 and MUX2-1 are respectively connected to the data lines Data11, Data12, and Data13.
  • connection with the data lines Data11, Data12, and Data13 and the connection with the data voltage lead-in line Data' provide data voltage signals for the three data lines Data11, Data12, and Data13 corresponding to the column pixel unit through the other.
  • both the first data selector and the second data selector may include the aforementioned sixteenth transistor T16, seventeenth transistor T17, and eighteenth transistor T18, and each transistor in the second data selector
  • the connection relationship with the source driver, the timing controller, the data line Data11, the data line Data12, and the data line Data13 is the same as the connection relationship between the transistors in the first data selector.
  • the connection relationship has been described in the above content, and will not be repeated here.
  • the first data selector and the second data selector are both arranged on the side of the signal input end of the data line Data of the substrate.
  • the display substrate not only includes the above-mentioned structure, but also includes a first electrostatic ring structure connected between the data voltage lead-in line Data' and the first data selector, and connected to The second electrostatic ring structure between the data voltage lead-in line Data' and the second data selector; wherein the first electrostatic ring structure and the second electrostatic ring structure may be antistatic structures with the same structure to prevent the display substrate from being prepared
  • the static electricity generated in the process causes the channel of the transistor in the display substrate to be broken down by static electricity.
  • the structure of the first electrostatic ring and the data voltage lead-in line ( Figure 5 shows four data signal lead-in lines, namely Data1', Data2', Data3', and Data4).
  • ') is connected with a first protection resistor; between the first static ring structure and the first data selector is connected with a second protection resistor; between the second static ring structure and the data voltage lead-in line is connected with a third protection Resistance; a fourth protection resistor is connected between the second electrostatic ring structure and the second data selector.
  • the reason why the first protection resistor, the second protection resistor, the third protection resistor, and the fourth protection resistor are provided is to protect the transistors in the pixel unit in the display substrate to a certain extent, and at the same time, it can make the first electrostatic ring structure
  • the structure of the second static ring and the static ring will not be easily broken down by static electricity, and play the role of static electricity protection for many times.
  • the resistance values of the first protection resistor, the second protection resistor, the third protection resistor, and the fourth protection resistor all include but are not limited to 400 ⁇ -500 ⁇ .
  • first electrostatic ring structure (second electrostatic ring structure) which includes four transistors: the first electrostatic transistor T19, the second electrostatic transistor T20, and the third electrostatic transistor.
  • the first electrode of the first electrostatic transistor T19 is connected to its control electrode and the data voltage lead-in line Data'
  • the second electrode of the first electrostatic transistor T19 is connected to the first electrode and the control electrode of the second electrostatic transistor T20
  • the second electrostatic transistor The second electrode of T20 is connected to the high-level signal terminal VGH
  • the second electrode of the third electrostatic transistor T21 is connected to the control electrode and the data voltage lead-in line Data1'
  • the second electrode of the third electrostatic transistor T21 is connected to the fourth electrostatic transistor T22.
  • the second electrode and the control electrode, and the second electrode of the fourth electrostatic transistor T22 is connected to the low working level signal terminal VGL.
  • the first electrostatic transistor T19 and the second electrostatic transistor T20 are turned on, passing the high level of the branch where the first electrostatic transistor T19 and the second electrostatic transistor T20 are located.
  • the signal terminal VGH leads the static electricity. It should be understood that at this time, the voltage value of the positive high voltage should generally be greater than the voltage value connected to the high-level voltage terminal VGH connected to the second electrode of the second electrostatic transistor T20.
  • the third electrostatic transistor T21 and the fourth electrostatic transistor T22 are turned on, passing the low-level signal of the branch where the third electrostatic transistor T21 and the fourth transistor T22 are located
  • the terminal VGL leads the static electricity.
  • the working principle of the second electrostatic ring structure is the same as the working principle of the first electrostatic ring structure, so it will not be repeated here.
  • an embodiment of the present invention provides a display substrate.
  • the display substrate is formed by laser cutting the faulty structure in each signal supply module S after failure detection of the above-mentioned display substrate.
  • the process disconnects the structure from other structures in the display substrate (that is, the "X" in Figure 9 indicates the cut-off position); if which signal is supplied to the signal supply circuit and redundant signal supply in the module S If none of the circuits fails, then any one of the signal supply circuit and the redundant signal supply circuit in the group of signal supply modules S is electrically disconnected from other structures in the display substrate to reduce the load on the display substrate.
  • the display substrate in the embodiment of the present invention includes a substrate; a plurality of pixel units arranged in an array, a plurality of signal lines, and a signal supply module S are arranged on the substrate; wherein, the signal supply module S includes: A supply circuit and a redundant signal supply circuit; only one of the signal supply circuit and the redundant signal supply circuit of each of the signal supply modules S passes through at least one of the plurality of signal lines and the plurality of pixel units At least one electrical connection.
  • the display substrate in the embodiment of the present invention is made of the above-mentioned display substrate, after fault detection, the circuit structure of each signal supply module S that has a fault is combined with other electrical structures in the display substrate through a laser cutting process. Disconnect the electrical connection; specifically, the connection between the output end of the faulty circuit structure and the signal line can be cut off to avoid the faulty circuit structure from outputting an error signal to the signal line.
  • the signal supply circuit nor the redundant signal supply circuit in the signal supply module S fails, then any one of the signal supply circuit and the redundant signal supply circuit in the signal supply module S will be connected to the display substrate.
  • the other electrical structures are disconnected from the electrical connection to obtain the display substrate in this embodiment. Therefore, the yield rate of the display substrate in the embodiment of the present invention is higher.
  • the signal supply circuit in the signal supply module S in the embodiment of the present invention may be the above-mentioned first shift register, and in this case, the redundant signal supply circuit is the above-mentioned second shift register; of course, in the embodiment of the present invention
  • the signal supply circuit in the signal supply module S may also be the above-mentioned first data selector, and in this case, the redundant signal supply circuit may be the above-mentioned second data selector.
  • the first shift register, the second shift register, the first data selector, and the second data selector can all adopt the same structure as described above, so the details will not be repeated here.
  • the other structures of the display substrate of the embodiment of the present invention may also be the same as the structure of the above-mentioned display substrate, so the details will not be repeated.
  • an embodiment of the present invention also provides a display panel, which includes the above-mentioned display substrate.
  • the display device can be a liquid crystal display device or an electroluminescent display device, such as a liquid crystal panel, an OLED panel, a MicroLED panel, a MiniLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Products or parts that display features.

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Abstract

本发明提供一种显示基板及显示装置，属于显示技术领域。本发明的显示基板，其包括：基底；多个阵列排布的像素单元、多条信号线和信号供给模块，设置在基底上；其中，所述信号供给模块包括：信号供给电路和冗余信号供给电路；每个所述信号供给模块通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。

Description

显示基板及显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
微型无机发光二极管是新一代显示技术，比现有的OLED技术亮度更高、发光效率更好、功耗更低。但由于微型无机发光二极管显示基板的制备工序复杂，同时由于微型无机发光二极管是采用转印的方式形成显示基板上的，因此在微型无机发光二极管显示基板的制备工艺中出现较大的静电释放(ESD)，故如何降低ESD是亟需要解决的技术问题。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示装置。
第一方面，本发明实施例提供一种显示基板，其包括：
基底；
多个阵列排布的像素单元、多条信号线和信号供给模块，设置在基底上；其中，
所述信号供给模块包括：信号供给电路和冗余信号供给电路；
每个所述信号供给模块通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
其中，每个所述信号供给模块的信号供给电路和冗余信号供给电路通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
其中，每个所述像素单元包括多个子像素；所述信号线包括数据线组，且每组数据线组包括多条数据线；位于同一列的所述像素单元连接同一所述 数据线组，且位于同一列的所述子像素连接同一所述数据线，不同列的所述子像素连接不同所述数据线；
所述信号供给模块与所述数据线组一一对应设置；
所述信号供给电路包括：第一数据选择器；所述冗余信号供给电路包括：第二数据选择器；
每个所述信号供给模块的所述第一数据选择器和所述第二数据选择器通过与之对应的所述数据线组与所述像素单元电连接。
其中，所述显示基板还包括：数据电压引入线、第一静电环结构和第二静电环结构；
所述数据电压引入线通过所述第一静电环结构与所述第一数据选择器连接；在所述数据电压引入线和第一静电环结构之间连接有第一保护电阻；在所述第一静电环和所述第一数据选择器之间连接有第二保护电阻；
所述数据电压引入线通过所述第二静电环结构与所述第二数据选择器连接；在所述数据电压引入线和第二静电环结构之间连接有第三保护电阻；在所述第二静电环和所述第二数据选择器之间连接有第四保护电阻。
其中，所述第一静电环结构和第二静电环结构均包括第一静电晶体管、第二静电晶体管、第三静电晶体管、第四静电晶体管；
所述第一静电晶体管的第一极连接其控制极和所述数据电压引入线，第二极连接第二静电晶体管的第一极和控制极，第二静晶体管的第二极连接工作电平信号端；
第三静晶体管的第一极连接器控制极和数据电压引入线，第二极连接第四静电晶体管的第一极和控制极，第四静电晶体管的第二极连接非工作电平信号端。
其中，所述第一保护电阻、所述第二保护电阻、所述第三保护电阻、所述第四电阻的阻值均在400Ω-500Ω之间。
其中，所述像素单元包括三个子像素；所述数据线组包括三条数据线。
其中，所述第一数据选择器和所述第二数据选择器位于所述基底的所述数据线的信号输入端所在侧。
其中，所述信号线包括栅线；位于同一行的所述像素单元连接同一栅线；每个所述信号供给模块的所述信号供给电路包括：第一移位寄存器，所述冗余信号供给电路包括：第二移位寄存器；所述第一移位寄存器和所述第二移位寄存器成对设置且连接至同一栅线；
所述栅线连接至少一个所述信号供给模块中的一对所述第一移位寄存器和所述第二移位寄存器。
其中，所述栅线与两个所述信号供给模块连接，且两个所述信号供给模块分别与所述栅线的两个相对端连接。
其中，所述信号供给模块中的多个所述第一移位寄存器级联连接，多个所述第二移位寄存器级联连接；每级所述第一移位寄存器分别与不同的栅线连接；每级所述第二移位寄存器分别与不同的栅线连接；
第N级第一移位寄存器的信号输入端连接第N-1级所述第一移位寄存器的信号输出端；第N级所述第一移位寄存器的信号输出端连接第N-1级所述第一移位寄存器的信号输入端；
第N级所述第二移位寄存器的信号输入端连接第N-1级所述第二移位寄存器的信号输出端；第N级所述第二移位寄存器的信号输出端连接第N+1级所述第二移位寄存器的信号输入端，其中N为大于1的整数。
其中，
每个所述信号供给模块的信号供给电路和冗余信号供给电路中仅一者通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
其中，每个所述像素单元包括多个子像素；所述信号线包括数据线组，且每组数据线组包括多条数据线；位于同一列的所述像素单元连接同一所述数据线组，且位于同一列的所述子像素连接同一所述数据线，不同列的所述 子像素连接不同所述数据线；
所述信号供给模块与所述数据线组一一对应设置；
所述信号供给电路包括：第一数据选择器；所述冗余信号供给电路包括：第二数据选择器；
每个所述信号供给模块的所述第一数据选择器和所述第二数据选择器中仅一者通过与之对应的所述数据线组与所述像素单元电连接。
其中，所述显示基板还包括：数据电压引入线、第一静电环结构和第二静电环结构；
所述数据电压引入线通过所述第一静电环结构与所述第一数据选择器连接；在所述数据电压引入线和第一静电环结构之间连接有第一保护电阻；在所述第一静电环和所述第一数据选择器之间连接有第二保护电阻；
所述数据电压引入线通过所述第二静电环结构与所述第二数据选择器连接；在所述数据电压引入线和第二静电环结构之间连接有第三保护电阻；在所述第二静电环和所述第二数据选择器之间连接有第四保护电阻。
其中，所述第一静电环结构和第二静电环结构均包括第一静电晶体管、第二静电晶体管、第三静电晶体管、第四静电晶体管；
所述第一静电晶体管的第一极连接其控制极和所述数据电压引入线，第二极连接第二静电晶体管的第一极和控制极，第二静晶体管的第二极连接工作电平信号端；
第三静晶体管的第一极连接器控制极和数据电压引入线，第二极连接第四静电晶体管的第一极和控制极，第四静电晶体管的第二极连接非工作电平信号端。
其中，所述第一数据选择器和所述第二数据选择器位于所述基底的所述数据线的信号输入端所在侧。
其中，所述信号线包括栅线；位于同一行的所述像素单元连接同一栅线；每个所述信号供给模块的所述信号供给电路包括：第一移位寄存器，所述冗 余信号供给电路包括：第二移位寄存器；所述第一移位寄存器和所述第二移位寄存器成对设置且与同一栅线对应；
所述栅线仅与至少一个所述信号供给模块中的一对所述第一移位寄存器和所述第二移位寄存器中的一者连接。
其中，所述栅线与两个所述信号供给模块连接，且两个所述信号供给模块分别与所述栅线的两个相对端连接。
其中，所述信号供给模块中的多个所述第一移位寄存器级联连接，所述第二移位寄存器级联连接；每级所述第一移位寄存器分别与不同的栅线对应；每级所述第二移位寄存器分别与不同的栅线对应；
第N级所述第一移位寄存器的信号输入端连接第N-1级所述第一移位寄存器的信号输出端；第N级所述第一移位寄存器的信号输出端连接第N+1级所述第一移位寄存器的信号输入端；
第N级所述第二移位寄存器的信号输入端连接第N-1级所述第二移位寄存器的信号输出端；第N级所述第二移位寄存器的信号输出端连接第N+1级所述第二移位寄存器的信号输入端。
其中，所述像素单元包括发光器件；所述发光器件包括：微型无机发光二极管。
第三方面，本发明实施例提供一种显示面板，其包括上述的显示基板。
附图说明
图1为现有的显示基板的示意图。
图2为子像素中像素电路图。
图3为第一移位寄存器的电路图。
图4为第一数据选择器的电路图。
图5为本发明实施例的显示基板的示意图。
图6为第一静电环结构的位置示意图。
图7为第二静电环结构的位置示意图。
图8为第一静电环结构的结构示意图。
图9为本发明实施例中的另一显示基板的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1所示，本发明实施例的显示基板中，各个像素单元可以呈阵列排布；其中，每个像素单元可以包括三种不同颜色的子像素；例如包括红色子像素R、绿色子像素G、蓝色子像素B；在此需要说明的，在本发明实施例中子像素的颜色可以是根据每个子像素中的发光器件的颜色而定的；例如：子像素中的发光器件所发出的光为红光，此时则将该子像素称之为红色子像素R；当然，若显示基板中的各个发光器件的发光颜色均相同，例如各个发光器件所发出的光均为白光，此时，则根据应用该显示基板的显示面板中，与该显示基板相对设置的彩膜基板中彩膜的颜色而定；例如：某一子像素所对应的彩膜基板上彩膜的颜色为红色，则将该子像素称之为红色子像素R。
其中，如图1所示，给出一种示例性的显示基板的具体结构；该显示基 板包括多列数据线Data、多行栅线Gate，栅线Gate和数据线Data交叉设置，并在交叉位置处限定出子像素；其中，位于同一列的子像素的颜色相同，沿行方向每相邻的三个子像素构成一个像素单元，每个像素单元中的三个子像素分别为红色子像素R、绿色子像素G、蓝色子像素B；位于同一行的各个子像素连接同一条栅线Gate，位于同一列的各个子像素连接同一条数据线(其中，位于同一列的红色子像素R所连接的数据线为Data11，位于同一列的绿色子像素G所连接的数据线Data12，位于同一列的蓝色子像素B所连接的数据线Data13)；任一行栅线Gate的栅扫描信号由一级第一移位寄存器(例如，图1中示意了6级第一移位寄存器，即GOA1-1～GOA1-6，GOA1-1为第一行栅线Gate提供栅扫描信号)所提供。
如图5所示，以双边驱动为例，也即，每一条栅线Gate连接两个第一移位寄存器。具体的，每条栅线Gate所连接的两个第一移位寄存器可以分别连接在该栅线Gate的两端(例如：第一行栅线Gate的左右两端分别连接一个GOA1-1)；当然，第一移位寄存器也可以连接在该条栅线Gate的中间位置，或者其它任何位置。在本发明实施例中，由于采用双边驱动，相比于单边驱动，即一条栅线Gate只与一个第一移位寄存器连接的实施例，能够使接收信号的整根信号线上各处的电压具有较好的均一性，而能够减缓由于信号线本身线阻而出现靠近移位寄存器一端接收到的信号和远离移位寄存器一端接收到的信号存在电压差的情况。每一列像素单元所对应连接一个数据线组DATA，每个数据线组DATA中包括三条数据线(Data11、Data12、Data12)，且每个数据线组DATA连接一个第一数据选择器，且不同的数据线组DATA连接不同的第一数据选择器(也即，图1中所示的MUX1-1～MUX1-4，其中第一列像素单元中的三列子像素所连接的三条数据线连接MUX1-1，第二列像素单元中的三列子像素所连接的三条数据线连接MUX1-2)，此时可以通过第一数据选择器为与其连接数据线Data提供数据电压信号。其中，对于各个第一移位寄存器采用级联的方式连接在一起；具体的，除第一级和最后一级第一移位寄存器以外，第N级第一移位寄存器信号输出端Output连接第N+1 级第一移位寄存器的信号输入端Input，其中N为大于1的整数；例如：图1中所示的第一级第一移位寄存器GOA1-1的信号输出端Output连接第二级第一移位寄存器GOA1-2的信号输入端Input。
以下分别对子像素、第一移位寄存器、第一数据选择器的结构进行说明。
本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，栅极输入低电平时，源漏极导通；当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通。其中，下述的像素电路和第一数据选择器中的晶体管均是以N型晶体管为例进行说明的，可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下想到的，因此也是在本发明实施例的保护范围内的；下述的第一极为寄存器中的晶体管均是以P型晶体管为例进行说明的，可以想到的是采用N型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下想到的，因此也是在本发明实施例的保护范围内的。
其中，当各个晶体管选用N型晶体管时，工作电平信号端则为高电平信号端VGH；非工作电平信号端则为低电平信号端VGL；当各个晶体管选用P型晶体管时，工作电平信号端则为低电平信号端VGL；非工作电平信号端则为高电平信号端VGH。
每个子像素中均至少包括像素电路；如图2所示，给出一种示例性的像素电路，其包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一存储电容C1，以及发光器件D；其中，第一晶体管T1的第一极连接初始电压信号端Vint，第一晶体管T1的第二极连接第一存储电容C1的第二端、第二晶体管 T2的第一极和第三晶体管T3的控制极，第一晶体管T1的控制极连接复位信号端Reset；第二晶体管T2的第二极连接第三晶体管T3的第二极和第六晶体管T6的第一极，第二晶体管T2的控制极连接栅线Gate；第三晶体管T3的第一极连接第一电源电压端VDD；第四晶体管T4的第一极连接数据线Data，第四晶体管T4的第二极连接第五晶体管T5的第二极、第七晶体管T7的第二极和第一存储电容C1的第一极；第四晶体管T4的控制极连接栅线；第五晶体管T5的第一极连接基准电压信号端Vref，第五晶体管T5的控制极连接发光控制线EM；第六晶体管T6的第二极连接发光器件D的第一极，第六晶体管T6的控制极连接发光控制线EM；第七晶体管T7的第一极连接基准电压信号端Vref，第七晶体管T7的控制极连接复位信号端Reset，发光器件的第二极连接第二电源电压端VSS。
其中，发光器件D可以是电流型发光二极管，进一步地，可以为电流型无机发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)，当然，在发明实施例中的发光器件D还可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。发光器件D的第一极和第二极中的一者为阳极，另一者为阴极。
在此需要说明的是，发光器件D采用微型无机发光二极管时，第三晶体管的沟道宽长比较发光器件采用机电致发光二极管时要宽一些，以满足对微型无机发光二极管的驱动要求。
如图3所述，给出了一种示例性的第一移位寄存器，其包括：第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第二存储电容C2和第三存储电容C3；其中，第八晶体管T8的第一极连接信号输入端Input，第八晶体管T8的第二端连接N1节点，第八晶体管T8的控制极连接第一时钟信号端；第九晶体管T9的第一极连接第一时钟信号端CLK，第九晶体管T9的第二极连接N2节点，第九晶体管T9的控制极连接N1节点；第十晶体管T10的 第一极连接低电平信号端VGL，第十晶体管T10的第二极连接N2节点，第十晶体管T10的控制极连接第一时钟信号端CLK；第十一晶体管T11的第一极连接高电平信号端VGH和第三存储电容C3的第二端，第十一晶体管T11的第二极连接信号输出端Output，第十一晶体管T11的控制极连接N2节点；第三存储电容C3的第一端连接N2节点；第十二晶体管T12的第一极连接第二时钟信号端CLKB，第十二晶体管T12的第二极连接第二存储电容C2的第二端和信号输出端Output，第十二晶体管T12的控制极连接第二存储电容C2的第一端；第十三晶体管T13的第一极连接高电平信号端VGH，第十三晶体管T13的第二极连接第十四晶体管T14的第一极，第十三晶体管T13的控制极连接N2节点；第十四晶体管T14的第二极连接N1节点，第十四晶体管T14的控制极连接第二时钟信号端；第十五晶体管T15的第一极连接N1节点，第十五晶体管T15的第二极连接第二存储电容C2的第一端，第十五晶体管T15的控制极连接低电平端VGL。
如图4所示，给出了一种示例性的第一数据选择器，其适用于一个像素单元包括红色子像素R、绿色子像素G、蓝色子像素B三个子像素的显示基板；该像素单元中的红色子像素连接数据线Data11、绿色子像素连接数据线Data12、蓝色子像素连接数据线Data13；相应的本发明实施例中，第一数据选择器包括：第十六晶体管T16、第十七晶体管T17、第十八晶体管T18；其中，第十六晶体管T16的第一极、第十七晶体管T17的第一极、第十八晶体管T18的第一极连接在一起，且通过数据电压引入线Data'与源极驱动器(图中未示)连接；第十六晶体管T16的第二极连接数据线Data11，第十六晶体管T16的控制极连接时序控制器(图中未示)的第一输出端；第十七晶体管T17的第二极连接数据线Data12，第十七晶体管T17的控制极连接时序控制器的第二输出端；第十八晶体管T18的第二极连接数据线Data13，第十八晶体管T18的控制极连接时序控制器的第三输出端。
具体的，通过时序控制器(图中未示)输出的时序信号控制第十六晶体管T16、第十七晶体管T17、第十八晶体管T18中的一者被打开，当时序控 制器控制第十六晶体管T16打开时，源极驱动器所提供的数据电压则通过数据电压引入线(图1中示意了4条数据引入线，Data1'、Data2'、Data3'、Data4')提供给与第十六晶体管T16连接的数据线Data11；同理，当时序控制器控制第十七晶体管T17打开时，源极驱动器所提供的数据电压则通过数据电压引入线Data'提供给与第十七晶体管T17连接的数据线Data12；当时序控制器控制第十八晶体管T18打开时，源极驱动器所提供的数据电压则通过数据电压引入线Data'提供给与第十八晶体管T18连接的数据线Data13。
根据上述显示基板的各部分结构的介绍，可以看出的具有微型无机发光二极管的显示基板的结构较为复杂，因此在制备时，工艺相较传统的液晶显示基板、有机电致发光二极管显示基板的制备工艺复杂，从而将会导致在制备过程中出现静电电荷的积累，导致显示基板中晶体管的沟道被击穿，特别是，像素电路中的晶体管被破坏后，会导致显示面板的显示出现点不良、线不良或面不良。
在此还需要说明的是，本发明实施例所提供的显示基板中，信号供给电路和冗余信号供给电路的结构可以相同，也可以为实现相同功能的不同电路结构。这样一来，可以在信号供给电路在出现故障时，通过冗余信号供给电路为显示基板中像素单元提供相同的信号，且信号供给电路和冗余信号供给电路采用相同的结构，便于显示基板的制备。当然，信号供给电路和冗余信号供给电路的结构也可以是不一样的，此时则需要冗余信号供给电路和与信号供给电路的功能完全一样。为了方便理解，在下述实施例中以信号供给电路和冗余信号供给电路采用相同的结构进行说明。
第一方面，本发明实施例提供一种显示基板，其包括基底，设置在基底上的像素单元、信号线、信号供给模块；其中，特别的是，在本发明实施例中每个信号供给模块S包括信号供给电路和冗余信号供给电路；每个信号供给模块S的信号供给电路和冗余信号供给电路通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。也即，每个信号供给模块S用以为与之连接的信号线所连接像素单元提供信号。
由于在本发明实施例中显示基板的信号供给模块S中设置有冗余信号供给电路，因此，在显示面板的制备过程中，即使出现静电电荷积累造成信号供给电路和与之对应冗余信号供给电路中的一者时损坏，均可以通过另一者为显示基板中的信号线提供相应的信号，以保证显示基板的正常工作。
在此需要说明的是，每个信号供给模块S中的信号供给电路和和冗余信号供给电路均为一个，当然，每个信号供给模块S也可以对应设置一个信号供给电路和多个冗余信号供给电路，在本发明实施例中以信号供给模块S中的信号供给电路和冗余信号供给电路成对设置，也即包括一个信号供给电路和一个冗余信号供给电路为例进行说明。在采用上述显示基板形成显示面板之前，需要将每个信号供给模块S中出现故障的电路结构通过激光切割工艺将该电路结构与显示基板中的其它电学结构断开电连接；具体的可以将出现故障的电路结构的输出端与信号线之间的连线切断，以避免出现故障的电路结构将错误信号输出给信号线。当然，若信号供给模块S中的信号供给电路和冗余信号供给电路均没有出现故障，则将这组信号供给模块S中的信号供给电路和冗余信号供给电路的任一者与显示基板中的其它电学结构断开电连接，以减小显示基板的负载。
在一些实施例中，如图5所示，信号线可以为栅线Gate，信号供给模块S中的信号供给电路可以为第一移位寄存器(图5示意了6第一移位寄存器，即GOA1-1～GOA1-6)，冗余信号供给电路则可以包括与第一移位寄存器结构相同的第二移位寄存器图5示意了6个第二移位寄存器，即GOA2-1～GOA2-6)。其中，每个信号供给模块S中的第一移位寄存器和第二移位寄存器连接同一条栅线Gate，用于为与该栅线Gate连接的像素单元提供栅扫描信号。
其中，第一移位寄存器和第二移位寄存器的结构与上述第一移位寄存器的结构相同，故在此不再重复描述。其中，应当理解的是，对于第二移位寄存器所连接的信号输入端Input、第一时钟信号端CLK、第二时钟信号端CLKB、高电平信号端VGH、低电平信号端VGL分别和与之对应的第一移 位寄存器的信号输入端Input、第一时钟信号端CLK、第二时钟信号端CLKB、高电平信号端VGH、低电平信号端VGL共用。
在一些实施例中，显示基板为双边驱动型显示基板，也即，一行像素单元由两个第一移位寄存器进行驱动，相应的，一行像素单元对应两个第二移位寄存器。具体的，以一行像素单元为例，该行像素单元连接一条栅线Gate，两个第一移位寄存器的信号输出端分别连接在该栅线Gate的两端，两个第二移位寄存器的信号输出端同样分别连接在该栅线Gate的两端，也即，第一位寄存器与第二寄存器一一对应设置。这样一来，若位于栅线Gate一端的第一移位寄存器和第二移位寄存器中的一者损坏，则可以通过另一者为该栅线Gate提供栅扫描信号。当然，在本发明实施例中两个第一移位寄存器也可以位于显示基板的中间区域，例如：第一位移寄存器单元位于两列像素单元之间，且驱动同一行的栅线的两个第一移位寄存器位于不同列的像素单元之间。在本发明实施例中并不对第一移位寄存器的位置做任何限定。
具体的，如图5所示，连接在栅线Gate左侧的各个第一位寄存器级联连接；各个第二移位寄存器级联连接；同理连接在栅线Gate右侧的各个第一位寄存器级联连接；各个第二移位寄存器级联连接；以连接在Gate左侧的各个第一位寄存器的连接方式和各个第二移位寄存器的连接方式为例进行说明。其中，GOA1-1的信号输出端连接GOA1-2的信号输入端；GOA1-2的信号输出端连接GOA1-3的信号输入端；GOA1-3的信号输出端连接GOA1-4的信号输入端；GOA1-4的信号输出端连接GOA1-5的信号输入端；GOA1-5的信号输出端连接GOA1-6的信号输入端；同理，GOA2-1的信号输出端连接GOA2-2的信号输入端；GOA2-2的信号输出端连接GOA2-3的信号输入端；GOA2-3的信号输出端连接GOA2-4的信号输入端；GOA2-4的信号输出端连接GOA2-5的信号输入端；GOA1-5的信号输出端连接GOA2-6的信号输入端。
在一些实施例中，如图5所示，信号线可以为数据线组DATA，每个数据线组DATA包括多条数据线(例如：图5中所示的每个数据线DATA包括 三条数据线Data11、Data12、Data13)，且对应连接一列像素单元。每个信号供给模块S中信号供给电路可以为第一数据选择器(图5示意了4个第一数据选择器MUX1-1～MUX1-4)，冗余信号供给电路可以为与第一数据选择器结构相同的第二数据选择器(图5示意了4个第二数据选择器MUX2-1～MUX2-4)，其中，第一数据选择器和第二数据选择器成对设置，也即一个信号供给模块S中包括一个第一数据选择和一个第二数据选择器，此时每个信号供给模块S用于为同一列像素单元提供数据电压信号。
为了描述方便，以每一列像素单元包括红、绿、蓝三种不同颜色的三列子像素为例，将位于同一列的红色子像素所连接的数据线称之为数据线Data11，同理，将位于同一列的绿色子像素所连接的数据线称之为数据线Data12，将位于同一列的蓝色子像素所连接的数据线称之为数据线Data13。以下，对位于第一列像素单元中的三列子线像素分别连接的数据线Data 11、数据线Data12、数据线Data13和第一数据选择器、第二数据选择器的连接关系进行具体说明。
具体的，如图5所示，每一列像素单元包括三种不同颜色的三列子像素，分别为一列红色子像素R、一列绿色子像素G、一列蓝色子像素B，每组数据线组DATA则包括三条数据线，分别为Data11、Data12、Data13；以MUX1-1和MUX2-1与数据线组的连接关系为例；其中，MUX1-1和MUX2-1的输入端均连接数据电压引入线Data'，MUX1-1和MUX2-1的三个输出端分别连接数据线Data11、Data12、Data13，这样一来，当MUX1-1和MUX2-1中的一者损坏时，则可以切断损坏的一者与数据线Data11、Data12、Data13的连接，以及与数据电压引入线Data'的连接，通过另外一者为列像素单元对应的三条数据线Data11、Data12、Data13提供数据电压信号。
其中，在一些实施例中，第一数据选择器和第二数据选择器均可以包括上述第十六晶体管T16、第十七晶体管T17、第十八晶体管T18，且第二数据选择器中各个晶体管与源极驱动器、时序控制器、数据线Data11、数据线Data12、数据线Data13的连接关系，与第一数据选择器中个晶体管的连接关 系相同。关于连接关系在上述内容中已经描述，在此不再赘述。
在一些实施例中，第一数据选择器和第二数据选择器均设置在基底的数据线Data的信号输入端所在侧。
在一些实施例中，如图6和图7所示，显示基板不仅包括上述结构，还包括连接在数据电压引入线Data'和第一数据选择器之间的第一静电环结构，以及连接在数据电压引入线Data'和第二数据选择器之间的第二静电环结构；其中，第一静电环结构和第二静电环结构可以是结构相同的抗静电结构，用于防止在制备显示基板的过程中所产生的静电造成显示基板中的晶体管的沟道被静电击穿。
在一些实施例中，如图6和7所示，在第一静电环结构与数据电压引入线(图5中示意了4条数据信号引入线，分别为Data1'、Data2'、Data3'、Data4')之间连接有第一保护电阻；在第一静电环结构和第一数据选择器之间连接有第二保护电阻；在第二静电环结构和数据电压引入线之间连接有第三保护电阻；在第二静电环结构和第二数据选择器之间连接有第四保护电阻。之所以设置第一保护电阻、第二保护电阻、第三保护电阻、第四保护电阻是为了，对显示基板中的像素单元中的晶体管起到一定的保护作用，同时可以使得第一静电环结构和第二静电环结构不会轻易被静电击穿，起到了多次静电保护的作用。
在一些实施例中，第一保护电阻、第二保护电阻、第三保护电阻、第四保护电阻的阻值均包括但不限于在400Ω-500Ω之间。
如图8所示，以下给出一种第一静电环结构(第二静电环结构)的具体电路结构，其包括四个晶体管分别为第一静电晶体管T19、第二静电晶体管T20、第三静电晶体管T21、第四静电晶体管T22；其中，第一静电晶体管T19、第二静电晶体管T20、第三静电晶体管T21、第四静电晶体管T22均可以N型或者P型晶体管；当各个晶体管选用N型晶体管时，上述的工作电平信号端则为高电平信号端VGH；非工作电平信号端则为低电平信号端VGL；当各个晶体管选用P型晶体管时，上述的工作电平信号端则为低电平 信号端VGL；非工作电平信号端则为高电平信号端VGH；以下第一静电环结构中的第一静电晶体管T19、第二静电晶体管T20、第三静电晶体管T21、第四静电晶体管T22均N型晶体管为例，对第一静电环结构的工作原理进行说明。
其中，第一静电晶体管T19的第一极连接其控制极和数据电压引入线Data'，第一静电晶体管T19的第二极连接第二静电晶体管T20的第一极和控制极，第二静电晶体管T20的第二极连接高电平信号端VGH；第三静电晶体管T21的第二极连接器控制极和数据电压引入线Data1'，第三静电晶体管T21的第二极连接第四静电晶体管T22的第二极和控制极，第四静电晶体管T22的第二极连接低工作电平信号端VGL。
当数据电压引入线Data1'所引入的数据为正向高压时，第一静电晶体管T19和第二静电晶体管T20导通，通过第一静电晶体管T19和第二静电晶体管T20所在支路的高电平信号端VGH将静电引出。应当理解的是，此时正高压的电压值通常应当大于第二静电晶体管T20的第二极所连接的高电平电压端VGH所接入的电压值。
当数据电压引入线Data1'所引入的数据为负向高压时，第三静电晶体管T21和第四静电晶体管T22导通，通过第三静电晶体管T21和第四晶体管T22所在支路的低电平信号端VGL将静电引出。
对于第二静电环结构的工作原理与第一静电环结构的工作原理相同，故在此不再赘述。
第二方面，如图9所示，本发明实施例提供了一种显示基板，该显示基板是由上述显示基板在经过故障检测后，将每个信号供给模块S中出现故障的结构通过激光切割工艺将该结构与显示基板中的其它结构断开电连接(也即图9中“X”示意切开的断开位置)；若哪一个信号供给模块S中的信号供给电路和冗余信号供给电路均没有出现故障，则将这组信号供给模块S中的信号供给电路和冗余信号供给电路的任一者与显示基板中的其它结构断开电连接，以减小显示基板的负载。也就是说，本发明实施例中的显示基板包 括基底；多个阵列排布的像素单元、多条信号线和信号供给模块S，设置在基底上；其中，所述信号供给模块S包括：信号供给电路和冗余信号供给电路；每个所述信号供给模块S的信号供给电路和冗余信号供给电路中仅一者通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
由于本发明实施例中的该显示基板是由上述显示基板在经过故障检测后，将每个信号供给模块S中出现故障的电路结构通过激光切割工艺将该电路结构与显示基板中的其它电学结构断开电连接；具体的可以将出现故障的电路结构的输出端与信号线之间的连线切断，以避免出现故障的电路结构将错误信号输出给信号线。当然，若信号供给模块S中的信号供给电路和冗余信号供给电路均没有出现故障，则将这组信号供给模块S中的信号供给电路和冗余信号供给电路的任一者与显示基板中的其它电学结构断开电连接，以得到本实施例中的显示基板，因此本发明实施例显示基板的良率更高。
其中，本发明实施例中的信号供给模块S中的信号供给电路可以为上述的第一移位寄存器，此时冗余信号供给电路为上述的第二移位寄存器；当然，本发明实施例中的信号供给模块S中的信号供给电路也可以为上述的第一数据选择器，此时冗余信号供给电路可以为上述的第二数据选择器。对于第一移位寄存器、第二移位寄存器、第一数据选择器、第二数据选择器均可以采用上述相同的结构，故在不在重复赘述。对于本发明实施例的显示基板的其它结构也可以与上述显示基板的结构相同，因此不再重复赘述。
第三方面，本发明实施例还提供一种显示面板，其包括上述的显示基板。其中，显示装置可以为液晶显示装置或者电致发光显示装置，例如液晶面板、OLED面板、MicroLED面板，MiniLED面板，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这 些变型和改进也视为本发明的保护范围。

Claims (21)

  1. 一种显示基板，其包括：
    基底；
    多个阵列排布的像素单元、多条信号线和信号供给模块，设置在基底上；其中，
    所述信号供给模块包括：信号供给电路和冗余信号供给电路；
    每个所述信号供给模块通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
  2. 根据权利要求1所述的显示基板，其中，每个所述信号供给模块的信号供给电路和冗余信号供给电路通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
  3. 根据权利要求1或2所述的显示基板，其中，每个所述像素单元包括多个子像素；所述信号线包括数据线组，且每组数据线组包括多条数据线；位于同一列的所述像素单元连接同一所述数据线组，且位于同一列的所述子像素连接同一所述数据线，不同列的所述子像素连接不同所述数据线；
    所述信号供给模块与所述数据线组一一对应设置；
    所述信号供给电路包括：第一数据选择器；所述冗余信号供给电路包括：第二数据选择器；
    每个所述信号供给模块的所述第一数据选择器和所述第二数据选择器通过与之对应的所述数据线组与所述像素单元电连接。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括：数据电压引入线、第一静电环结构和第二静电环结构；
    所述数据电压引入线通过所述第一静电环结构与所述第一数据选择器连接；在所述数据电压引入线和第一静电环结构之间连接有第一保护电阻；在所述第一静电环和所述第一数据选择器之间连接有第二保护电阻；
    所述数据电压引入线通过所述第二静电环结构与所述第二数据选择器连接；在所述数据电压引入线和第二静电环结构之间连接有第三保护电阻；在所述第二静电环和所述第二数据选择器之间连接有第四保护电阻。
  5. 根据权利要求4所述的显示基板，其中，所述第一静电环结构和第二静电环结构均包括第一静电晶体管、第二静电晶体管、第三静电晶体管、第四静电晶体管；
    所述第一静电晶体管的第一极连接其控制极和所述数据电压引入线，第二极连接第二静电晶体管的第一极和控制极，第二静晶体管的第二极连接工作电平信号端；
    第三静晶体管的第一极连接器控制极和数据电压引入线，第二极连接第四静电晶体管的第一极和控制极，第四静电晶体管的第二极连接非工作电平信号端。
  6. 根据权利要求4所述的显示基板，其中，所述第一保护电阻、所述第二保护电阻、所述第三保护电阻、所述第四电阻的阻值均在400Ω-500Ω之间。
  7. 根据权利要求3所述的显示基板，其中，所述像素单元包括三个子像素；所述数据线组包括三条数据线。
  8. 根据权利要求3所述的显示基板，其中，所述第一数据选择器和所述第二数据选择器位于所述基底的所述数据线的信号输入端所在侧。
  9. 根据权利要求1所述的显示基板，其中，所述信号线包括栅线；位于同一行的所述像素单元连接同一栅线；每个所述信号供给模块的所述信号供给电路包括：第一移位寄存器，所述冗余信号供给电路包括：第二移位寄存器；所述第一移位寄存器和所述第二移位寄存器成对设置且连接至同一栅线；
    所述栅线连接至少一个所述信号供给模块中的一对所述第一移位寄存器和所述第二移位寄存器。
  10. 根据权利要求9所述的显示基板，其中，所述栅线与两个所述信号 供给模块连接，且两个所述信号供给模块分别与所述栅线的两个相对端连接。
  11. 根据权利要求9或10所述的显示基板，其中，所述信号供给模块中的多个所述第一移位寄存器级联连接，多个所述第二移位寄存器级联连接；每级所述第一移位寄存器分别与不同的栅线连接；每级所述第二移位寄存器分别与不同的栅线连接；
    第N级第一移位寄存器的信号输入端连接第N-1级所述第一移位寄存器的信号输出端；第N级所述第一移位寄存器的信号输出端连接第N-1级所述第一移位寄存器的信号输入端；
    第N级所述第二移位寄存器的信号输入端连接第N-1级所述第二移位寄存器的信号输出端；第N级所述第二移位寄存器的信号输出端连接第N+1级所述第二移位寄存器的信号输入端，其中N为大于1的整数。
  12. 根据权利要求1所述的显示基板，其中，
    每个所述信号供给模块的信号供给电路和冗余信号供给电路中仅一者通过所述多条信号线中的至少一条与所述多个像素单元中的至少一个电连接。
  13. 根据权利要求12所述的显示基板，其中，每个所述像素单元包括多个子像素；所述信号线包括数据线组，且每组数据线组包括多条数据线；位于同一列的所述像素单元连接同一所述数据线组，且位于同一列的所述子像素连接同一所述数据线，不同列的所述子像素连接不同所述数据线；
    所述信号供给模块与所述数据线组一一对应设置；
    所述信号供给电路包括：第一数据选择器；所述冗余信号供给电路包括：第二数据选择器；
    每个所述信号供给模块的所述第一数据选择器和所述第二数据选择器中仅一者通过与之对应的所述数据线组与所述像素单元电连接。
  14. 根据权利要求13所述的显示基板，其中，所述显示基板还包括：数据电压引入线、第一静电环结构和第二静电环结构；
    所述数据电压引入线通过所述第一静电环结构与所述第一数据选择器连接；在所述数据电压引入线和第一静电环结构之间连接有第一保护电阻；在所述第一静电环和所述第一数据选择器之间连接有第二保护电阻；
    所述数据电压引入线通过所述第二静电环结构与所述第二数据选择器连接；在所述数据电压引入线和第二静电环结构之间连接有第三保护电阻；在所述第二静电环和所述第二数据选择器之间连接有第四保护电阻。
  15. 根据权利要求14所述的显示基板，其中，所述第一静电环结构和第二静电环结构均包括第一静电晶体管、第二静电晶体管、第三静电晶体管、第四静电晶体管；
    所述第一静电晶体管的第一极连接其控制极和所述数据电压引入线，第二极连接第二静电晶体管的第一极和控制极，第二静晶体管的第二极连接工作电平信号端；
    第三静晶体管的第一极连接器控制极和数据电压引入线，第二极连接第四静电晶体管的第一极和控制极，第四静电晶体管的第二极连接非工作电平信号端。
  16. 根据权利要求13所述的显示基板，其中，所述第一数据选择器和所述第二数据选择器位于所述基底的所述数据线的信号输入端所在侧。
  17. 根据权利要求12所述的显示基板，其中，所述信号线包括栅线；位于同一行的所述像素单元连接同一栅线；每个所述信号供给模块的所述信号供给电路包括：第一移位寄存器，所述冗余信号供给电路包括：第二移位寄存器；所述第一移位寄存器和所述第二移位寄存器成对设置且与同一栅线对应；
    所述栅线仅与至少一个所述信号供给模块中的一对所述第一移位寄存器和所述第二移位寄存器中的一者连接。
  18. 根据权利要求17所述的显示基板，其中，所述栅线与两个所述信号供给模块连接，且两个所述信号供给模块分别与所述栅线的两个相对端连接。
  19. 根据权利要求17或18所述的显示基板，其中，所述信号供给模块中的多个所述第一移位寄存器级联连接，所述第二移位寄存器级联连接；每级所述第一移位寄存器分别与不同的栅线对应；每级所述第二移位寄存器分别与不同的栅线对应；
    第N级所述第一移位寄存器的信号输入端连接第N-1级所述第一移位寄存器的信号输出端；第N级所述第一移位寄存器的信号输出端连接第N+1级所述第一移位寄存器的信号输入端；
    第N级所述第二移位寄存器的信号输入端连接第N-1级所述第二移位寄存器的信号输出端；第N级所述第二移位寄存器的信号输出端连接第N+1级所述第二移位寄存器的信号输入端。
  20. 根据权利要求2-19中任一项所述的显示基板，其中，所述像素单元包括发光器件；所述发光器件包括：微型无机发光二极管。
  21. 一种显示面板，其包括权利要求1-20中任一项所述的显示基板。
PCT/CN2019/121249 2019-11-27 2019-11-27 显示基板及显示装置 WO2021102734A1 (zh)

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