WO2020199043A1 - 封装芯片及封装芯片的制作方法 - Google Patents

封装芯片及封装芯片的制作方法 Download PDF

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Publication number
WO2020199043A1
WO2020199043A1 PCT/CN2019/080673 CN2019080673W WO2020199043A1 WO 2020199043 A1 WO2020199043 A1 WO 2020199043A1 CN 2019080673 W CN2019080673 W CN 2019080673W WO 2020199043 A1 WO2020199043 A1 WO 2020199043A1
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WIPO (PCT)
Prior art keywords
bracket
cover plate
chip
substrate
space
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PCT/CN2019/080673
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English (en)
French (fr)
Inventor
郑见涛
赵南
蒋尚轩
胡骁
陶军磊
江宇
吕建标
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980092147.9A priority Critical patent/CN113454774B/zh
Priority to PCT/CN2019/080673 priority patent/WO2020199043A1/zh
Publication of WO2020199043A1 publication Critical patent/WO2020199043A1/zh
Priority to US17/489,403 priority patent/US20220020659A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling

Definitions

  • the embodiments of the present application relate to the field of electronic packaging technology, in particular to a packaged chip and a manufacturing method of the packaged chip.
  • an integrated heat sink can be bonded to the chip, and a thermal interface material (Thermal Interface Material, TIM) can be arranged between the chip and the integrated heat sink.
  • a thermal interface material Thermal Interface Material, TIM
  • TIM is a general term for materials used for coating between heat sink devices and heating devices to reduce the thermal resistance of the contact interface between them. This is because all surfaces will have roughness, so when two surfaces are in contact with each other, it is impossible to completely touch each other. There will always be some air gaps in them, and the thermal conductivity of air is very small, which causes A relatively large contact thermal resistance. The use of TIM can fill this air gap, which can reduce contact thermal resistance and improve heat dissipation performance.
  • the packaged chip in the prior art usually includes a substrate, a chip arranged on the substrate, and an integrated heat sink.
  • the integrated heat sink includes a bracket supported on the substrate and a cover plate arranged on the bracket.
  • a layer of TIM is arranged between the chip and the cover plate to improve the heat dissipation performance of the heat sink.
  • the existing TIM is usually made of metal indium. Since the substrate, chip and cover are made of different materials, the coefficient of thermal expansion is also different. At room temperature or working temperature, the chip and substrate will deform. When the deformation of the TIM is transferred to the TIM, the corners of the TIM will be pulled and deformed and layered, and even cracking of the TIM, which seriously affects the thermal conductivity of the TIM and reduces the heat dissipation performance of the packaged chip.
  • the embodiments of the present application provide a packaged chip and a manufacturing method of the packaged chip, which solves the problem of poor heat dissipation performance of the existing packaged chip.
  • the first aspect of the embodiments of the present application provides a packaged chip, including: a substrate, a chip, and a heat sink;
  • the heat sink includes a first bracket, a second bracket, and a cover plate.
  • the first bracket and the second bracket are disposed on the base plate.
  • the cover plate is supported by the first bracket and the second bracket.
  • the first support is a sealed ring support, the first support and the cover plate enclose a first space, the chip is accommodated in the first space, the chip and the cover
  • a thermal interface material is arranged between the plates, a hole communicating with the first space is arranged on the cover plate, and the hole and the first space are filled with filling material; the second bracket is located in the first space.
  • the filling material is injected into the first space so that the first space becomes a solid whole, which can limit the deformation of the chip and the substrate, thereby avoiding TIM cracking or heat loss, so that the cover plate can fully contact the According to the chip, the heat generated during the operation of the chip is transmitted to the external environment through the cover plate in time, and the heat dissipation performance of the packaged chip is improved.
  • the heat sink in the embodiment of the present application includes two brackets. Compared with only one bracket, the substrate can be pressed on the circuit board better, and the soldering warping can be avoided when the substrate is soldered on the circuit board.
  • first bracket, the second bracket, and the cover plate are integrally formed, and the first bracket and the second bracket are respectively connected to the substrate by an adhesive.
  • first ends of the first bracket and the second bracket are respectively connected to the substrate by an adhesive, and the second ends of the first bracket and the second bracket They are respectively connected with the cover plate through adhesive parts.
  • connection mode of the cover plate and the first bracket and the second bracket does not limit the connection mode of the cover plate and the first bracket and the second bracket, and those skilled in the art can choose according to needs.
  • the second bracket is a ring-shaped bracket arranged around the first bracket and the chip, and the second bracket or the adhesive between the second bracket and the substrate There is an opening.
  • the second bracket is configured as an annular bracket, which can better press the substrate on the circuit board, and avoid welding warpage when the substrate is soldered on the circuit board.
  • the second bracket includes two or more support members, and the support members are evenly arranged on the substrate outside the first space.
  • the material of the thermal interface material TIM and the filling material are the same, the materials of the thermal interface material TIM and the filling material are both silica gel, or the thermal interface material TIM and the
  • the filling material is made of polyolefin resin, and the thermal interface material TIM and the filling material are integrally formed by injection molding.
  • the cover plate includes a first cover plate opposite to the chip, a second cover plate opposite to the first bracket, and a second cover plate located between the first cover plate and the second cover plate.
  • the hole is located on the first cover plate or the third cover plate, and the filling material is injected into the first space through the hole.
  • the packaged chip of the present application injects the filling material into the first space through the hole, and after the filling material is cured, the hole is also sealed as a whole, and the entire packaged chip has a solid structure and is completely isolated from the external environment. Therefore, the internal structure of the packaged chip can be prevented from being corroded by impurities in the air, and the electrical performance and heat dissipation performance of the packaged chip can be improved.
  • the material of the thermal interface material TIM is different from that of the filling material, the material of the thermal interface material TIM is indium, the material of the filling material is silica gel or polyolefin resin, and the filling material The material is formed by injection molding after the thermal interface material TIM is formed.
  • the TIM can be selected from a metal material capable of conducting electricity, and the filling material can be selected from an insulating material. Therefore, those skilled in the art can separately determine the materials of the TIM and the filling material according to needs, providing more choices.
  • the cover plate includes a first cover plate opposite to the chip, a second cover plate opposite to the first bracket, and a second cover plate located between the first cover plate and the second cover plate.
  • the hole is located on the third cover plate in the middle, and the filling material is injected into the first space through the hole.
  • the hole can avoid the position of the pre-formed TIM, so that the filling material can be injected directly into the first space.
  • This application does not limit the specific location, size and number of holes.
  • a production of a packaged chip wherein the material of the thermal interface material TIM is indium, and the material of the filling material is silica gel or polyolefin resin
  • the method includes: Fixed on the first surface of the substrate; place the thermal interface material TIM on the surface of the chip away from the substrate, and at the same time, apply adhesive on the first surface of the substrate; The ends are respectively connected with the adhesive, the second ends of the first bracket and the second bracket are connected with a cover plate, and the cover plate is in contact with the thermal interface material TIM, wherein the first bracket Surrounding the chip, the second bracket surrounding the first bracket, the first surface of the substrate, the cover plate, and the first bracket collectively enclose a first space, and the cover of the first space
  • the plate is provided with holes, wherein the cover plate is integrally formed with the first support and the second support, or the cover plate is connected to the first support and the second support through an adhesive; Melt the thermal interface material TIM
  • a third aspect of the embodiments of the present application provides a method for manufacturing a packaged chip, wherein the thermal interface material TIM and the filling material are made of silica gel, or the thermal interface material TIM and the filling material are made of silica gel.
  • the material is all polyolefin resin, and the method includes: fixing the chip on the first surface of the substrate; applying two circles of adhesive on the first surface of the substrate; connecting the first support and the second support The first ends of the first support and the second ends of the second support are respectively connected with the adhesive, and the second ends of the first support and the second support are connected with a cover plate, and the cover plate is in contact with the thermal interface material TIM, wherein the The first bracket surrounds the chip, the second bracket surrounds the first bracket, the first surface of the substrate, the cover plate and the first bracket jointly enclose a first space, the first Holes are provided on the cover plate of the space, wherein the cover plate is integrally formed with the first bracket and the second bracket, or the cover plate is connected to the first
  • FIG. 1 is a cross-sectional view of a packaged chip provided by an embodiment of the application
  • FIG. 2 is a diagram of a use state of a packaged chip provided by an embodiment of the application.
  • FIG. 3 is a top view of a packaged chip provided by an embodiment of the application.
  • FIG. 4 is a top view of another packaged chip provided by an embodiment of the application.
  • FIG. 5 is a cross-sectional view of another packaged chip provided by an embodiment of the application.
  • FIG. 6 is a flowchart of a method for manufacturing a packaged chip according to an embodiment of the application.
  • Figures 7a, 7b, 7c, 7d, 7e, and 7f are schematic diagrams of structures respectively obtained by performing the various manufacturing steps shown in Figure 6;
  • FIG. 8 is a flowchart of another method for manufacturing a packaged chip according to an embodiment of the application.
  • Figures 9a, 9b, 9c, 9d, 9e, and 9f are schematic diagrams of the structures respectively obtained by performing the production steps shown in Figure 8;
  • FIG. 10 is a flowchart of another method for manufacturing a packaged chip provided by an embodiment of the application.
  • Fig. 11a, Fig. 11b, and Fig. 11c are respectively schematic diagrams of the structures obtained by performing the various manufacturing steps shown in Fig. 10.
  • FIG. 1 is a cross-sectional view of a packaged chip provided by an embodiment of the application.
  • the packaged chip includes: a substrate 10, a chip 20, and a heat sink 30.
  • the chip 20 is located on one surface of the substrate 10 and is electrically connected to the substrate 10.
  • the heat sink 30 and the first surface of the substrate 10 enclose a sealed space, the chip 20 is located in the sealed space, and the heat sink 30 can be used to protect the chip 20 or Heat the chip 20.
  • Fig. 2 shows the state of use of the packaged chip.
  • the packaged chip 1 is set on a circuit board 2 during use.
  • the circuit board 2 is used to carry the packaged chip, and the packaged chip 1 is fixed on
  • the circuit board 2 is electrically connected to the circuit board 2.
  • the circuit board 2 can be a common printed circuit board.
  • the substrate 10 and the circuit board 2 respectively include opposite first and second surfaces, and the second surface of the substrate 10 is opposite to the first surface of the circuit board.
  • the substrate 10 When the substrate 10 is specifically set, the substrate 10 is located on the first surface of the circuit board 2, and the substrate 10 is fixedly connected to the circuit board 2 through solder balls. It should be understood that the substrate 10 and the circuit board 2 shown in FIG. The welding between is only a specific implementation, and other connection methods can also be used for connection in the embodiments of the present application. In addition, for the substrate 10, substrates 10 of different materials such as silicon, ceramics, and organic substrates 10 can be used.
  • the chip 20 may be, for example, a die, or a package structure in which the die is packaged.
  • the chip 20 is, for example, located on the first surface of the substrate 10.
  • the chip 20 includes a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface.
  • the second surface of the chip 20 is opposite to the first surface of the substrate 10.
  • solder balls 50 can be used for connection, or jumpers can also be used for connection, no matter which It only needs to be able to realize electrical connection.
  • a filler 60 may be injected into the gap of the solder ball 50.
  • the material of the filling material 60 may specifically be one or more of silica gel, polyolefin resin, epoxy resin, modified epoxy resin, silicone resin and modified silicone resin.
  • the chip 20 generates heat during use.
  • a heat sink 30 is provided on the chip 20.
  • the heat sink 30 When the heat sink 30 is specifically installed, the heat sink 30 includes, for example, a bracket (302, 303) provided on the first surface of the substrate 10, and a cover plate 301 covering the bracket.
  • the bracket (302, 303) is fixedly connected to the substrate 10, for example.
  • the specific fixing method can be welded, bonded, snap-fitted or connected by connecting pieces (such as bolts or screws).
  • the cross section of the cover plate 301 in the present application is rectangular.
  • the cover plate 301 is not limited to a rectangular cross section, and the cross section may also be circular, trapezoidal or other shapes.
  • the shape of the cover plate 301 is consistent with the shape of the substrate 10.
  • the substrate 10 used to carry the chip 20 also becomes larger, and the size of the cover plate 301 of the heat sink 30 also becomes larger, which makes it difficult to weld the substrate 10
  • the substrate 10 undergoes thermal expansion and deformation.
  • the heat sink 30 is stronger, so the substrate can be pressed tightly to avoid deformation of the substrate.
  • the existing heat sink usually only has one layer of brackets arranged along the periphery of the substrate 10, and the periphery of the substrate can only be pressed by the brackets. The position of the substrate 10 close to the center is prone to large deformation, which will cause the center of the substrate 10 to move toward Bending in the direction close to or away from the radiator cover plate 301 causes soldering warpage and affects the stability of the packaged chip.
  • FIG. 3 is a top view of a packaged chip provided by an embodiment of the application.
  • the top view is a diagram when the structure of the packaged chip shown in FIG. 1 is viewed from top to bottom.
  • the figure adopts a perspective method to show the outline of the bracket.
  • the first bracket 302 and the second bracket 303 are arranged on the first surface of the substrate 10, and the cover 301 is first
  • the bracket 302 and the second bracket 303 are supported on the base plate 10
  • the first bracket 301 is, for example, a sealed ring-shaped bracket
  • the first surface of the base plate 10 the cover plate 301 and the first bracket 302 jointly enclose a first space 70
  • the chip 20 is accommodated in the first space 70, thereby avoiding the corrosion of the circuit of the chip 20 caused by impurities in the outside air, and the electrical performance of the chip 20 is reduced.
  • the second bracket 303 is located outside the first space.
  • the second bracket 303 may be arranged to surround the first bracket 302 and the chip 20.
  • the ring-shaped bracket is formed, and the second bracket 303 is arranged along the periphery of the substrate 10.
  • the contact area between the support and the substrate is increased, so that when the substrate is heated to produce a bending tendency, the substrate can be better pressed on the circuit board to avoid Soldering warpage occurs when the substrate is soldered to the circuit board.
  • the first bracket 302, the second bracket 303, the cover plate 301 and the first surface of the substrate 10 jointly enclose a second space 80, in order to avoid the second space 80 when the substrate 10 is soldered to the circuit board 2.
  • the expansion and contraction of the air with temperature changes affect the performance of the packaged chip.
  • an opening 3017 may be provided on the second bracket 303 or the bonding member between the second bracket 303 and the substrate 10.
  • the second bracket 303 may include two or more support members.
  • FIG. 4 is a top view of another packaged chip provided in an embodiment of the present application. As shown in FIG. 4, the second bracket 303 includes four supporting members, and the supporting members are evenly arranged along the periphery of the substrate 10, for example.
  • the second bracket 303 may be arranged along the periphery of the first surface of the substrate 10, and the first bracket 302 may be arranged on the second bracket 303 and the chip 20, for example.
  • the middle position Therefore, when the substrate 10 is soldered to the circuit board 2 and the substrate 10 undergoes thermal expansion, the second bracket can press the periphery of the substrate 10, and the first bracket 302 can press the substrate 10 around the chip 20.
  • the first support 302 and the second support 303 can be uniformly stressed and press the substrate 10 evenly on the circuit board. The substrate 10 cannot be bent.
  • the radiator 300 is provided with two brackets 302 and 303. Compared with a radiator with only one bracket, the substrate 10 can be pressed on the circuit board better, and the substrate 10 can be prevented from being soldered to the circuit board. When the board 2 is mounted, welding warpage occurs.
  • the heat sink 300 since the size of the chip is usually smaller than the substrate, the heat sink will be faced with the choice of size. Assuming that the plane size of the cover plate of the heat sink 300 is similar to that of the substrate, then In order to maintain the balance of the heat sink, the position of the first bracket 302 will also be close to the edge of the substrate 10. In this case, the position of the substrate 10 close to the center is prone to greater deformation, which will cause the center of the substrate 10 to move closer or farther away.
  • the direction of the radiator cover 301 is bent, causing soldering warpage; and if the size of the radiator 300 is made smaller, and the first bracket 302 is placed close to the chip 20, the heat generated by the chip will be controlled by the radiator 300 Near the center of the substrate 10, uneven heat distribution may cause the chip to discover new structural risks during use.
  • the filling material in the packaged chip in the embodiment of the present invention, it is necessary to inject the filling material into the first space to avoid cracking of the thermal interface material.
  • the filling material will also be in the horizontal direction after solidification. Will be deformed by the influence of cold and heat. The larger the lateral area, the greater the deformation stress transferred to the middle, which may cause the thermal interface material in the center or the periphery of the chip to be pulled and cracked.
  • the size of the filling material to be injected can be controlled, and the stress risk caused by the filling material can be avoided.
  • the second bracket 303 as an annular bracket as shown in FIG. 3 as an example.
  • the cover 301, the first support 302, and the second support 303 can be made of metal materials, for example, copper, aluminum, or an alloy of the two.
  • the cover 301, the first support 302 and the second support 303 are used for the chip 20. Perform heat dissipation.
  • a TIM 40 may be arranged between the chip 20 and the cover plate 301 to effectively conduct the heat generated by the chip 20 to the outside.
  • the TIM 40 is arranged between the chip 20 and the cover plate 301 to reduce the contact thermal resistance between the chip 20 and the cover plate 301. This is because all surfaces will have roughness, so when the chip 20 and the surface of the cover 301 are in contact with each other, it is impossible to completely contact each other. There will always be some air gaps in it, and the thermal conductivity of air is very high. Therefore, it causes a relatively large contact thermal resistance.
  • the use of TIM40 can fill this air gap, which can reduce the contact thermal resistance and improve the heat dissipation performance.
  • the TIM 40 includes, for example, a first surface and a second surface opposite to each other.
  • the first surface of the TIM 40 is adjacent to the cover 301, and the second surface of the TIM 40 is adjacent to the first surface of the chip 20.
  • the TIM 40 is arranged between the cover plate 301 and the chip 20, so that the cover plate 301 can fully contact the chip 20, so that the heat generated during the operation of the chip 20 is timely conducted to the external environment.
  • the TIM40 can be made of thermal interface materials that can conduct electricity, such as low melting point metals such as indium, and can also be made of insulating thermal interface materials, such as silica gel or polyolefin resin.
  • TIM40 When TIM40 is specifically set up, if TIM40 uses indium, for example, TIM40 can be placed on the first surface of chip 20, and then cover plate 301 is fixed on top of TIM40, and then the entire package structure is heated to melt TIM40 to fill chip 20 and The air gap between the cover plates 301.
  • indium for example, TIM40 can be placed on the first surface of chip 20, and then cover plate 301 is fixed on top of TIM40, and then the entire package structure is heated to melt TIM40 to fill chip 20 and The air gap between the cover plates 301.
  • the chip 20 is usually made of silicon, which is different from the copper, aluminum, or alloys of the cover plate 301, and has a large difference in thermal expansion coefficient.
  • the TIM40 is made of metal indium, at room temperature or working temperature, The TIM 40 is in a solid state. When the thermo-mechanical stress generated by the chip 20 and the substrate 10 due to the different thermal expansion coefficients is transferred to the TIM 40, it will cause delamination at the corners of the TIM 40 and affect the thermal conductivity of the TIM 40.
  • the melting point of metal indium is relatively low, about 156.61°C.
  • the chip 20 After the chip 20 is packaged, it needs to be electrically connected to the circuit board. At this time, the temperature needs to be heated to 220°C, which will cause the TIM40 to melt and remove the chip 20 and the heat sink. Loss in the gap between 30 affects the thermal conductivity of TIM40.
  • a filling material may be injected into the first space 70 to limit the deformation of the TIM 40.
  • the chip 20 further includes a side surface connecting the first surface of the chip 20 and the second surface of the chip 20
  • the TIM 40 includes a side surface connecting the first surface of the TIM 40 and the second surface of the TIM 40
  • the filling material may be adjacent to the chip 20 and the second surface of the TIM 40.
  • the filling material in order to prevent the filling material from connecting the heat sink 30 in the packaged chip to the substrate 10 and causing the packaged chip to short-circuit, the filling material should be an insulating material.
  • the material of the filling material may specifically be one or more of silica gel, polyolefin resin, epoxy resin, modified epoxy resin, silicone resin and modified silicone resin.
  • the filling material When filling the filling material into the first space 70, for example, the filling material should be melted first, and the liquid filling material should be injected into the first space 70, and then the filling material should be solidified and formed, or preliminarily solidified and formed, and the formed filling material should be solidified Adjacent to the side of the chip 20 and the TIM 40, the first space 70 becomes a solid structure, which enhances the connection between the substrate 10, the chip 20 and the cover plate 301 of the heat sink 30, so that the chip 20 and the substrate 10 are deformed Due to restrictions, the corners of TIM40 are no longer stratified.
  • the filling material can be the same material as TIM40, for example.
  • the first space can be directly filled with the filling material, and the filling material distributed between the cover plate 301 and the chip 20 can be used as the TIM. After the filling material is cured, the cover plate 301 and the chip 20 can be bonded Together, the two are more fully contacted, so that the heat generated when the chip 20 is working is conducted away in time. And the first space as a solid whole can limit the deformation of the chip and the substrate.
  • the packaged chip in the prior art also needs to provide an opening on the connection structure between the heat sink 30 and the substrate. This is because the existing packaged chip will expand or contract with the temperature change in the air in the sealed space. , Affect the stability of packaged chips. However, after the packaging is completed, the opening still exists, and the air in the external environment will enter the sealed space through the opening and corrode the internal structure of the packaged chip. As a result, the internal metal materials, such as the metal indium material used in the TIM40, are oxidized or sulfided, which affects the electrical performance and heat dissipation performance of the packaged chip.
  • a plurality of holes 3011 may be opened on the cover plate 301 first, and the filling material is filled into the first space through the holes 3011, and the space is sealed through the holes 3011 The original air in the middle is exhausted.
  • filling material is injected into the first space 70 through the hole 3011, and after the filling material is cured, the hole 3011 is also sealed as a whole, and the entire packaged chip has a solid structure and is completely separated from the external environment. Therefore, the internal structure of the packaged chip can be prevented from being corroded by impurities in the air, and the electrical performance and heat dissipation performance of the packaged chip can be improved.
  • the hole 3011 extends from the outer side to the inner side of the cover plate 301, and penetrates the cover plate 301, for example.
  • the cover plate 301 includes, for example, a first cover plate 3012 facing the first surface of the TIM40, a second cover plate 3013 facing the first bracket, and a third cover plate located between the first cover plate 3012 and the second cover plate 3013 3014, a fourth cover plate 3015 facing the second bracket, and a fifth cover plate 3016 located between the second cover plate 3013 and the fourth cover plate 3015.
  • the TIM40 When specifically setting the hole, if the TIM40 and the filling material are made of different materials, the TIM40 is located in the gap between the cover plate 301 and the chip 20. When the filling material is injected into the first space 70, the TIM40 should be avoided. Therefore, the hole 3011 can Located on the third cover 3014.
  • the filling material can be directly injected into the first space through the hole 3011, and the filling material distributed between the cover plate 301 and the chip 20 is used as the TIM. At this time, the hole 3011 can be located in the fourth space. Any position of the cover plate 3015 and the first cover plate 3012.
  • the hole 3011 includes, for example, an injection port through which the filling material can be injected into the first space surrounded by the support, the cover plate 301 and the substrate 10, and distributed between the side surfaces of the chip 20 and the TIM 40 and the first support.
  • the hole 3011 also includes, for example, a vent hole. After the filling material enters the sealed space enclosed by the bracket, the cover 301 and the base plate 10 through the injection port, the original air in the sealed space can be discharged through the vent hole. There may be one or more vent holes, and the vent holes are all distributed on the third cover 3014.
  • the embodiment of the present application takes one injection port and one vent hole as an example for description.
  • the injection port and the vent hole are both located on the third cover plate 3014.
  • the injection port and the vent hole Located on the opposite side.
  • the injection port and the vent hole may be disposed on opposite corners of the cover plate 301, for example.
  • the injection port and the vent hole may be arranged adjacent to each other.
  • connection structure between the first bracket 302 and the second bracket 303 and the substrate 10 and the connection structure between the first bracket 302 and the second bracket 303 and the cover plate 301 will be described below.
  • first bracket 302 and the second bracket 303 and the cover plate 301 may be integrally formed, for example, and the first bracket 302 and the second bracket 303 respectively include a second end connected to the cover plate 301, for example. And a first end extending away from the cover plate 301, wherein the first end of the first bracket 302 can be connected to the first surface of the substrate 10 through a first adhesive rubber ring 3021, and the first end of the second bracket 303
  • the second adhesive rubber ring 3031 may be connected to the first surface of the substrate 10.
  • the first adhesive rubber ring is used to seal the first space 70
  • the second adhesive rubber ring 3031 is used to seal the second space 80.
  • the first space 70 is, for example, a stable solid structure, filled with filling materials, and the first adhesive rubber ring 3021 for sealing the first space 70 may adopt a complete ring structure, for example.
  • the second space 80 is a hollow structure.
  • the second adhesive rubber ring 3031 for sealing the second space 80 is provided with an opening, for example 3017.
  • the opening 3017 can be arranged at any position of the second adhesive rubber ring 3031, and there can be one or more openings 3017. Those skilled in the art can determine the size and position of the opening 3017 according to needs, and this application does not limit this.
  • the first adhesive rubber ring 3021 is located on the peripheral side of the chip 20, and the second adhesive rubber ring 3031 surrounds the first adhesive rubber ring 3021, And the second adhesive rubber ring 3031 is located on the periphery of the substrate 10.
  • the first adhesive rubber ring 3021 and the second adhesive rubber ring 3031 respectively include, for example, a first surface and a second surface opposite to each other, and the first end of the first bracket 302 abuts on the first surface of the first adhesive rubber ring 3021 , The first end of the second bracket 303 abuts against the second surface of the second adhesive rubber ring 3031.
  • the first adhesive rubber ring 3021 and the second adhesive rubber ring 3031 can be formed by curing an adhesive, for example.
  • the specific connection process may be, for example, that the adhesive is first applied to the first surface of the substrate 10, and then the first bracket 302 and the second bracket 303 are pressed to compress the adhesive, and the adhesive is cured to form a second A first adhesive rubber ring 3021 connected to a bracket 302 and a second adhesive rubber ring 3031 connected to the second bracket 303.
  • the adhesive can also be applied to the first end of the first bracket 302 and the second bracket 303 first, and then the adhesive is attached to the first surface of the substrate 10 along with the bracket, and is located on the first bracket 302 and the second bracket.
  • the adhesive at the first end of the two brackets 303 is cured to form a first adhesive rubber ring 3021 and a second adhesive rubber ring 3031 respectively.
  • the first bracket 302, the second bracket 303, and the cover plate 301 are formed separately, and the first bracket 302 and the second bracket 303 include, for example, opposite first ends and second ends.
  • the first end of the first bracket 302 may be connected to the first surface of the substrate 10 through a first adhesive rubber ring 3021, and the second end of the first bracket 302 may be connected to the cover plate through a third adhesive rubber ring 3022, for example. 301 connection.
  • the first end of the second bracket 303 may be connected to the first surface of the substrate 10 through a second adhesive rubber ring 3031, for example, and the second end of the second bracket 303 may be connected to the cover plate 301 through a fourth adhesive rubber ring 3032, for example. connection.
  • the first adhesive rubber ring and the third adhesive rubber ring 3022 are used to seal the first space 70, and the second adhesive rubber ring 3031 and the fourth adhesive rubber ring 3032 are used to seal the second space 80.
  • the first space 70 is, for example, a stable solid structure filled with filling materials.
  • the first adhesive rubber ring 3021 and the third adhesive rubber ring 3022 for sealing the first space 70 may, for example, adopt a complete ring structure.
  • the second space 80 is a hollow structure.
  • the second adhesive rubber ring 3031 and the fourth adhesive used to seal the second space 80 The rubber ring 3032 is provided with an opening 3017, for example.
  • the opening 3017 may be provided only on the second adhesive rubber ring 3031 or the fourth adhesive rubber ring 3032, or both the second adhesive rubber ring 3031 and the fourth adhesive rubber ring 3032 may be provided with openings 3017.
  • Those skilled in the art can determine the number, size and position of the openings according to needs, and this application does not limit this.
  • the specific forming process of the third adhesive rubber ring 3022 and the fourth adhesive rubber ring 3032 may be that the adhesive is first applied to the second ends of the first bracket 302 and the second bracket 303, and then the cover The board 301 compresses the adhesive, the adhesive on the first bracket 302 is cured to form a third adhesive apron 3022, and the adhesive on the second bracket 303 is cured to form a fourth adhesive apron 3032.
  • the adhesive can also be applied to the cover plate 301 first, and then the adhesive is attached to the second end of the first bracket 302 along with the cover plate 301 to form a third adhesive rubber ring 3022, which is attached to the second bracket The second end of 303 forms a fourth adhesive rubber ring 3032.
  • the adhesive rubber ring in the embodiment of this application takes a rectangular ring structure as an example.
  • the adhesive rubber ring is not limited to a rectangular ring shape, and may also be a circular ring shape or an elliptical shape. Ring, trapezoid ring or other shapes.
  • the shape and size of the adhesive rubber ring are consistent with the shape and size of the bracket.
  • the TIM40 is made of indium and the filling material is made of silica gel or polyolefin resin, such as As shown in Figure 6, the method includes:
  • the chip is fixed on the first surface of the substrate.
  • Fixing the chip 20 on the first surface of the substrate 10 includes: as shown in FIG. 7a, a solder ball 50 is arranged on the first surface of the chip 20, and the solder ball 50 is connected to the first surface of the substrate 10 by reflow soldering. The surface connection, and as shown in FIG. 7b, a filler material 60 is injected into the gap of the solder ball 50.
  • the first ends of the first bracket 302 and the second bracket 303 are respectively connected with an adhesive, and the second ends of the first bracket 302 and the second bracket 303 are connected with a cover plate 301, and the cover plate 301 is in contact with the TIM 40, wherein the first support 302 surrounds the chip 20, the second support 303 surrounds the first support 302, the first surface of the substrate 10, the cover 301 and the first support 302 jointly enclose a first space 70, 20 is accommodated in the first space 70.
  • the cover 301 includes a first cover 3012 opposite to the TIM40, a second cover 3013 opposite to the first bracket 302, a third cover 3014 opposite to the second bracket 303, a first cover 3012 and two covers
  • the fourth cover plate 3015 between the plates 301, and the fifth cover plate 3016 between the second cover plate 3013 and the third cover plate 3014, the fourth cover plate 3015 is provided with a hole 3011.
  • the adhesive may be applied to the first ends of the first bracket 302 and the second bracket 303 first, and then the adhesive is attached to the substrate 10 along with the bracket.
  • the first surface may be applied to the first ends of the first bracket 302 and the second bracket 303 first, and then the adhesive is attached to the substrate 10 along with the bracket. The first surface.
  • the adhesive at the first end of the first bracket 302 is cured to form a first adhesive apron 3021, and the adhesive at the second end of the first bracket 302 is cured to form a third adhesive apron 3022.
  • the adhesive at the first end of the two brackets 303 is cured to form a second adhesive apron 3031, and the adhesive at the second end of the second bracket 303 is cured to form a fourth adhesive apron 3032.
  • the first adhesive rubber ring 3021 and the third adhesive rubber ring 3022 are used to seal the first space 70, and the second adhesive rubber ring 3031 and the fourth adhesive rubber ring 3032 are used to seal the second space 80.
  • the first adhesive rubber ring 3021 and the third adhesive rubber ring 3022 are, for example, a complete ring structure, and the second adhesive rubber ring 3031 and the fourth adhesive rubber ring 3032 are provided with openings communicating with the external environment.
  • a filling material is injected through the hole 3011, wherein the filling material is adjacent to the side surfaces of the chip 20 and the TIM 40 and fills the first space 70.
  • solder balls are arranged on the second surface of the substrate 10.
  • solder balls can be arranged on the second surface of the substrate 10, and the solder balls can be connected to the first surface of the circuit board by reflow soldering.
  • this application does not limit the sequence of the foregoing steps, and the sequence of the foregoing steps can be adjusted according to different manufacturing processes.
  • the filling material is injected into the solder ball gap of the chip 20, which may be before the step S107.
  • the filling material for filling the solder ball gap and the filling material for filling the first space 70 may be different materials.
  • step S102 can be merged into step S107, that is, the filling material is injected into the first space 70 and the solder ball gap of the chip 20 at the same time. At this time, the filling material used to fill the solder ball gap and the first space The filling material of 70 is the same.
  • this application also provides a method for manufacturing any one of the above packaged chips as described above.
  • the TIM and the filling material in the packaged chip are made of silica gel, as shown in FIG. 8 As shown, the method includes:
  • the chip 20 is fixed on the first surface of the substrate 10.
  • Fixing the chip 20 on the first surface of the substrate 10 includes: arranging solder balls on the first surface of the chip 20 and connecting the solder balls to the first surface of the substrate 10 through reflow soldering. And as shown in FIG. 9b, a filling material is injected into the gap between the chip 20 and the first surface and the first surface of the substrate 10.
  • the first ends of the first bracket 302 and the second bracket 303 are respectively connected with an adhesive, and the second ends of the first bracket 302 and the second bracket 303 are connected with a cover plate 301.
  • the first bracket 302 surrounds the chip 20
  • the second bracket 303 surrounds the first bracket 302
  • the cover plate 301 and the first bracket 302 jointly enclose a first space 70
  • the chip 20 is accommodated in the first space 70.
  • Space 70 is provided in the first space 70.
  • the cover plate 301 includes a first cover plate 3012 opposite to the chip 20, a second cover plate 3013 opposite to the first support 302, a third cover plate 3014 opposite to the second support 303, located on the first cover plate 3012 and two
  • the fourth cover plate 3015 between the cover plates 301 and the fifth cover plate 3016 between the second cover plate 3013 and the third cover plate 3014, the first cover plate 3012 or the fourth cover plate 3015 is provided with a hole 3011 .
  • a filling material is injected through the hole 3011, where the filling material is adjacent to the side surfaces of the chip 20 and the TIM 40 and fills the first space 70.
  • solder balls are arranged on the second surface of the substrate 10.
  • solder balls can be arranged on the second surface of the substrate 10, and the solder balls can be connected to the first surface of the circuit board by reflow soldering.
  • step S103 and step S203 the second ends of the first bracket 302 and the second bracket 303 are connected with a cover plate 301, for example, including: the first bracket 302 and the second bracket 303 can be integrally formed with the cover plate 301, for example, Or the first bracket 302 and the second bracket 303 may be fixedly connected to the cover 301 by an adhesive rubber ring.
  • first bracket 302, the second bracket 303 and the cover plate 301 are integrally formed, the first bracket 302, the second bracket 303, and the base plate 10 can be integrated as a whole, and only the first bracket 302 and the second bracket 303 are required. One end is fixedly connected to the first surface of the substrate 10.
  • the manufacturing method of the packaged chip further includes the following steps:
  • the adhesive may be applied to the cover plate 301 first, and then the adhesive is attached to the first bracket 302 and the second bracket along with the cover plate 301 The second end of 303.
  • the manufacturing method of the packaged chip provided in the embodiment of the present application has the same technical effect as the package structure of the chip 20 provided in the foregoing embodiment, and will not be repeated here.

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Abstract

本申请实施例公开了一种封装芯片及封装芯片的制作方法，该封装芯片包括：基板、芯片、和散热器；所述散热器包括第一支架、第二支架和盖板，所述第一支架和所述第二支架设置在所述基板上，所述盖板被所述第一支架和所述第二支架支撑于所述基板上；所述第一支架为密封的环形支架，所述第一支架和所述盖板围成第一空间，所述芯片被容纳在所述第一空间内，所述芯片和所述盖板之间设置有热界面材料，所述盖板上设置有与所述第一空间相通的孔，所述孔和所述第一空间中被充满填充材料；所述第二支架位于所述第一空间外部。

Description

封装芯片及封装芯片的制作方法 技术领域
本申请实施例涉及电子封装技术领域，尤其涉及一种封装芯片及封装芯片的制作方法。
背景技术
随着微电子技术的发展，电子芯片的集成度日益增加，且各个电子芯片的功耗也越来越大，因此，电子芯片，如计算机中的中央处理器(central processing unit，简称CPU)上的热流密度也越来越高。
为了提高芯片的散热性能，可以在芯片上粘接一个集成散热器，并在芯片和集成散热器之间设置热界面材料(Thermal Interface Material，简称TIM)。
TIM是用于涂敷在散热器件与发热器件之间，以降低它们之间接触介面热阻所使用的材料的总称。这是由于凡是表面都会有粗糙度，所以当两个表面接触在一起的时候，不可能完全接触在一起，总会有一些空气隙夹杂在其中，而空气的导热系数非常之小，因此就造成了比较大的接触热阻。而使用TIM就可以填充这个空气隙，这样就可以降低接触热阻，提高散热性能。
现有技术的封装芯片通常包括基板，以及设置在基板上的芯片和集成散热器，其中，集成散热器包括支撑在所述基板上的支架，以及设置在所述支架上的盖板，在所述芯片和所述盖板之间设有一层TIM，以提高散热器的散热性能。
现有的TIM通常采用金属铟制成，由于基板、芯片和盖板分别采用不同材质制成，热膨胀系数也各不相同，在室温或工作温度时，芯片和基板会发生形变，当芯片和基板的形变传递到TIM时，会使得TIM的边角位置处受到拉扯而变形分层，甚至会造成TIM开裂，严重影响TIM的导热性能，降低了封装芯片的散热性能。
发明内容
本申请实施例提供一种封装芯片及封装芯片的制作方法，解决了现有封装芯片散热性能差的问题。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种封装芯片，包括：基板、芯片、和散热器；
所述散热器包括第一支架、第二支架和盖板，所述第一支架和第二支架设置在所述基板上，所述盖板被所述第一支架和第二支架支撑于所述基板上；所述第一支架为密封的环形支架，所述第一支架和所述盖板围成第一空间，所述芯片被容纳在所述第一空间内，所述芯片和所述盖板之间设置有热界面材料，所述盖板上设置有与所述第一空间相通的孔，所述孔和所述第一空间中被充满填充材料；所述第二支架位于所述第一空间外部。
本申请实施例通过在第一空间中注入填充材料，使得第一空间成为一个实心的整体，能够限制芯片和基板的形变，进而能够避免TIM开裂或者受热流失，使得所述盖板可充分接触所述芯片，从而将该芯片工作时产生的热量通过盖板及时传导至外界环境中， 提高了该封装芯片的散热性能。
此外，本申请实施例中的散热器包括两个支架，与仅设置一个支架相比，能够更好的将基板压在电路板上，避免将基板焊接在电路板时产生焊接翘曲。
并且，本申请中只需要在第一支架围设的第一空间中注入填充材料，能够节省填充材料的用量。
在可选的实现方式中，所述第一支架、所述第二支架与所述盖板一体成型，所述第一支架和所述第二支架分别通过粘接件与所述基板连接。
在可选的实现方式中，所述第一支架和所述第二支架的第一端分别通过粘接件与所述基板连接，且所述第一支架和所述第二支架的第二端分别通过粘接件与所述盖板连接。
本申请对盖板和第一支架、第二支架的连接方式不做限定，本领域技术人员可根据需要选择。
在可选的实现方式中，所述第二支架为环绕所述第一支架和所述芯片设置的环形支架，所述第二支架或所述第二支架与所述基板之间的粘接件上设有开口。
由此，将该第二支架设置成环形支架，能够更好的将基板压在电路板上，避免将基板焊接在电路板时产生焊接翘曲。
在可选的实现方式中，所述第二支架包括2个或2个以上的支撑件，所述支撑件均匀排布在所述第一空间外部的基板上。
在可选的实现方式中，所述热界面材料TIM与所述填充材料的材质相同，所述热界面材料TIM和所述填充材料的材质均为硅胶，或者所述热界面材料TIM和所述填充材料的材质均为聚烯烃树脂，所述热界面材料TIM和所述填充材料通过注塑的方式一体成型。
由此，能够简化填充材料的填充操作，提高了工作效率。
在可选的实现方式中，所述盖板包括与所述芯片相对的第一盖板、与所述第一支架相对的第二盖板和位于所述第一盖板和第二盖板之间的第三盖板，所述孔位于所述第一盖板或所述第三盖板上，所述填充材料经由所述孔注入到所述第一空间中。
由此，本申请的封装芯片在通过该孔向第一空间中注入填充材料，并使得填充材料固化后，该孔也被密封为一体，整个封装芯片内部为实心结构，与外界环境完全隔开，能够避免封装芯片的内部结构受到空气中杂质的侵蚀，提高了封装芯片的电气性能和散热性能。
在可选的实现方式中，所述热界面材料TIM与所述填充材料的材质不同，所述热界面材料TIM的材质为铟，所述填充材料的材质为硅胶或聚烯烃树脂，所述填充材料在所述热界面材料TIM成型后，通过注塑的方式成型。
其中，TIM可选择能够导电的金属材质，填充材料可选择绝缘材质，由此，本领域技术人员可根据需要分别确定TIM和填充材料的材质，提供了更多的选择。
在可选的实现方式中，所述盖板包括与所述芯片相对的第一盖板、与所述第一支架相对的第二盖板和位于所述第一盖板和第二盖板之间的第三盖板，所述孔位于所述第三盖板上，所述填充材料经由所述孔注入到所述第一空间中。
由此，所述孔能够避开预先成型的TIM的位置，从而可以直接向第一空间中注入 填充材料。
本申请对孔的具体位置，大小和数量不做限制。
本申请实施例的第二方面，提供一种封装芯片的制作，其中，所述热界面材料TIM的材质为铟，所述填充材料的材质为硅胶或聚烯烃树脂，所述方法包括：将芯片固定在基板的第一表面上；在芯片背离所述基板的表面上放置热界面材料TIM，同时，在所述基板的第一表面涂抹粘结剂；将第一支架和第二支架的第一端分别与所述粘结剂连接，所述第一支架和所述第二支架的第二端连接有盖板，所述盖板与所述热界面材料TIM接触，其中，所述第一支架环绕所述芯片，所述第二支架环绕所述第一支架，所述基板的第一表面、所述盖板和所述第一支架共同围设成第一空间，所述第一空间的盖板上设有孔，其中，所述盖板与所述第一支架、第二支架一体成型，或所述盖板通过粘接剂与所述第一支架和所述第二支架连接；加热以融化所述热界面材料TIM，使得所述热界面材料TIM密封所述芯片与所述盖板之间的缝隙；固化所述热界面材料TIM，使得所述芯片通过固化后的热界面材料TIM与所述盖板连接，同时固化所述粘接剂，以形成粘接胶圈；通过所述孔注入填充材料，以填充所述第一空间；固化所述填充材料。
本申请实施例的第三方面，提供一种封装芯片的制作方法，其中，所述热界面材料TIM和所述填充材料的材质均为硅胶，或者所述热界面材料TIM和所述填充材料的材质均为聚烯烃树脂，所述方法包括：将芯片固定在基板的第一表面上；在所述基板的第一表面涂抹两圈粘结剂；将所述第一支架和所述第二支架的第一端分别与所述粘结剂连接，所述第一支架和所述第二支架的第二端连接有盖板，所述盖板与所述热界面材料TIM接触，其中，所述第一支架环绕所述芯片，所述第二支架环绕所述第一支架，所述基板的第一表面、所述盖板和所述第一支架共同围设成第一空间，所述第一空间的盖板上设有孔，其中，所述盖板与所述第一支架、第二支架一体成型，或所述盖板通过粘接剂与所述第一支架和所述第二支架连接；固化所述粘接剂，以形成粘接胶圈；通过所述孔注入填充材料，以填充所述第一空间；固化所述填充材料。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为本申请实施例提供的一种封装芯片的剖视图；
图2为本申请实施例提供的一种封装芯片的使用状态图；
图3为本申请实施例提供的一种封装芯片的俯视图；
图4为本申请实施例提供的另一种封装芯片的俯视图；
图5为本申请实施例提供的另一种封装芯片的剖视图；
图6为本申请实施例提供的一种制造封装芯片的方法流程图；
图7a、图7b、图7c、图7d、图7e、图7f分别为执行图6所示的各个制作步骤分别得到的结构示意图；
图8为本申请实施例提供的另一种制造封装芯片的方法流程图；
图9a、图9b、图9c、图9d、图9e、图9f分别为执行图8所示的各个制作步骤分别得到的结构示意图；
图10为本申请实施例提供的另一种制造封装芯片的方法流程图；
图11a、图11b、图11c分别为执行图10所示的各个制作步骤分别得到的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
下面结合附图对本申请实施例提供的封装芯片进行说明。图1为本申请实施例提供的封装芯片的剖视图。如图1所示，该封装芯片包括：基板10、芯片20、和散热器30。所述芯片20位于所述基板10的一个表面上，并与所述基板10电连接。所述散热器30与所述基板10的第一表面围设成一个密封的空间，所述芯片20位于所述密封空间内，所述散热器30既可以用于保护芯片20，还可以用于为芯片20进行散热。
图2示出了该封装芯片的使用状态图，如图2所示，封装芯片1在使用时设置在一个电路板2上，该电路板2例如用于承载该封装芯片，封装芯片1固定在该电路板2上，并与该电路板2电连接。其中，该电路板2可以为常见的印刷电路板。
继续参考图1及图2，基板10和电路板2分别包括相对的第一表面和第二表面，基板10的第二表面与电路板的第一表面相对。
在具体设置基板10时，基板10例如位于电路板2的第一表面上，并且基板10例如通过焊球与电路板2固定连接，应当理解的是，图1所示的基板10与电路板2之间的焊接仅仅为一种具体的实施方式，在本申请实施例中还可以采用其他的连接方式进行连接。此外，对于该基板10可以采用如硅、陶瓷、有机基板10等不同材质的基板10。
芯片20例如可以是裸片，也可以是封装了裸片的封装结构。在具体设置芯片20时，芯片20例如位于基板10的第一表面，芯片20包括相对的第一表面和第二表面，以及连接第一表面和第二表面的侧面，芯片20与基板10连接时，芯片20的第二表面与基板10的第一表面相对，在芯片20与基板10的电路层连接时，例如可以采用焊球50进行连接，或者还可以采用跳线进行连接，无论采用哪种方式，只需要能够实现电连接即可。
在通过焊球50进行连接时，例如还可以在焊球50的间隙中注入填充材料60。填充材料60的材质具体可以为：硅胶、聚烯烃树脂、环氧树脂，改性环氧树脂，硅树脂和改性硅树脂中的一种或多种。
芯片20在使用中会产生热量，为了将芯片20产生的热量传递至外部环境中以进 行散热，例如还在芯片20上罩设有散热器30。
具体设置该散热器30时，该散热器30例如包括设置在基板10第一表面的支架(302，303)，以及盖合在支架上的盖板301。该支架(302，303)例如与基板10固定连接。具体的固定方式可采用焊接、粘接、卡合连接或者采用连接件(如螺栓或螺钉)进行连接。
参考图3、图4，本申请中的盖板301的横截面为长方形状。当然在能够实现本发明目的的情况下，盖板301并不局限于截面为长方形，截面也可以为圆形、梯形或其他形状。在本发明实施例中，盖板301的形状与基板10的形状保持一致。
目前，随着现有的芯片20越做越大，用于承载芯片20的基板10也随之变大，散热器30的盖板301尺寸也适应性变大，这就使得在将基板10焊接到电路板2上时，基板10受热膨胀变形，其中，散热器30强度较大，因此能够将基板压紧，避免基板变形。但是现有的散热器通常只有沿基板10的周边设置的一层支架，只能通过支架压住基板的周边，基板10靠近中心的位置则容易产生较大的形变，会使得基板10的中心向靠近或远离散热器盖板301的方向弯曲，产生焊接翘曲，影响封装芯片的稳固性。
为此，本申请实施例提供了一种双支架结构的封装芯片，图3为本申请实施例提供的一种封装芯片的俯视图。该俯视图为从上往下俯视图1所示的封装芯片的结构时的附图，其中，为便于描述，图中采用透视法，示出了支架的轮廓。如图3所示，该支架可以为2个，分别为第一支架302和第二支架303，第一支架302和第二支架303设置在基板10的第一表面上，盖板301被第一支架302和第二支架303支撑于基板10上，第一支架301例如为密封的环形支架，且，基板10的第一表面、盖板301和第一支架302共同围设成第一空间70，芯片20被容纳于该第一空间70内，从而避免了外界空气中的杂质对芯片20电路的腐蚀造成芯片20电气性能的下降。
第二支架303则位于第一空间外部，具体设置第二支架303时，如图3所示，在本申请的一个实施例中，可以将第二支架303设置成环绕第一支架302和芯片20的环形支架，并使得第二支架303沿基板10的周边设置。
由此，通过设置两个支架，与仅设置一个支架相比，增加了支架与基板之间的接触面积，从而当基板受热产生弯曲趋势时，能够更好的将基板压在电路板上，避免将基板焊接在电路板时产生焊接翘曲。
其中，第一支架302、第二支架303、盖板301和基板10的第一表面共同围设成第二空间80，为避免在将基板10焊接到电路板2上时，第二空间80中的空气随温度变化膨胀和收缩影响封装芯片的性能，例如可以在第二支架303或第二支架303与基板10的粘接件上设置开口3017。
在本申请的另一个实施例中，第二支架303可以包括2个或2个以上的支撑件，图4为本申请实施例提供的另一种封装芯片的俯视图。如图4所示，第二支架303包括4个支撑件，该支撑件例如沿基板10的周边均匀排布。
此外，具体设置该第一支架302和该第二支架303时，该第二支架303例如可以沿基板10第一表面的周边设置，该第一支架302例如可以设置在第二支架303和芯片20中间的位置。由此，在将基板10焊接到电路板2上时，基板10受热膨胀产生变形趋势时，第二支架能够压住基板10的周边，第一支架302能够压住芯片20周围的基 板10，第一支架302和第二支架303可以均匀受力，将基板10均匀的压在电路板上。使得基板10无法弯曲。
在本申请实施例中，散热器300设置两个支架302和303，与仅设置一个支架的散热器相比，能够更好的将基板10压在电路板上，避免在将基板10焊接到电路板2上时，产生焊接翘曲。
如果散热器300只使用第一支架302的话，由于芯片的尺寸通常都小于基板，散热器就要面临着尺寸的选择，假设将散热器的300的盖板的平面尺寸做到与基板相近，那为了维持散热器的平衡，第一支架302的位置也会靠近所述基板10的边缘，这样的话，基板10靠近中心的位置则容易产生较大的形变，会使得基板10的中心向靠近或远离散热器盖板301的方向弯曲，产生焊接翘曲；而如果将散热器300的尺寸做小，让第一支架302在靠近芯片20的位置，这样会导致芯片产生的热量被散热器300控制在基板10的中心附近，热量分布不均匀会导致芯片在使用过程中发现新的结构风险。
当采用第一支架302和第二支架303这样的双重支架支撑散热器300后，就不会产生上述的问题。
进一步的，本发明实施例中的封装芯片中，需要通过向第一空间注入填充材料来避免热界面材料的开裂，可是如果第一空间的横向面积很大，填充材料凝固后在水平方向上也会受到冷热影响而产生变形，横向面积越大，那么传递到中间的变形应力自然也会越大，从而有可能会导致处于中心部位的热界面材料或者芯片周边受到拉扯而产生开裂，而在本发明中，通过双层支架的设计，使得需要注入填充材料的大小能够得到控制，避免填充材料带来的应力风险。
本申请对第二支架的具体结构不做限制，本领域技术人员可根据需要进行选择，这些均属于本申请的保护范围。
为便于描述，本申请以下实施例均以第二支架303为如图3中所示的环形支架为例进行说明。
盖板301、第一支架302和第二支架303，例如可由金属材料，例如，铜、铝或二者的合金制成，盖板301和第一支架302和第二支架303用于为芯片20进行散热。
为了进一步提高封装芯片的散热性能，例如还可以在芯片20和盖板301之间设置TIM40，以有效地将芯片20产生的热量向外界传导。
参考图1，将TIM40设置在芯片20与盖板301之间，能够降低芯片20与盖板301之间的接触热阻。这是由于，凡是表面都会有粗糙度，所以当芯片20与盖板301的表面接触在一起的时候，不可能完全接触在一起，总会有一些空气隙夹杂在其中，而空气的导热系数非常之小，因此就造成了比较大的接触热阻。而使用TIM40就可以填充这个空气隙，这样就可以降低接触热阻，提高散热性能。
TIM40例如包括相对的第一表面和第二表面，TIM40的第一表面例如与盖板301邻接，TIM40的第二表面例如与芯片20的第一表面邻接。
本申请实施例提供的封装芯片，通过在盖板301和芯片20之间设置TIM40，使得盖板301可充分接触芯片20，从而将该芯片20工作时产生的热量及时传导至外界环境中。
TIM40例如可以采用能够导电的热界面材料，例如，铟等低熔点金属，也可以采 用绝缘的热界面材料，例如硅胶或者聚烯烃树脂。
具体设置TIM40时，若TIM40采用铟，例如可以先将TIM40放置在芯片20的第一表面，再将盖板301固定在TIM40的上方，接着加热整个封装结构，使得TIM40融化，以填充芯片20与盖板301之间的空气隙。
然而，芯片20通常采用硅制成，与盖板301采用的铜、铝或二者的合金等的材质不同，热膨胀系数相差较大，若TIM40采用金属铟制成，在室温或工作温度时，TIM40处于固态，芯片20和基板10由于热膨胀系数不同产生的热机械应力传递至TIM40时，会使得TIM40的边角处产生分层，影响TIM40的导热性能。此外，金属铟熔点较低，约为156.61℃，芯片20完成封装之后还还需要电连接到电路板上，此时，需要将温度加热至220℃，会使得TIM40融化，从芯片20和散热器30之间的缝隙中流失，影响TIM40的导热性能。
为了避免TIM40开裂或受热流失，例如可以在第一空间70中注入填充材料，以限制TIM40的形变。其中，芯片20还包括连接芯片20的第一表面和芯片20的第二表面的侧面，TIM40包括连接TIM40的第一表面和TIM40的第二表面的侧面，填充材料例如可以邻接芯片20和TIM40的侧面设置。
其中，为了避免填充材料将封装芯片中的散热器30等于基板10导通，造成封装芯片短路，填充材料应采用绝缘材料。填充材料的材质具体可以为：硅胶、聚烯烃树脂、环氧树脂，改性环氧树脂，硅树脂和改性硅树脂中的一种或多种。
在将填充材料填充至第一空间70时，例如应先将填充材料熔融，并将液态的填充材料注入第一空间70，再使得填充材料固化成型，或者初步固化成型，固化成型后的填充材料邻接芯片20和TIM40的侧面设置，将第一空间70变成一个实心结构的整体，增强了基板10、芯片20与散热器30的盖板301之间的连接，使得芯片20和基板10的变形受到限制，TIM40的边角不再分层。
并且，在将封装芯片电连接至电路板的过程中，封装芯片中的TIM40即使受热被再次融化，液态TIM40的流动也会受到填充材料的限制，不会流到其他位置造成TIM40流失或者造成其他器件的短路。
若TIM40采用硅胶或者聚烯烃树脂，填充材料例如可以采用与TIM40相同的材质。填充时，无需单独设置TIM，可以直接通过填充材料填充第一空间，并将分布于盖板301和芯片20之间的填充材料作为TIM，填充材料固化后可以将盖板301与芯片20粘接在一起，使得二者更充分接触，从而将芯片20工作时产生的热量及时传导出去。并且第一空间作为一个实心的整体，能够限制芯片和基板的形变。
本申请实施例通过在第一空间中注入填充材料，能够避免TIM开裂或者受热流失，进而使得盖板可充分接触芯片，从而将该芯片工作时产生的热量通过盖板及时传导至外界环境中。
此外，现有技术中的封装芯片例如还需要在散热器30与基板的连接结构上设置开口，这是由于现有的封装芯片，随着温度变化，密封空间内的空气会随之膨胀或收缩，影响封装芯片的稳定性。但封装完成后，该开口依然存在，外界环境中的空气会通过该开口进入该密封空间中，侵蚀封装芯片的内部结构。使得内部的金属材料，例如TIM40所采用的金属铟材料，产生氧化或硫化，影响封装芯片的电气性能和散热性能。
对于此，本申请实施例在第一空间注入填充材料时，例如可以先在盖板301上开设若干孔3011，并通过孔3011将填充材料填充至第一空间内，以及通过孔3011将密封空间中原有的空气排出。并且，本申请的封装芯片在通过孔3011向第一空间70中注入填充材料，并使得填充材料固化后，孔3011也被密封为一体，整个封装芯片内部为实心结构，与外界环境完全隔开，能够避免封装芯片的内部结构受到空气中杂质的侵蚀，提高了封装芯片的电气性能和散热性能。
具体设置该孔3011时，该孔3011例如从盖板301的外侧延伸至其内侧，并贯通该盖板301。
盖板301例如包括正对TIM40的第一表面的第一盖板3012、正对第一支架的第二盖板3013，位于第一盖板3012和第二盖板3013之间的第三盖板3014，以及正对第二支架的第四盖板3015，以及位于第二盖板3013和第四盖板3015之间的第五盖板3016。
具体设置该孔时，若TIM40和填充材料采用不同材料，TIM40位于盖板301和芯片20之间的缝隙中，在向第一空间70注入填充材料时，应避开TIM40，因此，孔3011可以位于第三盖板3014上。
若TIM40和填充材料采用相同材料，可以直接通过孔3011向第一空间中注入填充材料，并将分布于盖板301和芯片20之间的填充材料作为TIM，此时，孔3011可以位于第四盖板3015和第一盖板3012的任意位置。
孔3011例如包括注入口，填充材料例如可以通过该注入口注入由支架、盖板301以及基板10一起围成的第一空间内，并分布在芯片20与TIM40的侧面和第一支架之间。注入口可以为多个，多个注入口可以均匀分布在第三盖板3014上。基于此，填充材料可均匀地通过该注入口填充到密封空间内，使得盖板301充分、均匀地接触芯片20，从而将该芯片20工作时产生的热量及时传导出来，提高了散热效率。
孔3011例如还包括通气孔，填充材料由注入口进入由支架、盖板301以及基板10一起围成的密封的空间后，密封空间中原有的空气可以通过通气孔排出。通气孔可以为一个或多个，通气孔均分布在第三盖板3014上。
本申请对注入口和通气孔的具体数量不做限制，本领域技术人员可根据需要进行设置。
本申请实施例以一个注入口和一个通气孔为例进行说明，参考图2，注入口和通气孔均位于第三盖板3014上，在本申请的一个实施例中，注入口和通气孔可以位于相对侧。在本申请的另一个实施例中，注入口和通气孔例如可相对设置在盖板301的对角上。或者，注入口和通气孔可以彼此相邻设置。
并且，本申请中只需要在第一空间中注入填充材料，能够节省填充材料的用量。
以下对第一支架302和第二支架303与基板10，以及第一支架302和第二支架303与盖板301之间的连接结构进行说明。
在本申请的一种实现方式中，第一支架302和第二支架303与盖板301例如可以是一体成型，第一支架302和第二支架303例如分别包括与盖板301连接的第二端和向背离盖板301方向延伸的第一端，其中，第一支架302的第一端例如可以通过第一粘接胶圈3021与基板10的第一表面连接，第二支架303的第一端例如可以通过第二粘接胶圈3031与基板10的第一表面连接。
其中，第一粘结胶圈用于密封第一空间70，第二粘接胶圈3031用于密封第二空间80。
第一空间70例如为稳定的实心结构，其内部填充有填充材料，用于密封第一空间70的第一粘接胶圈3021例如可以采用完整的环形结构。
第二空间80则为中空结构，为避免第二空间80中的空气随温度变化膨胀和收缩影响封装芯片的性能，用于密封第二空间80的第二粘接胶圈3031上例如开设有开口3017。开口3017可以设置在第二粘接胶圈3031的任意位置，开口3017可以为一个，也可以为多个。本领域技术人员可根据需要确定开口3017的大小和位置，本申请对此不做限制。
具体设置第一粘接胶圈3021和第二粘接胶圈3031时，第一粘接胶圈3021例如位于芯片20的周侧，第二粘接胶圈3031环绕第一粘接胶圈3021，且第二粘接胶圈3031位于基板10的周边。第一粘接胶圈3021和第二粘接胶圈3031例如分别包括相对的第一表面和第二表面，第一支架302的第一端抵接在第一粘接胶圈3021的第一表面，第二支架303的第一端抵接在第二粘接胶圈3031的第二表面。
第一粘接胶圈3021、第二粘接胶圈3031例如均可由粘接剂固化而成。具体连接过程例如可以是，粘接剂首先被涂抹在基板10的第一表面，然后，使得第一支架302和第二支架303将该粘接剂压紧，粘接剂固化后分别形成与第一支架302连接的第一粘接胶圈3021，以及与第二支架303连接的第二粘接胶圈3031。
此外，也可以先将粘接剂涂抹在第一支架302和第二支架303的第一端，然后，该粘接剂随着支架附着在基板10的第一表面，位于第一支架302和第二支架303第一端的粘接剂固化后分别形成第一粘接胶圈3021和第二粘接胶圈3031。
参考图5，在本申请的另一种实现方式中，第一支架302、第二支架303与盖板301分别成型，第一支架302和第二支架303例如包括相对的第一端和第二端，第一支架302的第一端例如可以通过第一粘接胶圈3021与基板10的第一表面连接，第一支架302的第二端例如可以通过第三粘接胶圈3022与盖板301连接。第二支架303的第一端例如可以通过第二粘接胶圈3031与基板10的第一表面连接，且第二支架303的第二端例如可以通过第四粘接胶圈3032与盖板301连接。
其中，第一粘结胶圈和第三粘接胶圈3022用于密封第一空间70，第二粘接胶圈3031和第四粘接胶圈3032用于密封第二空间80。
第一空间70例如为稳定的实心结构，其内部填充有填充材料，用于密封第一空间70的第一粘接胶圈3021和第三粘接胶圈3022例如可以采用完整的环形结构。
第二空间80则为中空结构，为避免第二空间80中的空气随温度变化膨胀和收缩影响封装芯片的性能，用于密封第二空间80的第二粘接胶圈3031和第四粘接胶圈3032上例如开设有开口3017。其中，例如可以仅在第二粘接胶圈3031或第四粘接胶圈3032上设置开口3017，也可以在第二粘接胶圈3031和第四粘接胶圈3032上均设置开口3017，本领域技术人员可根据需要确定开口的数量、大小和位置，本申请对此不做限制。
其中，第一粘接胶圈3021和第二粘接胶圈3031的成型过程参考上述，在此不再赘述。
第三粘接胶圈3022和第四粘接胶圈3032的具体成型过程可以是，该粘接剂首先被涂抹在该第一支架302和该第二支架303的第二端，然后，使得盖板301将该粘接剂压紧，第一支架302上的粘接剂固化后形成第三粘接胶圈3022，第二支架303上的粘接剂固化后形成第四粘接胶圈3032。
此外，粘接剂也可以先涂抹在盖板301上，然后，该粘接剂随着盖板301附着在第一支架302的第二端形成第三粘接胶圈3022，附着在第二支架303的第二端则形成第四粘接胶圈3032。
本申请实施例中的粘接胶圈以长方形环状结构为例，当然在能够实现本发明目的的情况下，粘接胶圈并不局限于长方形环状，也可以为圆环状、椭圆形环状、梯形环状或其他形状。在本申请实施例中，粘接胶圈的形状和大小与支架的形状和大小保持一致。
本申请提供一种用于对如上的任意一种封装芯片进行制作的方法，在该封装芯片如图1所示TIM40的材质为铟，填充材料的材质为硅胶或者聚烯烃树脂的情况下，如图6所示，该方法包括：
S101、如图7a、图7b所示，将芯片固定在基板的第一表面上。
将芯片20固定在基板10的第一表面上，包括：如图7a所示，在芯片20的第一表面上设置焊球50，并通过回流焊的方式将焊球50与基板10的第一表面连接，以及如图7b所示，在焊球50的间隙中注入填充材料60。
S102、如图7c所示，在芯片20背离基板10的表面上放置TIM40，同时，在基板10的第一表面上涂抹粘结剂101。
S103、如图7d所示，将第一支架302和第二支架303的第一端分别与粘结剂连接，第一支架302和第二支架303的第二端连接有盖板301，盖板301与TIM40接触，其中，第一支架302环绕芯片20，第二支架303环绕第一支架302，基板10的第一表面、盖板301和第一支架302共同围设成第一空间70，芯片20容纳于第一空间70。盖板301包括与TIM40相对的第一盖板3012、与第一支架302相对的第二盖板3013、与第二支架303相对的第三盖板3014、位于第一盖板3012和其二盖板301之间的第四盖板3015，以及位于第二盖板3013和第三盖板3014之间的第五盖板3016，第四盖板3015上设有孔3011。
在本申请实施例的另一种实现方式中，也可以先将粘接剂涂抹在第一支架302和第二支架303的第一端，然后，该粘接剂随着支架附着在基板10的第一表面。
S104、如图7d所示，加热以融化TIM40，使得TIM40的第一表面与芯片20的第二表面连接，TIM40的第二表面与盖板301连接。
S105、如图7d所示，固化TIM40，使得芯片20通过固化后的TIM40与盖板301连接，同时固化粘接剂，以形成粘接胶圈。
其中，位于第一支架302第一端的粘接剂固化后形成第一粘接胶圈3021，位于第一支架302的第二端的粘接剂固化后形成第三粘接胶圈3022，位于第二支架303的第一端的粘接剂固化后形成第二粘接胶圈3031，位于第二支架303的第二端的粘接剂固化后形成第四粘接胶圈3032。
第一粘接胶圈3021和第三粘接胶圈3022用于密封第一空间70，第二粘接胶圈 3031和第四粘接胶圈3032用于密封第二空间80。
第一粘接胶圈3021和第三粘接胶圈3022例如为完整的环形结构，第二粘接胶圈3031和第四粘接胶圈3032上则设置有与外部环境相连通的开口。
S106、如图7e所示，通过孔3011注入填充材料，其中，填充材料邻接芯片20和TIM40的侧面，并填充第一空间70。
S107、如图7e所示，固化填充材料。
S108、如图7f所示，在基板10的第二表面上设置焊球。
芯片20完成封装后，例如可以在基板10的第二表面上设置焊球，并通过回流焊的方式将焊球与电路板的第一表面连接。
要说明的是，本申请对上述步骤的先后顺序不做限定，根据制作工艺的不同，可以对上述步骤的先后顺序进行调整。例如，上述步骤S101中在将芯片20固定在基板10第一表面时，如图7b所示，在芯片20的焊球间隙中注入填充材料，可以位于步骤S107之前。此时，用于填充焊球间隙的填充材料与填充第一空间70的填充材料可采用不同材料。
或者，又例如，上述步骤S102可以合并入步骤S107，即同时向第一空间70和芯片20的焊球间隙中注入填充材料，此时，用于填充焊球间隙的填充材料与填充第一空间70的填充材料材质相同。
此外，本申请还提供一种用于对如上的用于对如上的任意一种封装芯片进行制作的方法，在该封装芯片中的TIM和填充材料均为硅胶材质的情况下，如图8所示，该方法包括：
S201、如图9a、图9b所示，将芯片20固定在基板10的第一表面上。
将芯片20固定在基板10的第一表面上，包括：在芯片20的第一表面上设置焊球，并通过回流焊的方式将焊球与基板10的第一表面连接。以及如图9b所示，在芯片20和第一表面和基板10的第一表面的间隙注入填充材料。
S202、如图9c所示，在基板10的第一表面上涂抹粘结剂；
S203、如图9d所示，将第一支架302和第二支架303的第一端分别与粘结剂连接，第一支架302和第二支架303的第二端连接有盖板301。其中，第一支架302环绕芯片20，第二支架303环绕第一支架302，基板10的第一表面、盖板301和第一支架302共同围设成第一空间70，芯片20容纳于第一空间70。盖板301包括与芯片20相对的第一盖板3012、与第一支架302相对的第二盖板3013、与第二支架303相对的第三盖板3014、位于第一盖板3012和其二盖板301之间的第四盖板3015，以及位于第二盖板3013和第三盖板3014之间的第五盖板3016，第一盖板3012或第四盖板3015上设有孔3011。
S204、如图9d所示，固化粘接剂，以形成粘接胶圈。
S205、如图9e所示，通过孔3011注入填充材料，其中，填充材料邻接芯片20和TIM40的侧面，并填充第一空间70。
S206、如图9e所示，固化填充材料。
S207、如图9f所示，在基板10的第二表面上设置焊球。
芯片20完成封装后，例如可以在基板10的第二表面上设置焊球，并通过回流焊 的方式将焊球与电路板的第一表面连接。
其中，在步骤S103和步骤S203中，第一支架302和第二支架303的第二端连接有盖板301，例如包括：第一支架302和第二支架303例如可以和盖板301一体成型，或者第一支架302和第二支架303可以通过粘接胶圈与与盖板301固定连接。
若第一支架302和第二支架303和盖板301一体成型，则可以将第一支架302、第二支架303、基板10作为一个整体，只需要将第一支架302和第二支架303的第一端固定连接与基板10的第一表面固定连接。
若第一支架302和第二支架303通过粘接胶圈与与盖板301固定连接，则如图10所示，所述封装芯片的制作方法还包括如下步骤：
S1031、如图11a所示，将第一支架和第二支架的第一端与粘结剂101连接，盖板与TIM接触，其中，第一支架环绕芯片，第二支架第一支架，基板的第一表面、盖板和第一支架共同围设成第一空间，基板的第一表面、第一支架、第二支架和盖板共同围设成第二空间,第一空间的盖板上设有孔；
S1032、如图11b所示，在第一支架302和第二支架303的第二端涂抹粘接剂101。
S1032、如图11c所示，将盖板301与第一支架302和第二支架303的第二端连接。
其中，在本申请实施例的另一种实现方式中，也可以先将粘接剂涂抹在盖板301上，然后，该粘接剂随着盖板301附着在第一支架302和第二支架303的第二端。
本申请实施例提供的封装芯片的制作方法，与前述实施例提供的芯片20封装结构具有相同的技术效果，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种封装芯片，其特征在于，包括：基板、芯片、和散热器；
    所述散热器包括第一支架、第二支架和盖板，所述第一支架和所述第二支架设置在所述基板上，所述盖板被所述第一支架和所述第二支架支撑于所述基板上；
    所述第一支架为密封的环形支架，所述第一支架和所述盖板围成第一空间，所述芯片被容纳在所述第一空间内，所述芯片和所述盖板之间设置有热界面材料，
    所述盖板上设置有与所述第一空间相通的孔，所述孔和所述第一空间中被充满填充材料；
    所述第二支架位于所述第一空间外部。
  2. 根据权利要求1所述的封装芯片，其特征在于，所述第一支架、所述第二支架与所述盖板一体成型，所述第一支架和所述第二支架分别通过粘接件与所述基板连接。
  3. 根据权利要求1所述的封装芯片，其特征在于，所述第一支架和所述第二支架的第一端分别通过粘接件与所述基板连接，且所述第一支架和所述第二支架的第二端分别通过粘接件与所述盖板连接。
  4. 根据权利要求2或3所述的封装芯片，其特征在于，所述第二支架为环绕所述第一支架和所述芯片设置的环形支架，所述第二支架沿所述基板的周边设置，所述第二支架或所述第二支架与所述基板之间的粘接件上设有开口。
  5. 根据权利要求1-3任一项所述的封装芯片，其特征在于，所述第二支架包括2个或2个以上的支撑件，所述支撑件沿所述基板的周边均匀排布。
  6. 根据权利要求1-5任一项所述的封装芯片，其特征在于，所述热界面材料和所述填充材料的材质均为硅胶，或者所述热界面材料和所述填充材料的材质均为聚烯烃树脂，所述热界面材料和所述填充材料通过注塑的方式一体成型。
  7. 根据权利要求6所述的封装芯片，其特征在于，所述盖板包括与所述芯片相对的第一盖板、与所述第一支架相对的第二盖板和位于所述第一盖板和第二盖板之间的第三盖板，所述孔位于所述第一盖板或所述第三盖板上，所述填充材料经由所述孔注入到所述第一空间中。
  8. 根据权利要求1-5任一项所述的封装芯片，其特征在于，所述热界面材料的材质为铟，所述填充材料的材质为硅胶或聚烯烃树脂，所述填充材料在所述热界面材料成型后，通过注塑的方式成型。
  9. 根据权利要求8所述的封装芯片，其特征在于，所述盖板包括与所述芯片相对的第一盖板、与所述第一支架相对的第二盖板和位于所述第一盖板和第二盖板之间的第三盖板，所述孔位于所述第三盖板上，所述填充材料经由所述孔注入到所述第一空间中。
  10. 一种封装芯片的制作方法，其特征在于，热界面材料的材质为铟，填充材料的材质为硅胶或聚烯烃树脂，所述方法包括：
    将芯片固定在基板的第一表面上；
    在芯片背离所述基板的表面上放置热界面材料，同时，在所述基板的第一表面涂抹粘结剂；
    将第一支架和第二支架的第一端分别与所述粘结剂连接，所述第一支架和所述第 二支架的第二端连接有盖板，所述盖板与所述热界面材料接触，其中，所述第一支架环绕所述芯片，所述第二支架环绕所述第一支架，所述基板的第一表面、所述盖板和所述第一支架共同围设成第一空间，所述第一空间的盖板上设有孔，其中，所述盖板与所述第一支架、第二支架一体成型，或所述盖板通过粘接剂与所述第一支架和所述第二支架连接；
    加热以融化所述热界面材料，使得所述热界面材料密封所述芯片与所述盖板之间的缝隙；
    固化所述热界面材料，使得所述芯片通过固化后的热界面材料与所述盖板连接，同时固化所述粘接剂，以形成粘接胶圈；
    通过所述孔注入填充材料，以填充所述第一空间；
    固化所述填充材料。
  11. 一种封装芯片的制作方法，其特征在于，热界面材料和填充材料的材质均为硅胶，或者所述热界面材料和所述填充材料的材质均为聚烯烃树脂，所述方法包括：
    将芯片固定在基板的第一表面上；
    在所述基板的第一表面涂抹两圈粘结剂；
    将所述第一支架和所述第二支架的第一端分别与所述粘结剂连接，所述第一支架和所述第二支架的第二端连接有盖板，所述盖板与所述热界面材料接触，其中，所述第一支架环绕所述芯片，所述第二支架环绕所述第一支架，所述基板的第一表面、所述盖板和所述第一支架共同围设成第一空间，所述第一空间的盖板上设有孔，其中，所述盖板与所述第一支架、第二支架一体成型，或所述盖板通过粘接剂与所述第一支架和所述第二支架连接；
    固化所述粘接剂，以形成粘接胶圈；
    通过所述孔注入填充材料，以填充所述第一空间；
    固化所述填充材料。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113363219A (zh) * 2021-05-11 2021-09-07 苏州通富超威半导体有限公司 一种bga产品、热压设备及热压工艺
CN113380725A (zh) * 2021-04-29 2021-09-10 苏州通富超威半导体有限公司 芯片封装结构及封装方法
WO2023085607A1 (ko) * 2021-11-09 2023-05-19 삼성전자주식회사 열 전도성 계면 물질을 수용하는 인쇄 회로 기판 구조체를 포함하는 전자 장치

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11350220B2 (en) * 2020-01-17 2022-05-31 Sae Magnetics (H.K.) Ltd. MEMS package, MEMS microphone and method of manufacturing the MEMS package
TWI774357B (zh) * 2021-05-07 2022-08-11 宏齊科技股份有限公司 具有高散熱效能的半導體裝置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587882A (en) * 1995-08-30 1996-12-24 Hewlett-Packard Company Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate
CN101556940A (zh) * 2008-04-08 2009-10-14 力成科技股份有限公司 具有散热片的半导体封装结构
US20150170990A1 (en) * 2013-12-18 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming semiconductor package using carbon nano material in molding compound
CN108511404A (zh) * 2017-02-28 2018-09-07 华为技术有限公司 芯片封装系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8970029B2 (en) * 2009-07-30 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced heat spreader for flip chip packaging
CN102449759B (zh) * 2011-09-30 2013-08-28 华为技术有限公司 一种散热器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587882A (en) * 1995-08-30 1996-12-24 Hewlett-Packard Company Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate
CN101556940A (zh) * 2008-04-08 2009-10-14 力成科技股份有限公司 具有散热片的半导体封装结构
US20150170990A1 (en) * 2013-12-18 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming semiconductor package using carbon nano material in molding compound
CN108511404A (zh) * 2017-02-28 2018-09-07 华为技术有限公司 芯片封装系统

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380725A (zh) * 2021-04-29 2021-09-10 苏州通富超威半导体有限公司 芯片封装结构及封装方法
CN113363219A (zh) * 2021-05-11 2021-09-07 苏州通富超威半导体有限公司 一种bga产品、热压设备及热压工艺
CN113363219B (zh) * 2021-05-11 2024-02-06 苏州通富超威半导体有限公司 一种bga产品、热压设备及热压工艺
WO2023085607A1 (ko) * 2021-11-09 2023-05-19 삼성전자주식회사 열 전도성 계면 물질을 수용하는 인쇄 회로 기판 구조체를 포함하는 전자 장치

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