WO2019141161A1 - 一种晶圆封装器件 - Google Patents

一种晶圆封装器件 Download PDF

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Publication number
WO2019141161A1
WO2019141161A1 PCT/CN2019/071744 CN2019071744W WO2019141161A1 WO 2019141161 A1 WO2019141161 A1 WO 2019141161A1 CN 2019071744 W CN2019071744 W CN 2019071744W WO 2019141161 A1 WO2019141161 A1 WO 2019141161A1
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WIPO (PCT)
Prior art keywords
wafer
substrate
metal
heat
package device
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Application number
PCT/CN2019/071744
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English (en)
French (fr)
Inventor
汤佳杰
葉冠宏
林来存
刘国文
郑帅
张华锋
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19741747.0A priority Critical patent/EP3723121B1/en
Publication of WO2019141161A1 publication Critical patent/WO2019141161A1/zh
Priority to US16/931,819 priority patent/US11430760B2/en

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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Definitions

  • the present invention relates to the field of electronics and communication technologies, and in particular, to a wafer package device.
  • a conventional wafer package device 100 includes an upper substrate 101 and a lower substrate 102 disposed opposite to each other, and a wafer 103 disposed on a surface of the upper substrate 101 facing the lower substrate 102, the upper layer A molding material 104 is filled between the substrate 101 and the lower substrate 102 to increase the support strength of the entire package structure.
  • the upper substrate 101 and the lower substrate 102 are electrically connected by an in-line ball grid array 105.
  • the power of the wafer 103 increases, the amount of heat generated by the wafer 103 during operation is also increased.
  • the internal temperature thereof is too high, which affects the workability and service life of the wafer 103.
  • the embodiment of the present application provides a memory control circuit, which can be used to solve the problem that the object storage device has poor flexibility, low access efficiency, and limited adaptation scenarios.
  • inventions of the present invention provide a wafer package device.
  • the wafer package device includes:
  • the heat conducting layer is disposed between the wafer and the second substrate, and the heat conducting layer is configured to form a heat dissipation path between the wafer and the second substrate;
  • the plastic seal is used to wrap the wafer.
  • the thermally conductive layer is a thermally conductive adhesive.
  • the heat conductive layer includes: a first heat conductive layer and a second heat conductive layer, wherein the first heat conductive layer is disposed on a surface of the wafer facing the second substrate, the second The heat conductive layer is disposed on a surface of the first heat conductive layer facing the second substrate.
  • the first heat conductive layer is a metal layer
  • the second heat conductive layer is a heat conductive paste
  • the first thermally conductive layer is a metal layer and the second thermally conductive layer is a solder paste.
  • the first heat conducting layer is a thermally conductive paste
  • the second heat conducting layer is a plurality of metal pillars, wherein the plurality of metal pillars are distributed in a discrete array.
  • the area of the heat generated by the wafer corresponds to a density of the metal pillar corresponding to a density of the metal pillar corresponding to a region where the heat generated by the wafer is less.
  • the molding is also used to wrap the first thermally conductive layer and a portion of the second thermally conductive layer adjacent the first thermally conductive layer.
  • the thermally conductive layer includes a plurality of metal pillars, wherein the plurality of metal pillars are distributed in a discrete array.
  • the region of the heat generated by the wafer corresponds to a density of the metal pillar corresponding to a density of the metal pillar corresponding to a smaller region of heat generated by the wafer.
  • the first electrically conductive component comprises a plurality of metal balls.
  • the plastic seal is also used to wrap the plurality of metal balls.
  • the first conductive member includes: a plurality of metal balls and a plurality of metal pillars, wherein the metal pillars are disposed on a surface of the wafer facing the first substrate, and the metal balls are disposed at the The metal pillar is adjacent to one end of the first substrate for electrically connecting the metal pillar and the first substrate.
  • the molding is also used to wrap the plurality of metal posts of the first conductive member.
  • the second conductive member is a plurality of metal balls.
  • the second electrically conductive member is a plurality of metal posts.
  • the molding is also used to wrap the portion of the second conductive member adjacent to the first substrate.
  • the second conductive component comprises:
  • first metal balls are disposed on a surface of the first substrate facing the second substrate
  • second metal balls are disposed on a surface of the second substrate facing the first substrate
  • the metal pillar being disposed between the first metal ball and the second metal ball for electrically connecting the first metal ball and the second metal Metal ball.
  • the plastic seal is also used to wrap a portion of the plurality of metal posts of the second conductive member proximate the first substrate.
  • the invention provides a wafer package device, which forms a heat dissipation path between a wafer and a second substrate through a heat conduction layer disposed between the wafer and the second substrate, so that the wafer generates a large amount of heat during normal operation. It can be discharged to the second substrate through the thermal conductive layer to maintain the normal operating temperature of the wafer and improve the service life of the wafer.
  • 3 is another wafer package device according to an embodiment of the present invention.
  • FIG. 5 is a heat distribution diagram of a wafer according to an embodiment of the present invention.
  • FIG. 6 is still another wafer package device according to an embodiment of the present invention.
  • FIG. 7 is still another wafer package device according to an embodiment of the present invention.
  • FIG. 8 is still another wafer package device according to an embodiment of the present invention.
  • FIG. 9 is still another wafer package device according to an embodiment of the present invention.
  • an embodiment of the present invention provides a wafer package device 200, wherein the wafer package device 200 includes a wafer 21, a heat conductive layer 26, a plastic package, and oppositely disposed first substrate 22 and second substrate. twenty three.
  • the wafer 21 is disposed on a surface of the first substrate 22 facing the second substrate 23, and the wafer 21 and the first substrate 22 are electrically connected by a first conductive member 24.
  • the second substrate 23 and the first substrate 22 are electrically connected by the second conductive member 25.
  • the heat conductive layer 26 is disposed between the wafer 21 and the second substrate 23, and the heat conductive layer 26 is used to dissipate heat generated by the wafer 21 through the second substrate 23.
  • the plastic seal is used to wrap the wafer 21.
  • a heat dissipation channel is provided between the wafer 21 and the second substrate 23, and the wafer 21 is lowered in the normal state.
  • the temperature at work is advantageous for extending the service life of the wafer 21 and maintaining the performance of the wafer 21.
  • a plurality of metal heat conductive wires 231 in the vertical direction and a plurality of metal heat conductive wires 232 in the horizontal direction are disposed inside the second substrate 23.
  • the metal heat conductive wire 231 and the metal heat conductive wire 232 may cross each other to form a plurality of heat dissipation paths.
  • a plurality of interconnected heat dissipation channels formed by the plurality of metal heat conductive wires 231 and the plurality of metal heat conductive wires 232 are transmitted to the external environment to avoid the second substrate 23
  • the internal temperature is too high, which affects the heat dissipation.
  • the heat conductive layer 26 may be a thermal conductive adhesive, and the thermal conductive adhesive generally has a high thermal conductivity. The heat generated by the wafer 21 is transferred to the second substrate 23 through the thermal conductive paste.
  • the thermally conductive layer 26 can include a first thermally conductive layer 261 and a side surface of the first thermally conductive layer 261.
  • the first heat conduction layer 261 may be a metal layer made of gold, silver or other metal having good thermal conductivity, and the metal layer can derive the heat generated by the wafer 21 with high efficiency.
  • the second heat conductive layer 262 may be a thermal conductive adhesive or a solder paste having a lower interface thermal resistance to better dissipate heat and form a physical connection between the first heat conductive layer 261 and the second substrate 23.
  • the first heat conductive layer 261 may be a thermal conductive adhesive
  • the second heat conductive layer 262 may be The utility model comprises a plurality of metal columns, wherein the metal column is made of copper or other metal with better thermal conductivity, such as gold or silver.
  • a physical connection between the metal post and the second substrate 23 can be achieved by soldering, and a heat conduction path is established.
  • the plurality of metal pillars in the second thermally conductive layer 262 may be distributed in a discrete array, such as in a rectangular array.
  • the plurality of metal pillars in the second heat conductive layer 262 transfer the heat radiated from the first heat conductive layer 261 to the second substrate 23.
  • the second heat conducting layer 262 is disposed in a discrete array distribution to improve the soldering yield of the plurality of metal pillars and the second substrate 23 in the second heat conducting layer 262, so that the thickness of the second heat conducting layer 262 is more uniform, and the area soldering is better. So that the area heat can be dissipated more quickly.
  • FIG. 5 is a heat distribution diagram of the wafer 21 during normal operation.
  • the edge region 510 generates less heat
  • the central region 520 generates more heat. Therefore, the distribution of the plurality of metal pillars in the second heat conductive layer 262 can be set in accordance with the distribution of heat generated by the chip.
  • the distribution density of the plurality of metal pillars in the corresponding second heat conduction layer 262 is large, and the region where the chip generates less heat (for example, the edge region) 510), the distribution density of the plurality of metal pillars in the corresponding second heat conduction layer 262 is small, thereby facilitating the efficiency of heat dissipation of the wafer 21.
  • the plurality of metal pillars in the second heat conductive layer 262 may be patterned to distribute the first heat conductive layer.
  • the heat dissipated by the 261 is transmitted to the second substrate 23, wherein a region where the heat generated by the wafer is larger corresponds to a density of the metal pillar corresponding to a smaller region of the heat generated by the wafer corresponding to the metal pillar density.
  • the plurality of metal pillars in the second heat conductive layer 262 may be disposed at a position where the plurality of metal pillars are located according to the heat distribution map of the wafer 21 as shown in FIG.
  • the column distribution density is large, and the distribution density of the metal columns away from the central area of the wafer 21 is small.
  • the metal pillar having a large distribution density can transfer the heat generated by the wafer 21 to the second substrate 23 with higher efficiency, so that the heat of the wafer 21 in the heat-concentrated region can be better dissipated.
  • the heat conductive layer 26 may further include a plurality of metal pillars for transferring heat radiated from the wafer 21 to the second substrate. twenty three.
  • the plurality of metal pillars in the heat conducting layer 26 may be distributed in a discrete array, for example, in a rectangular array, to improve the soldering yield of the heat conducting layer 26, avoiding uneven thickness caused by the continuous heat conducting layer, and poor soldering in some areas. The problem is that the area heat can be quickly dissipated.
  • One end of the plurality of metal posts of the heat conductive layer 26 in contact with the second substrate 23 is joined to the second substrate 23 by solder to provide better soldering strength.
  • the plurality of metal pillars in the heat conducting layer 26 may also be patterned to transmit heat radiated from the heat conductive layer 26 to the second substrate 23, wherein the region where the heat generated by the wafer corresponds to the density of the metal pillar is greater than The lesser area of heat generated by the wafer corresponds to the density of the metal pillars.
  • the plurality of metal pillars in the heat conductive layer 26 may be disposed at a position where the plurality of metal pillars are located according to the heat distribution map of the wafer 21 as shown in FIG. 5, wherein the metal pillars are distributed near the central region of the wafer 21. The density is large, and the distribution of the metal pillars away from the central area of the wafer 21 is small.
  • the metal pillar having a large distribution density can transfer the heat generated by the wafer 21 to the second substrate 23 with higher efficiency, so that the heat of the wafer 21 in the heat-concentrated region can be better dissipated.
  • the first substrate 22 and the wafer 21 may be electrically connected by a plurality of first conductive members 24 connected between the wafer 21 and the first substrate 22.
  • a wafer package device 200, in one implementation of the first conductive member 24, the first conductive member 24 can be a plurality of metal balls.
  • the metal balls may be disposed on the surface of the first substrate 22, and may be disposed in such a manner that the plurality of metal balls may be distributed in a discrete array, for example, in a rectangular array, so that the electricity between the wafer 21 and the first substrate 22 is The signal can be turned on better.
  • the metal ball can be a solder ball.
  • the plurality of first conductive members 24 includes a plurality of metal balls 241 and a plurality of metal posts 242.
  • the metal post 242 has one end connected to the wafer 21 and the other end connected to the metal ball 241.
  • the metal ball 241 is connected between the first substrate 22 and the metal post 242.
  • the metal balls 241 and the metal pillars 242 are disposed on the surface of the first substrate 22, and may be disposed in such a manner that the plurality of metal balls 241 and the plurality of metal pillars 242 may be distributed in a discrete array, for example, in a rectangular array, so that The electrical signal between the wafer 21 and the first substrate 22 can be better turned on.
  • the metal ball 241 may be a solder ball.
  • the first substrate 22 and the second substrate 23 are electrically connected by the second conductive member 24.
  • the second conductive member 25 may be a metal ball, such as a solder ball, or other metal solder ball having a high electrical conductivity to pass an electrical signal in the first substrate 22 through the second The conductive member 25 is transferred to the second substrate 23.
  • the second conductive member 25 can be a metal post, such as a copper post, or other metal post having a high electrical conductivity.
  • the second conductive member 25 may be a first metal ball 251, a plurality of metal pillars 252, and a plurality of Two metal balls 253.
  • the first metal ball 251 is disposed on the surface of the first substrate 22 facing the second substrate 23, and the second metal ball 253 is disposed on the surface of the second substrate 23 facing the first substrate 22.
  • One end of the metal pillar 252 and the first metal ball The 251 is connected and the other end is connected to the second metal ball 253.
  • the first metal ball 251, the metal post 252, and the second metal ball 253 form an electrical connection path between the first substrate 22 and the second substrate 23.
  • the first metal ball 251 and the second metal ball 253 may be tin balls.
  • the metal pillar 252 may be made of copper or other metal having good electrical conductivity.
  • the wafer package device 200 may further include a molding member 28 disposed between the first substrate 22 and the second substrate 23.
  • the surface of the wafer 21 facing the second substrate 23 is exposed outside the molding member 28 for connecting with the heat conducting layer 26 to dissipate the heat of the wafer 21; the portion of the second conductive member 25 close to the second substrate is exposed. Outside the plastic seal 28.
  • a wafer package device 200 as shown in FIG. 9 in another implementation of the mold package 28 , the mold package 28 can also be used to wrap the wafer 21 , the first conductive member 24 , and the second conductive member 25 .
  • the portion of the second conductive member 25 adjacent to the second substrate 23 is exposed outside the molding member 28; the portion of the second heat conducting layer 262 adjacent to the second substrate 23 is exposed outside the molding member 28.
  • the molding member 28 can also be used to wrap the wafer 21, the metal post 242 of the first conductive member 24, and the A metal post 252 of the two conductive members 25.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种晶圆封装器件，所述晶圆封装器件包括晶圆，以及相对设置的第一基板和第二基板，其中所述晶圆设置于所述第一基板朝向所述第二基板的表面；所述晶圆和所述第一基板通过第一导电部件形成电气连接；所述第一基板和所述第二基板通过第二导电部件形成电气连接；所述晶圆和所述第二基板通过导热层形成散热通路。所述晶圆封装器件还包括塑封件，用于包裹所述晶圆。设置于晶圆和第二基板之间的导热层能够将晶圆产生的大量热量快速散出至第二基板，使晶圆维持正常温度。

Description

一种晶圆封装器件 技术领域
本发明涉及电子及通信技术领域，尤其涉及一种晶圆封装器件。
背景技术
如图1所示，一种现有的晶圆封装器件100包括相对设置的上层基板101和下层基板102，以及设置在上层基板101朝向所述下层基板102的表面的晶圆103，所述上层基板101和所述下层基板102之间填充有塑封材料104，以增加整个封装结构的支撑强度。所述上层基板101和下层基板102之间通过内嵌式球栅阵列105形成电气连接。随着晶圆103的功率的增加，晶圆103在运行过程中产生的热量也越来越多。当晶圆103产生的热量累积而不能快速散出，其内部的温度会过高，影响晶圆103的工作性能和使用寿命。
发明内容
本申请的实施例提供了一种存储器控制电路，可以用于解决对象存储设备的灵活性较差、访问效率低和适应场景有限的问题。
本发明的目的在于提供一种具有较高散热效率的晶圆封装器件，以实现将晶圆产生的热量通过导热层以较高效率散出。
第一方面，本发明的实施例提供一种晶圆封装器件。所述晶圆封装器件包括：
晶圆，塑封件，导热层，以及相对设置的第一基板和第二基板，其中所述晶圆设置于所述第一基板朝向所述第二基板的表面；所述晶圆与所述第一基板之间通过第一导电部件电气连接，所述第二基板与所述第一基板之间通过第二导电部件电气连接；
所述导热层设置于所述晶圆和所述第二基板之间，所述导热层用于形成所述晶圆和所述第二基板之间的散热通路；
所述塑封件，用于包裹所述晶圆。
在一个可能的设计中，所述导热层为导热胶。
在一个可能的设计中，所述导热层包括：第一导热层和第二导热层，其中，所述第一导热层设置于所述晶圆朝向所述第二基板的表面，所述第二导热层设置于所述第一导热层朝向所述第二基板的表面。
在一个可能的设计中，所述第一导热层为金属层，所述第二导热层为导热胶。
在一个可能的设计中，所述第一导热层为金属层，所述第二导热层为锡膏。
在一个可能的设计中，所述第一导热层为导热胶，所述第二导热层为多个金属柱，其中所述多个金属柱呈离散的阵列分布。
在一个可能的设计中，所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量较少的区域对应的所述金属柱的密度。
在一个可能的设计中，所述塑封件还用于包裹所述第一导热层以及所述第二导热 层的靠近所述第一导热层的部分。
在一个可能的设计中，所述导热层包括多个金属柱，其中所述多个金属柱呈离散的阵列分布。
在一个可能的设计中，所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。
在一个可能的设计中，所述第一导电部件包括多个金属球。
在一个可能的设计中，所述塑封件还用于包裹所述多个金属球。
在一个可能的设计中，所述第一导电部件包括：多个金属球和多个金属柱，其中所述金属柱设置于所述晶圆朝向第一基板的表面，所述金属球设置于所述金属柱靠近所述第一基板的一端，用于电气连接所述金属柱和所述第一基板。
在一个可能的设计中，所述塑封件还用于包裹所述第一导电部件的所述多个金属柱。
在一个可能的设计中，所述第二导电部件为多个金属球。
在一个可能的设计中，所述第二导电部件为多个金属柱。
在一个可能的设计中，所述塑封件还用于包裹所述第二导电部件靠近第一基板的部分。
在一个可能的设计中，所述第二导电部件包括：
多个第一金属球、多个金属柱和多个第二金属球，其中所述第一金属球设置于所述第一基板朝向所述第二基板的表面，所述第二金属球设置于所述第二基板的朝向所述第一基板的表面，所述金属柱设置于所述第一金属球和第二金属球之间，用于电气连接第一所述第一金属球和第二金属球。
在一个可能的设计中，所述塑封件还用于包裹所述第二导电部件的所述多个金属柱的靠近所述第一基板的部分。
本发明提供的一种晶圆封装器件，通过设置于晶圆和第二基板之间的导热层，形成晶圆和第二基板之间的散热通路，使晶圆在正常工作时产生的大量热量能够通过导热层散出至第二基板，维持晶圆正常的工作温度，提高晶圆的使用寿命。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为现有技术中的一种晶圆封装器件；
图2为本发明实施例提供的一种晶圆封装器件；
图3为本发明实施例提供的另一种晶圆封装器件；
图4为本发明实施例提供的又一种晶圆封装器件；
图5为本发明实施例提供的一种晶圆的热量分布图；
图6为本发明实施例提供的再一种晶圆封装器件；
图7为本发明实施例提供的再一种晶圆封装器件；
图8为本发明实施例提供的再一种晶圆封装器件；
图9为本发明实施例提供的再一种晶圆封装器件；
附图标记说明：21-晶圆，22-第一基板，23-第二基板，24-第一导电部件，25-第二导电部件，26-导热层。
具体实施方式
如图2所示，本发明的实施例提供一种晶圆封装器件200，其中晶圆封装器件200包括：晶圆21，导热层26，塑封件以及相对设置的第一基板22和第二基板23。晶圆21设置在第一基板22的朝向第二基板23的表面，晶圆21与第一基板22之间通过第一导电部件24电气连接。第二基板23与第一基板22之间通过第二导电部件25电气连接。晶圆21与第二基板23之间设置所述导热层26，导热层26用于将晶圆21产生的热量通过第二基板23散出。所述塑封件用于包裹所述晶圆21。
在本发明的上述实施例中，通过在晶圆21与第二基板23之间设置导热层26，从而在晶圆21与第二基板23之间提供了一条散热通道，降低晶圆21在正常工作时的温度，有利于延长晶圆21的使用寿命，保持晶圆21的工作性能。
此外，第二基板23内部设置有多个垂直方向的金属导热线231和多个水平方向的金属导热线232。金属导热线231和金属导热线232可以相互交叉，以形成多条散热通路。晶圆21产生的热量通过导热层26传输至第二基板23时，通过多个金属导热线231和多个金属导热线232形成的多个互通的散热通道传输至外部环境，避免第二基板23内部的温度过高，影响热量散出。
具体来讲，导热层26可以为导热胶，导热胶一般具有较高的热导率。晶圆21产生的热量通过导热胶传输至第二基板23。
如图3所示的一种晶圆封装器件200，在导热层26的另一种实现方式中，导热层26可以包括第一导热层261，以及覆盖于第一导热层261的一侧表面的第二导热层262。第一导热层261可以为金属层，材质为具有较好导热性能的金、银或其他金属，金属层能够将晶圆21产生的热量以较高的效率导出。第二导热层262可以为导热胶，或界面热阻更低的锡膏，以起到更好的散热作用，并形成第一导热层261和第二基板23之间的物理连接。
如图4所示的一种晶圆封装器件400，在第一导热层261和第二导热层262的另一种实现方式中，第一导热层261可以为导热胶，第二导热层262可以包括多个金属柱，其中金属柱的材质可以为铜，或其他导热性能较好的金属，如金或银。金属柱与第二基板23之间可以通过焊接的方式实现物理连接，并建立导热路径。
第二导热层262中的多个金属柱可以呈离散的阵列分布，例如呈矩形的阵列分布。第二导热层262中的多个金属柱将第一导热层261散出的热量传输至第二基板23。将第二导热层262设置成离散的阵列分布可以提高第二导热层262中的多个金属柱与第二基板23的焊接良率，使第二导热层262的厚度更加均匀，区域焊接更加良好，从而使区域热量能更快速地散出。
晶圆21在正常工作时，不同区域产生的热量并非均匀分布。如图5所示的是晶圆21在正常工作时产生的热量分布图，在长度相等的时间段内，边缘区域510产生较少的热量，而中心区域520则产生较多的热量。因此，第二导热层262中的多个金属柱的分布情况可以按照芯片产生的热量的分布来设置。例如：在芯片产生热量较多的区 域(例如:中心区域520)，对应的第二导热层262中的多个金属柱的分布密度较大，在芯片产生热量较少的区域(例如:边缘区域510)，对应的第二导热层262中的多个金属柱的分布密度较小，从而，更有利于提高晶圆21的热量散出的效率。
如图6所示的一种晶圆封装器件200，在第二导热层262的另外一种实现方式中，第二导热层262中的多个金属柱可以呈图形化分布，将第一导热层261散出的热量传输至第二基板23，其中晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。具体来说，第二导热层262中的多个金属柱可以按照如图5所示的晶圆21的热量分布图来设置多个金属柱所在的位置，其中，靠近晶圆21中心区域的金属柱分布密度较大，远离晶圆21中心区域的金属柱分布密度较小。分布密度较大的金属柱可以将晶圆21产生的热量以更高的效率传递至第二基板23，使晶圆21在发热集中区域的热量能够更好散出。
如图7所示的一种晶圆封装器件200，在导热层26的另外一种实现方式中，导热层26还可以包括多个金属柱，将晶圆21散出的热量传输至第二基板23。其中，导热层26中的多个金属柱可以呈离散的阵列分布，例如呈矩形的阵列分布，以提高导热层26的焊接良率，避免了连续导热层产生的厚度不均匀、部分区域焊接不良的问题，使区域热量能够快速地散出。导热层26的多个金属柱与第二基板23接触的一端通过焊锡与第二基板23连接，以提供更好的焊接强度。导热层26中的多个金属柱还可以呈图形化分布，将导热层26散出的热量传输至第二基板23，其中晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。具体来说，导热层26中的多个金属柱可以按照如图5所示的晶圆21的热量分布图来设置多个金属柱所在的位置，其中，靠近晶圆21中心区域的金属柱分布密度较大，远离晶圆21中心区域的金属柱分布密度较小。分布密度较大的金属柱可以将晶圆21产生的热量以更高的效率传递至第二基板23，使晶圆21在发热集中区域的热量能够更好散出。在晶圆封装器件200的实施例中，第一基板22与晶圆21可以通过连接在晶圆21与第一基板22之间的多个第一导电部件24实现电气连接。如图8所示的一种晶圆封装器件200，在第一导电部件24的一种实现方式中，第一导电部件24可以为多个金属球。金属球可以设置于第一基板22表面，具体设置的方式可以为：多个金属球可以呈离散的阵列分布，例如呈矩形的阵列分布，以使得晶圆21和第一基板22之间的电信号能够更好地导通。金属球可以为锡球。
如图8所示的一种晶圆封装器件200，在第一导电部件的另外一种实现方式中，多个第一导电部件24包括多个金属球241和多个金属柱242。其中，金属柱242的一端与晶圆21连接，另一端与金属球241连接；金属球241连接在第一基板22与金属柱242之间。金属球241与金属柱242均设置于第一基板22表面，具体设置的方式可以为：多个金属球241和多个金属柱242可以呈离散的阵列分布，例如呈矩形的阵列分布，以使得晶圆21和第一基板22之间的电信号能够更好地导通。金属球241可以为锡球。
在晶圆封装器件200的实施例中，具体来讲，第一基板22与第二基板23通过第二导电部件24实现电气连接。在第二导电部件的一种实现方式中，第二导电部件25可以为金属球，例如锡球，或其他具有高电导率的金属焊球，以将第一基板22中的电 信号通过第二导电部件25传递至第二基板23。在第二导电部件25的另外一种实现方式中，第二导电部件25可以为金属柱，例如铜柱，或其他具有高电导率的金属柱。
如图8所示的一种晶圆封装器件200，在第二导电部件25的另外一种实现方式中，第二导电部件25可以为第一金属球251、多个金属柱252和多个第二金属球253。其中，第一金属球251设置于第一基板22朝向第二基板23的表面，第二金属球253设置于第二基板23朝向第一基板22的表面，金属柱252的一端与第一金属球251连接，另一端与第二金属球253连接。第一金属球251、金属柱252和第二金属球253形成第一基板22和第二基板23之间的电气连接通路。第一金属球251和第二金属球253可以为锡球。金属柱252的材质可以为铜，或者其他导电性能较好的金属。
在本发明的上述实施例中，具体来讲，晶圆封装器件200还可以包括塑封件28，塑封件28设置于第一基板22和第二基板23之间。
具体来讲，如图3所示的一种晶圆封装器件300，其中塑封件28可以用于包裹晶圆21、第一导电部件24、以及第二导电部件25的靠近第一基板22的部分。其中，晶圆21朝向第二基板23的表面裸露于塑封件28之外，用于和导热层26连接以将晶圆21的热量散出；第二导电部件25的靠近第二基板的部分裸露于塑封件28之外。
如图9所示的一种晶圆封装器件200，在塑封件28的另外一种实现方式中，塑封件28还可以用于包裹晶圆21、第一导电部件24、第二导电部件25的靠近第一基板22的部分、第一导热层261、以及第二导热层262的靠近晶圆21的部分。其中，第二导电部件25的靠近第二基板23的部分裸露于塑封件28之外；第二导热层262的靠近第二基板23的部分裸露于塑封件28之外。
如图8所示的一种晶圆封装器件200，在塑封件28的另外一种实现方式中，塑封件28还可以用于包裹晶圆21、第一导电部件24的金属柱242、以及第二导电部件25的金属柱252。
以上的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步的详细说明。此外，以上仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (16)

  1. 一种晶圆封装器件，其特征在于，包括：
    晶圆，塑封件，导热层，以及相对设置的第一基板和第二基板，其中所述晶圆设置于所述第一基板朝向所述第二基板的表面；所述晶圆与所述第一基板之间通过第一导电部件电气连接，所述第二基板与所述第一基板之间通过第二导电部件电气连接；
    所述导热层设置于所述晶圆和所述第二基板之间，所述导热层用于形成所述晶圆和所述第二基板之间的散热通路；
    所述塑封件，用于包裹所述晶圆。
  2. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述导热层为导热胶。
  3. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述导热层包括：
    第一导热层和第二导热层，其中，所述第一导热层设置于所述晶圆朝向所述第二基板的表面，所述第二导热层设置于所述第一导热层朝向所述第二基板的表面。
  4. 如权利要求3所述的一种晶圆封装器件，其特征在于，所述第一导热层为金属层，所述第二导热层为导热胶。
  5. 如权利要求3所述的一种晶圆封装器件，其特征在于，所述第一导热层为金属层，所述第二导热层为锡膏。
  6. 如权利要求3所述的一种晶圆封装器件，其特征在于，所述第一导热层为导热胶，所述第二导热层为多个金属柱，其中所述多个金属柱呈离散的阵列分布。
  7. 如权利要求6所述的一种晶圆封装器件，其特征在于，所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。
  8. 如权利要求3至7任意一项所述的一种晶圆封装器件，其特征在于，所述塑封件还用于包裹所述第一导热层以及所述第二导热层的靠近所述第一导热层的部分。
  9. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述导热层包括多个金属柱，其中所述多个金属柱呈离散的阵列分布。
  10. 如权利要求9所述的一种晶圆封装器件，其特征在于，所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。
  11. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述第一导电部件包括：
    多个金属球和多个金属柱，其中所述金属柱设置于所述晶圆朝向第一基板的表面，所述金属球设置于所述金属柱靠近所述第一基板的一端，用于电气连接所述金属柱和所述第一基板。
  12. 如权利要求11所述的一种晶圆封装器件，其特征在于，所述塑封件还用于包裹所述第一导电部件的所述多个金属柱。
  13. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述第二导电部件为多个金属柱。
  14. 如权利要求13所述的一种晶圆封装器件，其特征在于，所述塑封件还用于包裹所述第二导电部件靠近第一基板的部分。
  15. 如权利要求1所述的一种晶圆封装器件，其特征在于，所述第二导电部件包括：
    多个第一金属球、多个金属柱和多个第二金属球，其中所述第一金属球设置于所述第一基板朝向所述第二基板的表面，所述第二金属球设置于所述第二基板的朝向所述第一基板的表面，所述金属柱设置于所述第一金属球和第二金属球之间，用于电气连接第一所述第一金属球和第二金属球。
  16. 如权利要求15所述的一种晶圆封装器件，其特征在于，所述塑封件还用于包裹所述第二导电部件的所述多个金属柱的靠近所述第一基板的部分。
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