WO2020195694A1 - Circuit amplificateur - Google Patents

Circuit amplificateur Download PDF

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Publication number
WO2020195694A1
WO2020195694A1 PCT/JP2020/009594 JP2020009594W WO2020195694A1 WO 2020195694 A1 WO2020195694 A1 WO 2020195694A1 JP 2020009594 W JP2020009594 W JP 2020009594W WO 2020195694 A1 WO2020195694 A1 WO 2020195694A1
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Prior art keywords
transistor
input
amplifier circuit
inverter circuit
terminal
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PCT/JP2020/009594
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English (en)
Japanese (ja)
Inventor
知玄 木村
武史 陶山
弥生 芝藤
毅 関谷
隆文 植村
Original Assignee
株式会社Ｓｃｒｅｅｎホールディングス
国立大学法人大阪大学
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Priority to JP2021508932A priority Critical patent/JP7148102B2/ja
Publication of WO2020195694A1 publication Critical patent/WO2020195694A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Definitions

  • the present invention relates to an amplifier circuit configured by using a transistor, and is applicable to an amplifier circuit using a thin film transistor such as an organic transistor.
  • CMOS Complementary Metal Oxide Semiconductor
  • Patent Document 1 describes a circuit that performs the same function as a CMOS inverter by using only a P-type thin film transistor. Such a circuit is called a "pseudo-CMOS inverter". Further, for example, Patent Document 2 proposes to use the circuit as an amplifier circuit by connecting a feedback resistor between the input and output of the pseudo CMOS inverter circuit.
  • the present invention has been made in view of the above problems, and in an amplifier circuit using a pseudo-CMOS inverter circuit and having an input capacitor, it does not complicate the manufacturing process, and has excellent frequency characteristics and a short start-up time.
  • the purpose is to provide technologies that can be compatible with each other.
  • One aspect of the present invention is an amplifier circuit that amplifies a signal input to an input terminal and outputs it from an output terminal, and in order to achieve the above object, an output in which an input signal input to the input unit is inverted.
  • a capacitor connected between the input terminal and the input unit of the inverter circuit, and between the input unit and the output unit of the inverter circuit. It is provided with a feedback element connected to.
  • a plurality of transistors having the same conduction type of the semiconductor channels constitute a pseudo CMOS inverter, and the feedback element has the same conduction type as the transistor constituting the pseudo CMOS inverter.
  • the feedback element connected between the input and output of the pseudo CMOS inverter is composed of the same conduction type transistor as the transistor constituting the pseudo CMOS inverter. Therefore, the process for forming the transistor to be the feedback element can be incorporated in the process for manufacturing the transistor constituting the pseudo CMOS inverter. More specifically, when forming a transistor constituting a pseudo CMOS inverter, a transistor serving as a feedback element can also be formed. Therefore, as compared with the case of forming a simple inverter circuit, the manufacturing process is basically the same except for the number of transistors to be formed, and it is not necessary to provide a new process.
  • the transistor serving as the feedback element constitutes a two-terminal element in which the drain electrode and the gate electrode are connected.
  • a forward current flows from the output side to the input side of the inverter circuit. That is, the feedback element functions as a diode.
  • the potential of the output unit of the pseudo CMOS inverter circuit becomes a high potential (ideally, the power supply potential). Therefore, immediately after the power is turned on, a relatively large forward voltage is applied to the diode which is the feedback element, and a current flows from the output unit to the input unit of the inverter circuit via the diode in the low resistance state.
  • the potential of the input unit rises, while the potential of the output unit where the inverting voltage is output decreases.
  • the circuit is in a steady state when both potentials are in equilibrium. At this time, the voltage between the terminals of the feedback element is small, and the feedback element is in a high resistance state.
  • the feedback element since the feedback element has a low resistance immediately after the power is turned on, the time constant determined by the combination with the input capacitor is relatively small. Therefore, the potential difference between the input and output of the inverter circuit converges in a short time and reaches a steady state. That is, the startup time is short.
  • the steady state since the feedback element has a high resistance, the time constant is large, and the frequency characteristic (more specifically, the amplification degree in the low frequency region) is improved. Therefore, in this amplifier circuit, it is possible to achieve both excellent frequency characteristics and a short start-up time.
  • the manufacturing process is not complicated by forming the feedback element. Further, since the feedback element has a low resistance immediately after the power is turned on, the start-up time is short, but the resistance is high in the steady state, so that the decrease in amplification degree in the low frequency range can be suppressed. That is, in the present invention, it is possible to achieve both excellent frequency characteristics and a short start-up time without complicating the manufacturing process.
  • One embodiment of the present invention is an amplifier circuit using a so-called pseudo CMOS inverter.
  • the pseudo-CMOS inverter is an inverter circuit that imitates the circuit configuration and function of a CMOS (Complementary Metal Oxide Semiconductor) inverter by combining transistors having the same conduction type.
  • CMOS Complementary Metal Oxide Semiconductor
  • the circuit configuration of a CMOS inverter and an amplifier circuit using a CMOS inverter and its operating principle are known. Therefore, the description is omitted here, and the pseudo CMOS inverter circuit will be described first.
  • FIG. 1A and 1B are diagrams showing a configuration example of a pseudo CMOS inverter. More specifically, FIG. 1A is a diagram showing an example of a circuit configuration of a pseudo CMOS inverter, and FIG. 1B is a diagram showing an example of its operating characteristics.
  • the pseudo CMOS inverter 100 includes four transistors 101 to 104. All of these transistors 101 to 104 are depletion type transistors having a P type conduction type. For example, all the transistors 101 to 104 may have the same structure. Therefore, it is possible to simultaneously form these transistors 101 to 104 in the same manufacturing process. In the following description, the "pseudo-CMOS inverter" may be simply referred to as an "inverter".
  • the gate (G) terminal of the first transistor 101 is connected to the input terminal Vi'. Further, the source (S) terminal is connected to a power source (not shown), and an appropriate positive potential power supply voltage Vdd is applied.
  • the drain D terminal is connected to the source terminal of the second transistor 102.
  • the gate terminal of the second transistor 102 is connected to the source terminal, and the power supply voltage Vs1 is applied to the drain terminal.
  • the power supply voltage Vs1 is lower than the potential of the power supply voltage Vdd, and can be, for example, a ground potential or an appropriate negative potential.
  • the gate terminal of the third transistor 103 is connected to the gate terminal of the first transistor 101. That is, the gate terminal of the first transistor 101 and the gate terminal of the third transistor 103 are connected to the input terminal Vi'in parallel with each other.
  • a power supply voltage Vdd is applied to the source terminal of the third transistor 103.
  • the drain terminal of the third transistor 103 is connected to the source terminal of the fourth transistor 104, and further connected to the output terminal Vo'.
  • the gate terminal of the fourth transistor 104 is connected to the drain terminal of the first transistor 101, the source terminal of the second transistor 102, and the gate terminal.
  • a power supply voltage Vs2 is applied to the drain terminal of the fourth transistor 104.
  • the power supply voltage Vs2 can be shared with, for example, the power supply voltage Vs1.
  • Vs1 and Vs2 it is possible to modulate the operating characteristics by making these power supply voltages Vs1 and Vs2 different.
  • the case where the power supply voltages Vs1 and Vs2 have the same potential, for example, both have the ground potential will be considered.
  • the pseudo CMOS inverter 100 configured in this way outputs the L level to the output terminal Vo'when an H level signal is input to the input terminal Vi', while the L level signal is input to the input terminal Vi'. At that time, it functions as an inverting circuit that outputs the H level to the output terminal Vo'.
  • both the input terminal and the input voltage applied to the input terminal are represented by reference numerals Vi'.
  • both the output terminal and the output voltage appearing therein are represented by the reference numerals Vo'.
  • the output voltage Vo' is a value close to the power supply voltage Vdd.
  • the output voltage Vo'almost becomes the power supply voltage Vs2.
  • Vs2 0, the output voltage Vo'is almost the ground potential.
  • the output voltage Vo' fluctuates greatly at a voltage Vn intermediate between the ground potential and the power supply voltage Vdd.
  • the output voltage Vo ′ fluctuates greatly with respect to a slight change in the input voltage Vi ′.
  • the inverter circuit can be used as an inverting amplifier circuit.
  • FIG. 2 is a diagram showing an example in which an inverter circuit is used as an amplifier circuit. More specifically, FIG. 2A shows a circuit configuration example of the amplifier circuit 50, and FIG. 2B is a diagram showing the frequency characteristics of the voltage gain thereof. Further, FIG. 2C is a diagram for explaining the start-up time of the amplifier circuit 50.
  • the pseudo CMOS inverter 100 is operated as an inverting amplifier circuit by connecting a resistor R as a feedback element between the input terminal Vi'and the output terminal Vo' of the pseudo CMOS inverter 100 described above. be able to.
  • both terminals Due to the voltage feedback from the output terminal Vo'to the input terminal Vi', both terminals have the same potential in the no-signal state. More specifically, when both the input voltage Vi'and the output voltage Vo'are the voltage Vn, the equilibrium state is reached. Therefore, since a DC potential appears at the input terminal Vi', an input capacitor C for cutting DC is provided between the input terminal Vi of the amplifier circuit 50 and the input terminal Vi'of the inverter 10.
  • the input terminal of the amplifier circuit 50 and the input voltage applied to the amplifier circuit 50 are both represented by reference numerals Vi.
  • both the output terminal and the output voltage appearing therein are represented by the symbol Vo.
  • the output terminal Vo of the amplifier circuit 50 is electrically the same as the output terminal Vo'of the inverter 100.
  • the potential of the input terminal Vi'of the inverter 100 shows a change according to the signal centering on the voltage Vn.
  • the output voltage Vo'of the inverter 100 changes significantly in response to this, so that the amplified signal appears at the output terminal Vo of the amplifier circuit 50.
  • the amplifier circuit 50 functions as an inverting amplifier circuit.
  • the input capacitor C limits the transmission of low frequency signals. Therefore, in the actual amplifier circuit 50, as shown by the solid line in FIG. 2B, the voltage gain decreases at a frequency lower than the frequency determined by the time constant of the input capacitor C and the resistor R.
  • the time constant may be increased, that is, the resistance value of the resistor R and the capacitance of the input capacitor C may be increased.
  • the time constant formed by the input capacitor C and the resistor R is large.
  • the time constant is large, there is a problem that the start-up time until the amplifier circuit 50 reaches the steady state after the power is turned on becomes long. That is, with respect to the time constants of the input capacitor C and the resistor R, there is a trade-off relationship between the low-frequency voltage gain and the start-up time.
  • the amplifier circuit of the present embodiment described below can solve this problem, suppress a decrease in gain in a low frequency range, and suppress an increase in start-up time.
  • FIG. 3A to 3C are diagrams showing the configuration of the amplifier circuit of this embodiment. More specifically, FIG. 3A shows a circuit configuration of an amplifier circuit 10 in this embodiment, and FIG. 3B is a diagram showing an example of operating characteristics of a transistor 111 used as a feedback element. Further, FIG. 3C is a diagram showing an example of changes in the input voltage and the output voltage in the amplifier circuit 10.
  • a transistor 111 is used as a feedback element connected between the input / output terminals of the inverter 100.
  • the transistor 111 has the same conduction type as the transistors 101 to 104 constituting the inverter 100.
  • a depletion type transistor whose conduction type is P type is used.
  • the source (S) terminal is connected to the output terminal Vo'of the inverter 100, and the drain D terminal is connected to the input terminal Vi'of the inverter 100. Therefore, in the transistor 111 having the P-type channel, the forward current of the channel flows from the output terminal Vo'of the inverter 100 toward the input terminal Vi'. Further, the gate (G) terminal is connected to the drain terminal, and the transistor 111 functions as a two-terminal element, specifically, a diode.
  • the source-drain voltage Vsd which is the source potential when the drain potential of the transistor 111 is used as a reference, the drain current Id flowing from the source terminal to the drain terminal, and the transistor when viewed as a two-terminal element.
  • the drain current Id of the transistor 111 which operates as a diode by short-circuiting between the gate and drain hardly flows when the source-drain voltage Vsd is smaller than the threshold voltage Vth peculiar to the transistor. (Cut-off state).
  • a drain current Id having a magnitude corresponding to the magnitude of the source-drain voltage Vsd flows (on state).
  • the threshold voltage Vth in the general definition is expressed as a gate potential with reference to the source potential.
  • the above-mentioned source-drain voltage Vsd is defined as a source potential with reference to the drain potential in order to make it a positive value. Therefore, the positive and negative are opposite to those when the source potential is used as a reference. From this, it is assumed that the threshold voltage Vth in comparison with the source-drain voltage Vsd referred to here is expressed by an absolute value.
  • the resistance Rsd of the transistor 111 shows a large value when the source-drain voltage Vsd is smaller than the threshold voltage Vth.
  • the output voltage Vo'of the inverter 100 is almost the power supply voltage Vdd and the input voltage Vi'is almost 0 immediately after the power is turned on. From this state, the output voltage Vo'gradually decreases, while the input voltage Vi' gradually increases, and finally both voltages converge to the voltage Vn and the circuit reaches a steady state.
  • the time required for this depends on the time constant determined by the resistance value of the feedback element and the capacitance of the input capacitor.
  • the difference between the output voltage Vo'and the input voltage Vi' of the inverter 100, that is, the source-drain voltage Vsd of the transistor 111 is large, so that the transistor 111 is low. It is in a resistance state. For example, if the source-drain voltage Vsd at time T1 shown in FIG. 3C is sufficiently larger than the threshold voltage Vth of the transistor 111, the resistance Rsd is small as shown in the lower part of FIG. 3B.
  • the time constant determined by the resistance Rsd and the capacitance of the input capacitor C is small, and as shown by the solid line in FIG. 3C, the voltage difference between the input and output rapidly decreases. That is, the start-up time until the circuit converges to the steady state is shorter than the case where the feedback element having a large resistance value shown by the dotted line in FIG. 3C is used.
  • the source-drain voltage Vsd of the transistor 111 becomes sufficiently small, and at this time, as shown in the lower part of FIG. 3C.
  • the resistance Rsd has a large value.
  • the time constant formed by the resistor Rsd and the input capacitor C becomes large, so that the decrease in gain in the low frequency region can be suppressed.
  • the transistor 111 In order to obtain the effect of shortening the start-up time by putting the feedback element in a low resistance state, the transistor 111 needs to be turned on immediately after the power is turned on. Therefore, it is necessary that at least the threshold voltage Vth of the transistor 111 is a magnitude between the ground potential and the power supply voltage Vdd. Then, from the viewpoint of further shortening the start-up time, it is desirable that the state in which the resistance Rsd is small continues for as long as possible. Therefore, it is desirable that the threshold voltage Vth of the transistor 111 is as small as possible.
  • the allowable input voltage as an amplifier circuit becomes small. This is because when the amplitude of the input voltage Vi to the amplifier circuit 10 increases and the output voltage Vo increases accordingly, the voltage applied to both ends of the transistor 111, which is a feedback element (that is, the source-drain voltage Vsd) also increases. This is because when the voltage exceeds the threshold voltage Vth, the transistor 111 becomes in a low resistance state and the gain decreases. From this point of view, it is desirable that the threshold voltage Vth (accurately, its absolute value) of the transistor 111 is a large value as close as possible to the power supply voltage Vdd.
  • the threshold voltage Vth of the transistor 111 serving as a feedback element be appropriate. ..
  • the threshold voltage Vth can be set to about half of the power supply voltage Vdd.
  • the amplifier circuit 10 of this embodiment shortens the start-up time until the steady state is reached after the power is turned on, and suppresses the decrease in gain in the low frequency region after the start-up to obtain excellent frequency characteristics. It is something that can be done.
  • the transistors 101 to 104 constituting the pseudo CMOS inverter 100 and the transistors 111 functioning as feedback elements can be formed as the same conduction type transistors. Therefore, it is also excellent in terms of manufacturing process. Specifically, the process of forming the transistor 111 to be the feedback element can be incorporated into the process of forming the transistors 101 to 104 constituting the pseudo CMOS inverter 100, and the number of steps is increased by adding the feedback element. Absent.
  • FIG. 4A and 4B are diagrams showing a layout example of the amplifier circuit of this embodiment. More specifically, FIG. 4A shows an example of a circuit layout when the amplifier circuit 10 shown in FIG. 3A is composed of a thin film transistor. Further, FIG. 4B is a diagram illustrating a cross-sectional structure of a transistor which is a component of a circuit. In FIG. 4A, the shaded structure represents the organic semiconductor thin film SC that functions as a channel CH. As the material of the semiconductor thin film which is the main part of the thin film transistor, various materials known as semiconductor materials can be used.
  • the transistors 101 to 104 constituting the inverter 100 and the transistors 111 serving as feedback elements can basically have the same structure. Therefore, each transistor can be manufactured by the same manufacturing process.
  • reference numerals Tr are typically attached in order to handle the transistors 101 to 104 and 111 in a unified manner.
  • the transistor Tr is basically a drain electrode Ed and a source electrode Es formed on the substrate SB, an organic semiconductor thin film SC connecting them, an insulating film IG covering the surface of the organic semiconductor thin film SC, and insulation. It has a structure in which gate electrodes Eg facing the organic semiconductor thin film SC are sequentially laminated via a film IG.
  • Each of these functional layers can be formed by an appropriate film forming method according to each material, such as coating, vacuum deposition, chemical vapor deposition, photolithography, printing, and plating.
  • the drain electrode and the source electrode are structurally the same and can be exchanged with each other.
  • the transistors configured in this way are connected to each other with an appropriate wiring pattern PT as shown in FIG. 4A. This makes it possible to form the amplifier circuit 10 shown in FIG. 3A.
  • the input capacitor C can be configured by two electrodes E1 and E2 that are close to each other via the insulating film IG.
  • the manufacturing process for forming such a structure can also be shared with the process for manufacturing transistors.
  • the wiring pattern PT it is also necessary to connect the electrodes isolated from each other by the insulating film IG.
  • the wiring pattern PT is the insulating film IG. It may be formed so as to connect both electrodes along the upper surface of the.
  • both electrodes are separated by an insulating film IG. ..
  • the amplifier circuit 10 of the above embodiment is configured by combining P-type and depletion-type transistors 101 to 104, 111.
  • a similar circuit can be configured by a transistor having an N-type conduction type or an enhancement type transistor.
  • the circuit configuration is partially different due to the difference in the operating characteristics.
  • FIG. 5 is a diagram showing a configuration example of an amplifier circuit using each type of transistor.
  • the amplifier circuit 10 in the upper left column is composed of a depletion-type transistor using a P-type semiconductor. That is, the amplifier circuit 10 is the same as the circuit of the present embodiment shown in FIG. 3A. Since the circuit configuration of the pseudo CMOS inverter using each type of transistor is known, detailed description thereof will be omitted. Further, in these circuits, the power supply on the low potential side is shared and represented as the power supply voltage Vss.
  • the amplifier circuit 20 in the upper right column is an example of a circuit composed of P-type and enhancement-type transistors.
  • the amplifier circuit 20 includes transistors 201 to 204 that form a pseudo CMOS inverter, and transistors 211 that serve as feedback elements.
  • the circuit configuration is almost the same as that of the depletion type, but the gate potential of the transistor 202 is the same potential as the drain terminal as shown by the dotted line, depending on the magnitude of the threshold voltage Vth of the transistor 202. In some cases, an appropriate control voltage Vc may be applied as shown by the solid line.
  • the amplifier circuit 30 in the lower left column is an example of a circuit composed of N-type and depletion-type transistors.
  • the amplifier circuit 30 includes transistors 301 to 304 that form a pseudo CMOS inverter, and transistors 311 that serve as feedback elements.
  • the circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 10 is reversed.
  • the transistor 311 serving as a feedback element is the same as the P-type transistor in that the drain gate is connected and used as a diode. However, there is a difference in that the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter.
  • the amplifier circuit 40 in the lower right column is an example of a circuit composed of N-type and enhancement type transistors.
  • the amplifier circuit 40 includes transistors 401 to 404 that form a pseudo CMOS inverter, and transistors 411 that serve as feedback elements.
  • the circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 20 is reversed.
  • the transistor 411 serving as the feedback element is connected between the drain and the gate, and the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter.
  • the circuit configuration of the inverter differs partly depending on the type of transistor used (P type / N type, depletion type / enhancement type), but a feedback element is connected to this to operate as an amplifier circuit.
  • the modification of the circuit is common. That is, connecting an input capacitor to the input side and using a diode-connected transistor as a feedback element.
  • both P-type and N-type are connected between the gate and drain, and the input / output of the inverter is such that the direction of the forward current in the channel matches the direction from the output side to the input side of the inverter. It is inserted in between.
  • the feedback transistor has a low resistance immediately after the power is turned on, and the time constant formed by the input capacitor C becomes small. Therefore, the start-up time required for the circuit to reach a steady state can be shortened. On the other hand, after reaching the steady state, the feedback transistor has a high resistance. Therefore, it is possible to suppress a decrease in gain in a low frequency region that depends on the time constant formed by the input capacitor C. That is, the amplifier circuit according to the present invention can achieve both excellent frequency characteristics and a short start-up time. Further, the feedback transistor can be formed in the same manufacturing process as the transistor constituting the inverter. Therefore, the process is not complicated as compared with the case of simply manufacturing the inverter, and it is possible to efficiently manufacture the amplifier circuit.
  • the input terminal Vi and the output terminal Vo correspond to the "input terminal” and the “output terminal” of the present invention, respectively.
  • the pseudo-CMOS inverter 100 which is a component of the amplifier circuit 10, corresponds to the "inverter circuit” of the present invention, and its input terminal Vi'and output terminal Vo'are the "input unit” and “input unit” of the present invention, respectively. It corresponds to the "output section”.
  • the capacitor C and the transistor 111 function as the "capacitor” and the "feedback element” of the present invention, respectively.
  • the amplifier circuit according to the present invention is realized by a combination of organic thin film transistors using an organic semiconductor material.
  • the amplifier circuit of the present invention is not limited to the organic thin film transistor, and can be configured by using various semiconductor elements.
  • each of the amplifier circuits 10 to 40 of the above-described embodiment is configured by combining either a depletion type or an enhancement type transistor.
  • mixing P-type semiconductors and N-type semiconductors in one circuit requires that different materials be used to form circuits, especially when organic semiconductor materials are used, which complicates the manufacturing process. It is not preferable because it becomes.
  • the conduction type is unified to either P type or N type, it is permissible to mix depletion type transistors and enhancement type transistors.
  • an appropriate bias voltage may be applied to the gate terminal. According to such an aspect, it is possible to control the effective threshold voltage Vth of the transistor by the gate bias.
  • the transistor constituting the feedback element may be connected to the input portion of the inverter circuit, and the source electrode may be connected to the output portion of the inverter circuit.
  • the conduction type of the transistor constituting the inverter circuit is N type
  • the drain electrode of the transistor constituting the feedback element may be connected to the output portion of the inverter circuit
  • the source electrode may be connected to the input portion of the inverter circuit. ..
  • the transistor as a feedback element can make the direction in which the current flows from the output unit to the input unit of the inverter circuit the forward direction of the channel current, and the feedback element according to the present invention. Will function effectively as.
  • the gate threshold voltage of the transistor constituting the feedback element may be configured so that its absolute value is a value between the ground potential and the power supply voltage of the inverter circuit. According to such a configuration, the transistor is surely turned on immediately after the power is turned on when the potential difference between the input / output portions of the inverter circuit becomes substantially the power supply voltage. Therefore, the effect of shortening the start-up time due to the low resistance can be surely obtained. Further, when the potential difference between the input / output portions of the inverter circuit is almost 0, the transistor is in the cutoff state. Therefore, it is possible to surely obtain the effect of improving the frequency characteristics by increasing the resistance.
  • the transistor constituting the inverter circuit and the feedback element may be an organic semiconductor transistor.
  • the transistor constituting the inverter circuit and the feedback element may be an organic semiconductor transistor.
  • the transistors constituting the inverter circuit and the feedback element may be simultaneously formed by the same manufacturing process.
  • the plurality of transistors constituting the inverter circuit and the feedback element have the same conduction type.
  • the structure of each transistor can be the same in principle. Therefore, it is possible to simultaneously form a plurality of transistors in the same process as the manufacturing process for forming one transistor. As a result, it is possible to manufacture an amplifier circuit having excellent characteristics at a low manufacturing cost.
  • the amplifier circuit according to the present invention can be mounted on various electronic devices such as a display device, a touch panel device, and a wearable electronic device.
  • an amplifier circuit can be configured using a thin film transistor, it is also suitable for mounting an amplifier circuit on the surface of a glass substrate, a flexible resin substrate, or the like.
  • Amplifier circuit 100 Pseudo CMOS inverter (inverter circuit) 101-104, 201-204, 301-304, 401-404 Transistors 111, 211, 311, 411 Feedback Transistors C Input Capacitors Vi input terminal Vi'input unit Vo output terminal Vo'output unit

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention concerne un circuit amplificateur 10 pour amplifier un signal entré dans une borne d'entrée Vi et pour délivrer en sortie le signal amplifié à partir d'une borne de sortie Vo, le circuit amplificateur 10 étant pourvu : d'un circuit d'onduleur 100 pour délivrer en sortie un signal de sortie, obtenu par inversion d'un signal d'entrée entré dans une partie d'entrée Vi', à partir d'une partie de sortie Vo' vers le terminal de sortie ; un condensateur d'entrée C connecté entre la borne d'entrée et la partie d'entrée du circuit onduleur ; et un élément de rétroaction 111 connecté entre la partie d'entrée et la partie de sortie Dans le circuit onduleur, une pluralité de transistors 101-104 du même type conducteur constituent un onduleur pseudo CMOS. L'élément de rétroaction est connecté au circuit onduleur de telle sorte que la grille et le drain d'un transistor 111 du même type conducteur que le transistor 101, etc. sont connectés, et un courant vers l'avant dans un canal s'écoule de la partie de sortie à la partie d'entrée. Il est rendu possible d'obtenir à la fois d'excellentes caractéristiques de fréquence et un temps de démarrage court sans compliquer le processus de fabrication.
PCT/JP2020/009594 2019-03-28 2020-03-06 Circuit amplificateur WO2020195694A1 (fr)

Priority Applications (1)

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JP2021508932A JP7148102B2 (ja) 2019-03-28 2020-03-06 増幅回路

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JP2019062242 2019-03-28
JP2019-062242 2019-03-28

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WO2020195694A1 true WO2020195694A1 (fr) 2020-10-01

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794953A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd Ｍｏｓ反転増幅回路
WO2003003461A1 (fr) * 2001-06-27 2003-01-09 Renesas Technology Corp. Dispositif de circuit integre a semiconducteur et procede de reduction du bruit
JP2007104367A (ja) * 2005-10-05 2007-04-19 National Institute Of Advanced Industrial & Technology 絶縁ゲート電界効果トランジスタを用いた多入力ｃｍｏｓ増幅器と、それを用いた高利得多入力ｃｍｏｓ増幅器、高安定多入力ｃｍｏｓ増幅器、高利得高安定多入力ｃｍｏｓ増幅器、多入力ｃｍｏｓ差動増幅器
WO2009147770A1 (fr) * 2008-06-02 2009-12-10 パナソニック株式会社 Circuit amplificateur de signal d'horloge
JP2015169815A (ja) * 2014-03-07 2015-09-28 セイコーエプソン株式会社 アクチュエーター装置、触覚ディスプレイおよび駆動方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111211781B (zh) 2020-02-10 2021-01-15 华南理工大学 一种基于薄膜晶体管的开关电容比较器、方法及芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794953A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd Ｍｏｓ反転増幅回路
WO2003003461A1 (fr) * 2001-06-27 2003-01-09 Renesas Technology Corp. Dispositif de circuit integre a semiconducteur et procede de reduction du bruit
JP2007104367A (ja) * 2005-10-05 2007-04-19 National Institute Of Advanced Industrial & Technology 絶縁ゲート電界効果トランジスタを用いた多入力ｃｍｏｓ増幅器と、それを用いた高利得多入力ｃｍｏｓ増幅器、高安定多入力ｃｍｏｓ増幅器、高利得高安定多入力ｃｍｏｓ増幅器、多入力ｃｍｏｓ差動増幅器
WO2009147770A1 (fr) * 2008-06-02 2009-12-10 パナソニック株式会社 Circuit amplificateur de signal d'horloge
JP2015169815A (ja) * 2014-03-07 2015-09-28 セイコーエプソン株式会社 アクチュエーター装置、触覚ディスプレイおよび駆動方法

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JP7148102B2 (ja) 2022-10-05

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