WO2020195694A1 - Amplifier circuit - Google Patents

Amplifier circuit Download PDF

Info

Publication number
WO2020195694A1
WO2020195694A1 PCT/JP2020/009594 JP2020009594W WO2020195694A1 WO 2020195694 A1 WO2020195694 A1 WO 2020195694A1 JP 2020009594 W JP2020009594 W JP 2020009594W WO 2020195694 A1 WO2020195694 A1 WO 2020195694A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
input
amplifier circuit
inverter circuit
terminal
Prior art date
Application number
PCT/JP2020/009594
Other languages
French (fr)
Japanese (ja)
Inventor
知玄 木村
武史 陶山
弥生 芝藤
毅 関谷
隆文 植村
Original Assignee
株式会社Ｓｃｒｅｅｎホールディングス
国立大学法人大阪大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社Ｓｃｒｅｅｎホールディングス, 国立大学法人大阪大学 filed Critical 株式会社Ｓｃｒｅｅｎホールディングス
Priority to JP2021508932A priority Critical patent/JP7148102B2/en
Publication of WO2020195694A1 publication Critical patent/WO2020195694A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Definitions

  • the present invention relates to an amplifier circuit configured by using a transistor, and is applicable to an amplifier circuit using a thin film transistor such as an organic transistor.
  • CMOS Complementary Metal Oxide Semiconductor
  • Patent Document 1 describes a circuit that performs the same function as a CMOS inverter by using only a P-type thin film transistor. Such a circuit is called a "pseudo-CMOS inverter". Further, for example, Patent Document 2 proposes to use the circuit as an amplifier circuit by connecting a feedback resistor between the input and output of the pseudo CMOS inverter circuit.
  • the present invention has been made in view of the above problems, and in an amplifier circuit using a pseudo-CMOS inverter circuit and having an input capacitor, it does not complicate the manufacturing process, and has excellent frequency characteristics and a short start-up time.
  • the purpose is to provide technologies that can be compatible with each other.
  • One aspect of the present invention is an amplifier circuit that amplifies a signal input to an input terminal and outputs it from an output terminal, and in order to achieve the above object, an output in which an input signal input to the input unit is inverted.
  • a capacitor connected between the input terminal and the input unit of the inverter circuit, and between the input unit and the output unit of the inverter circuit. It is provided with a feedback element connected to.
  • a plurality of transistors having the same conduction type of the semiconductor channels constitute a pseudo CMOS inverter, and the feedback element has the same conduction type as the transistor constituting the pseudo CMOS inverter.
  • the feedback element connected between the input and output of the pseudo CMOS inverter is composed of the same conduction type transistor as the transistor constituting the pseudo CMOS inverter. Therefore, the process for forming the transistor to be the feedback element can be incorporated in the process for manufacturing the transistor constituting the pseudo CMOS inverter. More specifically, when forming a transistor constituting a pseudo CMOS inverter, a transistor serving as a feedback element can also be formed. Therefore, as compared with the case of forming a simple inverter circuit, the manufacturing process is basically the same except for the number of transistors to be formed, and it is not necessary to provide a new process.
  • the transistor serving as the feedback element constitutes a two-terminal element in which the drain electrode and the gate electrode are connected.
  • a forward current flows from the output side to the input side of the inverter circuit. That is, the feedback element functions as a diode.
  • the potential of the output unit of the pseudo CMOS inverter circuit becomes a high potential (ideally, the power supply potential). Therefore, immediately after the power is turned on, a relatively large forward voltage is applied to the diode which is the feedback element, and a current flows from the output unit to the input unit of the inverter circuit via the diode in the low resistance state.
  • the potential of the input unit rises, while the potential of the output unit where the inverting voltage is output decreases.
  • the circuit is in a steady state when both potentials are in equilibrium. At this time, the voltage between the terminals of the feedback element is small, and the feedback element is in a high resistance state.
  • the feedback element since the feedback element has a low resistance immediately after the power is turned on, the time constant determined by the combination with the input capacitor is relatively small. Therefore, the potential difference between the input and output of the inverter circuit converges in a short time and reaches a steady state. That is, the startup time is short.
  • the steady state since the feedback element has a high resistance, the time constant is large, and the frequency characteristic (more specifically, the amplification degree in the low frequency region) is improved. Therefore, in this amplifier circuit, it is possible to achieve both excellent frequency characteristics and a short start-up time.
  • the manufacturing process is not complicated by forming the feedback element. Further, since the feedback element has a low resistance immediately after the power is turned on, the start-up time is short, but the resistance is high in the steady state, so that the decrease in amplification degree in the low frequency range can be suppressed. That is, in the present invention, it is possible to achieve both excellent frequency characteristics and a short start-up time without complicating the manufacturing process.
  • One embodiment of the present invention is an amplifier circuit using a so-called pseudo CMOS inverter.
  • the pseudo-CMOS inverter is an inverter circuit that imitates the circuit configuration and function of a CMOS (Complementary Metal Oxide Semiconductor) inverter by combining transistors having the same conduction type.
  • CMOS Complementary Metal Oxide Semiconductor
  • the circuit configuration of a CMOS inverter and an amplifier circuit using a CMOS inverter and its operating principle are known. Therefore, the description is omitted here, and the pseudo CMOS inverter circuit will be described first.
  • FIG. 1A and 1B are diagrams showing a configuration example of a pseudo CMOS inverter. More specifically, FIG. 1A is a diagram showing an example of a circuit configuration of a pseudo CMOS inverter, and FIG. 1B is a diagram showing an example of its operating characteristics.
  • the pseudo CMOS inverter 100 includes four transistors 101 to 104. All of these transistors 101 to 104 are depletion type transistors having a P type conduction type. For example, all the transistors 101 to 104 may have the same structure. Therefore, it is possible to simultaneously form these transistors 101 to 104 in the same manufacturing process. In the following description, the "pseudo-CMOS inverter" may be simply referred to as an "inverter".
  • the gate (G) terminal of the first transistor 101 is connected to the input terminal Vi'. Further, the source (S) terminal is connected to a power source (not shown), and an appropriate positive potential power supply voltage Vdd is applied.
  • the drain D terminal is connected to the source terminal of the second transistor 102.
  • the gate terminal of the second transistor 102 is connected to the source terminal, and the power supply voltage Vs1 is applied to the drain terminal.
  • the power supply voltage Vs1 is lower than the potential of the power supply voltage Vdd, and can be, for example, a ground potential or an appropriate negative potential.
  • the gate terminal of the third transistor 103 is connected to the gate terminal of the first transistor 101. That is, the gate terminal of the first transistor 101 and the gate terminal of the third transistor 103 are connected to the input terminal Vi'in parallel with each other.
  • a power supply voltage Vdd is applied to the source terminal of the third transistor 103.
  • the drain terminal of the third transistor 103 is connected to the source terminal of the fourth transistor 104, and further connected to the output terminal Vo'.
  • the gate terminal of the fourth transistor 104 is connected to the drain terminal of the first transistor 101, the source terminal of the second transistor 102, and the gate terminal.
  • a power supply voltage Vs2 is applied to the drain terminal of the fourth transistor 104.
  • the power supply voltage Vs2 can be shared with, for example, the power supply voltage Vs1.
  • Vs1 and Vs2 it is possible to modulate the operating characteristics by making these power supply voltages Vs1 and Vs2 different.
  • the case where the power supply voltages Vs1 and Vs2 have the same potential, for example, both have the ground potential will be considered.
  • the pseudo CMOS inverter 100 configured in this way outputs the L level to the output terminal Vo'when an H level signal is input to the input terminal Vi', while the L level signal is input to the input terminal Vi'. At that time, it functions as an inverting circuit that outputs the H level to the output terminal Vo'.
  • both the input terminal and the input voltage applied to the input terminal are represented by reference numerals Vi'.
  • both the output terminal and the output voltage appearing therein are represented by the reference numerals Vo'.
  • the output voltage Vo' is a value close to the power supply voltage Vdd.
  • the output voltage Vo'almost becomes the power supply voltage Vs2.
  • Vs2 0, the output voltage Vo'is almost the ground potential.
  • the output voltage Vo' fluctuates greatly at a voltage Vn intermediate between the ground potential and the power supply voltage Vdd.
  • the output voltage Vo ′ fluctuates greatly with respect to a slight change in the input voltage Vi ′.
  • the inverter circuit can be used as an inverting amplifier circuit.
  • FIG. 2 is a diagram showing an example in which an inverter circuit is used as an amplifier circuit. More specifically, FIG. 2A shows a circuit configuration example of the amplifier circuit 50, and FIG. 2B is a diagram showing the frequency characteristics of the voltage gain thereof. Further, FIG. 2C is a diagram for explaining the start-up time of the amplifier circuit 50.
  • the pseudo CMOS inverter 100 is operated as an inverting amplifier circuit by connecting a resistor R as a feedback element between the input terminal Vi'and the output terminal Vo' of the pseudo CMOS inverter 100 described above. be able to.
  • both terminals Due to the voltage feedback from the output terminal Vo'to the input terminal Vi', both terminals have the same potential in the no-signal state. More specifically, when both the input voltage Vi'and the output voltage Vo'are the voltage Vn, the equilibrium state is reached. Therefore, since a DC potential appears at the input terminal Vi', an input capacitor C for cutting DC is provided between the input terminal Vi of the amplifier circuit 50 and the input terminal Vi'of the inverter 10.
  • the input terminal of the amplifier circuit 50 and the input voltage applied to the amplifier circuit 50 are both represented by reference numerals Vi.
  • both the output terminal and the output voltage appearing therein are represented by the symbol Vo.
  • the output terminal Vo of the amplifier circuit 50 is electrically the same as the output terminal Vo'of the inverter 100.
  • the potential of the input terminal Vi'of the inverter 100 shows a change according to the signal centering on the voltage Vn.
  • the output voltage Vo'of the inverter 100 changes significantly in response to this, so that the amplified signal appears at the output terminal Vo of the amplifier circuit 50.
  • the amplifier circuit 50 functions as an inverting amplifier circuit.
  • the input capacitor C limits the transmission of low frequency signals. Therefore, in the actual amplifier circuit 50, as shown by the solid line in FIG. 2B, the voltage gain decreases at a frequency lower than the frequency determined by the time constant of the input capacitor C and the resistor R.
  • the time constant may be increased, that is, the resistance value of the resistor R and the capacitance of the input capacitor C may be increased.
  • the time constant formed by the input capacitor C and the resistor R is large.
  • the time constant is large, there is a problem that the start-up time until the amplifier circuit 50 reaches the steady state after the power is turned on becomes long. That is, with respect to the time constants of the input capacitor C and the resistor R, there is a trade-off relationship between the low-frequency voltage gain and the start-up time.
  • the amplifier circuit of the present embodiment described below can solve this problem, suppress a decrease in gain in a low frequency range, and suppress an increase in start-up time.
  • FIG. 3A to 3C are diagrams showing the configuration of the amplifier circuit of this embodiment. More specifically, FIG. 3A shows a circuit configuration of an amplifier circuit 10 in this embodiment, and FIG. 3B is a diagram showing an example of operating characteristics of a transistor 111 used as a feedback element. Further, FIG. 3C is a diagram showing an example of changes in the input voltage and the output voltage in the amplifier circuit 10.
  • a transistor 111 is used as a feedback element connected between the input / output terminals of the inverter 100.
  • the transistor 111 has the same conduction type as the transistors 101 to 104 constituting the inverter 100.
  • a depletion type transistor whose conduction type is P type is used.
  • the source (S) terminal is connected to the output terminal Vo'of the inverter 100, and the drain D terminal is connected to the input terminal Vi'of the inverter 100. Therefore, in the transistor 111 having the P-type channel, the forward current of the channel flows from the output terminal Vo'of the inverter 100 toward the input terminal Vi'. Further, the gate (G) terminal is connected to the drain terminal, and the transistor 111 functions as a two-terminal element, specifically, a diode.
  • the source-drain voltage Vsd which is the source potential when the drain potential of the transistor 111 is used as a reference, the drain current Id flowing from the source terminal to the drain terminal, and the transistor when viewed as a two-terminal element.
  • the drain current Id of the transistor 111 which operates as a diode by short-circuiting between the gate and drain hardly flows when the source-drain voltage Vsd is smaller than the threshold voltage Vth peculiar to the transistor. (Cut-off state).
  • a drain current Id having a magnitude corresponding to the magnitude of the source-drain voltage Vsd flows (on state).
  • the threshold voltage Vth in the general definition is expressed as a gate potential with reference to the source potential.
  • the above-mentioned source-drain voltage Vsd is defined as a source potential with reference to the drain potential in order to make it a positive value. Therefore, the positive and negative are opposite to those when the source potential is used as a reference. From this, it is assumed that the threshold voltage Vth in comparison with the source-drain voltage Vsd referred to here is expressed by an absolute value.
  • the resistance Rsd of the transistor 111 shows a large value when the source-drain voltage Vsd is smaller than the threshold voltage Vth.
  • the output voltage Vo'of the inverter 100 is almost the power supply voltage Vdd and the input voltage Vi'is almost 0 immediately after the power is turned on. From this state, the output voltage Vo'gradually decreases, while the input voltage Vi' gradually increases, and finally both voltages converge to the voltage Vn and the circuit reaches a steady state.
  • the time required for this depends on the time constant determined by the resistance value of the feedback element and the capacitance of the input capacitor.
  • the difference between the output voltage Vo'and the input voltage Vi' of the inverter 100, that is, the source-drain voltage Vsd of the transistor 111 is large, so that the transistor 111 is low. It is in a resistance state. For example, if the source-drain voltage Vsd at time T1 shown in FIG. 3C is sufficiently larger than the threshold voltage Vth of the transistor 111, the resistance Rsd is small as shown in the lower part of FIG. 3B.
  • the time constant determined by the resistance Rsd and the capacitance of the input capacitor C is small, and as shown by the solid line in FIG. 3C, the voltage difference between the input and output rapidly decreases. That is, the start-up time until the circuit converges to the steady state is shorter than the case where the feedback element having a large resistance value shown by the dotted line in FIG. 3C is used.
  • the source-drain voltage Vsd of the transistor 111 becomes sufficiently small, and at this time, as shown in the lower part of FIG. 3C.
  • the resistance Rsd has a large value.
  • the time constant formed by the resistor Rsd and the input capacitor C becomes large, so that the decrease in gain in the low frequency region can be suppressed.
  • the transistor 111 In order to obtain the effect of shortening the start-up time by putting the feedback element in a low resistance state, the transistor 111 needs to be turned on immediately after the power is turned on. Therefore, it is necessary that at least the threshold voltage Vth of the transistor 111 is a magnitude between the ground potential and the power supply voltage Vdd. Then, from the viewpoint of further shortening the start-up time, it is desirable that the state in which the resistance Rsd is small continues for as long as possible. Therefore, it is desirable that the threshold voltage Vth of the transistor 111 is as small as possible.
  • the allowable input voltage as an amplifier circuit becomes small. This is because when the amplitude of the input voltage Vi to the amplifier circuit 10 increases and the output voltage Vo increases accordingly, the voltage applied to both ends of the transistor 111, which is a feedback element (that is, the source-drain voltage Vsd) also increases. This is because when the voltage exceeds the threshold voltage Vth, the transistor 111 becomes in a low resistance state and the gain decreases. From this point of view, it is desirable that the threshold voltage Vth (accurately, its absolute value) of the transistor 111 is a large value as close as possible to the power supply voltage Vdd.
  • the threshold voltage Vth of the transistor 111 serving as a feedback element be appropriate. ..
  • the threshold voltage Vth can be set to about half of the power supply voltage Vdd.
  • the amplifier circuit 10 of this embodiment shortens the start-up time until the steady state is reached after the power is turned on, and suppresses the decrease in gain in the low frequency region after the start-up to obtain excellent frequency characteristics. It is something that can be done.
  • the transistors 101 to 104 constituting the pseudo CMOS inverter 100 and the transistors 111 functioning as feedback elements can be formed as the same conduction type transistors. Therefore, it is also excellent in terms of manufacturing process. Specifically, the process of forming the transistor 111 to be the feedback element can be incorporated into the process of forming the transistors 101 to 104 constituting the pseudo CMOS inverter 100, and the number of steps is increased by adding the feedback element. Absent.
  • FIG. 4A and 4B are diagrams showing a layout example of the amplifier circuit of this embodiment. More specifically, FIG. 4A shows an example of a circuit layout when the amplifier circuit 10 shown in FIG. 3A is composed of a thin film transistor. Further, FIG. 4B is a diagram illustrating a cross-sectional structure of a transistor which is a component of a circuit. In FIG. 4A, the shaded structure represents the organic semiconductor thin film SC that functions as a channel CH. As the material of the semiconductor thin film which is the main part of the thin film transistor, various materials known as semiconductor materials can be used.
  • the transistors 101 to 104 constituting the inverter 100 and the transistors 111 serving as feedback elements can basically have the same structure. Therefore, each transistor can be manufactured by the same manufacturing process.
  • reference numerals Tr are typically attached in order to handle the transistors 101 to 104 and 111 in a unified manner.
  • the transistor Tr is basically a drain electrode Ed and a source electrode Es formed on the substrate SB, an organic semiconductor thin film SC connecting them, an insulating film IG covering the surface of the organic semiconductor thin film SC, and insulation. It has a structure in which gate electrodes Eg facing the organic semiconductor thin film SC are sequentially laminated via a film IG.
  • Each of these functional layers can be formed by an appropriate film forming method according to each material, such as coating, vacuum deposition, chemical vapor deposition, photolithography, printing, and plating.
  • the drain electrode and the source electrode are structurally the same and can be exchanged with each other.
  • the transistors configured in this way are connected to each other with an appropriate wiring pattern PT as shown in FIG. 4A. This makes it possible to form the amplifier circuit 10 shown in FIG. 3A.
  • the input capacitor C can be configured by two electrodes E1 and E2 that are close to each other via the insulating film IG.
  • the manufacturing process for forming such a structure can also be shared with the process for manufacturing transistors.
  • the wiring pattern PT it is also necessary to connect the electrodes isolated from each other by the insulating film IG.
  • the wiring pattern PT is the insulating film IG. It may be formed so as to connect both electrodes along the upper surface of the.
  • both electrodes are separated by an insulating film IG. ..
  • the amplifier circuit 10 of the above embodiment is configured by combining P-type and depletion-type transistors 101 to 104, 111.
  • a similar circuit can be configured by a transistor having an N-type conduction type or an enhancement type transistor.
  • the circuit configuration is partially different due to the difference in the operating characteristics.
  • FIG. 5 is a diagram showing a configuration example of an amplifier circuit using each type of transistor.
  • the amplifier circuit 10 in the upper left column is composed of a depletion-type transistor using a P-type semiconductor. That is, the amplifier circuit 10 is the same as the circuit of the present embodiment shown in FIG. 3A. Since the circuit configuration of the pseudo CMOS inverter using each type of transistor is known, detailed description thereof will be omitted. Further, in these circuits, the power supply on the low potential side is shared and represented as the power supply voltage Vss.
  • the amplifier circuit 20 in the upper right column is an example of a circuit composed of P-type and enhancement-type transistors.
  • the amplifier circuit 20 includes transistors 201 to 204 that form a pseudo CMOS inverter, and transistors 211 that serve as feedback elements.
  • the circuit configuration is almost the same as that of the depletion type, but the gate potential of the transistor 202 is the same potential as the drain terminal as shown by the dotted line, depending on the magnitude of the threshold voltage Vth of the transistor 202. In some cases, an appropriate control voltage Vc may be applied as shown by the solid line.
  • the amplifier circuit 30 in the lower left column is an example of a circuit composed of N-type and depletion-type transistors.
  • the amplifier circuit 30 includes transistors 301 to 304 that form a pseudo CMOS inverter, and transistors 311 that serve as feedback elements.
  • the circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 10 is reversed.
  • the transistor 311 serving as a feedback element is the same as the P-type transistor in that the drain gate is connected and used as a diode. However, there is a difference in that the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter.
  • the amplifier circuit 40 in the lower right column is an example of a circuit composed of N-type and enhancement type transistors.
  • the amplifier circuit 40 includes transistors 401 to 404 that form a pseudo CMOS inverter, and transistors 411 that serve as feedback elements.
  • the circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 20 is reversed.
  • the transistor 411 serving as the feedback element is connected between the drain and the gate, and the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter.
  • the circuit configuration of the inverter differs partly depending on the type of transistor used (P type / N type, depletion type / enhancement type), but a feedback element is connected to this to operate as an amplifier circuit.
  • the modification of the circuit is common. That is, connecting an input capacitor to the input side and using a diode-connected transistor as a feedback element.
  • both P-type and N-type are connected between the gate and drain, and the input / output of the inverter is such that the direction of the forward current in the channel matches the direction from the output side to the input side of the inverter. It is inserted in between.
  • the feedback transistor has a low resistance immediately after the power is turned on, and the time constant formed by the input capacitor C becomes small. Therefore, the start-up time required for the circuit to reach a steady state can be shortened. On the other hand, after reaching the steady state, the feedback transistor has a high resistance. Therefore, it is possible to suppress a decrease in gain in a low frequency region that depends on the time constant formed by the input capacitor C. That is, the amplifier circuit according to the present invention can achieve both excellent frequency characteristics and a short start-up time. Further, the feedback transistor can be formed in the same manufacturing process as the transistor constituting the inverter. Therefore, the process is not complicated as compared with the case of simply manufacturing the inverter, and it is possible to efficiently manufacture the amplifier circuit.
  • the input terminal Vi and the output terminal Vo correspond to the "input terminal” and the “output terminal” of the present invention, respectively.
  • the pseudo-CMOS inverter 100 which is a component of the amplifier circuit 10, corresponds to the "inverter circuit” of the present invention, and its input terminal Vi'and output terminal Vo'are the "input unit” and “input unit” of the present invention, respectively. It corresponds to the "output section”.
  • the capacitor C and the transistor 111 function as the "capacitor” and the "feedback element” of the present invention, respectively.
  • the amplifier circuit according to the present invention is realized by a combination of organic thin film transistors using an organic semiconductor material.
  • the amplifier circuit of the present invention is not limited to the organic thin film transistor, and can be configured by using various semiconductor elements.
  • each of the amplifier circuits 10 to 40 of the above-described embodiment is configured by combining either a depletion type or an enhancement type transistor.
  • mixing P-type semiconductors and N-type semiconductors in one circuit requires that different materials be used to form circuits, especially when organic semiconductor materials are used, which complicates the manufacturing process. It is not preferable because it becomes.
  • the conduction type is unified to either P type or N type, it is permissible to mix depletion type transistors and enhancement type transistors.
  • an appropriate bias voltage may be applied to the gate terminal. According to such an aspect, it is possible to control the effective threshold voltage Vth of the transistor by the gate bias.
  • the transistor constituting the feedback element may be connected to the input portion of the inverter circuit, and the source electrode may be connected to the output portion of the inverter circuit.
  • the conduction type of the transistor constituting the inverter circuit is N type
  • the drain electrode of the transistor constituting the feedback element may be connected to the output portion of the inverter circuit
  • the source electrode may be connected to the input portion of the inverter circuit. ..
  • the transistor as a feedback element can make the direction in which the current flows from the output unit to the input unit of the inverter circuit the forward direction of the channel current, and the feedback element according to the present invention. Will function effectively as.
  • the gate threshold voltage of the transistor constituting the feedback element may be configured so that its absolute value is a value between the ground potential and the power supply voltage of the inverter circuit. According to such a configuration, the transistor is surely turned on immediately after the power is turned on when the potential difference between the input / output portions of the inverter circuit becomes substantially the power supply voltage. Therefore, the effect of shortening the start-up time due to the low resistance can be surely obtained. Further, when the potential difference between the input / output portions of the inverter circuit is almost 0, the transistor is in the cutoff state. Therefore, it is possible to surely obtain the effect of improving the frequency characteristics by increasing the resistance.
  • the transistor constituting the inverter circuit and the feedback element may be an organic semiconductor transistor.
  • the transistor constituting the inverter circuit and the feedback element may be an organic semiconductor transistor.
  • the transistors constituting the inverter circuit and the feedback element may be simultaneously formed by the same manufacturing process.
  • the plurality of transistors constituting the inverter circuit and the feedback element have the same conduction type.
  • the structure of each transistor can be the same in principle. Therefore, it is possible to simultaneously form a plurality of transistors in the same process as the manufacturing process for forming one transistor. As a result, it is possible to manufacture an amplifier circuit having excellent characteristics at a low manufacturing cost.
  • the amplifier circuit according to the present invention can be mounted on various electronic devices such as a display device, a touch panel device, and a wearable electronic device.
  • an amplifier circuit can be configured using a thin film transistor, it is also suitable for mounting an amplifier circuit on the surface of a glass substrate, a flexible resin substrate, or the like.
  • Amplifier circuit 100 Pseudo CMOS inverter (inverter circuit) 101-104, 201-204, 301-304, 401-404 Transistors 111, 211, 311, 411 Feedback Transistors C Input Capacitors Vi input terminal Vi'input unit Vo output terminal Vo'output unit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Logic Circuits (AREA)

Abstract

The present invention provides an amplifier circuit 10 for amplifying a signal inputted into an input terminal Vi and outputting the amplified signal from an output terminal Vo, the amplifier circuit 10 being provided with: an inverter circuit 100 for outputting an output signal, obtained by inverting an input signal inputted into an input part Vi', from an output part Vo' to the output terminal; an input capacitor C connected between the input terminal and the input part of the inverter circuit; and a feedback element 111 connected between the input part and the output part. In the inverter circuit, a plurality of transistors 101-104 of the same conductive type constitute a pseudo CMOS inverter. The feedback element is connected to the inverter circuit so that the gate and drain of a transistor 111 of the same conductive type as the transistor 101, etc., are connected, and a forward current in a channel flows from the output part to the input part. It is made possible to obtain both excellent frequency characteristics and a short startup time without complicating the manufacturing process.

Description

増幅回路Amplifier circuit
　この発明は、トランジスタを用いて構成される増幅回路に関し、例えば有機トランジスタなどの薄膜トランジスタを用いる増幅回路に適用可能なものである。 The present invention relates to an amplifier circuit configured by using a transistor, and is applicable to an amplifier circuit using a thin film transistor such as an organic transistor.
　例えば表示装置やタッチパネル装置、ウェアラブル電子装置等を製造することを目的として、ガラス板や樹脂板、樹脂シート等の基板の表面に薄膜トランジスタなどの薄膜半導体素子を形成するための技術が研究されている。特に近年では、その性能や生産技術の向上が著しく、また材料によっては印刷技術を利用したデバイス作成が可能であるとの観点から、薄膜半導体素子の材料として有機半導体が注目されている。 For example, for the purpose of manufacturing display devices, touch panel devices, wearable electronic devices, etc., techniques for forming thin film semiconductor elements such as thin film transistors on the surface of substrates such as glass plates, resin plates, and resin sheets are being studied. .. Particularly in recent years, organic semiconductors have been attracting attention as materials for thin film semiconductor devices from the viewpoint that their performance and production technology have been remarkably improved and that it is possible to create a device using printing technology depending on the material.
　このような材料により形成される半導体デバイスでは、一般的にその伝導型は使用される半導体材料の種類に大きく依存する。このため、互いに特性の揃ったＰ型デバイスとＮ型デバイスとを混在させた、いわゆるコンプリメンタリ型の回路を構成することが困難である。このことに関して、Ｐ型またはＮ型の一方のみを用いてＣＭＯＳ（Complementary Metal Oxide Semiconductor）回路と同等の機能を実現した回路も考案されている。 In a semiconductor device formed of such a material, its conduction type generally largely depends on the type of semiconductor material used. For this reason, it is difficult to construct a so-called complementary type circuit in which P-type devices and N-type devices having the same characteristics are mixed. In this regard, circuits have been devised that realize the same functions as CMOS (Complementary Metal Oxide Semiconductor) circuits using only one of P-type and N-type.
　例えば特許文献１には、Ｐ型の薄膜トランジスタのみを用いてＣＭＯＳインバータと同等の機能を果たす回路が記載されている。このような回路は「擬ＣＭＯＳインバータ」と称呼されている。また例えば特許文献２には、擬ＣＭＯＳインバータ回路の入出力間に帰還抵抗を接続することで、該回路を増幅回路として利用することが提案されている。 For example, Patent Document 1 describes a circuit that performs the same function as a CMOS inverter by using only a P-type thin film transistor. Such a circuit is called a "pseudo-CMOS inverter". Further, for example, Patent Document 2 proposes to use the circuit as an amplifier circuit by connecting a feedback resistor between the input and output of the pseudo CMOS inverter circuit.
特開２０１５－２０４７０２号公報Japanese Unexamined Patent Publication No. 2015-204702 特開２０１７－２１７０９８号公報JP-A-2017-217098
　特許文献２に記載された、擬ＣＭＯＳインバータ回路を用いた増幅回路においては、以下の２つの点において改善の余地が残されている。第１に、帰還素子としての抵抗体を、他の半導体トランジスタの製造プロセスとは別に作り込む、または外付けする必要があり、製造工程が複雑になる。第２に、レベルシフトまたは直流遮断等の目的で増幅回路に入力キャパシタを接続するとき、回路の周波数特性と電源投入時の起動の速さとの両立が難しいという問題がある。より詳しくは後述するが、具体的には以下の通りである。 In the amplifier circuit using the pseudo CMOS inverter circuit described in Patent Document 2, there is room for improvement in the following two points. First, a resistor as a feedback element needs to be manufactured or externally attached separately from the manufacturing process of other semiconductor transistors, which complicates the manufacturing process. Secondly, when an input capacitor is connected to an amplifier circuit for the purpose of level shifting or DC cutoff, there is a problem that it is difficult to achieve both the frequency characteristics of the circuit and the start-up speed when the power is turned on. More details will be described later, but the specifics are as follows.
　周波数特性と起動の速さとの間には、帰還素子と入力キャパシタとで決まる時定数に対してトレードオフの関係がある。すなわち、回路の周波数特性を改善するためには時定数は大きい方がよい一方、電源投入時に回路が定常状態に至るまでの時間（本明細書では「起動時間」と称する）を短くするためには、時定数は小さい方が好ましい。 There is a trade-off relationship between the frequency characteristics and the start-up speed with respect to the time constant determined by the feedback element and the input capacitor. That is, in order to improve the frequency characteristics of the circuit, it is better to have a large time constant, but in order to shorten the time until the circuit reaches a steady state when the power is turned on (referred to as "startup time" in the present specification). It is preferable that the time constant is small.
　この発明は上記課題に鑑みなされたものであり、擬ＣＭＯＳインバータ回路を用い、かつ入力キャパシタを有する増幅回路において、製造プロセスを複雑にすることなく、しかも、優れた周波数特性と短い起動時間とを両立させることのできる技術を提供することを目的とする。 The present invention has been made in view of the above problems, and in an amplifier circuit using a pseudo-CMOS inverter circuit and having an input capacitor, it does not complicate the manufacturing process, and has excellent frequency characteristics and a short start-up time. The purpose is to provide technologies that can be compatible with each other.
　この発明の一の態様は、入力端子に入力される信号を増幅して出力端子から出力する増幅回路であって、上記目的を達成するため、入力部に入力される入力信号を反転させた出力信号を出力部から前記出力端子へ出力するインバータ回路と、前記入力端子と前記インバータ回路の前記入力部との間に接続されたキャパシタと、前記インバータ回路の前記入力部と前記出力部との間に接続された帰還素子とを備える。ここで、前記インバータ回路では、半導体チャネルの伝導型が互いに同じである複数のトランジスタが擬ＣＭＯＳインバータを構成し、前記帰還素子は、前記擬ＣＭＯＳインバータを構成する前記トランジスタと伝導型が同じであるトランジスタのゲート電極とドレイン電極とを接続した二端子素子であり、該二端子素子は、チャネルにおける順方向の電流が前記出力部から前記入力部へ向けて流れるように前記インバータ回路に接続される。 One aspect of the present invention is an amplifier circuit that amplifies a signal input to an input terminal and outputs it from an output terminal, and in order to achieve the above object, an output in which an input signal input to the input unit is inverted. Between an amplifier circuit that outputs a signal from an output unit to the output terminal, a capacitor connected between the input terminal and the input unit of the inverter circuit, and between the input unit and the output unit of the inverter circuit. It is provided with a feedback element connected to. Here, in the inverter circuit, a plurality of transistors having the same conduction type of the semiconductor channels constitute a pseudo CMOS inverter, and the feedback element has the same conduction type as the transistor constituting the pseudo CMOS inverter. It is a two-terminal element that connects a gate electrode and a drain electrode of a transistor, and the two-terminal element is connected to the inverter circuit so that a forward current in a channel flows from the output unit to the input unit. ..
　前述した特許文献２に記載の増幅回路では、帰還素子として抵抗が用いられていた。一方、上記のように構成された発明では、擬ＣＭＯＳインバータの入出力間に接続される帰還素子が、擬ＣＭＯＳインバータを構成するトランジスタと同じ伝導型のトランジスタにより構成されている。このため、帰還素子となるトランジスタを形成するためのプロセスは、擬ＣＭＯＳインバータを構成するトランジスタを製造するプロセス中に組み込むことが可能である。より具体的には、擬ＣＭＯＳインバータを構成するトランジスタを形成する際に、帰還素子となるトランジスタを併せて形成することができる。したがって、単なるインバータ回路を形成する場合と比較して、製造工程としては形成されるトランジスタの数が異なるだけで基本的に同じであり、新たな工程を設ける必要がない。 In the amplifier circuit described in Patent Document 2 described above, a resistor was used as a feedback element. On the other hand, in the invention configured as described above, the feedback element connected between the input and output of the pseudo CMOS inverter is composed of the same conduction type transistor as the transistor constituting the pseudo CMOS inverter. Therefore, the process for forming the transistor to be the feedback element can be incorporated in the process for manufacturing the transistor constituting the pseudo CMOS inverter. More specifically, when forming a transistor constituting a pseudo CMOS inverter, a transistor serving as a feedback element can also be formed. Therefore, as compared with the case of forming a simple inverter circuit, the manufacturing process is basically the same except for the number of transistors to be formed, and it is not necessary to provide a new process.
　また、帰還素子となるトランジスタは、ドレイン電極とゲート電極とが接続された二端子素子を構成している。該二端子素子では、インバータ回路の出力側から入力側に順方向の電流が流れる。つまり帰還素子はダイオードとして機能する。無入力状態のとき擬ＣＭＯＳインバータ回路の出力部の電位は高電位（理想的には電源電位）となる。このため電源投入直後においては、帰還素子であるダイオードに比較的大きな順方向電圧が印加されることになり、低抵抗状態の該ダイオードを介してインバータ回路の出力部から入力部に電流が流れ込む。これにより入力部の電位が上昇する一方、反転電圧が出力される出力部では電位が低下する。両電位が均衡した時点で回路は定常状態となる。このとき帰還素子の端子間電圧は小さく、帰還素子は高抵抗状態となる。 Further, the transistor serving as the feedback element constitutes a two-terminal element in which the drain electrode and the gate electrode are connected. In the two-terminal element, a forward current flows from the output side to the input side of the inverter circuit. That is, the feedback element functions as a diode. In the no-input state, the potential of the output unit of the pseudo CMOS inverter circuit becomes a high potential (ideally, the power supply potential). Therefore, immediately after the power is turned on, a relatively large forward voltage is applied to the diode which is the feedback element, and a current flows from the output unit to the input unit of the inverter circuit via the diode in the low resistance state. As a result, the potential of the input unit rises, while the potential of the output unit where the inverting voltage is output decreases. The circuit is in a steady state when both potentials are in equilibrium. At this time, the voltage between the terminals of the feedback element is small, and the feedback element is in a high resistance state.
　このように、電源投入直後には帰還素子は低抵抗であるため、入力キャパシタとの組み合わせで決まる時定数は比較的小さい。したがって、インバータ回路の入出力間の電位差は短時間で収束し定常状態に至る。つまり、起動時間が短い。一方、定常状態においては、帰還素子が高抵抗であるため時定数が大きく、周波数特性（より具体的には低周波域での増幅度）が向上する。したがって、この増幅回路では、優れた周波数特性と短い起動時間とを両立させることが可能である。 In this way, since the feedback element has a low resistance immediately after the power is turned on, the time constant determined by the combination with the input capacitor is relatively small. Therefore, the potential difference between the input and output of the inverter circuit converges in a short time and reaches a steady state. That is, the startup time is short. On the other hand, in the steady state, since the feedback element has a high resistance, the time constant is large, and the frequency characteristic (more specifically, the amplification degree in the low frequency region) is improved. Therefore, in this amplifier circuit, it is possible to achieve both excellent frequency characteristics and a short start-up time.
　上記のように、本発明によれば、インバータ回路を構成するトランジスタと同じ伝導型のトランジスタを帰還素子として用いるので、帰還素子を形成することにより製造工程が複雑となることはない。また、帰還素子は、電源投入直後には低抵抗となるため起動時間が短い一方、定常状態では高抵抗となるため、低周波数域での増幅度の低下が抑えられる。すなわち、本発明では、製造プロセスを複雑にすることなく、しかも、優れた周波数特性と短い起動時間とを両立させることが可能である。 As described above, according to the present invention, since the same conduction type transistor as the transistor constituting the inverter circuit is used as the feedback element, the manufacturing process is not complicated by forming the feedback element. Further, since the feedback element has a low resistance immediately after the power is turned on, the start-up time is short, but the resistance is high in the steady state, so that the decrease in amplification degree in the low frequency range can be suppressed. That is, in the present invention, it is possible to achieve both excellent frequency characteristics and a short start-up time without complicating the manufacturing process.
　この発明の前記ならびにその他の目的と新規な特徴は、添付図面を参照しながら次の詳細な説明を読めば、より完全に明らかとなるであろう。ただし、図面は専ら解説のためのものであって、この発明の範囲を限定するものではない。 The above and other objectives and novel features of the present invention will become more completely apparent by reading the following detailed description with reference to the accompanying drawings. However, the drawings are for illustration purposes only and do not limit the scope of the invention.
擬ＣＭＯＳインバータの構成例を示す図である。It is a figure which shows the configuration example of the pseudo CMOS inverter. 擬ＣＭＯＳインバータの動作特性例を示す図である。It is a figure which shows the operation characteristic example of the pseudo CMOS inverter. インバータ回路を増幅回路として使用した例を示す図である。It is a figure which shows the example which used the inverter circuit as an amplifier circuit. 増幅回路の電圧利得の周波数特性を示す図である。It is a figure which shows the frequency characteristic of the voltage gain of an amplifier circuit. 増幅回路の起動時間を説明する図である。It is a figure explaining the start-up time of an amplifier circuit. 本実施形態における増幅回路の回路構成を示す図である。It is a figure which shows the circuit structure of the amplifier circuit in this embodiment. 帰還素子として用いられるトランジスタの動作特性例を示す図である。It is a figure which shows the example of the operation characteristic of the transistor used as a feedback element. 増幅回路における入力電圧および出力電圧の変化例を示す図である。It is a figure which shows the change example of the input voltage and the output voltage in an amplifier circuit. 増幅回路を薄膜トランジスタにより構成する場合の回路レイアウトの例を示す図である。It is a figure which shows the example of the circuit layout when the amplifier circuit is composed of thin film transistors. 回路の構成部品であるトランジスタの断面構造を例示する図である。It is a figure which illustrates the cross-sectional structure of the transistor which is a component of a circuit. 各タイプのトランジスタによる増幅回路の構成例を示す図である。It is a figure which shows the structural example of the amplifier circuit by each type of transistor.
　以下、本発明に係る増幅回路のいくつかの実施形態について、図面を参照しながら説明する。本発明の一実施形態は、いわゆる擬ＣＭＯＳインバータを使用した増幅回路である。擬ＣＭＯＳインバータは、伝導型が互いに同一であるトランジスタの組み合わせにより、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）インバータの回路構成および機能を模したインバータ回路である。ＣＭＯＳインバータ、およびＣＭＯＳインバータを用いた増幅回路の回路構成およびその動作原理は公知である。そのため、ここでは説明を省略し、まず擬ＣＭＯＳインバータ回路について説明する。 Hereinafter, some embodiments of the amplifier circuit according to the present invention will be described with reference to the drawings. One embodiment of the present invention is an amplifier circuit using a so-called pseudo CMOS inverter. The pseudo-CMOS inverter is an inverter circuit that imitates the circuit configuration and function of a CMOS (Complementary Metal Oxide Semiconductor) inverter by combining transistors having the same conduction type. The circuit configuration of a CMOS inverter and an amplifier circuit using a CMOS inverter and its operating principle are known. Therefore, the description is omitted here, and the pseudo CMOS inverter circuit will be described first.
　図１Ａおよび図１Ｂは擬ＣＭＯＳインバータの構成例を示す図である。より具体的には、図１Ａは擬ＣＭＯＳインバータの回路構成の一例を示す図であり、図１Ｂはその動作特性例を示す図である。擬ＣＭＯＳインバータ１００は、４つのトランジスタ１０１～１０４を備えている。これらのトランジスタ１０１～１０４はいずれも、Ｐ型の伝導型を有するデプレション型トランジスタである。例えば全てのトランジスタ１０１～１０４が、同一構造を有するものであってよい。したがって、これらのトランジスタ１０１～１０４を同一の製造プロセスで同時に形成することが可能である。なお、以下の説明においては、「擬ＣＭＯＳインバータ」を単に「インバータ」と称することがある。 1A and 1B are diagrams showing a configuration example of a pseudo CMOS inverter. More specifically, FIG. 1A is a diagram showing an example of a circuit configuration of a pseudo CMOS inverter, and FIG. 1B is a diagram showing an example of its operating characteristics. The pseudo CMOS inverter 100 includes four transistors 101 to 104. All of these transistors 101 to 104 are depletion type transistors having a P type conduction type. For example, all the transistors 101 to 104 may have the same structure. Therefore, it is possible to simultaneously form these transistors 101 to 104 in the same manufacturing process. In the following description, the "pseudo-CMOS inverter" may be simply referred to as an "inverter".
　第１のトランジスタ１０１のゲート（Ｇ）端子は入力端子Ｖｉ’に接続されている。また、そのソース（Ｓ）端子は図示しない電源に接続されて、適宜の正電位の電源電圧Ｖｄｄが印加されている。ドレインＤ端子は第２のトランジスタ１０２のソース端子と接続されている。第２のトランジスタ１０２のゲート端子はソース端子に接続され、ドレイン端子には電源電圧Ｖｓ１が印加される。電源電圧Ｖｓ１は電源電圧Ｖｄｄの電位より低く、例えば接地電位または適宜の負電位とすることができる。 The gate (G) terminal of the first transistor 101 is connected to the input terminal Vi'. Further, the source (S) terminal is connected to a power source (not shown), and an appropriate positive potential power supply voltage Vdd is applied. The drain D terminal is connected to the source terminal of the second transistor 102. The gate terminal of the second transistor 102 is connected to the source terminal, and the power supply voltage Vs1 is applied to the drain terminal. The power supply voltage Vs1 is lower than the potential of the power supply voltage Vdd, and can be, for example, a ground potential or an appropriate negative potential.
　第３のトランジスタ１０３のゲート端子は、第１のトランジスタ１０１のゲート端子と接続されている。つまり、第１のトランジスタ１０１のゲート端子と第３のトランジスタ１０３のゲート端子とは互いに並列に、入力端子Ｖｉ’に接続されている。第３のトランジスタ１０３のソース端子には電源電圧Ｖｄｄが印加されている。また、第３のトランジスタ１０３のドレイン端子は第４のトランジスタ１０４のソース端子に接続され、さらに出力端子Ｖｏ’に接続されている。 The gate terminal of the third transistor 103 is connected to the gate terminal of the first transistor 101. That is, the gate terminal of the first transistor 101 and the gate terminal of the third transistor 103 are connected to the input terminal Vi'in parallel with each other. A power supply voltage Vdd is applied to the source terminal of the third transistor 103. Further, the drain terminal of the third transistor 103 is connected to the source terminal of the fourth transistor 104, and further connected to the output terminal Vo'.
　第４のトランジスタ１０４のゲート端子は第１のトランジスタ１０１のドレイン端子、第２のトランジスタ１０２のソース端子およびゲート端子に接続されている。第４のトランジスタ１０４のドレイン端子には電源電圧Ｖｓ２が印加されている。電源電圧Ｖｓ２は例えば電源電圧Ｖｓ１と共通とすることができる。なお、既に知られているように、擬ＣＭＯＳインバータ回路の特徴として、これらの電源電圧Ｖｓ１、Ｖｓ２を異ならせることによりその動作特性を変調することが可能である。ただし、以下では最も簡単な例として電源電圧Ｖｓ１、Ｖｓ２を同電位、例えばいずれも接地電位とした場合で考える。 The gate terminal of the fourth transistor 104 is connected to the drain terminal of the first transistor 101, the source terminal of the second transistor 102, and the gate terminal. A power supply voltage Vs2 is applied to the drain terminal of the fourth transistor 104. The power supply voltage Vs2 can be shared with, for example, the power supply voltage Vs1. As already known, as a feature of the pseudo CMOS inverter circuit, it is possible to modulate the operating characteristics by making these power supply voltages Vs1 and Vs2 different. However, in the following, as the simplest example, the case where the power supply voltages Vs1 and Vs2 have the same potential, for example, both have the ground potential, will be considered.
　このように構成された擬ＣＭＯＳインバータ１００は、入力端子Ｖｉ’にＨレベルの信号が入力されたときには出力端子Ｖｏ’にＬレベルを出力する一方、入力端子Ｖｉ’にＬレベルの信号が入力されたときには出力端子Ｖｏ’にＨレベルを出力する反転回路として機能する。なお、以下の説明において特に区別する必要がない限り、入力端子およびこれに印加される入力電圧をいずれも符号Ｖｉ’により表す。同様に、出力端子およびこれに現れる出力電圧をいずれも符号Ｖｏ’により表す。 The pseudo CMOS inverter 100 configured in this way outputs the L level to the output terminal Vo'when an H level signal is input to the input terminal Vi', while the L level signal is input to the input terminal Vi'. At that time, it functions as an inverting circuit that outputs the H level to the output terminal Vo'. Unless otherwise specified in the following description, both the input terminal and the input voltage applied to the input terminal are represented by reference numerals Vi'. Similarly, both the output terminal and the output voltage appearing therein are represented by the reference numerals Vo'.
　具体的には、図１Ｂに示すように、入力電圧Ｖｉ’が接地電位（０Ｖ）に近いときには、出力電圧Ｖｏ’は、ほぼ電源電圧Ｖｄｄに近い値となる。一方、入力電圧Ｖｉ’が電源電圧Ｖｄｄに近いときには、出力電圧Ｖｏ’は、ほぼ電源電圧Ｖｓ２となる。Ｖｓ２＝０とした本例では、出力電圧Ｖｏ’はほぼ接地電位となる。そして、接地電位と電源電圧Ｖｄｄとの中間的な電圧Ｖｎにおいて、出力電圧Ｖｏ’は大きく変動する。言い換えれば、この電圧Ｖｎの近辺では入力電圧Ｖｉ’の僅かな変化に対して出力電圧Ｖｏ’が大きく変動する。この性質を利用して、インバータ回路を反転増幅回路として利用することが可能である。 Specifically, as shown in FIG. 1B, when the input voltage Vi'is close to the ground potential (0V), the output voltage Vo'is a value close to the power supply voltage Vdd. On the other hand, when the input voltage Vi'is close to the power supply voltage Vdd, the output voltage Vo'almost becomes the power supply voltage Vs2. In this example in which Vs2 = 0, the output voltage Vo'is almost the ground potential. Then, the output voltage Vo'variably fluctuates greatly at a voltage Vn intermediate between the ground potential and the power supply voltage Vdd. In other words, in the vicinity of this voltage Vn, the output voltage Vo ′ fluctuates greatly with respect to a slight change in the input voltage Vi ′. Utilizing this property, the inverter circuit can be used as an inverting amplifier circuit.
　図２はインバータ回路を増幅回路として使用した例を示す図である。より具体的には、図２Ａは増幅回路５０の回路構成例を示し、図２Ｂはその電圧利得の周波数特性を示す図である。また、図２Ｃは増幅回路５０の起動時間を説明する図である。図２Ａに示すように、前述した擬ＣＭＯＳインバータ１００の入力端子Ｖｉ’と出力端子Ｖｏ’との間に帰還素子としての抵抗Ｒを接続することにより、擬ＣＭＯＳインバータ１００を反転増幅回路として動作させることができる。 FIG. 2 is a diagram showing an example in which an inverter circuit is used as an amplifier circuit. More specifically, FIG. 2A shows a circuit configuration example of the amplifier circuit 50, and FIG. 2B is a diagram showing the frequency characteristics of the voltage gain thereof. Further, FIG. 2C is a diagram for explaining the start-up time of the amplifier circuit 50. As shown in FIG. 2A, the pseudo CMOS inverter 100 is operated as an inverting amplifier circuit by connecting a resistor R as a feedback element between the input terminal Vi'and the output terminal Vo' of the pseudo CMOS inverter 100 described above. be able to.
　出力端子Ｖｏ’から入力端子Ｖｉ’への電圧帰還により、無信号状態では両端子が同電位となる。より具体的には、入力電圧Ｖｉ’と出力電圧Ｖｏ’とがいずれも電圧Ｖｎであるとき平衡状態となる。したがって入力端子Ｖｉ’に直流電位が現れることとなるので、増幅回路５０の入力端子Ｖｉとインバータ１０の入力端子Ｖｉ’との間には直流カット用の入力キャパシタＣが設けられる。なお、以下の説明において特に区別する必要がない限り、増幅回路５０の入力端子およびこれに印加される入力電圧をいずれも符号Ｖｉにより表す。同様に、出力端子およびこれに現れる出力電圧をいずれも符号Ｖｏにより表す。増幅回路５０の出力端子Ｖｏは、インバータ１００の出力端子Ｖｏ’と電気的には同一である。 Due to the voltage feedback from the output terminal Vo'to the input terminal Vi', both terminals have the same potential in the no-signal state. More specifically, when both the input voltage Vi'and the output voltage Vo'are the voltage Vn, the equilibrium state is reached. Therefore, since a DC potential appears at the input terminal Vi', an input capacitor C for cutting DC is provided between the input terminal Vi of the amplifier circuit 50 and the input terminal Vi'of the inverter 10. Unless otherwise specified in the following description, the input terminal of the amplifier circuit 50 and the input voltage applied to the amplifier circuit 50 are both represented by reference numerals Vi. Similarly, both the output terminal and the output voltage appearing therein are represented by the symbol Vo. The output terminal Vo of the amplifier circuit 50 is electrically the same as the output terminal Vo'of the inverter 100.
　増幅回路５０の入力端子Ｖｉに信号が入力されると、インバータ１００の入力端子Ｖｉ’の電位は電圧Ｖｎを中心として信号に応じた変化を示す。これに応じてインバータ１００の出力電圧Ｖｏ’が大きく変化することで、増幅された信号が増幅回路５０の出力端子Ｖｏに現れる。図１Ｂに示されるように、入力電圧Ｖｉ’の上昇に対し出力電圧Ｖｏ’は低下する方向に変化するから、増幅回路５０は反転増幅回路として機能する。 When a signal is input to the input terminal Vi of the amplifier circuit 50, the potential of the input terminal Vi'of the inverter 100 shows a change according to the signal centering on the voltage Vn. The output voltage Vo'of the inverter 100 changes significantly in response to this, so that the amplified signal appears at the output terminal Vo of the amplifier circuit 50. As shown in FIG. 1B, since the output voltage Vo'changes in the direction of decreasing with respect to the increase of the input voltage Vi', the amplifier circuit 50 functions as an inverting amplifier circuit.
　増幅回路５０の電圧利得（＝Ｖｏ／Ｖｉ）としては、図２Ｂに点線で示すように、ある周波数より低い周波数領域で一定であり、より高い周波数で一様に低下する特性が理想的である。しかしながら、入力キャパシタＣによって低周波信号の伝達が制限される。そのため実際の増幅回路５０においては、図２Ｂに実線で示すように、入力キャパシタＣと抵抗Ｒとの時定数で決まる周波数より低い周波数では電圧利得が低下する。これを抑制するためには、時定数を大きく、つまり抵抗Ｒの抵抗値および入力キャパシタＣの容量を大きくすればよい。 Ideally, the voltage gain (= Vo / Vi) of the amplifier circuit 50 is constant in a frequency region lower than a certain frequency and uniformly decreases in a higher frequency, as shown by a dotted line in FIG. 2B. .. However, the input capacitor C limits the transmission of low frequency signals. Therefore, in the actual amplifier circuit 50, as shown by the solid line in FIG. 2B, the voltage gain decreases at a frequency lower than the frequency determined by the time constant of the input capacitor C and the resistor R. In order to suppress this, the time constant may be increased, that is, the resistance value of the resistor R and the capacitance of the input capacitor C may be increased.
　ただし、時定数を大きくすることで、特に電源投入直後において次のような問題が生じ得る。電源投入直後の増幅回路５０では、図２Ｃに示すように、インバータ１００の入力電圧Ｖｉ’がほぼ０、出力電圧Ｖｏ’がほぼ電源電圧Ｖｄｄである。これらの電位差が帰還素子である抵抗Ｒの両端に加わるため、抵抗Ｒを介して出力端子Ｖｏ’から入力端子Ｖｉ’に向かって電流が流れ込む。これにより入力端子Ｖｉ’の電位が上昇する一方、出力端子Ｖｏ’の電位は低下し、
　　Ｖｉ’＝Ｖｏ’≒Ｖｎ
となった時点で電位の変化が収束し回路は定常状態に達する。収束までに要する時間Ｔｓは、入力キャパシタＣと抵抗Ｒとがなす時定数が大きいほど長くなる。 However, by increasing the time constant, the following problems may occur, especially immediately after the power is turned on. In the amplifier circuit 50 immediately after the power is turned on, as shown in FIG. 2C, the input voltage Vi'of the inverter 100 is substantially 0, and the output voltage Vo'is approximately the power supply voltage Vdd. Since these potential differences are applied to both ends of the resistor R, which is a feedback element, a current flows from the output terminal Vo'to the input terminal Vi' through the resistor R. As a result, the potential of the input terminal Vi'is increased, while the potential of the output terminal Vo' is decreased.
Vi'= Vo'≒ Vn
At the time when, the change in potential converges and the circuit reaches a steady state. The time Ts required for convergence increases as the time constant formed by the input capacitor C and the resistor R increases.
　このように、低域における電圧利得の低下を抑えるためには、入力キャパシタＣと抵抗Ｒとがなす時定数が大きい方が好ましい。一方、時定数が大きいと、電源投入後に増幅回路５０が定常状態に到達するまでの起動時間が長くなってしまうという問題がある。つまり、入力キャパシタＣと抵抗Ｒとの時定数に関して、低域の電圧利得と起動時間とはトレードオフの関係にある。以下に説明する本実施形態の増幅回路は、この問題を解消し、低域での利得低下を抑制し、しかも起動時間の増大を抑えることができるものである。 As described above, in order to suppress the decrease in voltage gain in the low frequency range, it is preferable that the time constant formed by the input capacitor C and the resistor R is large. On the other hand, if the time constant is large, there is a problem that the start-up time until the amplifier circuit 50 reaches the steady state after the power is turned on becomes long. That is, with respect to the time constants of the input capacitor C and the resistor R, there is a trade-off relationship between the low-frequency voltage gain and the start-up time. The amplifier circuit of the present embodiment described below can solve this problem, suppress a decrease in gain in a low frequency range, and suppress an increase in start-up time.
　また、特にトランジスタが有機半導体の製造プロセスによって形成されるものである場合には、このプロセスによって安定した抵抗体を形成する方法はまだ確立されていない。このため、抵抗を含む回路を製造するためには抵抗器を外付けする必要が生じ、製造工程が複雑になる。一方、本実施形態の増幅回路は抵抗を使用していないため、このような問題は生じない。 Further, especially when the transistor is formed by an organic semiconductor manufacturing process, a method for forming a stable resistor by this process has not yet been established. Therefore, in order to manufacture a circuit including a resistor, it is necessary to attach a resistor externally, which complicates the manufacturing process. On the other hand, since the amplifier circuit of this embodiment does not use a resistor, such a problem does not occur.
　図３Ａないし図３Ｃは本実施形態の増幅回路の構成を示す図である。より具体的には、図３Ａは本実施形態における増幅回路１０の回路構成を示し、図３Ｂは帰還素子として用いられるトランジスタ１１１の動作特性例を示す図である。また、図３Ｃは増幅回路１０における入力電圧および出力電圧の変化例を示す図である。 3A to 3C are diagrams showing the configuration of the amplifier circuit of this embodiment. More specifically, FIG. 3A shows a circuit configuration of an amplifier circuit 10 in this embodiment, and FIG. 3B is a diagram showing an example of operating characteristics of a transistor 111 used as a feedback element. Further, FIG. 3C is a diagram showing an example of changes in the input voltage and the output voltage in the amplifier circuit 10.
　図３Ａに示すように、この実施形態の増幅回路１０では、インバータ１００の入出力端子間に接続する帰還素子として、トランジスタ１１１が用いられる。トランジスタ１１１は、インバータ１００を構成するトランジスタ１０１～１０４と同じ伝導型を有している。この例では、伝導型がＰ型のデプレション型トランジスタが用いられる。 As shown in FIG. 3A, in the amplifier circuit 10 of this embodiment, a transistor 111 is used as a feedback element connected between the input / output terminals of the inverter 100. The transistor 111 has the same conduction type as the transistors 101 to 104 constituting the inverter 100. In this example, a depletion type transistor whose conduction type is P type is used.
　トランジスタ１１１では、ソース（Ｓ）端子がインバータ１００の出力端子Ｖｏ’に、ドレインＤ端子がインバータ１００の入力端子Ｖｉ’に接続されている。したがって、Ｐ型チャネルを有するトランジスタ１１１においては、チャネルの順方向電流は、インバータ１００の出力端子Ｖｏ’から入力端子Ｖｉ’に向かって流れる。また、ゲート（Ｇ）端子はドレイン端子と接続されており、トランジスタ１１１は二端子素子、具体的にはダイオードとして機能する。 In the transistor 111, the source (S) terminal is connected to the output terminal Vo'of the inverter 100, and the drain D terminal is connected to the input terminal Vi'of the inverter 100. Therefore, in the transistor 111 having the P-type channel, the forward current of the channel flows from the output terminal Vo'of the inverter 100 toward the input terminal Vi'. Further, the gate (G) terminal is connected to the drain terminal, and the transistor 111 functions as a two-terminal element, specifically, a diode.
　以下の説明のために、トランジスタ１１１のドレイン電位を基準としたときのソース電位であるソース・ドレイン間電圧Ｖｓｄ、ソース端子からドレイン端子に向けて流れるドレイン電流Ｉｄ、二端子素子としてみたときのトランジスタ１１１の抵抗Ｒｓｄを導入する。これらの物理量の間には下式：
　　Ｖｏ’－Ｖｉ’＝Ｖｓｄ＝Ｒｓｄ・Ｉｄ　…　（式１）
の関係がある。ただし、抵抗Ｒｓｄは一定ではなくソース・ドレイン間電圧Ｖｓｄによって変化する。 For the following explanation, the source-drain voltage Vsd, which is the source potential when the drain potential of the transistor 111 is used as a reference, the drain current Id flowing from the source terminal to the drain terminal, and the transistor when viewed as a two-terminal element. The resistor Rsd of 111 is introduced. Between these physical quantities is the following equation:
Vo'-Vi'= Vsd = Rsd · Id ... (Equation 1)
There is a relationship. However, the resistance Rsd is not constant and changes depending on the source-drain voltage Vsd.
　図３Ｂの上段に示すように、ゲート・ドレイン間が短絡されダイオードとして動作するトランジスタ１１１のドレイン電流Ｉｄは、ソース・ドレイン間電圧Ｖｓｄが当該トランジスタ固有のしきい値電圧Ｖｔｈより小さいときにはほとんど流れない（カットオフ状態）。ソース・ドレイン間電圧Ｖｓｄがしきい値電圧Ｖｔｈより大きくなると、ソース・ドレイン間電圧Ｖｓｄの大きさに応じた大きさのドレイン電流Ｉｄが流れる（オン状態）。なお、一般的な定義におけるしきい値電圧Ｖｔｈは、ソース電位を基準としたときのゲート電位として表される。一方、上記したソース・ドレイン間電圧Ｖｓｄは、正の値とするためにドレイン電位を基準としたソース電位として定義されている。したがって、ソース電位を基準とする場合とは正負が逆になる。このことから、ここでいうソース・ドレイン間電圧Ｖｓｄとの比較におけるしきい値電圧Ｖｔｈは、その大きさを絶対値で表したものとする。 As shown in the upper part of FIG. 3B, the drain current Id of the transistor 111 which operates as a diode by short-circuiting between the gate and drain hardly flows when the source-drain voltage Vsd is smaller than the threshold voltage Vth peculiar to the transistor. (Cut-off state). When the source-drain voltage Vsd becomes larger than the threshold voltage Vth, a drain current Id having a magnitude corresponding to the magnitude of the source-drain voltage Vsd flows (on state). The threshold voltage Vth in the general definition is expressed as a gate potential with reference to the source potential. On the other hand, the above-mentioned source-drain voltage Vsd is defined as a source potential with reference to the drain potential in order to make it a positive value. Therefore, the positive and negative are opposite to those when the source potential is used as a reference. From this, it is assumed that the threshold voltage Vth in comparison with the source-drain voltage Vsd referred to here is expressed by an absolute value.
　このため、図３Ｂの下段に示すように、トランジスタ１１１の抵抗Ｒｓｄは、ソース・ドレイン間電圧Ｖｓｄがしきい値電圧Ｖｔｈより小さいときには大きな値を示す。一方、これよりソース・ドレイン間電圧Ｖｓｄが大きくなるほど小さな値を示す。このことは、次のような作用をもたらす。 Therefore, as shown in the lower part of FIG. 3B, the resistance Rsd of the transistor 111 shows a large value when the source-drain voltage Vsd is smaller than the threshold voltage Vth. On the other hand, the larger the source-drain voltage Vsd is, the smaller the value is. This has the following effects.
　図２Ｃを用いて先に説明したように、電源投入直後においてはインバータ１００の出力電圧Ｖｏ’はほぼ電源電圧Ｖｄｄであり、入力電圧Ｖｉ’はほぼ０である。この状態から、出力電圧Ｖｏ’は次第に低下する一方、入力電圧Ｖｉ’は次第に上昇して最終的に両電圧が電圧Ｖｎに収束して回路が定常状態に達する。これに要する時間は、帰還素子の抵抗値と入力キャパシタの容量とで決まる時定数に依存する。 As described earlier with reference to FIG. 2C, the output voltage Vo'of the inverter 100 is almost the power supply voltage Vdd and the input voltage Vi'is almost 0 immediately after the power is turned on. From this state, the output voltage Vo'gradually decreases, while the input voltage Vi' gradually increases, and finally both voltages converge to the voltage Vn and the circuit reaches a steady state. The time required for this depends on the time constant determined by the resistance value of the feedback element and the capacitance of the input capacitor.
　本実施形態の回路においても同様であるが、電源投入直後ではインバータ１００の出力電圧Ｖｏ’と入力電圧Ｖｉ’との差、つまりトランジスタ１１１のソース・ドレイン間電圧Ｖｓｄが大きいため、トランジスタ１１１は低抵抗状態である。例えば、図３Ｃに示す時刻Ｔ１におけるソース・ドレイン間電圧Ｖｓｄがトランジスタ１１１のしきい値電圧Ｖｔｈより十分大きければ、図３Ｂ下段に示すように抵抗Ｒｓｄは小さい。 The same applies to the circuit of the present embodiment, but immediately after the power is turned on, the difference between the output voltage Vo'and the input voltage Vi' of the inverter 100, that is, the source-drain voltage Vsd of the transistor 111 is large, so that the transistor 111 is low. It is in a resistance state. For example, if the source-drain voltage Vsd at time T1 shown in FIG. 3C is sufficiently larger than the threshold voltage Vth of the transistor 111, the resistance Rsd is small as shown in the lower part of FIG. 3B.
　このため、抵抗Ｒｓｄと入力キャパシタＣの容量とで決まる時定数は小さく、図３Ｃに実線で示すように、入出力間の電圧差は急速に小さくなる。つまり、回路が定常状態に収束するまでの起動時間が、図３Ｃに点線で示す、抵抗値の大きな帰還素子を使用した場合に比べて短くなる。 Therefore, the time constant determined by the resistance Rsd and the capacitance of the input capacitor C is small, and as shown by the solid line in FIG. 3C, the voltage difference between the input and output rapidly decreases. That is, the start-up time until the circuit converges to the steady state is shorter than the case where the feedback element having a large resistance value shown by the dotted line in FIG. 3C is used.
　一方、例えば図３Ｃに示す時刻Ｔ２のように、回路が定常状態に達した後では、トランジスタ１１１のソース・ドレイン間電圧Ｖｓｄが十分に小さくなっており、このとき、図３Ｃ下段に示すように抵抗Ｒｓｄは大きな値となっている。回路が増幅動作を行う定常状態においては、抵抗Ｒｓｄと入力キャパシタＣとがなす時定数が大きくなるため、低周波数領域での利得の低下を抑制することができる。 On the other hand, for example, at time T2 shown in FIG. 3C, after the circuit reaches a steady state, the source-drain voltage Vsd of the transistor 111 becomes sufficiently small, and at this time, as shown in the lower part of FIG. 3C. The resistance Rsd has a large value. In the steady state in which the circuit performs the amplification operation, the time constant formed by the resistor Rsd and the input capacitor C becomes large, so that the decrease in gain in the low frequency region can be suppressed.
　帰還素子が低抵抗状態となることで起動時間を短縮する、との効果を得るためには、電源投入直後にトランジスタ１１１がオン状態となる必要がある。したがって、少なくともトランジスタ１１１のしきい値電圧Ｖｔｈが、接地電位と電源電圧Ｖｄｄとの間の大きさであることが必要である。そして、起動時間をさらに短縮するとの観点からは、抵抗Ｒｓｄが小さい状態ができるだけ長く続くことが望ましい。したがって、トランジスタ１１１のしきい値電圧Ｖｔｈはできるだけ小さいことが望ましい。 In order to obtain the effect of shortening the start-up time by putting the feedback element in a low resistance state, the transistor 111 needs to be turned on immediately after the power is turned on. Therefore, it is necessary that at least the threshold voltage Vth of the transistor 111 is a magnitude between the ground potential and the power supply voltage Vdd. Then, from the viewpoint of further shortening the start-up time, it is desirable that the state in which the resistance Rsd is small continues for as long as possible. Therefore, it is desirable that the threshold voltage Vth of the transistor 111 is as small as possible.
　しかしながら、帰還素子が高抵抗となるソース・ドレイン間電圧Ｖｓｄの電圧範囲が狭くなると、増幅回路としての許容入力電圧は小さくなってしまう。というのは、増幅回路１０への入力電圧Ｖｉの振幅が大きくなり、これに応じて出力電圧Ｖｏが大きくなると、帰還素子であるトランジスタ１１１の両端に加わる電圧（つまりソース・ドレイン間電圧Ｖｓｄ）も大きくなり、これがしきい値電圧Ｖｔｈを超えるとトランジスタ１１１が低抵抗状態となり利得が低下してしまうからである。この観点からは、トランジスタ１１１のしきい値電圧Ｖｔｈ（正確にはその絶対値）は、電源電圧Ｖｄｄにできるだけ近い大きな値であることが望ましいことになる。 However, if the voltage range of the source-drain voltage Vsd at which the feedback element has a high resistance becomes narrow, the allowable input voltage as an amplifier circuit becomes small. This is because when the amplitude of the input voltage Vi to the amplifier circuit 10 increases and the output voltage Vo increases accordingly, the voltage applied to both ends of the transistor 111, which is a feedback element (that is, the source-drain voltage Vsd) also increases. This is because when the voltage exceeds the threshold voltage Vth, the transistor 111 becomes in a low resistance state and the gain decreases. From this point of view, it is desirable that the threshold voltage Vth (accurately, its absolute value) of the transistor 111 is a large value as close as possible to the power supply voltage Vdd.
　このように、図３Ａの回路が、起動時間を短縮しつつ増幅回路として適切に動作するためには、帰還素子となるトランジスタ１１１が有するしきい値電圧Ｖｔｈを適切なものとすることが望まれる。例えば、しきい値電圧Ｖｔｈを電源電圧Ｖｄｄの半分程度とすることができる。 As described above, in order for the circuit of FIG. 3A to properly operate as an amplifier circuit while shortening the start-up time, it is desired that the threshold voltage Vth of the transistor 111 serving as a feedback element be appropriate. .. For example, the threshold voltage Vth can be set to about half of the power supply voltage Vdd.
　以上のように、この実施形態の増幅回路１０は、電源投入後に定常状態に達するまでの起動時間を短くし、しかも起動後には低周波数領域における利得の低下を抑えて、優れた周波数特性を得ることができるものである。さらに、擬ＣＭＯＳインバータ１００を構成するトランジスタ１０１～１０４と、帰還素子として機能するトランジスタ１１１とを、同じ伝導型のトランジスタとして形成することができる。このため、製造プロセスの面でも優れている。具体的には、帰還素子となるトランジスタ１１１を形成するプロセスを、擬ＣＭＯＳインバータ１００を構成するトランジスタ１０１～１０４を形成するプロセスに組み入れることができ、帰還素子を追加することによる工程の増加が生じない。 As described above, the amplifier circuit 10 of this embodiment shortens the start-up time until the steady state is reached after the power is turned on, and suppresses the decrease in gain in the low frequency region after the start-up to obtain excellent frequency characteristics. It is something that can be done. Further, the transistors 101 to 104 constituting the pseudo CMOS inverter 100 and the transistors 111 functioning as feedback elements can be formed as the same conduction type transistors. Therefore, it is also excellent in terms of manufacturing process. Specifically, the process of forming the transistor 111 to be the feedback element can be incorporated into the process of forming the transistors 101 to 104 constituting the pseudo CMOS inverter 100, and the number of steps is increased by adding the feedback element. Absent.
　図４Ａおよび図４Ｂは本実施形態の増幅回路のレイアウト例を示す図である。より具体的には、図４Ａは図３Ａに示す増幅回路１０を薄膜トランジスタにより構成する場合の回路レイアウトの例を示す。また、図４Ｂは回路の構成部品であるトランジスタの断面構造を例示する図である。図４Ａにおいて、斜線を付した構造物は、チャネルＣＨとして機能する有機半導体薄膜ＳＣを表している。薄膜トランジスタの主要部となる半導体薄膜の材料としては、半導体材料として知られている種々のものを用いることができる。 4A and 4B are diagrams showing a layout example of the amplifier circuit of this embodiment. More specifically, FIG. 4A shows an example of a circuit layout when the amplifier circuit 10 shown in FIG. 3A is composed of a thin film transistor. Further, FIG. 4B is a diagram illustrating a cross-sectional structure of a transistor which is a component of a circuit. In FIG. 4A, the shaded structure represents the organic semiconductor thin film SC that functions as a channel CH. As the material of the semiconductor thin film which is the main part of the thin film transistor, various materials known as semiconductor materials can be used.
　図４Ａに示すように、インバータ１００を構成するトランジスタ１０１～１０４と帰還素子となるトランジスタ１１１とは、基本的にいずれも同一構造とすることが可能である。したがって、各トランジスタを同一の製造プロセスで製造することが可能である。図４Ｂ右側では、各トランジスタ１０１～１０４、１１１を統一的に扱うため、代表的に符号Ｔｒを付している。同図に示すように、トランジスタＴｒは基本的に、基板ＳＢに形成されたドレイン電極Ｅｄおよびソース電極Ｅｓ、これらを接続する有機半導体薄膜ＳＣ、有機半導体薄膜ＳＣの表面を覆う絶縁膜ＩＧ、絶縁膜ＩＧを介して有機半導体薄膜ＳＣと対向するゲート電極Ｅｇが順次積層された構造を有している。これらの各機能層は、塗布、真空蒸着、化学的気相成長、フォトリソグラフィ、印刷、めっき等、それぞれの材料に応じた適宜の成膜方法により形成することが可能である。このようなトランジスタにおいて、ドレイン電極とソース電極とは構造的には同一であり相互に交換可能である。 As shown in FIG. 4A, the transistors 101 to 104 constituting the inverter 100 and the transistors 111 serving as feedback elements can basically have the same structure. Therefore, each transistor can be manufactured by the same manufacturing process. On the right side of FIG. 4B, reference numerals Tr are typically attached in order to handle the transistors 101 to 104 and 111 in a unified manner. As shown in the figure, the transistor Tr is basically a drain electrode Ed and a source electrode Es formed on the substrate SB, an organic semiconductor thin film SC connecting them, an insulating film IG covering the surface of the organic semiconductor thin film SC, and insulation. It has a structure in which gate electrodes Eg facing the organic semiconductor thin film SC are sequentially laminated via a film IG. Each of these functional layers can be formed by an appropriate film forming method according to each material, such as coating, vacuum deposition, chemical vapor deposition, photolithography, printing, and plating. In such a transistor, the drain electrode and the source electrode are structurally the same and can be exchanged with each other.
　このように構成されたトランジスタ同士が、図４Ａに示すように適宜の配線パターンＰＴで相互に接続される。これにより、図３Ａに示す増幅回路１０を形成することが可能である。なお、入力キャパシタＣについては、図４Ｂ左側に示すように、絶縁膜ＩＧを介して近接対向する２つの電極Ｅ１，Ｅ２により構成することが可能である。このような構造を形成するための製造プロセスも、トランジスタを製造するプロセスと共通化することが可能である。 The transistors configured in this way are connected to each other with an appropriate wiring pattern PT as shown in FIG. 4A. This makes it possible to form the amplifier circuit 10 shown in FIG. 3A. As shown on the left side of FIG. 4B, the input capacitor C can be configured by two electrodes E1 and E2 that are close to each other via the insulating film IG. The manufacturing process for forming such a structure can also be shared with the process for manufacturing transistors.
　また、配線パターンＰＴについては、絶縁膜ＩＧにより相互に隔離された電極同士を接続する必要もある。例えば図４Ｂ左側に示すキャパシタＣの電極板Ｅ１と図４Ｂ右側に示すトランジスタＴｒのゲート電極Ｅｇとを接続する場合（トランジスタＴｒがトランジスタ１０１として機能する場合に相当）、配線パターンＰＴは絶縁膜ＩＧの上面に沿って両電極を接続するように形成されればよい。 Further, for the wiring pattern PT, it is also necessary to connect the electrodes isolated from each other by the insulating film IG. For example, when the electrode plate E1 of the capacitor C shown on the left side of FIG. 4B and the gate electrode Eg of the transistor Tr shown on the right side of FIG. 4B are connected (corresponding to the case where the transistor Tr functions as the transistor 101), the wiring pattern PT is the insulating film IG. It may be formed so as to connect both electrodes along the upper surface of the.
　一方、例えば図４Ｂ右側に示すトランジスタＴｒのゲート電極Ｅｇとドレイン電極Ｅｄとを接続する場合（トランジスタＴｒが帰還用トランジスタ１１１として機能する場合に相当）、両電極が絶縁膜ＩＧによって隔てられている。この場合には、絶縁膜ＩＧに部分的に貫通孔を設けて上下の配線を電気的に接続する、いわゆるヴィアホール接続によって配線パターンＰＴを形成することが可能である。 On the other hand, for example, when the gate electrode Eg of the transistor Tr shown on the right side of FIG. 4B and the drain electrode Ed are connected (corresponding to the case where the transistor Tr functions as a feedback transistor 111), both electrodes are separated by an insulating film IG. .. In this case, it is possible to form the wiring pattern PT by a so-called via hole connection in which the insulating film IG is partially provided with a through hole to electrically connect the upper and lower wirings.
　なお、上記実施形態の増幅回路１０は、Ｐ型かつデプレション型のトランジスタ１０１～１０４，１１１を組み合わせて構成されている。しかしながら、伝導型がＮ型であるトランジスタや、エンハンスメント型のトランジスタによっても同様の回路を構成することが可能である。ただし、その動作特性の差異に起因して回路構成は部分的に異なる。 The amplifier circuit 10 of the above embodiment is configured by combining P-type and depletion-type transistors 101 to 104, 111. However, a similar circuit can be configured by a transistor having an N-type conduction type or an enhancement type transistor. However, the circuit configuration is partially different due to the difference in the operating characteristics.
　図５は各タイプのトランジスタによる増幅回路の構成例を示す図である。このうち左上欄の増幅回路１０は、Ｐ型半導体を使用したデプレション型トランジスタにより構成されたものである。すなわち増幅回路１０は、図３Ａに示した本実施形態の回路と同じものである。なお、各タイプのトランジスタを用いた擬ＣＭＯＳインバータの回路構成は公知であるので、詳しい説明を省略する。また、これらの回路においては低電位側の電源を共通化し、電源電圧Ｖｓｓとして表している。 FIG. 5 is a diagram showing a configuration example of an amplifier circuit using each type of transistor. Of these, the amplifier circuit 10 in the upper left column is composed of a depletion-type transistor using a P-type semiconductor. That is, the amplifier circuit 10 is the same as the circuit of the present embodiment shown in FIG. 3A. Since the circuit configuration of the pseudo CMOS inverter using each type of transistor is known, detailed description thereof will be omitted. Further, in these circuits, the power supply on the low potential side is shared and represented as the power supply voltage Vss.
　また、右上欄の増幅回路２０は、Ｐ型、エンハンスメント型トランジスタにより構成された回路の例である。この増幅回路２０は、擬ＣＭＯＳインバータを構成するトランジスタ２０１～２０４と、帰還素子となるトランジスタ２１１とを備えている。回路構成はデプレション型のものと概ね同じであるが、トランジスタ２０２のゲート電位については、当該トランジスタ２０２が有するしきい値電圧Ｖｔｈの大きさに応じて、点線で示すようにドレイン端子と同電位とされるケースと、実線で示すように適宜の制御電圧Ｖｃが印加される場合とがあり得る。 The amplifier circuit 20 in the upper right column is an example of a circuit composed of P-type and enhancement-type transistors. The amplifier circuit 20 includes transistors 201 to 204 that form a pseudo CMOS inverter, and transistors 211 that serve as feedback elements. The circuit configuration is almost the same as that of the depletion type, but the gate potential of the transistor 202 is the same potential as the drain terminal as shown by the dotted line, depending on the magnitude of the threshold voltage Vth of the transistor 202. In some cases, an appropriate control voltage Vc may be applied as shown by the solid line.
　左下欄の増幅回路３０は、Ｎ型、デプレション型トランジスタにより構成された回路の例である。この増幅回路３０は、擬ＣＭＯＳインバータを構成するトランジスタ３０１～３０４と、帰還素子となるトランジスタ３１１とを備えている。インバータの回路構成は、Ｐ型の増幅回路１０の極性を反転したものとなる。また、帰還素子となるトランジスタ３１１は、ドレイン・ゲート間が接続されてダイオードとして用いられる点についてはＰ型のものと同じである。ただし、ドレイン端子がインバータの出力側に、ソース端子がインバータの入力側に接続される点で相違がある。Ｎ型トランジスタにおいては、前述の（式１）に代えて下式：
　　Ｖｏ’－Ｖｉ’＝Ｖｄｓ＝Ｒｄｓ・Ｉｄ　…　（式２）
の関係が成立する。ここで、符号Ｖｄｓはソース端子に対するドレイン端子電位、符号Ｒｄｓはドレイン・ソース間の抵抗である。 The amplifier circuit 30 in the lower left column is an example of a circuit composed of N-type and depletion-type transistors. The amplifier circuit 30 includes transistors 301 to 304 that form a pseudo CMOS inverter, and transistors 311 that serve as feedback elements. The circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 10 is reversed. Further, the transistor 311 serving as a feedback element is the same as the P-type transistor in that the drain gate is connected and used as a diode. However, there is a difference in that the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter. In the N-type transistor, instead of the above-mentioned (Equation 1), the following equation:
Vo'-Vi'= Vds = Rds · Id ... (Equation 2)
Relationship is established. Here, the reference numeral Vds is the drain terminal potential with respect to the source terminal, and the reference numeral Rds is the resistance between the drain and the source.
　また、右下欄の増幅回路４０は、Ｎ型、エンハンスメント型トランジスタにより構成された回路の例である。この増幅回路４０は、擬ＣＭＯＳインバータを構成するトランジスタ４０１～４０４と、帰還素子となるトランジスタ４１１とを備えている。インバータの回路構成は、Ｐ型の増幅回路２０の極性を反転したものとなる。この場合も、帰還素子となるトランジスタ４１１は、ドレイン・ゲート間が接続され、ドレイン端子がインバータの出力側に、ソース端子がインバータの入力側にそれぞれ接続される。 The amplifier circuit 40 in the lower right column is an example of a circuit composed of N-type and enhancement type transistors. The amplifier circuit 40 includes transistors 401 to 404 that form a pseudo CMOS inverter, and transistors 411 that serve as feedback elements. The circuit configuration of the inverter is such that the polarity of the P-type amplifier circuit 20 is reversed. In this case as well, the transistor 411 serving as the feedback element is connected between the drain and the gate, and the drain terminal is connected to the output side of the inverter and the source terminal is connected to the input side of the inverter.
　このように、使用されるトランジスタのタイプ（Ｐ型／Ｎ型、デプレション型／エンハンスメント型）によってインバータの回路構成が一部異なるが、これに帰還素子を接続して増幅回路として動作させるための回路の改変については共通している。それは、入力側に入力キャパシタを接続することと、トランジスタをダイオード接続したものを帰還素子として用いることとである。このときのトランジスタについては、Ｐ型、Ｎ型とも、ゲート・ドレイン間を接続し、チャネルにおける順方向電流の方向がインバータの出力側から入力側へ向かう方向と一致するように、インバータの入出力間に介挿される。 In this way, the circuit configuration of the inverter differs partly depending on the type of transistor used (P type / N type, depletion type / enhancement type), but a feedback element is connected to this to operate as an amplifier circuit. The modification of the circuit is common. That is, connecting an input capacitor to the input side and using a diode-connected transistor as a feedback element. Regarding the transistor at this time, both P-type and N-type are connected between the gate and drain, and the input / output of the inverter is such that the direction of the forward current in the channel matches the direction from the output side to the input side of the inverter. It is inserted in between.
　これにより、いずれの回路例においても、電源投入直後においては帰還用トランジスタが低抵抗となり、入力キャパシタＣとでなす時定数が小さくなる。そのため、回路が定常状態に達するまでに要する起動時間を短くすることができる。一方、定常状態に達した後には、帰還用トランジスタが高抵抗となる。そのため、入力キャパシタＣとでなす時定数に依存する低周波数領域での利得低下を抑制することができる。すなわち、本発明に係る増幅回路は、優れた周波数特性と短い起動時間とを両立させることができる。また、帰還用トランジスタを、インバータを構成するトランジスタと同じ製造プロセス中で形成することができる。このため、単にインバータを製造する場合と比べて工程が複雑になることはなく、効率的に増幅回路を製造することが可能である。 As a result, in any of the circuit examples, the feedback transistor has a low resistance immediately after the power is turned on, and the time constant formed by the input capacitor C becomes small. Therefore, the start-up time required for the circuit to reach a steady state can be shortened. On the other hand, after reaching the steady state, the feedback transistor has a high resistance. Therefore, it is possible to suppress a decrease in gain in a low frequency region that depends on the time constant formed by the input capacitor C. That is, the amplifier circuit according to the present invention can achieve both excellent frequency characteristics and a short start-up time. Further, the feedback transistor can be formed in the same manufacturing process as the transistor constituting the inverter. Therefore, the process is not complicated as compared with the case of simply manufacturing the inverter, and it is possible to efficiently manufacture the amplifier circuit.
　以上説明したように、本実施形態の増幅回路１０においては、その入力端子Ｖｉおよび出力端子Ｖｏが、それぞれ本発明の「入力端子」および「出力端子」に相当している。一方、増幅回路１０の構成要素である擬ＣＭＯＳインバータ１００が本発明の「インバータ回路」に相当しており、その入力端子Ｖｉ’および出力端子Ｖｏ’が、それぞれ本発明の「入力部」および「出力部」に相当している。また、上記実施形態では、キャパシタＣおよびトランジスタ１１１がそれぞれ本発明の「キャパシタ」および「帰還素子」として機能している。 As described above, in the amplifier circuit 10 of the present embodiment, the input terminal Vi and the output terminal Vo correspond to the "input terminal" and the "output terminal" of the present invention, respectively. On the other hand, the pseudo-CMOS inverter 100, which is a component of the amplifier circuit 10, corresponds to the "inverter circuit" of the present invention, and its input terminal Vi'and output terminal Vo'are the "input unit" and "input unit" of the present invention, respectively. It corresponds to the "output section". Further, in the above embodiment, the capacitor C and the transistor 111 function as the "capacitor" and the "feedback element" of the present invention, respectively.
　なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて上述したもの以外に種々の変更を行うことが可能である。例えば、上記した実施形態は、本発明に係る増幅回路を、有機半導体材料を用いた有機薄膜トランジスタの組み合わせにより実現したものである。しかしながら、本発明の増幅回路は、有機薄膜トランジスタに限定されず、各種の半導体素子を用いて構成することが可能である。 The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above embodiment, the amplifier circuit according to the present invention is realized by a combination of organic thin film transistors using an organic semiconductor material. However, the amplifier circuit of the present invention is not limited to the organic thin film transistor, and can be configured by using various semiconductor elements.
　また、上記実施形態の各増幅回路１０～４０はいずれも、デプレション型またはエンハンスメント型のいずれかのトランジスタを組み合わせて構成されたものである。ここで、Ｐ型半導体およびＮ型半導体を１つの回路中で混在させることは、特に有機半導体材料を使用する場合には、それぞれ異なる材料を用いて回路を形成する必要があり、製造工程が複雑になるため好ましくない。これに対し、伝導型についてはＰ型またはＮ型のいずれかに統一する一方で、デプレション型のトランジスタとエンハンスメント型のトランジスタとを混在させることは許容される。 Further, each of the amplifier circuits 10 to 40 of the above-described embodiment is configured by combining either a depletion type or an enhancement type transistor. Here, mixing P-type semiconductors and N-type semiconductors in one circuit requires that different materials be used to form circuits, especially when organic semiconductor materials are used, which complicates the manufacturing process. It is not preferable because it becomes. On the other hand, while the conduction type is unified to either P type or N type, it is permissible to mix depletion type transistors and enhancement type transistors.
　また、ゲート端子がドレイン端子またはソース端子に直結されたトランジスタにおいては、このような直結に代えて、ゲート端子に適宜のバイアス電圧が印加された態様で使用されてもよい。このような態様によれば、ゲートバイアスにより当該トランジスタの実効的なしきい値電圧Ｖｔｈを制御することが可能となる。 Further, in a transistor in which the gate terminal is directly connected to the drain terminal or the source terminal, instead of such a direct connection, an appropriate bias voltage may be applied to the gate terminal. According to such an aspect, it is possible to control the effective threshold voltage Vth of the transistor by the gate bias.
　以上、具体的な実施形態を例示して説明してきたように、本発明に係る増幅回路においては、例えばインバータ回路を構成するトランジスタの伝導型がＰ型であれば、帰還素子を構成するトランジスタのドレイン電極がインバータ回路の入力部に、ソース電極がインバータ回路の出力部にそれぞれ接続されればよい。また、インバータ回路を構成するトランジスタの伝導型がＮ型であれば、帰還素子を構成するトランジスタのドレイン電極がインバータ回路の出力部に、ソース電極がインバータ回路の入力部にそれぞれ接続されればよい。これらの構成によれば、帰還素子としてのトランジスタが、インバータ回路の出力部から入力部に向かって電流が流れる方向をチャネル電流の順方向となるようにすることができ、本発明に係る帰還素子として有効に機能することになる。 As described above by exemplifying a specific embodiment, in the amplifier circuit according to the present invention, for example, if the conduction type of the transistor constituting the inverter circuit is P type, the transistor constituting the feedback element The drain electrode may be connected to the input portion of the inverter circuit, and the source electrode may be connected to the output portion of the inverter circuit. If the conduction type of the transistor constituting the inverter circuit is N type, the drain electrode of the transistor constituting the feedback element may be connected to the output portion of the inverter circuit, and the source electrode may be connected to the input portion of the inverter circuit. .. According to these configurations, the transistor as a feedback element can make the direction in which the current flows from the output unit to the input unit of the inverter circuit the forward direction of the channel current, and the feedback element according to the present invention. Will function effectively as.
　また例えば、帰還素子を構成するトランジスタのゲートしきい値電圧は、その絶対値が接地電位とインバータ回路の電源電圧との間の値であるように構成されてよい。このような構成によれば、インバータ回路の入出力部間の電位差がほぼ電源電圧となる電源投入直後において、当該トランジスタが確実にオン状態となる。そのため、低抵抗化による起動時間の短縮効果を確実に得ることができる。また、インバータ回路の入出力部間の電位差がほぼ０である状態ではトランジスタがカットオフ状態となる。そのため、高抵抗化による周波数特性の改善効果を確実に得ることが可能となる。 Further, for example, the gate threshold voltage of the transistor constituting the feedback element may be configured so that its absolute value is a value between the ground potential and the power supply voltage of the inverter circuit. According to such a configuration, the transistor is surely turned on immediately after the power is turned on when the potential difference between the input / output portions of the inverter circuit becomes substantially the power supply voltage. Therefore, the effect of shortening the start-up time due to the low resistance can be surely obtained. Further, when the potential difference between the input / output portions of the inverter circuit is almost 0, the transistor is in the cutoff state. Therefore, it is possible to surely obtain the effect of improving the frequency characteristics by increasing the resistance.
　また例えば、インバータ回路および帰還素子を構成するトランジスタは、有機半導体トランジスタであってよい。本発明では、単一の伝導型を有するトランジスタの組み合わせによって優れた特性を有する増幅回路を構成することが可能である。このような特徴は、同一材料で相補的な伝導型のトランジスタを形成することが困難である有機半導体を用いる場合に特に有効なものとなるからである。 Further, for example, the transistor constituting the inverter circuit and the feedback element may be an organic semiconductor transistor. In the present invention, it is possible to construct an amplifier circuit having excellent characteristics by combining transistors having a single conduction type. This is because such a feature becomes particularly effective when an organic semiconductor, which is difficult to form a complementary conduction type transistor from the same material, is used.
　また例えば、インバータ回路および帰還素子を構成するトランジスタは、互いに同一の製造プロセスにより同時に形成されたものであってよい。本発明に係る増幅回路では、インバータ回路および帰還素子を構成する複数のトランジスタが、互いに同一の伝導型を有する。また、各トランジスタの構造も、原理的には同一のものとすることができる。このため、１つのトランジスタを形成するための製造プロセスと同一の工程で、複数のトランジスタを同時に形成することが可能である。これにより、低い製造コストで優れた特性の増幅回路を製造することができる。 Further, for example, the transistors constituting the inverter circuit and the feedback element may be simultaneously formed by the same manufacturing process. In the amplifier circuit according to the present invention, the plurality of transistors constituting the inverter circuit and the feedback element have the same conduction type. Further, the structure of each transistor can be the same in principle. Therefore, it is possible to simultaneously form a plurality of transistors in the same process as the manufacturing process for forming one transistor. As a result, it is possible to manufacture an amplifier circuit having excellent characteristics at a low manufacturing cost.
　以上、特定の実施例に沿って発明を説明したが、この説明は限定的な意味で解釈されることを意図したものではない。発明の説明を参照すれば、本発明のその他の実施形態と同様に、開示された実施形態の様々な変形例が、この技術に精通した者に明らかとなるであろう。故に、添付の特許請求の範囲は、発明の真の範囲を逸脱しない範囲内で、当該変形例または実施形態を含むものと考えられる。 The invention has been described above according to a specific embodiment, but this description is not intended to be interpreted in a limited sense. With reference to the description of the invention, various variations of the disclosed embodiments, as well as other embodiments of the present invention, will be apparent to those familiar with the art. Therefore, the appended claims are considered to include such modifications or embodiments without departing from the true scope of the invention.
　この発明に係る増幅回路は、例えば表示装置やタッチパネル装置、ウェアラブル電子装置等の各種電子装置に搭載可能である。特に、薄膜トランジスタを用いて増幅回路を構成することができるので、ガラス基板や柔軟な樹脂基板等の表面に増幅回路を実装する用途にも好適である。 The amplifier circuit according to the present invention can be mounted on various electronic devices such as a display device, a touch panel device, and a wearable electronic device. In particular, since an amplifier circuit can be configured using a thin film transistor, it is also suitable for mounting an amplifier circuit on the surface of a glass substrate, a flexible resin substrate, or the like.
　１０～４０　増幅回路
　１００　擬ＣＭＯＳインバータ（インバータ回路）
　１０１～１０４、２０１～２０４、３０１～３０４、４０１～４０４　トランジスタ
　１１１、２１１、３１１、４１１　帰還用トランジスタ
　Ｃ　入力キャパシタ（キャパシタ）
　Ｖｉ　入力端子
　Ｖｉ’　入力部
　Ｖｏ　出力端子
　Ｖｏ’　出力部 10-40 Amplifier circuit 100 Pseudo CMOS inverter (inverter circuit)
101-104, 201-204, 301-304, 401-404 Transistors 111, 211, 311, 411 Feedback Transistors C Input Capacitors
Vi input terminal Vi'input unit Vo output terminal Vo'output unit

Claims (6)

  1. 　入力端子に入力される信号を増幅して出力端子から出力する増幅回路であって、
    　入力部に入力される入力信号を反転させた出力信号を出力部から前記出力端子へ出力するインバータ回路と、
    　前記入力端子と前記インバータ回路の前記入力部との間に接続されたキャパシタと、
    　前記インバータ回路の前記入力部と前記出力部との間に接続された帰還素子と
    を備え、
    　前記インバータ回路では、半導体チャネルの伝導型が互いに同じである複数のトランジスタが擬ＣＭＯＳインバータを構成し、
    　前記帰還素子は、前記擬ＣＭＯＳインバータを構成する前記トランジスタと伝導型が同じであるトランジスタのゲート電極とドレイン電極とを接続した二端子素子であり、該二端子素子は、チャネルにおける順方向の電流が前記出力部から前記入力部へ向けて流れるように前記インバータ回路に接続される、増幅回路。     An amplifier circuit that amplifies the signal input to the input terminal and outputs it from the output terminal.
    An inverter circuit that outputs an output signal that is an inverted input signal input to the input unit from the output unit to the output terminal.
    A capacitor connected between the input terminal and the input portion of the inverter circuit,
    A feedback element connected between the input unit and the output unit of the inverter circuit is provided.
    In the inverter circuit, a plurality of transistors having the same conduction type of semiconductor channels constitute a pseudo CMOS inverter.
    The feedback element is a two-terminal element in which a gate electrode and a drain electrode of a transistor having the same conduction type as the transistor constituting the pseudo CMOS inverter are connected, and the two-terminal element is a forward current in a channel. Is connected to the inverter circuit so as to flow from the output unit to the input unit.
  2. 　前記インバータ回路を構成する前記トランジスタの伝導型がＰ型であり、
    　前記帰還素子を構成する前記トランジスタのドレイン電極が前記インバータ回路の前記入力部に、ソース電極が前記インバータ回路の前記出力部にそれぞれ接続されている請求項１に記載の増幅回路。     The conduction type of the transistor constituting the inverter circuit is P type.
    The amplifier circuit according to claim 1, wherein the drain electrode of the transistor constituting the feedback element is connected to the input unit of the inverter circuit, and the source electrode is connected to the output unit of the inverter circuit.
  3. 　前記インバータ回路を構成する前記トランジスタの伝導型がＮ型であり、
    　前記帰還素子を構成する前記トランジスタのドレイン電極が前記インバータ回路の前記出力部に、ソース電極が前記インバータ回路の前記入力部にそれぞれ接続されている請求項１に記載の増幅回路。     The conduction type of the transistor constituting the inverter circuit is N type.
    The amplifier circuit according to claim 1, wherein the drain electrode of the transistor constituting the feedback element is connected to the output unit of the inverter circuit, and the source electrode is connected to the input unit of the inverter circuit.
  4. 　前記帰還素子を構成する前記トランジスタのゲートしきい値電圧の絶対値が、接地電位と前記インバータ回路の電源電圧との間の値である請求項１ないし３のいずれかに記載の増幅回路。 The amplifier circuit according to any one of claims 1 to 3, wherein the absolute value of the gate threshold voltage of the transistor constituting the feedback element is a value between the ground potential and the power supply voltage of the inverter circuit.
  5. 　前記インバータ回路および前記帰還素子を構成する前記トランジスタが、有機半導体トランジスタである請求項１ないし４のいずれかに記載の増幅回路。 The amplifier circuit according to any one of claims 1 to 4, wherein the inverter circuit and the transistor constituting the feedback element are organic semiconductor transistors.
  6. 　前記インバータ回路および前記帰還素子を構成する前記トランジスタが、互いに同一の製造プロセスにより同時に形成された請求項１ないし５のいずれかに記載の増幅回路。 The amplifier circuit according to any one of claims 1 to 5, wherein the inverter circuit and the transistors constituting the feedback element are simultaneously formed by the same manufacturing process.
PCT/JP2020/009594 2019-03-28 2020-03-06 Amplifier circuit WO2020195694A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021508932A JP7148102B2 (en) 2019-03-28 2020-03-06 amplifier circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-062242 2019-03-28
JP2019062242 2019-03-28

Publications (1)

Publication Number Publication Date
WO2020195694A1 true WO2020195694A1 (en) 2020-10-01

Family

ID=72610077

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/009594 WO2020195694A1 (en) 2019-03-28 2020-03-06 Amplifier circuit

Country Status (2)

Country Link
JP (1) JP7148102B2 (en)
WO (1) WO2020195694A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794953A (en) * 1993-09-20 1995-04-07 Fujitsu Ltd Mos inverting amplifier circuit
WO2003003461A1 (en) * 2001-06-27 2003-01-09 Renesas Technology Corp. Semiconductor integrated circuit device and method for reducing noise
JP2007104367A (en) * 2005-10-05 2007-04-19 National Institute Of Advanced Industrial & Technology Multi-input cmos amplifier using insulated gate field effect transistor, high-gain multi-input cmos amplifier, highly stable multi-input cmos amplifier, high-gain highly stable multi-input cmos amplifier, and multi-input cmos differential amplifier
WO2009147770A1 (en) * 2008-06-02 2009-12-10 パナソニック株式会社 Clock signal amplifier circuit
JP2015169815A (en) * 2014-03-07 2015-09-28 セイコーエプソン株式会社 Actuator device, tactile display and drive method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111211781B (en) * 2020-02-10 2021-01-15 华南理工大学 Switch capacitor comparator based on thin film transistor, method and chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794953A (en) * 1993-09-20 1995-04-07 Fujitsu Ltd Mos inverting amplifier circuit
WO2003003461A1 (en) * 2001-06-27 2003-01-09 Renesas Technology Corp. Semiconductor integrated circuit device and method for reducing noise
JP2007104367A (en) * 2005-10-05 2007-04-19 National Institute Of Advanced Industrial & Technology Multi-input cmos amplifier using insulated gate field effect transistor, high-gain multi-input cmos amplifier, highly stable multi-input cmos amplifier, high-gain highly stable multi-input cmos amplifier, and multi-input cmos differential amplifier
WO2009147770A1 (en) * 2008-06-02 2009-12-10 パナソニック株式会社 Clock signal amplifier circuit
JP2015169815A (en) * 2014-03-07 2015-09-28 セイコーエプソン株式会社 Actuator device, tactile display and drive method

Also Published As

Publication number Publication date
JP7148102B2 (en) 2022-10-05
JPWO2020195694A1 (en) 2021-11-18

Similar Documents

Publication Publication Date Title
JP5253275B2 (en) Amplifier circuit for condenser microphone
US5057722A (en) Delay circuit having stable delay time
US7317358B2 (en) Differential amplifier circuit
WO2007043389A1 (en) Cmos amplifier using 4-terminal dual insulating gate field-effect transistor, multi-input cmos amplifier using the same, high-gain multi-input cmos amplifier, high-gain highly-stable multi-input cmos amplifier, and multi-input cmos differential amplifier
US8258868B2 (en) Differential input for ambipolar devices
US6545502B1 (en) High frequency MOS fixed and variable gain amplifiers
GB2126817A (en) Differential amplifier
WO2020195694A1 (en) Amplifier circuit
GB2134737A (en) Amplifier
JPH04127467A (en) Semiconductor integrated circuit device
US8072268B2 (en) Operational amplifier
JP2006245740A (en) Amplifier circuit and electret condenser microphone using same
US4785258A (en) CMOS amplifier circuit which minimizes power supply noise coupled via a substrate
JP3145650B2 (en) Operational amplifier phase compensation circuit and operational amplifier using the same
US20050231275A1 (en) Operational amplifier
US5682120A (en) Differential amplifier circuit using lateral-type bipolar transistors with back gates
US6982597B2 (en) Differential input circuit
US10461702B2 (en) Amplifier circuit having poly resistor with biased depletion region
JP2009147501A (en) Semiconductor device
JP2023018971A (en) Amplifier circuit and method of manufacturing the same
CN110263468B (en) On-chip CMOS capacitor and chip
US6492866B1 (en) Electronic circuit with bulk biasing for providing accurate electronically controlled resistance
JP4686758B2 (en) Multi-input CMOS amplifier using insulated gate field effect transistor and high-gain multi-input CMOS amplifier, high-stable multi-input CMOS amplifier, high-gain high-stable multi-input CMOS amplifier, multi-input CMOS differential amplifier using the same
TWI763688B (en) Input device
JP2894964B2 (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20777825

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021508932

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20777825

Country of ref document: EP

Kind code of ref document: A1