CN111211781B - Switch capacitor comparator based on thin film transistor, method and chip - Google Patents
Switch capacitor comparator based on thin film transistor, method and chip Download PDFInfo
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- CN111211781B CN111211781B CN202010084810.5A CN202010084810A CN111211781B CN 111211781 B CN111211781 B CN 111211781B CN 202010084810 A CN202010084810 A CN 202010084810A CN 111211781 B CN111211781 B CN 111211781B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Abstract
The invention discloses a switch capacitor comparator based on a thin film transistor, a method and a chip, wherein the comparator comprises a phase inverter module, a switch module, a first capacitor and a second capacitor, and the switch module comprises a first thin film transistor, a second thin film transistor and a third thin film transistor; the source electrode of the third thin film transistor is respectively connected with the source electrode of the first thin film transistor, one end of the first capacitor and one end of the second capacitor, the drain electrode of the first thin film transistor is connected with the reference voltage, the other end of the second capacitor is respectively connected with the input end of the phase inverter module and the drain electrode of the second thin film transistor, and the source electrode of the second thin film transistor is connected with the output end of the phase inverter module. The invention adopts three thin film transistors as switches, effectively controls the on and off of the switches through an external clock signal, and divides the working process of the comparator into a sampling process and a comparison process, thereby improving the resolution of the comparator and being widely applied to the field of integrated circuits.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a switched capacitor comparator based on a thin film transistor, a method and a chip.
Background
Metal oxide thin film transistors (MO-TFTs) have been rapidly developed in recent years, because they have advantages of low manufacturing cost, good light transmittance, and capability of being formed on flexible substrates. The MO-TFT based high-resolution comparator can be applied to an analog-to-digital converter (ADC), and the resolution of the comparator is determined by the highest number of bits that the ADC can reach. The method has wide application prospect in the fields of biomedical electric signals such as electroencephalogram EEG (0-100 hz), electrocardiogram ECG (0-150 hz) and electromyogram (20-500 hz), touch sensor arrays and the like.
Limited by the development of the process manufacturing level, the existing metal oxide thin film transistor can only manufacture an n-type device, and the absence of a complementary device, namely a p-type TFT, makes it difficult for a comparator with a traditional structure based on TFT design to achieve high resolution, which is undoubtedly a very important performance index of the comparator.
The noun explains:
pseudo CMOS: the output transistors are controlled by the preceding stage transistors, so that two output transistors can achieve a complementary cut-off structure similar to a Complementary Metal Oxide Semiconductor (CMOS).
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a switched capacitor comparator with high resolution, a control method, a design method and a chip.
The technical scheme adopted by the invention is as follows:
a switch capacitor comparator based on a thin film transistor comprises an inverter module, a switch module, a first capacitor and a second capacitor, wherein the switch module comprises a first thin film transistor, a second thin film transistor and a third thin film transistor;
the drain electrode of the third thin film transistor is used as a signal input end of the comparator, a third clock signal is input to the gate electrode of the third thin film transistor, the source electrode of the third thin film transistor is respectively connected with the source electrode of the first thin film transistor, one end of the first capacitor and one end of the second capacitor, the first clock signal is input to the gate electrode of the first thin film transistor, the drain electrode of the first thin film transistor is connected with a reference voltage, the other end of the first capacitor is grounded, the other end of the second capacitor is respectively connected with the input end of the inverter module and the drain electrode of the second thin film transistor, the second clock signal is input to the gate electrode of the second thin film transistor, the source electrode of the second thin film transistor is connected with the output end of the inverter module, and the output end of the inverter module is used as the output end of the comparator.
Further, the phase inverter module comprises a plurality of pseudo CMOS phase inverters connected in series, and each pseudo CMOS phase inverter comprises a plurality of thin film transistors.
Further, the pseudo CMOS inverter includes a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
the drain electrode of the fourth thin film transistor is connected with a first voltage, the gate electrode of the fourth thin film transistor is connected with the source electrode, the source electrode of the fourth thin film transistor is respectively connected with the drain electrode of the fifth thin film transistor and the gate electrode of the sixth thin film transistor, the gate electrode of the fifth thin film transistor is connected with the gate electrode of the seventh thin film transistor, the drain electrode of the sixth thin film transistor is connected with a second voltage, the source electrode of the sixth thin film transistor is connected with the drain electrode of the seventh thin film transistor, the source electrode of the fifth thin film transistor and the source electrode of the seventh thin film transistor are both grounded, the gate electrode of the fifth thin film transistor serves as the input end of the pseudo CMOS inverter, and the source electrode of the sixth thin film transistor serves as the output end of the pseudo CMOS inverter.
Further, the first voltage is an adjustable voltage.
Further, the phase inverter module comprises a first pseudo CMOS phase inverter, a second pseudo CMOS phase inverter and a third pseudo CMOS phase inverter, wherein the input end of the first pseudo CMOS phase inverter is used as the input end of the phase inverter module, the output end of the first pseudo CMOS phase inverter is connected with the input end of the second pseudo CMOS phase inverter, the output end of the second pseudo CMOS phase inverter is connected with the input end of the third pseudo CMOS phase inverter, and the output end of the third pseudo CMOS phase inverter is used as the output end of the phase inverter module.
Further, all the thin film transistors are n-type thin film transistors.
The other technical scheme adopted by the invention is as follows:
a chip comprises a clock module and a comparator, wherein the clock module is connected with the comparator, and the comparator adopts the switch capacitor comparator based on the thin film transistor.
Further, the clock module comprises a first clock unit, a second clock unit and a third clock unit;
the first clock unit is connected with a grid electrode of the first thin film transistor, the second clock unit is connected with a grid electrode of the second thin film transistor, and the third clock unit is connected with a grid electrode of the third thin film transistor;
when the sampling circuit is in a sampling phase, the first clock unit and the second clock unit output high levels, and the third clock unit outputs low levels;
when the comparison stage is in, the first clock unit and the second clock unit output low level, and the third clock unit outputs high level.
The other technical scheme adopted by the invention is as follows:
a control method of a switch capacitor comparator based on a thin film transistor comprises a sampling stage and a comparison stage;
while in the sampling phase:
controlling the first thin film transistor and the second thin film transistor to be started, controlling the third thin film transistor to be disconnected, and collecting reference voltage;
when in the comparison phase:
and controlling the first thin film transistor and the second thin film transistor to be disconnected, controlling the third thin film transistor to be started, collecting input voltage, comparing the input voltage with reference voltage, and outputting a comparison result.
The other technical scheme adopted by the invention is as follows:
a design method of a switched capacitor comparator based on a thin film transistor comprises the following steps:
acquiring the frequency of a clock signal according to the frequency of an input signal, wherein the frequency of the clock signal is greater than or equal to twice the frequency of the input signal;
and acquiring the amplification gain of the inverter module according to the preset resolution, and acquiring the series of pseudo CMOS inverters connected in the inverter module in series according to the amplification gain.
The invention has the beneficial effects that: the invention adopts three thin film transistors as switches, effectively controls the on and off of the switches through an external clock signal, and divides the working process of the comparator into a sampling process and a comparison process, thereby improving the resolution of the comparator.
Drawings
FIG. 1 is a schematic circuit diagram of a switched capacitor comparator based on a thin film transistor according to an embodiment;
FIG. 2 is a schematic circuit diagram of a pseudo CMOS inverter according to an embodiment;
FIG. 3 is a schematic circuit diagram of an inverter module according to an embodiment;
FIG. 4 is a simulation of DC bias of an inverter module in an embodiment;
FIG. 5 shows the comparator at f in the exampleCLK＝1Khz，ΔVATransient simulation diagram at 100 mV;
FIG. 6 shows the comparator at f in the exampleCLK＝1Khz，ΔVATransient simulation schematic at 24 mV;
FIG. 7 is a graph showing the relationship between the resolution of the comparator and the sampling frequency in the embodiment;
fig. 8 is a flowchart illustrating steps of a method for designing a tft-based switched capacitor comparator according to an embodiment.
Detailed Description
As shown in fig. 1, the present embodiment provides a thin film transistor-based switched capacitor comparator, including an inverter module, a switching module, a first capacitor C1 and a second capacitor C2, wherein the switching module includes a first thin film transistor T1, a second thin film transistor T2 and a third thin film transistor T3;
the drain of the third thin film transistor T3 serves as a signal input terminal of the comparator, the gate of the third thin film transistor T3 inputs the third clock signal CLK3, a source of the third thin film transistor T3 is connected to a source of the first thin film transistor T1, one end of the first capacitor C1 and one end of the second capacitor C2, the gate of the first thin film transistor T1 is inputted with a first clock signal CLK1, the drain of the first thin film transistor T1 is connected with a reference voltage, the other end of the first capacitor C1 is grounded, the other end of the second capacitor C2 is respectively connected with the input end of the inverter module and the drain electrode of the second thin film transistor T2, the gate of the second thin film transistor T2 inputs a second clock signal CLK2, and the source of the second thin film transistor T2 is connected to the output terminal of the inverter module, which serves as the output terminal of the comparator.
In this embodiment, the first capacitor is a first coupling capacitor, and the second capacitor is a second coupling capacitor, which has the function of blocking direct current and alternating current. The switchThe first thin film transistor, the second thin film transistor and the third thin film transistor in the module are controlled by a clock signal, when a clock CLK connected with a grid electrode is in a high level, the switch is closed, the transistors are in a conducting state, and when the clock CLK is in a low level, the switch is opened, and the transistors are in a cut-off state. The comparator operation is divided into two phases: the first phase is a sampling phase, in which the first clock signal CLK1 and the second clock signal CLK2 are turned on to control the first thin film transistor T1 and the second thin film transistor T2 to be turned on, and the third clock signal CLK3 is turned on to control the third thin film transistor T3 to be turned off. Since the first TFT T1 is turned on, the voltage at the point A is equal to the reference voltage VrefI.e. VA＝VrefSince the points B and C are the input node and the output node of the inverter module, the voltages at the two points are directly leveled to be equal potential during the sampling period when the switch T2 is turned on, i.e. the points B and C are the input node and the output node of the inverter module
The voltage V at this stage is due to the DC blocking and AC flowing effect of the second coupling capacitor C2A≠VB. The second phase is a comparison phase, in which the first clock signal CLK1 and the second clock signal CLK2 are switched to a low level to control the first thin film transistor T1 and the second thin film transistor T2 to be turned off, and the third clock signal CLK3 is switched to a high level to control the third thin film transistor T3 to be turned on; at the moment, the voltage at the point A is measured by V in the sampling stagerefInput signal V jumping into comparison phaseinI.e. the amount of voltage-generated jump Δ V at point AA＝Vin-VrefBy utilizing the characteristic that voltage at two ends of the capacitor cannot change suddenly, voltage at point B can also change in the same size through the coupling effect of the second capacitor C2, and the jump quantity delta VB＝ΔVAChange amount Δ V of voltage at point BBThen the voltage V at the output end C point of the comparator is obtained through the amplification and the phase inversion of the phase inverter moduleCIs determined by the size of the sampling phase
Corresponding jump to high potential approaching VDDOr the low potential approaches 0, i.e.The digital signals correspond to high and low levels. Thus, when the input signal V of the comparator isinGreater than a reference voltage VrefI.e. Δ VAIf the voltage is positive, the output end is a low level signal after the voltage is amplified and inverted by the inverter module; when the input signal V of the comparator isinLess than reference voltage VrefI.e. Δ VAAnd when the voltage is negative, the output end is a high level signal after the voltage is amplified and inverted by the inverter module. Therefore, the input signal V can be input by the high-low level state of the output end of the comparatorinAnd a reference voltage VrefFor high resolution comparisons.
Resolution of comparator (minimum discrimination voltage MDU), i.e. input voltage V which causes two level state transitions at outputinAnd a reference voltage VrefDifference value of (Δ V)A) The resolution depends on the magnitude of the dc gain of the inverter module. In order to increase the dc gain of the inverter module, the inverter module may be formed by using multi-stage pseudo CMOS inverters, and as shown in fig. 3, the inverter module of the present embodiment is formed by connecting 3-stage pseudo CMOS inverters in series. Specifically, the method comprises the following steps:
the phase inverter module comprises a first pseudo CMOS phase inverter, a second pseudo CMOS phase inverter and a third pseudo CMOS phase inverter, wherein the input end of the first pseudo CMOS phase inverter is used as the input end of the phase inverter module, the output end of the first pseudo CMOS phase inverter is connected with the input end of the second pseudo CMOS phase inverter, the output end of the second pseudo CMOS phase inverter is connected with the input end of the third pseudo CMOS phase inverter, and the output end of the third pseudo CMOS phase inverter is used as the output end of the phase inverter module.
The Pseudo CMOS inverter may be implemented by using inverters with various structures, in this embodiment, the Pseudo CMOS inverter uses a D-type Pseudo CMOS (Pseudo-D) inverter cascade, as shown in fig. 2, specifically:
the dummy CMOS inverter includes a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7;
a drain of the fourth thin film transistor T4 is connected to a first voltage, a gate of the fourth thin film transistor T4 is connected to a source thereof, a source of the fourth thin film transistor T4 is connected to a drain of the fifth thin film transistor T5 and a gate of the sixth thin film transistor T6, respectively, a gate of the fifth thin film transistor T5 is connected to a gate of the seventh thin film transistor T7, a drain of the sixth thin film transistor T6 is connected to a second voltage, a source of the sixth thin film transistor T6 is connected to a drain of the seventh thin film transistor T7, a source of the fifth thin film transistor T5 and a source of the seventh thin film transistor T7 are both grounded, a gate of the fifth thin film transistor T5 serves as an input terminal of the pseudo CMOS inverter, and a source of the sixth thin film transistor T6 serves as an output terminal of the pseudo CMOS inverter.
Wherein the gate and the source of the fourth thin film transistor T4 are connected, i.e. the gate-source voltage V gs0, so the power consumption is low; a first voltage VssAdjustable to further increase the output swing, in this embodiment, the second voltage is the supply voltage VDD. In addition, the inverter with the structure has larger direct current gain, can effectively improve the circuit gain, and provides possibility for realizing high resolution for the comparator.
Further as an alternative embodiment, all the thin film transistors are n-type thin film transistors. Only one type of transistor is needed to realize the method, so that the requirements on the process and the production are greatly reduced, and the cost is reduced.
The above comparator is described in detail below with reference to a simulation example.
By reasonably setting the width-to-length ratio of the inverter module thin film transistor, the inverter module thin film transistor is subjected to direct current simulation, and the output signal is differentiated, so that the obtained simulation result is shown in figure 4. It can be seen that the intersection of the input signal and the output signal is located
Nearby, the inverter module works in the region with the largest direct current gain which is 49.73 times, the possibility of realizing high resolution of the comparator is provided, and the high level state of the output signal approaches to the power supply voltage VDDThe low state approaches 0.
The working state of the thin film transistor is controlled by clock signals given by the gate electrodes of the thin film transistors T1-T3, and therefore the function that the ratio of the input signal to the reference voltage is large is achieved. According to the sampling theorem, the frequency f of the clock signalCLKShould be greater than or equal to the input signal frequency
Twice as much, i.e.
In this example, take
I.e. period
Reference voltage in VrefTake 3V as an example. First, the sampling frequency is 1Khz, i.e. fCLKWhen the input signal is at high level 3.1V and low level 2.9V, i.e., Δ V, 1KhzAWhen 100mV is obtained, transient simulation is performed on the comparator, and the simulation result is shown in fig. 5. From the simulation results, it can be seen that the comparator can perform resolution normally at a sampling frequency of 1Khz and a resolution of 100 mV. Further, the input signal V is continuously reducedinUntil the comparator cannot distinguish, at which time, the voltage is Δ VANamely the minimum discrimination voltage (MDU) that the comparator can distinguish under the condition, the minimum discrimination voltage of the comparator of the invention is 24mV under the condition of sampling frequency 1Khz and reference voltage 3V through transient simulation, namely the simulation result with resolution of 24mV. is shown in fig. 6.
In order to study the relationship between the resolution and the sampling frequency of the switched capacitor comparator of the pseudo-CMOS structure of the present invention, the sampling frequency f is taken separatelyCLK200hz, 500hz, 1Khz, 2Khz, 3Khz, 4Khz and 5Khz at a reference voltage VrefTransient simulation was performed on the comparator under the condition of 3V, and the obtained resolutions of 23mV, 24mV, 30mV, 35mV, 120mV, and 500mV. were plotted as curves of the relation between the sampling frequency and the resolution (minimum discrimination voltage MDU), respectively, as shown in fig. 7. Thus, the invention is falseThe minimum discrimination voltage value of the switched capacitor comparator with the CMOS structure is increased along with the increase of the sampling frequency, and in the region of the sampling frequency of less than 3Khz, the resolution of the switched capacitor comparator with the pseudo CMOS structure of the embodiment is maintained to be about 30mV, and the resolution can meet the requirements of most fields.
In summary, the switched capacitor comparator of the present embodiment has at least the following beneficial effects:
(1) the D-type Pseudo CMOS inverter (Pseudo-D) used in this embodiment has the advantages of low power consumption, high gain, wide output swing, and the like.
(2) In the inverter module of the embodiment, three D-type Pseudo CMOS inverters (Pseudo-D) are cascaded, so that the gain and the output swing of the whole circuit are remarkably improved, and the high level state of an output signal approaches to the power supply voltage VDDThe low state approaches 0.
(3) In the embodiment, three switches of the thin film transistor are utilized, the on and off of the switches are effectively controlled through an external clock signal, the working process of the comparator is divided into a sampling process and a comparison process, and the quality of the comparator is improved.
(4) The coupling capacitor in this embodiment effectively stores the electrical signal and couples the difference between the input signal and the reference voltage to the input node of the inverter module.
The embodiment also provides a chip, which comprises a clock module and a comparator, wherein the clock module is connected with the comparator, and the comparator adopts the switch capacitor comparator based on the thin film transistor.
As a further optional implementation, the clock module includes a first clock unit, a second clock unit, and a third clock unit;
the first clock unit is connected with a grid electrode of the first thin film transistor, the second clock unit is connected with a grid electrode of the second thin film transistor, and the third clock unit is connected with a grid electrode of the third thin film transistor;
when the sampling circuit is in a sampling phase, the first clock unit and the second clock unit output high levels, and the third clock unit outputs low levels;
when the comparison stage is in, the first clock unit and the second clock unit output low level, and the third clock unit outputs high level.
The chip of the embodiment corresponds to the thin film transistor-based switched capacitor comparator, and has corresponding functions and beneficial effects.
The embodiment also provides a control method of the switch capacitor comparator based on the thin film transistor, which comprises a sampling stage and a comparison stage;
while in the sampling phase:
controlling the first thin film transistor and the second thin film transistor to be started, controlling the third thin film transistor to be disconnected, and collecting reference voltage;
when in the comparison phase:
and controlling the first thin film transistor and the second thin film transistor to be disconnected, controlling the third thin film transistor to be started, collecting input voltage, comparing the input voltage with reference voltage, and outputting a comparison result.
The control method of the thin film transistor-based switched capacitor comparator of the present embodiment has a corresponding relationship with the thin film transistor-based switched capacitor comparator provided in the foregoing, and has corresponding functions and advantageous effects of the comparator.
As shown in fig. 8, the present embodiment further provides a design method of a switched capacitor comparator based on a thin film transistor, including the following steps:
s1, acquiring the frequency of a clock signal according to the frequency of the input signal, wherein the frequency of the clock signal is greater than or equal to twice the frequency of the input signal;
and S2, acquiring the amplification gain of the inverter module according to the preset resolution, and acquiring the series of pseudo CMOS inverters connected in the inverter module in series according to the amplification gain.
The design method of the thin film transistor-based switched capacitor comparator of the present embodiment has a corresponding relationship with the thin film transistor-based switched capacitor comparator provided above, and has corresponding functions and beneficial effects of the comparator.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A switched capacitor comparator based on a thin film transistor is characterized by comprising an inverter module, a switch module, a first capacitor and a second capacitor, wherein the switch module comprises a first thin film transistor, a second thin film transistor and a third thin film transistor;
the drain electrode of the third thin film transistor is used as a signal input end of the comparator, a third clock signal is input to the gate electrode of the third thin film transistor, the source electrode of the third thin film transistor is respectively connected with the source electrode of the first thin film transistor, one end of the first capacitor and one end of the second capacitor, the first clock signal is input to the gate electrode of the first thin film transistor, the drain electrode of the first thin film transistor is connected with a reference voltage, the other end of the first capacitor is grounded, the other end of the second capacitor is respectively connected with the input end of the inverter module and the drain electrode of the second thin film transistor, the second clock signal is input to the gate electrode of the second thin film transistor, the source electrode of the second thin film transistor is connected with the output end of the inverter module, and the output end of the inverter module is used as the output end of the comparator.
2. The thin film transistor-based switched capacitor comparator as claimed in claim 1, wherein the inverter module comprises a plurality of dummy CMOS inverters connected in series, each of the dummy CMOS inverters comprising a plurality of thin film transistors.
3. The thin film transistor-based switched capacitor comparator as claimed in claim 2, wherein the pseudo CMOS inverter comprises a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and a seventh thin film transistor;
the drain electrode of the fourth thin film transistor is connected with a first voltage, the gate electrode of the fourth thin film transistor is connected with the source electrode, the source electrode of the fourth thin film transistor is respectively connected with the drain electrode of the fifth thin film transistor and the gate electrode of the sixth thin film transistor, the gate electrode of the fifth thin film transistor is connected with the gate electrode of the seventh thin film transistor, the drain electrode of the sixth thin film transistor is connected with a second voltage, the source electrode of the sixth thin film transistor is connected with the drain electrode of the seventh thin film transistor, the source electrode of the fifth thin film transistor and the source electrode of the seventh thin film transistor are both grounded, the gate electrode of the fifth thin film transistor serves as the input end of the pseudo CMOS inverter, and the source electrode of the sixth thin film transistor serves as the output end of the pseudo CMOS inverter.
4. The thin film transistor-based switched capacitor comparator as claimed in claim 3, wherein the first voltage is an adjustable voltage.
5. The thin film transistor-based switched capacitor comparator as claimed in claim 3, wherein the inverter module comprises a first dummy CMOS inverter, a second dummy CMOS inverter and a third dummy CMOS inverter, wherein an input terminal of the first dummy CMOS inverter is used as an input terminal of the inverter module, an output terminal of the first dummy CMOS inverter is connected to an input terminal of the second dummy CMOS inverter, an output terminal of the second dummy CMOS inverter is connected to an input terminal of the third dummy CMOS inverter, and an output terminal of the third dummy CMOS inverter is used as an output terminal of the inverter module.
6. A switched capacitor comparator based on thin film transistors according to any of claims 1-5, characterized in that all thin film transistors are n-type thin film transistors.
7. A chip comprising a clock module and a comparator, wherein the clock module is connected with the comparator, and the comparator adopts a switched capacitor comparator based on a thin film transistor as claimed in any one of claims 1 to 6.
8. The chip of claim 7, wherein the clock module comprises a first clock unit, a second clock unit, and a third clock unit;
the first clock unit is connected with a grid electrode of the first thin film transistor, the second clock unit is connected with a grid electrode of the second thin film transistor, and the third clock unit is connected with a grid electrode of the third thin film transistor; when the sampling circuit is in a sampling phase, the first clock unit and the second clock unit output high levels, and the third clock unit outputs low levels;
when the comparison stage is in, the first clock unit and the second clock unit output low level, and the third clock unit outputs high level.
9. A control method based on the switched capacitor comparator of claim 1, comprising a sampling phase and a comparison phase;
while in the sampling phase:
controlling the first thin film transistor and the second thin film transistor to be started, controlling the third thin film transistor to be disconnected, and collecting reference voltage;
when in the comparison phase:
and controlling the first thin film transistor and the second thin film transistor to be disconnected, controlling the third thin film transistor to be started, collecting input voltage, comparing the input voltage with reference voltage, and outputting a comparison result.
10. A method for designing a switched capacitor comparator according to claim 2, comprising the steps of:
acquiring the frequency of a clock signal according to the frequency of an input signal, wherein the frequency of the clock signal is greater than or equal to twice the frequency of the input signal;
and acquiring the amplification gain of the inverter module according to the preset resolution, and acquiring the series of pseudo CMOS inverters connected in the inverter module in series according to the amplification gain.
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