CN101320975B - Ultra-low power consumption comparer based on time domain - Google Patents
Ultra-low power consumption comparer based on time domain Download PDFInfo
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- CN101320975B CN101320975B CN200810114513XA CN200810114513A CN101320975B CN 101320975 B CN101320975 B CN 101320975B CN 200810114513X A CN200810114513X A CN 200810114513XA CN 200810114513 A CN200810114513 A CN 200810114513A CN 101320975 B CN101320975 B CN 101320975B
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Abstract
A ultralow power dissipation analog to digital converter based on the time domain belongs to the field of the ultralow power dissipation analog to digital converter, characterized in that, on the basis of the available voltage-time converter VTC, an inversion signal CLKN and a feedback signal of reference output or a NOR gate NOR1 are controlled by a clock control signal CCLK, to cause the discharging process with different speed of the capacitance C1, the capacitance C2 to be interrupted, thereby accordingly advancing the working speed of the comparator.
Description
Technical field
" based on the ultra-low power consumption comparer of time-domain " direct applied technical field is the design of super low-power consumption analog-digital converter circuit, and the circuit that proposes is the important module that a class goes for main high-speed low-power-consumption ADC structure.
Background technology
Wireless sensor network (WSN) has application more and more widely in society and natural environment.Because the reliability that wireless sensor network has and the advantage of accuracy, especially emphasis is applied to military affairs, national security, fields such as medical treatment and environment perception.General wireless sensor network all is made up of a large amount of sensor nodes, makes power consumption become the important restrictions of sensor network design thus.Therefore, require that each module must consume very low energy in the sensor node.
A general integrated analog-digital converter (ADC) becomes digital signal to the analog signal conversion from transducer and is carried out next step processing by processor in the WSN node.In order to reach the requirement of super low-power consumption, non-limiting examples of suitable DC also should be a super low-power consumption.(document Benton H.Calhoun sees reference, Denis C.Daly, Naveen Verma, Daniel F.Finchelstein, DavidD.Wentzloff, Alice Wang, Seong-Hwan Cho, and Anantha P.Chandrakasan, " DesignConsiderations for Ultra-Low Energy Wireless Microsensor Nodes ") successive approximation type a/d C (SARADC) is a kind of suitable circuit structure of realizing super low-power consumption ADC.This is because SAR ADC hardware circuit is fewer, includes only three modules: digital analog converter (DAC), comparator and digital logic module.Wherein, comparator module is the maximum module of consumed energy.
The tradition comparator is earlier input voltage to be converted to electric current then this electric current to be converted to voltage again, uses low-power consumption latch (latch) at a high speed to come voltage to gained to compare at last and obtains the result.When carrying out optimised power consumption, this comparator performance has very big decline.In order to reduce the imbalance of this comparator, can be in one or several amplifier of latch front; But this method can be introduced bigger power consumption and complexity.(document Naveen Verma sees reference, and Anantha P.Chandrakasan, " AnUltra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes ", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.42, NO.6, JUNE 2007).
In order to overcome the above problems, can adopt comparator (TDC) based on time-domain.This comparator configuration is very simple and consumed energy is very low, and can be applied in the design of super low-power consumption SAR ADC.The mode of operation of this comparator is different from traditional comparator.It at first uses a voltage-time change-over circuit (VTC) that input voltage is converted to the time, by a trigger time is made comparisons again then or locks.Representative work comprises, a kind of comparator that Andrea Agnes et al proposes based on time-domain. (document Andrea Agnes sees reference, Edoardo Bonizzoni, Piero Malcovati and Franco Maloberti, " A 9.4-ENOB 1V 3.8 μ W 100kSs SAR ADC with Time domain comparator ", 2008 IEEEInternational Solid-State Circuits Conference) though. the time-domain comparator that Andrea Agnes is proposed can reach very low power consumption, but have two very big shortcomings: at first, the maximum speed of this comparator work has only 1.875MHz., and this makes the high sampling rate of ADC have only 100KS/s.Second problem is can waste a lot of energy in comparison procedure; This is because after comparator was made comparative result, VTC can continue discharge.
Summary of the invention
The objective of the invention is on the basis of existing time-domain comparator circuit, to make certain improvements, propose a kind of time-domain comparator configuration based on dynamic electric voltage-time converter.
The invention is characterized in: it contains: dynamic electric voltage-time change-over circuit and triggering feedback control circuit, wherein:
Described dynamic electric voltage-time change-over circuit comprises reference section, importation and feedback fraction;
Described reference section, contain: a PMOS manages M1, the 2nd PMOS manages M3, the one NMOS manages M5, the 2nd NMOS manages M7, the 3rd PMOS manages M9, the 3rd NMOS manages M11, first resistance R 1 and first capacitor C 1, wherein, the source electrode of described PMOS pipe (M1) meets supply voltage Vdd, the drain electrode of the one PMOS pipe M1 links to each other with the source electrode of described the 2nd PMOS pipe M3, the drain electrode of the 2nd PMOS pipe M3 links to each other with the source electrode of described NMOS pipe M5, the drain electrode of the one NMOS pipe M5 links to each other with the source electrode of described the 2nd NMOS pipe M7, the drain electrode of the 2nd NMOS pipe M7 is through first resistance R, 1 ground connection, the grid of described PMOS pipe M1 links to each other with the drain electrode of described the 2nd PMOS pipe M3, the grid incoming reference signal VREF of described the 2nd NMOS pipe M7, the source electrode of described the 3rd PMOS pipe M9 meets described supply voltage Vdd, the drain electrode of the 3rd PMOS pipe M9 links to each other with the source electrode of described the 3rd NMOS pipe M11, and the grounded drain of the 3rd NMOS pipe M11, in described reference section, the grid of described the 3rd PMOS pipe M9 connects described first capacitor C 1 more over the ground with after the drain electrode of described the 2nd PMOS pipe M3 links to each other;
Described importation, contain: the 4th PMOS manages M2, the 5th PMOS manages M4, the 4th NMOS manages M6, the 5th NMOS manages M8, the 6th PMOS manages M10, the 6th NMOS manages M12, second resistance R 2 and second capacitor C 2, wherein, the source electrode of described the 4th PMOS pipe M2 meets described supply voltage Vdd, and the drain electrode of the 4th PMOS pipe M2 connects the source electrode of described the 5th PMOS pipe M4, and the drain electrode of the 5th PMOS pipe M4 connects the source electrode of described the 4th NMOS pipe M6, and the drain electrode of the 4th NMOS pipe M6 connects the source electrode of described the 5th NMOS pipe M8, and the drain electrode of the 5th NMOS pipe M8 is through described second resistance R, 2 ground connection, the grid of described the 4th PMOS pipe M2 links to each other with the drain electrode of described the 5th PMOS pipe M4, the source electrode of described the 6th PMOS pipe M10 meets described supply voltage Vdd, and the drain electrode of the 6th PMOS pipe M10 links to each other with the source electrode of described the 6th NMOS pipe M12, and the grounded drain of the 6th NMOS pipe M12, after the drain electrode that the grid of described the 6th PMOS pipe M10 and described the 5th PMOS manage (M4) links to each other, connect described second capacitor C 2 more over the ground, the grid of described the 5th NMOS pipe M8 inserts input signal VIN;
The inversion signal CLKN of the described clock control signal CCLK of access after the grid of the 3rd NMOS pipe among the grid of the 2nd PMOS pipe M3 in the grid of the 5th PMOS in described importation pipe M4 and the described reference section back incoming clock control signal CCLK that links to each other, the grid of the 6th NMOS pipe M12 in the described importation and described reference section links to each other;
Described feedback fraction contains: NOR gate NOR1 and the 5th inverter I5, first input input of this NOR gate NOR1
The timeThe inversion signal CLKN of clock system signal CCLK, the inversion signal CLKN of this clock control signal CCLK is from the output of described the 5th inverter I5, the described clock control signal CCLK of the input termination of the 5th inverter I5, the output of this NOR gate NOR1 simultaneously with described reference section in NMOS pipe M5 link to each other with the grid of the 4th NMOSM6 in the described importation;
Described triggering feedback control circuit, contain: the first inverter I1 of series connection and the second inverter I2, the 3rd inverter I3 and the 4th inverter I4 of series connection, and trigger DFF, wherein: the drain electrode of the 6th PMOS pipe M10 in the described importation of input termination of the described first inverter I1, and the output of the described second inverter I2 links to each other with the data terminal D of described trigger DFF, the input of described the 3rd inverter I3 links to each other with the drain electrode of the 3rd PMOS pipe M9 in the described reference section, and the output of described the 4th inverter I4 is also connected to second input of described NOR gate NOR1 simultaneously after the clock end CLK with described trigger DFF links to each other;
Under reset mode, clock control signal CCLK is a low level, and first capacitor C 1 is charged to the threshold voltage V that voltage on this first capacitor C 1 is slightly larger than described supply voltage Vdd and described PMOS pipe M1
TP1Poor, simultaneously second capacitor C 2 is charged to voltage on this second capacitor C 2 and is slightly larger than the threshold voltage V that described supply voltage Vdd and described the 4th PMOS manage M2
TP2Poor;
Under comparison pattern, clock control signal CCLK is a high level, first capacitor C 1 and second capacitor C 2 are discharged with friction speed, described d type flip flop DFF is according to the size output comparative result of input voltage VIN with respect to reference voltage VREF, and in described d type flip flop DFF locking, the discharge process on first capacitor C 1 and second capacitor C 2 is interrupted by described NOR gate NOR1.
The invention has the beneficial effects as follows: compare with traditional time-domain comparator configuration, the present invention propose based on DVTC time-domain comparator, under identical test condition part, can save energy up to 80%; Its operating rate has also improved 5 times simultaneously.The circuit engineering that is proposed is suitable as the important module of super low-power consumption SAR adc circuit very much.
Description of drawings
Fig. 1 .TDC comparator block diagram.VINP is an input signal, and VREF is a comparison reference voltage, and CCLK is a comparator control signal and COMPOUT is the output of comparator.
The TDC that Fig. 2 .Andrea Agnes is proposed.VIN, VREF, meaning and Fig. 1 of CCLK and COMPOUT are similar.
Fig. 3. circuit structure diagram of the present invention.CCLKN is the anti-phase of CCLK, all the other and Fig. 2 same meaning.
The electric current of Fig. 4 .TDC comparator: (a) traditional TDC electric current (b) electric current of the present invention.
Change in voltage on Fig. 5 .TDC electric capacity: (a) traditional TDC (b) the present invention.
Fig. 6. the comparative result of minimum voltage difference of the present invention.
Fig. 7. the comparative result of various input voltages.
Fig. 8. the general block diagram of analog-digital converter.
Fig. 9 SAR ADC block diagram.
Figure 10 Flash ADC block diagram.
Figure 11 Pipeline block diagram.
Figure 12 sigma-delta block diagram.
Figure 13 ADC block diagram in parallel.
Embodiment
The technical scheme that the present invention solves its technical problem is: the TDC that the present invention proposes based on dynamic electric voltage-time change-over circuit DVTC, as shown in Figure 3.TDC of the present invention has and adopts the DVTC technology to reduce the energy that change in voltage consumed on the electric capacity, and improves the maximum speed of comparator simultaneously.
Fig. 2 is the comparator circuit that Andrea Agnes proposes.Mainly by two the part forms: voltage-time converter VTC with
Trigger Device DFFVoltage-time converter is made up of two branch roads: the output of VTC Input and VTC Reference.VTC Input is through three inverter I1, I2 and I3 link the data terminal D of trigger DFF and the output of VTC Reference also through three inverter I4, I5 and I6 link the trigger end of trigger DFF.The work of comparator comprises two kinds of patterns.At first at reset mode, CCLK is low level and by M7 and M1 two capacitor C 1 and C2 is charged to Vdd. M11 and M5 ground connection simultaneously.At this moment the output of trigger is that the output of comparator remains unchanged.At comparison pattern, CCLK can become high level and open M2 and M8, turn-offs M1 simultaneously, M7, M5, M11. at this moment two electric capacity can begin to discharge and the speed of discharging by VIN and VREF decision.Be reduced to the threshold value V of PMOS when M2 or M8 grid voltage
TPThe time, corresponding pipe can be charged to Vdd to its drain node.After VTC Reference upset, can trigger DFF, obtain comparative result.Because DFF prolongs triggering in decline, so if VIN＞VREF, VTC Input is upset earlier, and COMPOUT obtains " 0 " after DFF is triggered.Make COMPOUT obtain " 1 " if VIN＜VREF, VTC Reference upset earlier triggers DFF, finish comparing function.This comparator is input voltage to be become postpone and the delay that produces is made comparisons.
The TDC technology is based on following equation.Wherein, Δ t charges the needed time to capacitor C, and Δ V is the variation of voltage in the electric smelting in Δ t, and I is an electric current.
The present invention is made up of dynamic electric voltage-time converter (DVTC) and a trigger.DVTC be the invention core and by two the part form.Reference section is by M1, M3, and M5, M7, M9, M11, resistance R 1 and capacitor C 1 formed, and the importation is by M2, and M4, M6, M8, M10, M12 resistance R 2 and capacitor C 2 are formed.
CCLK controls M5 and M6 grid voltage through signal CLKN and DVTC reference section output signal that anti-phase I5 obtains by a NOR gate NOR1.Two inverter I1 are passed through in two outputs of DVTC respectively, I2 and I3, and I4 links trigger, and output comparative result COMPOUT.
Operation principle of the present invention and traditional TDC are similar, also comprise two patterns: when reset mode, CCLK is that low spot is flat, and C1 and C2 are charged to till M1 and the M2 shutoff, and M9 and M10 also can be turned off simultaneously.Like this, the voltage on two electric capacity is slightly larger than V
Dd-V
TP. at this moment M11 and M12 also turn-off.When comparison pattern, CCLK becomes high level, M3, and M4, M11 is turned off with M12 and M5 opens with M6. and two electric capacity are with different speed discharges, and the output of DVTC is in different time reversals.When the DVTC reference section reverses (M9 conducting) just trigger DFF.Because two outputs of DVTC become high asynchronism(-nization), so and DFF can represent that signal arrive first relatively be time rather than direct comparative voltage.When reversing, can trigger the reference section of DVTC trigger locking comparative result.At this moment electric capacity does not need to have discharged again, so this signal can turn-off M5 and M6 by NOR gate.Why Here it is says that VTC is dynamic, and it work in the needs electric current and shutoff unwanted the time.Voltage range on the electric capacity just is controlled in the very little zone.From formula (1), this side has reduced the energy that is consumed greatly, and speed has improved greatly simultaneously.
In order to verify performance of the present invention and the improved effect of being brought, we have used spectre
TMEmulation tool carries out emulation to circuit.Simulation result is relatively referring to table 1.
Table 1: the comparator performance
| Andrea Agnes | The present invention | |
| Technology (um) | 0.18 | 0.18 |
| Supply voltage (V) | 0.8～1 | 0.8～1V |
| High operation speed (MHz) | 1.875 | 12.5 |
| Energy consumption (fJ) | 1312 | 241 |
| Andrea Agnes | The present invention | |
| Resolution (bits) | 12 | 13 |
| |
0～ |
0～V dd |
Fig. 4 (b) is a current drain situation of the present invention.Be different from traditional comparator, current duration is not whole half period, and promptly electric current only exists in needs, reduces power consumption thus.Fig. 5 (b) is that capacitance voltage of the present invention changes.No matter how many input voltages is, the voltage on the C1, VC1 is limited in 530～590mV, and C2 voltage VC2 is limited in 430～590mV.From
See that the energy of DVTC input part branch consumption is that 131fJ and reference section energy consumption are less than 60fJ.So it is 241fJ that the DFF energy consumption is about the total energy consumption of 50fJ comparator.Capacitor C=0.8pF wherein, electric current I=1.2uA.The energy consumption of the comparator that Andrea proposes is that 1312fJ. (energy consumption that does not comprise DFF) is of the present invention as can be seen to the energy minimizing that is higher than 80%.Aspect speed, the present invention can reach the speed of 12.5MHz.This is 6 times of traditional TDC speed.Fig. 6 represents that resolution of the present invention is 122uV.And Fig. 7 represents the comparative result of the present invention at different input voltages.VIN-VREF=-122uV between 2ns and 3ns, and at 3ns and 4ns, VIN-VREF=122uV.
This comparator circuit comprises: first circuit produces an output signal to first input voltage value.The generation time of input signal is by the size decision of input voltage.Second circuit, second input voltage produce one with the big or small relevant input signal of input voltage.Determine the trigger of first and second time of arrival (toa).The NOR gate that can adjust impulse electricity stream automatically.Can do some changes in fact and obtain different functions: comparator can have one or two output, and comparator output can become pulse maybe can be by obtaining direct current signal after the filtering.
Another one advantage of the present invention is that it is digital comparator, without any need for amplifier, and current source, electric capacity or resistance, and only constitute by transistor.In addition, the progression that increases the inverter of DVTC output can reduce the shake that comparator is exported.The present invention can use in various main ADC (Fig. 8) the insides.Comprise successive approximation analog to digital C (as Fig. 9), Flash ADC (as Figure 10), Pipeline ADC (as Figure 11) and sigma-delta ADC (as Figure 12), and ADC in parallel (as Figure 13).Each sub-ADC in Figure 11 and Figure 13 structure can adopt the ADC that adopts the DVTC technology among Fig. 9,10,11,12 according to application demand and performance requirement.
Claims (1)
1. based on the ultra-low power consumption comparer of time-domain, it is characterized in that, contain: dynamic electric voltage-time change-over circuit and triggering feedback control circuit, wherein:
Described dynamic electric voltage-time change-over circuit comprises reference section, importation and feedback fraction;
Described reference section, contain: a PMOS manages (M1), the 2nd PMOS manages (M3), the one NMOS manages (M5), the 2nd NMOS manages (M7), the 3rd PMOS manages (M9), the 3rd NMOS manages (M11), first resistance (R1) and first electric capacity (C1), wherein, the source electrode of described PMOS pipe (M1) connects supply voltage (Vdd), the drain electrode of the one PMOS pipe (M1) links to each other with the source electrode that described the 2nd PMOS manages (M3), the drain electrode of the 2nd PMOS pipe (M3) links to each other with the source electrode that a described NMOS manages (M5), the drain electrode of the one NMOS pipe (M5) links to each other with the source electrode that described the 2nd NMOS manages (M7), the drain electrode of the 2nd NMOS pipe (M7) is through first resistance (R1) ground connection, the grid of described PMOS pipe (M1) links to each other with the drain electrode that described the 2nd PMOS manages (M3), the grid incoming reference signal (VREF) of described the 2nd NMOS pipe (M7), the source electrode of described the 3rd PMOS pipe (M9) connects described supply voltage (Vdd), the drain electrode of the 3rd PMOS pipe (M9) links to each other with the source electrode that described the 3rd NMOS manages (M11), and the grounded drain of the 3rd NMOS pipe (M11), in described reference section, after the drain electrode that the grid of described the 3rd PMOS pipe (M9) and described the 2nd PMOS manage (M3) links to each other, connect described first electric capacity (C1) more over the ground;
Described importation, contain: the 4th PMOS manages (M2), the 5th PMOS manages (M4), the 4th NMOS manages (M6), the 5th NMOS manages (M8), the 6th PMOS manages (M10), the 6th NMOS manages (M12), second resistance (R2) and second electric capacity (C2), wherein, the source electrode of described the 4th PMOS pipe (M2) connects described supply voltage (Vdd), and the drain electrode of the 4th PMOS pipe (M2) connects the source electrode of described the 5th PMOS pipe (M4), and the drain electrode of the 5th PMOS pipe (M4) connects the source electrode of described the 4th NMOS pipe (M6), and the drain electrode of the 4th NMOS pipe (M6) connects the source electrode of described the 5th NMOS pipe (M8), and the drain electrode of the 5th NMOS pipe (M8) is through described second resistance (R2) ground connection, the grid of described the 4th PMOS pipe (M2) links to each other with the drain electrode that described the 5th PMOS manages (M4), the source electrode of described the 6th PMOS pipe (M10) connects described supply voltage (Vdd), and the drain electrode of the 6th PMOS pipe (M10) links to each other with the source electrode that described the 6th NMOS manages (M12), and the grounded drain of the 6th NMOS pipe (M12), after the drain electrode that the grid of described the 6th PMOS pipe (M10) and described the 5th PMOS manage (M4) links to each other, connect described second electric capacity (C2) more over the ground, the grid of described the 5th NMOS pipe (M8) inserts input voltage (VIN);
The inversion signal (CLKN) of the described clock control signal of access (CCLK) after the grid of the 3rd NMOS pipe in the grid of the 2nd PMOS pipe (M3) in the grid of the 5th PMOS in described importation pipe (M4) and the described reference section back incoming clock control signal (CCLK) that links to each other, the grid of the 6th NMOS pipe (M12) in the described importation and described reference section links to each other;
Described feedback fraction, contain: NOR gate (NOR1) and the 5th inverter (I5), the inversion signal (CLKN) of first input input clock control signal (CCLK) of this NOR gate (NOR1), the inversion signal (CLKN) of this clock control signal (CCLK) is from the output of described the 5th inverter (I5), the described clock control signal of input termination (CCLK) of the 5th inverter (I5), the output of this NOR gate (NOR1) simultaneously with described reference section in NMOS pipe (M5) link to each other with the grid of the 4th NMOS (M6) in the described importation;
Described triggering feedback control circuit, contain: first inverter (I1) of series connection and second inverter (I2), the 3rd inverter (I3) and the 4th inverter (I4) of series connection, an and d type flip flop (DFF), wherein: the drain electrode of the 6th PMOS pipe (M10) in the described importation of input termination of described first inverter (I1), and the output of described second inverter (I2) links to each other with the data terminal (D) of described d type flip flop (DFF), the drain electrode of the 3rd PMOS pipe (M9) links to each other in the input of described the 3rd inverter (I3) and the described reference section, and the output of described the 4th inverter (I4) with second input that is also connected to described NOR gate (NOR1) after the clock end (CLK) of described d type flip flop (DFF) links to each other simultaneously;
Under reset mode, clock control signal (CCLK) is a low level, and first electric capacity (C1) is charged to the threshold voltage (V that voltage on this first electric capacity (C1) is slightly larger than described supply voltage (Vdd) and described PMOS pipe (M1)
TP1) poor, simultaneously second electric capacity (C2) is charged to the threshold voltage (V that voltage on this second electric capacity (C2) is slightly larger than described supply voltage (Vdd) and described the 4th PMOS pipe (M2)
TP2) poor;
Under comparison pattern, clock control signal (CCLK) is a high level, first electric capacity (C1) and second electric capacity (C2) discharge with friction speed, described d type flip flop (DFF) is according to the size output comparative result of input voltage (VIN) with respect to reference voltage (VREF), and in described d type flip flop (DFF) locking, the discharge process on first electric capacity (C1) and second electric capacity (C2) is interrupted by described NOR gate (NOR1).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101581794B1 (en) * | 2014-11-17 | 2015-12-31 | 금오공과대학교 산학협력단 | Time-domain voltage comparator |
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| CN101577548B (en) * | 2009-06-22 | 2011-05-11 | 清华大学 | Time domain comparator based on controllable load capacitor |
| CN101764613B (en) * | 2009-12-18 | 2012-05-16 | 清华大学 | Time domain comparer with low power dissipation feedback control structure |
| CN102006070B (en) * | 2010-12-22 | 2012-06-13 | 复旦大学 | Time-domain comparator applying maladjustment correction technology |
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| CN103532557B (en) * | 2013-11-05 | 2016-09-07 | 吴小刚 | A kind of all-parallel A/D converter of comparator based on voltage controlled oscillator |
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| CN109274376B (en) * | 2018-09-05 | 2022-03-11 | 东南大学 | Vernier ring-shaped time-to-digital converter capable of compressing maximum conversion time |
| CN109327209B (en) * | 2018-09-17 | 2021-03-12 | 中国电子科技集团公司第二十四研究所 | High-speed reproducible comparator circuit |
| CN111030698B (en) * | 2019-12-08 | 2023-04-07 | 复旦大学 | Voltage-to-time converter with discrete gain |
| CN111211781B (en) * | 2020-02-10 | 2021-01-15 | 华南理工大学 | Switch capacitor comparator based on thin film transistor, method and chip |
| CN111917397B (en) * | 2020-06-18 | 2021-08-10 | 华南理工大学 | Trigger circuit and chip based on unipolar transistor |
| CN117240288A (en) * | 2023-09-15 | 2023-12-15 | 华中科技大学 | Low-offset low-power-consumption voltage-time converter |
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