CN206524828U - A kind of comparator and analog-to-digital conversion device - Google Patents
A kind of comparator and analog-to-digital conversion device Download PDFInfo
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- CN206524828U CN206524828U CN201720226468.1U CN201720226468U CN206524828U CN 206524828 U CN206524828 U CN 206524828U CN 201720226468 U CN201720226468 U CN 201720226468U CN 206524828 U CN206524828 U CN 206524828U
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Abstract
The utility model embodiment discloses a kind of comparator and analog-to-digital conversion device, the comparator is made up of the first controlling switch, the second controlling switch, positive feedback loop, differential pair tube and control circuit, by controlling circuit to control the input of reference power source, so that differential pair tube is amplified to control node current potential, and state replacement is carried out using controlling switch control positive feedback loop, signal latch is carried out by positive feedback loop compared result simultaneously, so as to improve the output accuracy and speed of comparator.
Description
Technical field
The utility model embodiment is related to field of circuit technology, more particularly to a kind of comparator and analog-to-digital conversion device.
Background technology
Analog to digital converter (Analog to Digital Converter, ADC), abbreviation analog-to-digital conversion device can be by
The analog signal collected is converted into data signal, it is all had important application in various fields.With the development of science and technology,
To the performance requirement more and more higher of the analog-to-digital conversion device in signal acquiring system.And analog-to-digital conversion device is judged during the performance of comparator
The important parameter of performance.
Traditional comparator of application would generally be because of small input in Sigma-delta analog-digital converters (- Δ ADC)
Signal, such as noise, will cause comparator output result to invert.In addition, traditional dynamic latch comparator can by mismatch etc. because
Element produces certain influence on random offset voltage so that the comparison signal of comparator, which can not be stablized, to be exported.In the prior art, pass through
The problem of sluggish solution comparator is inverted is introduced, the influence to voltage is reduced using preposition amplifier, thus needs multiple clocks
Phase, different clocks width drives each circuit, so as to produce multiple working conditions.
However, in-Δ ADC, the introducing sluggishness of comparator can cause ADC precise decreasing, and the output speed of comparator
Degree is slower, further the reliability of influence output signal.
Utility model content
The utility model embodiment provides a kind of comparator and analog-to-digital conversion device, and the comparator is to improve the ratio of comparison signal
For the purpose of precision, and the output speed of comparative result, a kind of high accuracy, the comparator of high speed are realized.
In a first aspect, the utility model embodiment provides a kind of comparator, the comparator includes：First controlling switch,
Second controlling switch, positive feedback loop, differential pair tube and control circuit；
The control end of first controlling switch is electrically connected with the first clock signal terminal, signal input part and input power are electric
Connection and signal output part are electrically connected with the first control node, when the control end of second controlling switch is with described first
The electrical connection of clock signal end, signal input part are electrically connected and signal output part and the second control node electricity with the input power
Connection, first controlling switch and second controlling switch are used to control the positive feedback loop to carry out state replacement；
The control signal of the positive feedback loop is electrically connected with the input power, the first output end is controlled with described first
Node electrical connection, the second output end are electrically connected and control output end and the 3rd control node electricity with second control node
Connection, is latched for the current potential to first control node and second control node；
The differential pair tube include the first transistor and second transistor, the first electrode of the first transistor with it is described
The electrical connection of first control node, second electrode are electrically connected with the 3rd control node, and the control end of the first transistor is
First comparison signal input, the first electrode of the second transistor is electrically connected with second control node, second electrode
Electrically connected with the 3rd control node, the control end of the second transistor is the second comparison signal input；
The input of the control circuit is electrically connected with reference power source, output end is electrically connected with the 3rd control node, is used for
The reference power source is controlled to the 3rd control node input reference voltage；
Accordingly, first control node is made as the first output end, second control node of the comparator
For the second output end of the comparator.
Second aspect, the utility model embodiment provides a kind of analog-to-digital conversion device, and the analog-to-digital conversion device includes this practicality
The comparator that new embodiment is provided.
The utility model embodiment provide a kind of comparator and analog-to-digital conversion device, the comparator by the first controlling switch,
Second controlling switch, positive feedback loop, differential pair tube and control circuit composition, by controlling circuit to control the defeated of reference power source
Enter so that differential pair tube is amplified and using controlling switch control positive feedback loop progress state weight to control node current potential
Put, while signal latch is carried out by positive feedback loop compared result, so as to improve the output accuracy and speed of comparator.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram for comparator that the utility model embodiment one is provided；
Fig. 2A is a kind of circuit diagram for comparator that the utility model embodiment two is provided；
Fig. 2 B are a kind of comparator circuit figures with signal latch function that the utility model embodiment two is provided；
Fig. 2 C are a kind of comparator signal analogue simulation figures that the utility model embodiment two is provided；
Fig. 3 is a kind of structured flowchart for analog-to-digital conversion device that the utility model embodiment three is provided.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than limits of the present utility model.Further need exist for
It is bright, for the ease of description, the part related to the utility model rather than entire infrastructure are illustrate only in accompanying drawing.
Embodiment one
Fig. 1 is a kind of circuit diagram for comparator that the utility model embodiment one is provided, and the comparator is applicable to compare
Signal difference is away from less situation, and the comparator can be used in analog-to-digital conversion device, as shown in figure 1, the comparator includes：First control
Switch the 11, second controlling switch 12, positive feedback loop 20, differential pair tube N1 and N2 and control circuit 30.
Wherein, the control end of the first controlling switch 11 electrically connected with the first clock signal terminal Φ 1, signal input part and input
Power supply Vdd is electrically connected and signal output part is electrically connected with the first control node A, the control end of the second controlling switch 12 and the
The electrical connection of one clock signal terminal is electrically connected with inputting the first clock signal Φ 1, signal input part with input power Vdd, Yi Jixin
Number output end is electrically connected with the second control node B, and the first controlling switch 11 and the second controlling switch 12 are used to control positive feedback loop
20 carry out state replacement.
The control signal of positive feedback loop 20 is electrically connected with input power Vdd, the first output end and the first control node A are electric
Connect, the second output end is electrically connected with the second control node B and control output end is electrically connected with the 3rd control node C, be used for
Under the 3rd control node C control, the first control node A and the second control node B current potential are reset or latched.
Differential pair tube includes the first transistor N1 and second transistor N2, the first transistor N1 first electrode and the first control
Node A electrical connections processed, second electrode are electrically connected with the 3rd control node C, and the first transistor N1 control end compares letter for first
Number Vin+ input, second transistor N2 first electrode is electrically connected with the second control node B, second electrode and the 3rd control
Node C is electrically connected, and second transistor N2 control end is the second comparison signal Vin- input.
The input of control circuit 30 is electrically connected with reference power source Vref, output end is electrically connected with the 3rd control node C, is used
In control reference power source Vref to the 3rd control node C input reference voltages.Accordingly, the first control node A is used as comparator
The first output end, the second control node B as comparator the second output end.
Exemplary, when the first clock signal Φ 1 controls the first controlling switch 11 and the first time of the second controlling switch 12 to lead
When logical, input power Vdd electric signal is transmitted to the first control node A by the first controlling switch 11 respectively, passes through the second control
System switch 12 transmitted to the second control node B, with this so that being connected respectively with the first control node A and the second control node B
Positive feedback loop 20 carries out state replacement.At the same time, control circuit 30 control reference power source Vref is not carried to the 3rd control node C
Supply reference voltage.
When the first clock signal Φ 1 is inverted, the first controlling switch 11 and the second controlling switch 12 are off, defeated
Enter power supply Vdd and the first control node A and second is no longer transmitted separately to by the first controlling switch 11 and the second controlling switch 12
Control node B.Now, if by the first transistor N1 and second transistor N2 control end have respectively the first comparison signal Vin+ and
When second comparison signal Vin- is inputted, comparator enters and compares state, to the first comparison signal Vin+ and the second comparison signal
Vin- is compared.At the same time, control circuit 30 controls reference power source Vref to provide reference voltage to the 3rd control node C,
To drive differential pair tube, i.e. the first transistor N1 and second transistor N2, the first control node A and second after pull-down state replacement
Control node B high potential.Because the first comparison signal Vin+ and the second comparison signal Vin- of input are different, so that the
One control node A and the second control node B current potentials have different changes, when one of control node is reduced to low level,
Another control node still keeps high level.And positive feedback loop has the effect of positive feedback, the positive feedback effect is embodied in input
Signal is amplified so that low level signal continues to reduce, and high level signal continues to raise.Thus positive feedback loop can be by high electricity
The current potential of flat control node is raised, and the current potential of low level control node is continued to reduce, to cause between two potential nodes
Difference constantly amplify, to export the comparative result of degree of precision.
When the first clock signal Φ 1 is inverted again, reference power source Vref is no longer provided with reference to electricity to the 3rd control node C
Pressure, simultaneously because the positive feedback effect of positive feedback loop so that when the first controlling switch 11 and the second controlling switch 12 are turned on again,
Input power Vdd high level signal is transmitted separately to the first control again by the first controlling switch 11 and the second controlling switch 12
Node A processed and the second control node B, but due to the positive feedback effect of positive feedback loop so that the current potential of two control nodes is no longer
Change, so as to reach the effect of signal latch.Until the first clock signal is inverted again so that comparator is to compare shape
State, and input comparison signal change, can just cause comparator to carry out the process that above-mentioned signal compares again.
Wherein, the positive feedback loop can be the group of any component with positive feedback amplification or multiple components
Into such as can be two phase inverters connected back-to-back, NAND gate latch.
For example, electing the first transistor N1 and second transistor N2 as N-type transistor.In relatively state, compare letter
Number input Vin+ and Vin- input comparison signal, i.e., the first comparison signal inputted by the first transistor N1 grid respectively
Second comparison signal Vin- of Vin+ and second transistor N2 grid input.When the first comparison signal Vin+ is 500.1mv, the
When two comparison signal Vin- are 500mv, there is identical performance by the first transistor N1 and second transistor N2, so as to cause stream
It is different with the electric current of second transistor N2 source-drain electrodes through the first transistor N1 so that the first control node A potential change is very fast,
Low level is reduced to first, and the second control node B current potential is maintained as high level signal.By the positive feedback effect of positive feedback loop
So that the first control node A current potential continues to keep reduction, and the second control node B current potential continues to raise, and causes the first control
Node A processed and the second control node B potential difference are constantly amplified, so as to export corresponding comparative result.
The comparator that the utility model embodiment is provided is by controlling circuit to control the input of reference power source so that differential pair
Pipe is amplified and using controlling switch control positive feedback loop progress state replacement to control node current potential, while by positive and negative
Present ring compared result and carry out signal latch, so as to improve the output accuracy and speed of comparator.
Embodiment two
Fig. 2A is a kind of circuit diagram for comparator that the utility model embodiment two is provided, and the present embodiment is in above-described embodiment
On the basis of embody there is provided the physical circuit element of each circuit, as shown in Figure 2 A, control circuit 30 includes the
One switch SW1, second switch SW2, the 3rd switch SW3, the 4th switch SW4 and electric capacity C1.
Electric capacity C1 first end is electrically connected by first switch SW1 with reference power source Vref and by the 3rd switch SW3
Ground connection, electric capacity C1 the second end is grounded by second switch SW2 and is electrically connected by the 4th switch SW4 and the 3rd control node C
Connect, first switch SW1 control end, and second switch SW2 control end electrically connects to input with second clock signal end
Two clock signal Φ 2, the 3rd switch SW3 control end and the 4th switch SW4 control end are electrically connected with the first clock signal terminal
Connect to input the first clock signal Φ 1.
First switch SW1, second switch SW2, the 3rd switch SW3 and the 4th switch SW4 are both preferably N-type transistor,
The second clock signal Phi 2 then inputted in second clock signal end is high level, the first clock of the first clock signal terminal input
When signal Phi 1 is low level, first switch SW1 and second switch SW3 conductings, the 3rd switch SW3 and the 4th switch SW4 break
Open.The grid input high level signal of grid and second switch SW2 i.e. to first switch SW1 causes first switch SW1 and
Two switch SW2 conductings, cause the 3rd switch SW3 to the 3rd switch SW3 and the 4th switch SW4 grid input low level signal
Disconnected with the 4th switch SW4.Now, reference power source Vref passes through returning that the first switch SW1 and second switch SW2 of conducting are constituted
Road direction electric capacity C1 is charged so that electric capacity C1 the first pole plate is that close first switch SW1 pole plate is positively charged, and second
Pole plate is negatively charged.
When the first controlling switch 11 and the second controlling switch 12 are P-type transistor, i.e., the first controlling switch 11 corresponds to
Third transistor P1, the second controlling switch corresponds to the 4th transistor P2.Now, third transistor P1 control end be grid with
First clock signal terminal is electrically connected so that the first clock signal Φ 1 is inputted, first electrode i.e. source electrode is electrically connected with the first control node A
Connect and second electrode drains and electrically connected with input power Vdd, the 4th transistor P2 control end is grid and the first clock
Signal end electrically connect so that the first clock signal Φ 1 input, first electrode i.e. source electrode electrically connected with the second control node B and
Second electrode is that drain electrode is electrically connected with input power Vdd.
When the first clock signal Φ 1 that the first clock signal input terminal is inputted is low level, third transistor P1 and the
Four transistor P2 are turned on.When third transistor P1 and the 4th transistor P2 is turned on for the first time, the electricity of input power Vdd high level
Signal can be transmitted separately to the first control node A and second by the first transistor P1 of conducting and the second transistor P2 of conducting
Control node B.
It is preferably that the positive-feedback circuit of two phase inverter compositions, i.e. positive feedback loop 20 are anti-phase including first by positive feedback loop 20
Device F1 and the second phase inverter F2.Two phase inverters to connect in back-to-back fashion, i.e. the first phase inverter F1 input and second
Phase inverter F2 output end electrical connection, output end are electrically connected with the second phase inverter F2 input.Now, by the first phase inverter F1
Output end electrically connected with the first control node A, the output end of the second phase inverter is electrically connected with the second control node B so that with
First phase inverter F1 of the first control node A electrical connections output end is high level, and then causes the second phase inverter F2 input
Hold as high level, be high level with the output end of the second control node B the second phase inverters electrically connected so that first accordingly
The input of phase inverter is high level, so that phase inverter resets to tri-state, to complete the replacement of positive feedback loop.In addition,
First phase inverter F1 input control end, and the second phase inverter F2 input control end are electrically connected with input power Vdd, and first
Phase inverter F1 control output end and the control output end of the second phase inverter F2 are electrically connected with the 3rd control node C.
When the first phase inverter F1 and the second phase inverter F2 is both preferably made up of two opposite transistors of model, i.e.,
First phase inverter F1 is made up of the 5th transistor P3 of p-type and the 6th transistor N3 of N-type, and the second phase inverter F2 is by the of p-type
Seven transistor P4 and the 6th transistor N4 of N-type compositions.Wherein, the 5th transistor P3 control end is grid and the 6th transistor
N3 control end is that grid is electrically connected to form the first phase inverter F1 input, the 5th transistor P3 first electrode be source electrode with
6th transistor N3 first electrode source electrode is electrically connected to form the first phase inverter F1 output end, the 5th transistor P3 the second electricity
Pole is that drain electrode is electrically connected with input power Vdd, and the 6th transistor N3 second electrode is that drain electrode is electrically connected with the 3rd control node C
Connect.Likewise, the control end i.e. grid that the 7th transistor P4 control end is grid and the 8th transistor N4 is electrically connected to form
Two phase inverter F2 input, the 7th transistor P4 first electrode is source electrode and the 8th transistor N4 first electrode i.e. source electrode
Be electrically connected to form the second phase inverter F2 output end, and the 7th transistor P4 second electrode is that drain electrode is electrically connected with input power Vdd
Connect, the 8th transistor N4 second electrode is that drain electrode is electrically connected with the 3rd control node C.
Exemplary, when the first clock signal Φ 1 is low level, and second clock signal Phi 2 is high level, the 3rd crystal
Pipe P1 and the 4th transistor P2 conductings so that input power Vdd high level signal is transmitted separately to the first control node A and the
Two control node B, state replacement is carried out to the positive feedback loop of two back-to-back phase inverter compositions.Now, reference power source Vref to
Electric capacity C1 is charged.
When the first clock signal Φ 1 is high level, and second clock signal Phi 2 is low level, third transistor P1 and the
Four transistor P2 are no longer turned on, and electric capacity C1 discharges to the 3rd control node.When having comparison signal Vin+ and Vin- input, first
Transistor N1 and second transistor N2 conductings so that the first transistor N1 to the 3rd control node C is passed through by the first control node A
There is electric current Id1 to pass through, there is electric current Id2 to lead to by second transistor N2 to the 3rd control node C by the second control node B accordingly
Cross.Id1 and Id2 are collected to after the 3rd control node C, and reverse charging is carried out to electric capacity C1 by the 4th switch SW4 of conducting.Together
When, because the first phase inverter F1 and the second phase inverter F2 input are high level, therefore the 5th transistor P3 and the 7th crystal
Pipe P4 is not turned on, and the 6th transistor N3 and the 8th transistor N4 conductings.By the first control node A by the 6th transistor N3 by
Electric current Id3 passes through, and has electric current Id4 to pass through by the 8th transistor N4 by the second control node B.Id3 and Id4 equally can be through controls
The switch SW4 of node C and the 4th carry out reverse charging to electric capacity C1.Thus, the first control node A current potentials pass through the first transistor N1
Electric current with the 6th transistor N3 formation makes its current potential quickly reduce to electric capacity C1 reverse chargings, and eventually through the 3rd switch
SW3 is grounded.Likewise, the second control node B current potential by second transistor N2 and the 8th transistor N4 formation electric current to
Electric capacity C1 reverse chargings, make its current potential quickly reduce, and eventually through the 3rd switch SW3 ground connection.As the comparison signal Vin of input
+ it is different from Vin- when, it is different with second transistor N2 electric current to flow through the first transistor N1, causes the first control node A and
The speed that two control node B current potential declines is different, so that the first control node A and the second control node B current potential must
There is one of them to fall before for low level, and another control node still keeps high level.If the first comparison signal Vin inputted
+ being more than the second comparison signal Vin-, then the first control node A current potential drops to low level first.Now, the first phase inverter F1
Output end be changed into low level so that the second phase inverter F2 input is all low level, causes the second phase inverter F2 output
High level, so that will further keep the second control node B of high level signal current potential to draw high, accordingly, the first phase inverter
F1 input is high level, and the output end for causing the first phase inverter F1 is low level, so as to will further be reduced to low electricity first
First control node A of ordinary mail number current potential continues to drag down.Finally, exported by the first control node A and the second control node B
Comparison signal difference is exaggerated.
In addition, Fig. 2 B are the comparator circuit figures with latch that the utility model embodiment two is provided, such as Fig. 2 B institutes
Show, the comparator can also include signal latch.Can be preferably NAND gate signal latch by signal latch, it is first defeated
Enter to hold R to be electrically connected with the first control node A, the second input S is electrically connected with the second control node B, for the first control to be saved
Point A and the second control node B electric signal are converted into numerical signal and latched, to realize the further lock of comparator output signal
Deposit.
Exemplary, Fig. 2 C are a kind of comparator signal analogue simulation figures that the utility model embodiment two is provided, and are such as schemed
Shown in 2C, wherein, whole circuit is emulated under 180nm techniques, and supply voltage is 1V, and input clock clk is second clock signal
Φ 2, the clock cycle is 12ns, dutycycle 50%, and Φ 1 is its opposite phase, and those skilled in the art is it is contemplated that herein
Indicated no longer in figure.Input signal Vin- is that constant 500mV, Vin+ such as figure are the side that amplitude is swung in 499.9mV~500.1mV
Ripple, input differential signal is only ± 0.1mV.Finally, output signal Vo+ and Vo-, and exported after signal latch SR latches
Signal Q and, combined input signal Vin+ and clock signal clk and change.Its technical principle is implemented with the utility model
The comparator course of work of example narration is identical, will not be repeated here.
The utility model embodiment is by specific comparator circuit figure, by using two clock signals, two kinds of work
State realizes that the signal of comparator compares, and simplifies circuit structure, reduces power consumption, in addition using a capacitor control circuit control
Differential pair tube processed, saves area, is latched using signal latch is further to output signal, further increases comparison signal
Output stability and precision.
Embodiment three
Fig. 3 is a kind of structured flowchart for analog-to-digital conversion device that the utility model embodiment three is provided, and the analog-to-digital conversion device can
So that the analog signal collected is converted into the numerical signal that computer etc. can be handled directly, as shown in figure 3, the analog-to-digital conversion device
300 include the comparator 100 that the utility model embodiment is provided.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carried out for a person skilled in the art various bright
Aobvious change, readjust and substitute without departing from protection domain of the present utility model.Therefore, although pass through above example
The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from
In the case that the utility model is conceived, other more equivalent embodiments can also be included, and scope of the present utility model is by appended
Right determine.
Claims (11)
1. a kind of comparator, it is characterised in that including：First controlling switch, the second controlling switch, positive feedback loop, differential pair tube,
And control circuit；
The control end of first controlling switch is electrically connected with the first clock signal terminal, signal input part and input power are electrically connected
Connect and signal output part is electrically connected with the first control node, the control end of second controlling switch and first clock
Signal end is electrically connected, signal input part is electrically connected with the input power and signal output part is electrically connected with the second control node
Connect, first controlling switch and second controlling switch are used to control the positive feedback loop to carry out state replacement；
The control signal of the positive feedback loop is electrically connected with the input power, the first output end and first control node
Electrically connect, the second output end is electrically connected with second control node and control output end is electrically connected with the 3rd control node,
For under the control of the 3rd control node, being carried out to the current potential of first control node and second control node
Reset or latch；
The differential pair tube includes the first transistor and second transistor, the first electrode of the first transistor and described first
Control node electrical connection, second electrode are electrically connected with the 3rd control node, and the control end of the first transistor is first
Comparison signal input, the first electrode of the second transistor is electrically connected with second control node, second electrode and institute
The electrical connection of the 3rd control node is stated, the control end of the second transistor is the second comparison signal input；
The input of the control circuit is electrically connected with reference power source, output end is electrically connected with the 3rd control node, is used for
The reference power source is controlled to the 3rd control node input reference voltage；
Accordingly, first control node is used as institute as the first output end, second control node of the comparator
State the second output end of comparator.
2. comparator according to claim 1, it is characterised in that the control circuit includes：First switch, second open
Pass, the 3rd switch, the 4th switch and electric capacity；
The first end of the electric capacity is electrically connected by the first switch with the reference power source and by the described 3rd switch
Ground connection, the second end of the electric capacity is grounded by the second switch and by the described 4th switch and the described 3rd control
Node is electrically connected, and the control end of the control end of the first switch and the second switch is electrically connected with second clock signal end
Connect, the control end of the control end of the 3rd switch and the 4th switch is electrically connected with first clock signal terminal.
3. comparator according to claim 2, it is characterised in that the first switch, second switch, third switch and
Four switches are N-type transistor；
Accordingly, the second clock signal of the second clock signal end input is high level, and first clock signal terminal is defeated
When the first clock signal entered is low level, the first switch and second switch conducting, the described 3rd switchs and described
4th cut-offs out.
4. comparator according to claim 1, it is characterised in that first controlling switch is third transistor, described
Second controlling switch is the 4th transistor；
The control end of the third transistor is electrically connected with first clock signal terminal, first electrode is saved with the described first control
Point electrical connection and second electrode are electrically connected with the input power, when the control end of the 4th transistor is with described first
The electrical connection of clock signal end, first electrode are electrically connected and second electrode and input power electricity with second control node
Connection.
5. comparator according to claim 4, it is characterised in that the third transistor and the 4th transistor are P
Transistor npn npn；
Accordingly, when first clock signal terminal input the first clock signal be low level when, the third transistor and
4th transistor turns.
6. comparator according to claim 1, it is characterised in that the positive feedback loop is anti-including the first phase inverter and second
Phase device；
The input of first phase inverter is electrically connected with the output end of second phase inverter, output end and described second anti-phase
The input electrical connection of device, the output end of first phase inverter is electrically connected with first control node, and described second is anti-phase
The output end of device is electrically connected with second control node, the input control end of first phase inverter, and described second anti-
The input control end of phase device is electrically connected with the input power, the control output end of first phase inverter and described second anti-
The control output end of phase device is electrically connected with the 3rd control node.
7. comparator according to claim 6, it is characterised in that first phase inverter includes the 5th transistor and the 6th
Transistor, second phase inverter includes the 7th transistor and the 8th transistor；
The control end of 5th transistor and the control end of the 6th transistor are electrically connected to form first phase inverter
Input, the first electrode of the 5th transistor and the first electrode of the 6th transistor are electrically connected to form described first anti-
The output end of phase device, the control end of the 7th transistor and the control end of the 8th transistor are electrically connected to form described second
The input of phase inverter, the first electrode of the 7th transistor and the first electrode of the 8th transistor are electrically connected to form institute
State the second electrode of the output end of the second phase inverter, the second electrode of the 5th transistor, and the 7th transistor with
Second electrode and the institute of the input power electrical connection, the second electrode of the 6th transistor, and the 8th transistor
State the electrical connection of the 3rd control node.
8. comparator according to claim 7, it is characterised in that the 5th transistor and the 7th transistor are P
Transistor npn npn, the 6th transistor and the 8th transistor are N-type transistor.
9. according to any one of the claim 1-8 comparators, it is characterised in that also include：Signal latch；
The first input end of the signal latch is electrically connected with first control node, the second input is controlled with described second
Node electrical connection processed, for the electric signal of first control node and second control node to be converted into numerical signal simultaneously
Latch.
10. comparator according to claim 9, it is characterised in that the signal latch is NAND gate latch.
11. a kind of analog-to-digital conversion device, it is characterised in that including any described comparators of claim 1-10.
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| CN201720226468.1U CN206524828U (en) | 2017-03-09 | 2017-03-09 | A kind of comparator and analog-to-digital conversion device |
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| CN201720226468.1U CN206524828U (en) | 2017-03-09 | 2017-03-09 | A kind of comparator and analog-to-digital conversion device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106612119A (en) * | 2017-03-09 | 2017-05-03 | 深圳先进技术研究院 | Comparator and analog-to-digital converter |
| CN111585549A (en) * | 2019-02-18 | 2020-08-25 | 爱思开海力士有限公司 | Latch comparator, clock generation circuit and semiconductor device related thereto |
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2017
- 2017-03-09 CN CN201720226468.1U patent/CN206524828U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106612119A (en) * | 2017-03-09 | 2017-05-03 | 深圳先进技术研究院 | Comparator and analog-to-digital converter |
| CN111585549A (en) * | 2019-02-18 | 2020-08-25 | 爱思开海力士有限公司 | Latch comparator, clock generation circuit and semiconductor device related thereto |
| CN111585549B (en) * | 2019-02-18 | 2023-09-19 | 爱思开海力士有限公司 | Latch comparator, clock generation circuit and semiconductor device related thereto |
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