WO2020179206A1 - 表示装置 - Google Patents

表示装置 Download PDF

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Publication number
WO2020179206A1
WO2020179206A1 PCT/JP2019/051032 JP2019051032W WO2020179206A1 WO 2020179206 A1 WO2020179206 A1 WO 2020179206A1 JP 2019051032 W JP2019051032 W JP 2019051032W WO 2020179206 A1 WO2020179206 A1 WO 2020179206A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
emitting element
electrode
display device
substrate
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Ceased
Application number
PCT/JP2019/051032
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English (en)
French (fr)
Japanese (ja)
Inventor
池田　雅延
伊東　理
金谷　康弘
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Japan Display Inc
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Japan Display Inc
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Application filed by Japan Display Inc filed Critical Japan Display Inc
Publication of WO2020179206A1 publication Critical patent/WO2020179206A1/ja
Priority to US17/460,307 priority Critical patent/US11810886B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a display device.
  • the light emitting diode is connected to the array substrate by thermocompression bonding. Therefore, residual stress remains in the connection portion between the light emitting diode and the array substrate after cooling. Further, the connection area of the light emitting diode becomes smaller as the size of the light emitting diode becomes smaller, so that the connection reliability may be deteriorated due to the residual stress.
  • An object of the present invention is to provide a display device capable of improving connection reliability between a light emitting element and an array substrate.
  • a display device includes a substrate, a plurality of pixels provided on the substrate, a light-emitting element provided in each of the plurality of pixels, and a first electrode electrically connected to the light-emitting element. And a transistor provided on the substrate and electrically connected to the first electrode, and a plurality of conductive nano-layers provided between the first electrode and the light emitting element in a direction perpendicular to the substrate. It has a connecting layer containing particles.
  • FIG. 1 is a plan view schematically showing a display device according to the first embodiment.
  • FIG. 2 is a plan view showing a plurality of pixels.
  • FIG. 3 is a circuit diagram showing a pixel circuit.
  • FIG. 4 is a timing chart showing an operation example of the display device.
  • FIG. 5 is a sectional view taken along line VV'of FIG.
  • FIG. 6 is a sectional view taken along line VI-VI'of FIG.
  • FIG. 7 is an explanatory diagram for explaining a connection process between the light emitting element and the anode electrode.
  • FIG. 8 is an explanatory diagram for explaining the patterning method of the connection layer.
  • FIG. 9 is an explanatory diagram for explaining a first modification of the patterning method of the connection layer.
  • FIG. 1 is a plan view schematically showing a display device according to the first embodiment.
  • FIG. 2 is a plan view showing a plurality of pixels.
  • FIG. 3 is a circuit diagram showing a pixel circuit.
  • FIG. 10 is an explanatory diagram for explaining a second modification of the patterning method of the connection layer.
  • FIG. 11 is a sectional view showing the display device according to the second embodiment.
  • FIG. 12 is a sectional view showing the display device according to the third embodiment.
  • FIG. 13 is a sectional view showing the display device according to the fourth embodiment.
  • FIG. 1 is a plan view schematically showing the display device according to the first embodiment.
  • the display device 1 includes an array substrate 2, a pixel Pix, a drive circuit 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60.
  • the array board 2 is a drive circuit board for driving each pixel Pix, and is also called a backplane or an active matrix board.
  • the array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitors, various wirings, and the like.
  • the display device 1 has a display area AA and a peripheral area GA.
  • the display area AA is an area that is arranged so as to overlap the plurality of pixels Pix and displays an image.
  • the peripheral region GA is an region that does not overlap with the plurality of pixels Pix, and is arranged outside the display region AA.
  • the plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area AA of the substrate 21.
  • the first direction Dx and the second direction Dy are parallel to the surface of the substrate 21.
  • the first direction Dx is orthogonal to the second direction Dy.
  • the first direction Dx may intersect with the second direction Dy without being orthogonal to each other.
  • the third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy.
  • the third direction Dz corresponds to, for example, the normal direction of the substrate 21. Note that, hereinafter, the plan view refers to a positional relationship when viewed from the third direction Dz.
  • the drive circuit 12 has a plurality of gate lines (for example, light emission control scan line BG, reset control scan line RG, correction control scan line CG, initialization control scan line IG, write control) based on various control signals from the drive IC 210.
  • This is a circuit that drives the scanning line SG (see FIG. 3).
  • the drive circuit 12 sequentially or simultaneously selects a plurality of gate lines and supplies a gate drive signal to the selected gate lines. As a result, the drive circuit 12 selects the plurality of pixels Pix connected to the gate line.
  • the drive IC 210 is a circuit that controls the display of the display device 1.
  • the drive IC 210 is mounted as COG (Chip On Glass) in the peripheral region GA of the substrate 21.
  • the drive IC 210 is not limited to this, and may be mounted as a COF (Chip On Film) on a flexible printed board or a rigid board connected to the peripheral area GA of the board 21.
  • the cathode wiring 60 is provided in the peripheral region GA of the substrate 21.
  • the cathode wiring 60 is provided so as to surround the plurality of pixels Pix in the display area AA and the drive circuit 12 in the peripheral area GA.
  • the cathodes of the plurality of light emitting elements 3 are electrically connected to the common cathode wiring 60 and are supplied with a fixed potential (eg, ground potential). More specifically, the cathode terminal 32 (see FIG. 5) of the light emitting element 3 is connected to the cathode wiring 60 via the cathode electrode 22 (second electrode).
  • FIG. 2 is a plan view showing a plurality of pixels.
  • one pixel Pix includes a plurality of sub-pixels 49.
  • the pixel Pix includes a first subpixel 49R, a second subpixel 49G, and a third subpixel 49B.
  • the first sub-pixel 49R displays the primary color red as the first color.
  • the second sub-pixel 49G displays the primary color green as the second color.
  • the third sub-pixel 49B displays the primary color blue as the third color.
  • the first subpixel 49R and the third subpixel 49B are arranged in the first direction Dx.
  • the second sub pixel 49G and the third sub pixel 49B are arranged in the second direction Dy.
  • the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected.
  • any color such as a complementary color can be selected.
  • sub-pixels 49 when it is not necessary to distinguish the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B from each other, they are referred to as sub-pixels 49.
  • the sub-pixels 49 each include the light emitting element 3, the anode electrode 23 (first electrode), and the connection layer 24.
  • the display device 1 emits different light (for example, red, green, blue light) for each of the light emitting elements 3R, 3G, and 3B in the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B. Display the image with.
  • the light emitting element 3 is provided in each of the plurality of sub-pixels 49.
  • the light emitting element 3 is a light emitting diode (LED: Light Emitting Diode) chip having a size of about 3 ⁇ m or more and 300 ⁇ m or less in a plan view, and is called a micro LED (micro LED).
  • the display device 1 including the micro LED in each pixel is also called a micro LED display device. It should be noted that the micro of the micro LED does not limit the size of the light emitting element 3.
  • the plurality of light emitting elements 3 may emit four or more different colors of light.
  • the arrangement of the plurality of sub-pixels 49 is not limited to the configuration shown in FIG.
  • the first sub-pixel 49R may be adjacent to the second sub-pixel 49G in the first direction Dx.
  • the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B may be repeatedly arranged in this order in the first direction Dx.
  • FIG. 3 is a circuit diagram showing a pixel circuit.
  • the pixel circuits PIC-R, PIC-G, and PIC-B shown in FIG. 3 are provided corresponding to the first subpixel 49R, the second subpixel 49G, and the third subpixel 49B, respectively.
  • FIG. 3 shows a circuit diagram of the pixel circuit PIC-B and omits the pixel circuits PIC-R and PIC-G, the description of the pixel circuit PIC-B will be omitted. It can also be applied to PIC-G.
  • the pixel circuit PIC-B includes a light emitting element 3, five transistors, and three capacitors. Specifically, the pixel circuit PIC-B includes a light emission control transistor BCT, a correction transistor CCT, an initialization transistor IST, a writing transistor SST, and a driving transistor DRT. Some transistors may be shared by a plurality of adjacent subpixels 49. In the example shown in FIG. 3, the light emission control transistor BCT is shared by the three sub-pixels 49 via the common wiring L5. Further, the reset transistor RST is provided in the peripheral region GA, for example, one for each row of the sub-pixel 49. The drain of the reset transistor RST is connected to a plurality of pixel circuits PIC-R, PIC-G, and PIC-B via the common wiring L5.
  • the light emission control transistor BCT, the correction transistor CCT, the initialization transistor IST, the write transistor SST, the drive transistor DRT, and the reset transistor RST are each composed of an n-type TFT (Thin Film Transistor).
  • n-type TFT Thin Film Transistor
  • the present invention is not limited to this, and each transistor may be composed of a p-type TFT.
  • the power supply potential and the connection of the storage capacitor Cs may be appropriately adapted.
  • the light emission control scan line BG is connected to the gate of the light emission control transistor BCT.
  • the reset control scan line RG is connected to the gate of the reset transistor RST.
  • the correction control scan line CG is connected to the gate of the correction transistor CCT.
  • the initialization control scan line IG is connected to the gate of the initialization transistor IST.
  • the write control scan line SG is connected to the gate of the write transistor SST.
  • the light emission control scan line BG, the reset control scan line RG, the correction control scan line CG, the initialization control scan line IG, and the write control scan line SG are each connected to the drive circuit 12 provided in the peripheral region GA.
  • the drive circuit 12 has a light emission control scan line BG, a reset control scan line RG, a correction control scan line CG, an initialization control scan line IG, and a write control scan line SG, respectively, with a light emission control signal Vbg and a reset control signal Vrg.
  • the correction control signal Vcg, the initialization control signal Vig, and the write control signal Vsg are supplied.
  • the video signal Vsig is supplied to the plurality of pixel circuits PIC-R, PIC-G, and PIC-B via switch elements SELR, SELG, and SELB.
  • the drive IC 210 (see FIG. 1) outputs a control signal to the switch elements SELR, SELG, and SELB, and supplies a video signal Vsig to a plurality of pixel circuits PIC-R, PIC-G, and PIC-B in a time-division manner. ..
  • the video signal Vsig is supplied to the write transistor SST via the video signal line L3.
  • the drive IC 210 supplies the initialization potential Vini to the initialization transistor IST via the initialization signal line L4.
  • the drive circuit 12 supplies the reset power supply potential Vrst to the reset transistor RST via the reset signal line L6.
  • the light emission control transistor BCT, the correction transistor CCT, the initialization transistor IST, the writing transistor SST, and the reset transistor RST function as a switching element that selects conduction or non-conduction between two nodes.
  • the drive transistor DRT functions as a current control element that controls the current flowing through the light emitting element 3 according to the voltage between the gate and the drain.
  • the cathode (cathode terminal 32) of the light emitting element 3 is connected to the cathode power supply line L2.
  • the anode (anode terminal 33) of the light emitting element 3 is connected to the anode power supply line L1 via the drive transistor DRT, the correction transistor CCT, and the light emission control transistor BCT.
  • the anode power supply potential PVDD is supplied to the anode power supply line L1.
  • the cathode power supply potential PVSS is supplied to the cathode power supply line L2 via the cathode wiring 60 and the cathode electrode 22.
  • the anode power supply potential PVDD is higher than the cathode power supply potential PVSS.
  • the pixel circuit PIC-B includes a storage capacitor Cs and capacitors Cled and Cad.
  • the storage capacitance Cs is a capacitance formed between the gate and the source of the drive transistor DRT.
  • the capacitance Cled is a parasitic capacitance formed between the anode and the cathode of the light emitting element 3.
  • the capacitance Cad is an additional capacitance formed between the source of the drive transistor DRT and the anode of the light emitting element 3 and the anode power supply line L1.
  • FIG. 4 is a timing chart showing an operation example of the display device.
  • Each of the periods G1 to G4 shown in FIG. 4 is one horizontal period.
  • FIG. 4 shows the operation of driving the sub-pixels 49 in the first row to the sub-pixels 49 in the fourth row, the sub-pixels 49 in the last row are continuously driven after the fifth row. Further, in the following description, the period for driving from the sub-pixel 49 in the first row to the sub-pixel 49 in the last row is referred to as a frame period.
  • the period t0 is the previous frame light emission period. That is, in the period t0 until the processing in a certain frame period is started, the sub-pixel 49 continues the light emitting state of the previous frame.
  • the period t1 is the source initialization period of the drive transistor DRT. Specifically, in the period t1, the potentials of the light emission control scanning lines BG1 and BG2 become L (low) level according to each control signal supplied from the drive circuit 12, and the potentials of the correction control scanning lines CG1 and CG2 become H ( High level, and the potentials of the reset control scan lines RG1 and RG2 become H level. As a result, the light emission control transistor BCT is turned off (non-conduction state), and the correction transistor CCT and the reset transistor RST are turned on (conduction state).
  • the light emission control scan line BG1 indicates the light emission control scan line BG connected to the first row sub-pixel 49
  • the light emission control scan line BG2 indicates the light emission control scan line connected to the second row sub-pixel 49.
  • the light emission control scanning line BG3 indicates a light emission control scanning line BG connected to the sub-pixel 49 in the third line
  • the light emission control scanning line BG4 indicates a light emission control scanning line BG connected to the sub pixel 49 in the fourth line. Shown. The same applies to the scanning lines such as the correction control scanning lines CG1 and CG2 and the reset control scanning lines RG1 and RG2.
  • the current from the anode power supply line L1 is cut off by the light emission control transistor BCT in the sub-pixels 49 belonging to the first and second rows.
  • the light emission of the light emitting element 3 is stopped, and the electric charge remaining in the sub-pixel 49 flows to the outside through the reset transistor RST.
  • the source of the drive transistor DRT is fixed to the reset power supply potential Vrst.
  • the reset power supply potential Vrst is set to have a predetermined potential difference with respect to the cathode power supply potential PVSS. In this case, the potential difference between the reset power supply potential Vrst and the cathode power supply potential PVSS is smaller than the potential difference at which the light emitting element 3 starts emitting light.
  • the period t2 is the gate initialization period of the drive transistor DRT.
  • the potentials of the initialization control scan lines IG1 and IG2 are at the H level by the control signals supplied from the drive circuit 12.
  • the initialization transistor IST is turned on.
  • the gate of the drive transistor DRT is fixed to the initialization potential Vini via the initialization transistor IST.
  • the initialization potential Vini has a potential larger than the threshold value of the drive transistor DRT with respect to the reset power supply potential Vrst. Therefore, the drive transistor DRT is turned on.
  • the light emission control transistor BCT since the light emission control transistor BCT remains off, no current flows through the drive transistor DRT.
  • the period t3 is the offset cancel operation period. Specifically, in the period t3, the potentials of the light emitting control scanning lines BG1 and BG2 become H level and the potentials of the reset control scanning lines RG1 and RG2 become L level according to each control signal supplied from the drive circuit 12. As a result, the light emission control transistor BCT is turned on and the reset transistor RST is turned off.
  • the drive transistor DRT is turned on by the operation during the period t2. Therefore, current is supplied from the anode power supply line L1 (anode power supply potential PVDD) to the drive transistor DRT via the light emission control transistor BCT and the correction transistor CCT.
  • L1 anode power supply potential PVDD
  • the source of the drive transistor DRT is charged by the anode power supply potential PVDD, and the potential of the source rises.
  • the gate potential of the drive transistor DRT is the initialization potential Vini. Therefore, when the source potential of the drive transistor DRT becomes (Vini-Vth), the drive transistor DRT is turned off and the increase in potential stops.
  • Vth is the threshold voltage Vth of the drive transistor DRT.
  • the threshold voltage Vth varies from subpixel 49 to subpixel 49. Therefore, the potential of the source of the drive transistor DRT when the increase of the potential is stopped is different for each sub-pixel 49. In other words, the voltage corresponding to the threshold voltage Vth of the drive transistor DRT is acquired in each subpixel 49 by the operation in the period t3. At this time, a voltage of ((Vini-Vth)-PVSS) is applied to the light emitting element 3. Since this voltage is lower than the light emission start voltage of the light emitting element 3, no current flows in the light emitting element 3.
  • the driving of the sub-pixels 49 for two rows is simultaneously performed in the period t1 to the period t3, but the present invention is not limited to this.
  • the drive circuit 12 may be driven for each sub-pixel 49 in one row, or the sub-pixel 49 for three rows may be driven at the same time.
  • the period t4 and the period t5 are video signal writing operation periods. Specifically, in the period t4, the potentials of the correction control scanning lines CG1 and CG2 become L level, and the potentials of the initialization control scanning lines IG1 and IG2 become L level according to each control signal supplied from the drive circuit 12.
  • the write control scanning line SG1 becomes the H level.
  • the potentials of the correction control scanning lines CG1 and CG2 become L level
  • the potentials of the initialization control scanning lines IG1 and IG2 become L level
  • the writing control scanning line becomes L level according to each control signal supplied from the drive circuit 12.
  • SG2 becomes H level.
  • the correction transistor CCT is turned off, the initialization transistor IST is turned off, and the write transistor SST is turned on.
  • the video signal Vsig is input to the gate of the drive transistor DRT in the sub-pixel 49 belonging to the first row.
  • the gate potential of the drive transistor DRT changes from the initialization potential Vini to the potential of the video signal Vsig.
  • the source potential of the drive transistor DRT maintains (Vini-Vth).
  • the voltage between the gate and the source of the drive transistor DRT becomes (Vsig-(Vini-Vth)), which reflects the variation in the threshold voltage Vth between the sub-pixels 49.
  • the video signal Vsig is input to the gate of the drive transistor DRT, and the voltage between the gate of the drive transistor DRT and the source is (Vsig- (Vini-). Vth)).
  • the video signal line L3 extends in the second direction Dy (see FIG. 1) and is connected to the sub-pixels 49 of a plurality of rows belonging to the same column. Therefore, the period t4 and the period t5 in which the video writing operation is performed are performed for each row.
  • the period t6 is a light emitting operation period. Specifically, in the period t6, the potentials of the correction control scanning lines CG1 and CG2 become H level and the writing control scanning lines SG1 and SG2 become L level according to each control signal supplied from the drive circuit 12. As a result, the correction transistor CCT is turned on and the write transistor SST is turned off. A current is supplied from the anode power supply line L1 (anode power supply potential P VDD) to the drive transistor DRT via the light emission control transistor BCT and the correction transistor CCT.
  • L1 anode power supply potential P VDD
  • the drive transistor DRT supplies the light emitting element 3 with a current according to the voltage between the gate and the source set by the period t5.
  • the light emitting element 3 emits light with a brightness corresponding to this current.
  • the voltage between the anode and the cathode of the light emitting element 3 becomes a voltage according to the current value supplied through the drive transistor DRT.
  • the potential of the anode of the light emitting element 3 rises.
  • the voltage between the gate and the source of the drive transistor DRT is held by the holding capacitor Cs. Therefore, due to the coupling of the storage capacitor Cs, the gate potential of the drive transistor DRT also rises as the potential of the anode of the light emitting element 3 rises.
  • the gate of the drive transistor DRT has an additional capacitance such as a capacitance CAD in addition to the holding capacitance Cs, the increase in the gate potential of the drive transistor DRT is slightly smaller than the increase in the potential of the anode. However, since this value is known, it is advisable to determine the potential of the video signal Vsig so that the final voltage between the gate and the source of the drive transistor DRT has a desired current value.
  • the image for one frame is displayed.
  • the reset operation of the sub-pixels 49 belonging to the third row and the fourth row is executed in the period overlapping with the period t3.
  • the offset canceling operation of the sub-pixel 49 belonging to the third and fourth rows is executed in a period overlapping from the period t3 to the period t5.
  • the video signal writing operation of the sub-pixels 49 belonging to the third row and the fourth row is performed in a period overlapping with the period t6. After that, the image is displayed by repeating such an operation.
  • the configuration of the pixel circuit PIC shown in FIG. 3 and the operation example shown in FIG. 4 are merely examples, and can be changed as appropriate.
  • the number of wirings and the number of transistors in one subpixel 49 may be different.
  • the pixel circuit PIC can also adopt a configuration such as a current mirror circuit.
  • FIG. 5 is a cross-sectional view taken along the line VVV of FIG.
  • FIG. 6 is a sectional view taken along line VI-VI'of FIG.
  • the light emitting element 3 is provided on the array substrate 2.
  • the array substrate 2 has a substrate 21, an anode electrode 23, a connection layer 24, a counter electrode 25, a connection electrode 26a, various transistors, various wirings, and various insulating films.
  • the substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or alkali-free glass, or a resin substrate such as polyimide is used.
  • a flexible resin substrate is used as the substrate 21, the display device 1 can be configured as a sheet display.
  • the substrate 21 is not limited to polyimide, and other resin materials may be used.
  • the direction from the substrate 21 to the light emitting element 3 in the direction perpendicular to the surface of the substrate 21 is referred to as “upper” or simply “upper”. Further, the direction from the light emitting element 3 to the substrate 21 is referred to as “lower side” or simply “lower”.
  • the undercoat film 91 is provided on the substrate 21.
  • the undercoat film 91 has, for example, a three-layer laminated structure including insulating films 91a, 91b, and 91c.
  • the insulating film 91a is a silicon oxide film
  • the insulating film 91b is a silicon nitride film
  • the insulating film 91c is a silicon oxide film.
  • the lower insulating film 91a is provided to improve the adhesion between the substrate 21 and the undercoat film 91.
  • the middle-layer insulating film 91b is provided as a blocking film for moisture and impurities from the outside.
  • the upper insulating film 91c is provided as a block film that prevents hydrogen atoms contained in the silicon nitride film of the insulating film 91b from diffusing to the semiconductor layer 61 side.
  • the structure of the undercoat film 91 is not limited to that shown in FIG.
  • the undercoat film 91 may be a single-layer film or a two-layer laminated film, or may be laminated with four or more layers.
  • the substrate 21 is a glass substrate, the silicon nitride film has relatively good adhesion, so that the silicon nitride film may be directly formed on the substrate 21.
  • the light shielding film 65 is provided on the insulating film 91a.
  • the light-shielding film 65 is provided between the semiconductor layer 61 and the substrate 21.
  • the light-shielding film 65 can suppress the intrusion of light from the substrate 21 side into the channel region 61a of the semiconductor layer 61.
  • by forming the light shielding film 65 of a conductive material and applying a predetermined potential it is possible to give a back gate effect to the drive transistor DRT.
  • the light shielding film 65 may be provided on the substrate 21 and the insulating film 91a may be provided so as to cover the light shielding film 65.
  • the drive transistor DRT is provided on the undercoat film 91. Although the drive transistor DRT among the plurality of transistors is shown in FIG. 5, the light emission control transistor BCT, the initialization transistor IST, the correction transistor CCT, the write transistor SST, and the peripheral region GA included in the pixel circuit PIC are provided.
  • the reset transistor RST provided also has a laminated structure similar to that of the drive transistor DRT.
  • the drive transistor DRT has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64.
  • the semiconductor layer 61 is provided on the undercoat film 91.
  • the semiconductor layer 61 for example, polysilicon is used.
  • the semiconductor layer 61 is not limited to this, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low-temperature polysilicon, or the like.
  • a p-type TFT may be formed simultaneously.
  • the semiconductor layer 61 has a channel region 61a, a source region 61b, a drain region 61c, and a low concentration impurity region 61d.
  • the low concentration impurity region 61d is provided between the channel region 61a and the source region 61b, and is provided between the channel region 61a and the drain region 61c.
  • the gate insulating film 92 is provided on the undercoat film 91 so as to cover the semiconductor layer 61.
  • the gate insulating film 92 is, for example, a silicon oxide film.
  • the gate electrode 64 is provided on the gate insulating film 92.
  • the first wiring 66 is provided in the same layer as the gate electrode 64.
  • MoW molybdenum tungsten
  • the drive transistor DRT has a top gate structure in which the gate electrode 64 is provided above the semiconductor layer 61.
  • the driving transistor DRT is not limited to this, and may have a bottom gate structure in which the gate electrode 64 is provided below the semiconductor layer 61, and the gate electrode 64 is provided both above and below the semiconductor layer 61.
  • a dual gate structure may be used.
  • the interlayer insulating film 93 is provided on the gate insulating film 92 so as to cover the gate electrode 64.
  • the interlayer insulating film 93 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film.
  • the source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 93.
  • the source electrode 62 is connected to the source region 61b through a contact hole provided in the gate insulating film 92 and the interlayer insulating film 93.
  • the drain electrode 63 is connected to the drain region 61c via a contact hole provided in the gate insulating film 92 and the interlayer insulating film 93.
  • the source electrode 62 is connected to the second wiring 67 that serves as a leading wiring.
  • a three-layer laminated structure of titanium (Ti), aluminum (Al), and titanium (Ti) can be adopted.
  • a part of the second wiring 67 is formed in a region overlapping the first wiring 66.
  • the holding capacitance Cs is formed by the first wiring 66 and the second wiring 67 facing each other via the interlayer insulating film 93. Further, the first wiring 66 is formed in a region overlapping a part of the semiconductor layer 61.
  • the storage capacitance Cs also includes a capacitance formed by the semiconductor layer 61 and the first wiring 66 that face each other with the gate insulating film 92 interposed therebetween.
  • the flattening film 94 is provided on the interlayer insulating film 93 so as to cover the drive transistor DRT and the second wiring 67.
  • An organic material such as photosensitive acrylic is used as the flattening film 94.
  • Organic materials such as photosensitive acrylic are superior in coverage of wiring steps and surface flatness as compared with inorganic insulating materials formed by CVD or the like.
  • the counter electrode 25, the capacitive insulating film 95, the anode electrode 23, the connection layer 24, and the anode electrode insulating film 96 are laminated in this order on the flattening film 94.
  • the counter electrode 25 is made of a transparent conductive material such as ITO (Indium Tin Oxide).
  • the connection electrode 26a is provided in the same layer as the counter electrode 25.
  • the connection electrode 26a is provided so as to cover the inside of the contact hole H1 provided in the flattening film 94, and is connected to the second wiring 67 at the bottom of the contact hole H1.
  • the present invention is not limited to this, and the anode electrode 23 may be a material containing any one or more of molybdenum and titanium metals.
  • the anode electrode 23 may be an alloy containing any one or more of molybdenum and titanium, or a translucent conductive material.
  • a capacitance Cad is formed between the anode electrode 23 and the counter electrode 25 that face each other via the capacitance insulating film 95.
  • the counter electrode 25 formed of ITO also has a function as a barrier film for protecting various wirings such as the second wiring 67 in the process of forming the anode electrode 23 and the connection layer 24.
  • the counter electrode 25 is partially exposed to the etching environment.
  • the counter electrode 25 is changed to an anode electrode by an annealing treatment performed between the formation of the counter electrode 25 and the formation of the anode electrode 23. It has sufficient resistance to the etching of 23.
  • connection layer 24 is provided on the anode electrode 23.
  • the connecting layer 24 contains a plurality of conductive nanoparticles 51.
  • the connection layer 24 can be patterned by inkjet printing, screen printing, or the like using a conductive ink or a conductive paste containing a plurality of conductive nanoparticles 51. The patterning method of the connection layer 24 will be described later.
  • the anode electrode insulating film 96 is provided so as to cover the anode electrode 23 and the connection layer 24.
  • the anode electrode insulating film 96 is, for example, a silicon nitride film.
  • the anode electrode insulating film 96 covers the peripheral portion of the connection layer 24 and insulates the anode electrodes 23 of the adjacent sub-pixels 49.
  • the anode electrode insulating film 96 has an opening OP for mounting the light emitting element 3 at a position overlapping the connection layer 24.
  • the size of the opening OP is set to have a larger area than the light emitting element 3 in consideration of the amount of mounting deviation in the mounting process of the light emitting element 3. That is, the area of the connection layer 24 is larger than the area of the light emitting element 3 in a plan view from the direction perpendicular to the substrate 21.
  • the area of the anode electrode 23 is larger than the area of the light emitting element 3 in a plan view from a direction perpendicular to the substrate 21.
  • the light emitting elements 3R, 3G, 3B are mounted on the corresponding anode electrodes 23 via the connection layer 24. That is, the connection layer 24 is provided between the anode electrode 23 and the light emitting element 3 in the direction perpendicular to the substrate 21.
  • the light emitting element 3 has a semiconductor layer 31, a cathode terminal 32, and an anode terminal 33.
  • the semiconductor layer 31 may have a structure in which an n-type clad layer, an active layer, and a p-type clad layer are stacked.
  • the semiconductor layer 31 for example, a compound semiconductor such as gallium nitride (GaN) or aluminum indium phosphide (AlInP) is used.
  • the semiconductor layer 31 may use different materials for each of the light emitting elements 3R, 3G, 3B.
  • a multi-quantum well structure MQW structure in which a well layer composed of several atomic layers and a barrier layer are periodically stacked may be adopted for higher efficiency.
  • the light emitting element 3 may have a structure in which the semiconductor layer 31 is formed on the semiconductor substrate.
  • the cathode electrode 22 is provided over the upper surface of the element insulating film 97 and the upper surface of the cathode terminal 32.
  • a conductive material having translucency such as ITO is used for the cathode electrode 22. Thereby, the light emitted from the light emitting element 3 can be efficiently extracted to the outside.
  • the cathode electrode 22 is electrically connected to the cathode terminals 32 of the plurality of light emitting elements 3 mounted in the display area AA.
  • the display device 1 has a terminal portion 27, a bent area FA, and a cathode contact portion (contact hole H2) in the peripheral area GA.
  • the terminal portion 27 is a terminal connected to a wiring board such as a drive IC 210 or a flexible printed circuit board.
  • the bent region FA is a region of the array substrate 2 for bending the peripheral region GA on the terminal portion 27 side. When the bent area FA is provided, a flexible resin material is used as the substrate 21.
  • the flattening film 94 is removed in the peripheral region GA, the bent region FA and the region between the bent region FA and the end portion of the substrate 21.
  • the flattening film 94 is provided with a contact hole H2 in a region between the bent region FA and the display region AA.
  • the cathode wiring 60 is exposed on the bottom surface of the contact hole H2, and the thickness of the element insulating film 97 is provided so as to decrease from the peripheral portion of the display area AA toward the peripheral area GA.
  • the cathode electrode 22 is electrically connected to the cathode wiring 60 via the connection electrode 26b provided inside the contact hole H2.
  • the connection electrode 26b is provided in the same layer as the counter electrode 25 and the connection electrode 26a, and is made of the same material as the counter electrode 25 and the connection electrode 26a.
  • the display device 1 using the light emitting element 3 as a display element is configured.
  • the display device 1 may be provided with a cover glass, a touch panel, or the like on the upper side of the cathode electrode 22.
  • a filler made of resin or the like may be provided between the display device 1 and a member such as the cover glass.
  • the display device 1 is not limited to the face-up structure in which the upper portion of the light emitting element 3 is connected to the cathode electrode 22, and the lower portion of the light emitting element 3 is connected to the anode electrode 23 and the cathode electrode 22. It may be a structure.
  • a coating film 50 is formed on the anode electrode 23, and the anode terminal 33 of the light emitting element 3 is in contact with the coating film 50 (step ST1).
  • the coating film 50 is printed and formed by using a conductive paste or a conductive ink in which a plurality of conductive nanoparticles 51 are dispersed in a solvent 53.
  • the coating film 50 can be formed by screen printing, flexographic printing, or inkjet printing.
  • the conductive nanoparticles 51 for example, silver (Ag) or a silver alloy is used.
  • Each of the conductive nanoparticles 51 has a particle size of nano-order (for example, about 1 nm or more and about 30 nm or less) and has high surface energy. Therefore, when the conductive nanoparticles 51 are sintered, it is lower than, for example, a reflow process using a solder material or a normal conductive powder containing silver powder (for example, a particle size of 1 ⁇ m or more). It can be sintered at temperature. Therefore, it is possible to suppress the difference between the shrinkage amount of the light emitting element 3 and the shrinkage amount of the connection layer 24 when the connection step of the light emitting element 3 is cooled. Thereby, after cooling, the residual stress in the connecting portion between the light emitting element 3 and the anode electrode 23 can be suppressed.
  • the particle size of the conductive nanoparticles 51 used as the material of the connection layer 24 can be measured by, for example, a laser diffraction scattering method.
  • the connection layer 24 can be patterned by a printing method such as screen printing, flexographic printing, or inkjet printing.
  • the present invention is not limited to this, and various methods can be applied to the patterning of the connection layer 24.
  • FIG. 8 is an explanatory diagram for explaining the patterning method of the connection layer.
  • the film forming apparatus 100 includes an aerosol generator 101, a pipe 102, a nozzle 103, and an XY stage 104.
  • the film forming apparatus 100 can form the connection layer 24 by the aerosol deposition method.
  • Conductive nanoparticles 51 which is a raw material, are charged into the aerosol generator 101.
  • the conductive nanoparticles 51 are agitated and mixed in the aerosol generator 101 to be aerosolized.
  • the aerosol particles are densified through the pipe 102 and conveyed to the nozzle 103.
  • the aerosol particles conveyed to the nozzle 103 are accelerated by the carrier gas G. As a result, the aerosol beam 55 is emitted from the opening of the nozzle 103 toward the array substrate 2.
  • the film forming apparatus 100 can form the connection layer 24 on the anode electrode 23. Further, the film forming apparatus 100 can drive the XY stage 104 to form the connection layer 24 in a predetermined pattern. As described above, the film forming apparatus 100 can directly form the connection layer 24 on the anode electrode 23 by the aerosolized conductive nanoparticles 51.
  • FIG. 9 is an explanatory diagram for explaining a first modified example of the patterning method of the connection layer.
  • the film forming apparatus 200 includes a power supply 106, a nozzle 107, an electrode 108, and an XY stage 110.
  • the film forming apparatus 200 can form the connection layer 24 by an electrostatic coating method.
  • the solution 109 in which the conductive nanoparticles 51 are dispersed is put into the nozzle 107.
  • the electrode 108 is provided in the nozzle 107 and comes into contact with the solution 109.
  • the power supply 106 applies a positive high voltage between the array substrate 2 and the solution 109 in the nozzle 107.
  • a positive charge is generated in the solution 109 at the tip of the nozzle 107, and a negative charge is generated on the array substrate 2 side. Due to the electrostatic force generated between the solution 109 and the array substrate 2, a part of the solution 109 is ejected toward the array substrate 2.
  • the conductive nanoparticles 51 of the solution 109 are attracted onto the anode electrode 23 by electrostatic force to form the connecting layer 24.
  • the film forming apparatus 200 can adjust the amount, shape, and the like of the solution 109 ejected from the nozzle 107 by changing the voltage applied by the power supply 106. As a result, the film forming apparatus 200 can pattern the connection layer 24 into a fine shape.
  • FIG. 10 is an explanatory diagram for explaining a second modification of the patterning method of the connection layer.
  • the connection layer 24 is formed by the photolithography technique.
  • the film forming apparatus coats and forms the coating film 50 containing the conductive nanoparticles 51 on the entire surface of the array substrate 2 (step ST11).
  • the coating film 50 is formed so as to cover the plurality of anode electrodes 23.
  • the coating film 50 is heat-treated to remove the coating film 52 and the solvent 53 (see FIG. 7) that cover the surfaces of the conductive nanoparticles 51.
  • the heat treatment is performed at a temperature lower than the sintering temperature of the plurality of conductive nanoparticles 51.
  • a plurality of conductive nanoparticles 51 are deposited on the array substrate 2.
  • the film forming apparatus forms a resist 201 on the plurality of conductive nanoparticles 51 in a region overlapping the anode electrode 23, that is, a region where the connection layer 24 is to be provided (step ST12).
  • the film forming apparatus removes a plurality of conductive nanoparticles 51 in a region that does not overlap with the resist 201 by etching (step ST13).
  • the plurality of conductive nanoparticles 51 since the plurality of conductive nanoparticles 51 are not sintered, the plurality of conductive nanoparticles 51 have a higher etching rate than the anode electrode 23.
  • the connecting layer 24 containing the plurality of conductive nanoparticles 51 is formed on the anode electrode 23.
  • the anode electrode insulating film 96 is formed so as to cover the connection layer 24 and the anode electrode 23.
  • An opening OP is formed in the anode electrode insulating film 96 in a region overlapping the connection layer 24.
  • connection layer 24 is formed by the photolithography technique, so that the connection layer 24 can be formed in the same process as the manufacturing process of the array substrate 2. Therefore, the display device 1 can suppress the manufacturing cost.
  • FIG. 11 is a sectional view showing the display device according to the second embodiment.
  • the same components as those described in the above-described embodiment are designated by the same reference numerals, and duplicate description will be omitted.
  • the display device 1A of the second embodiment is different from the first embodiment in the configuration in which the anode electrode 23A is formed of a plurality of conductive nanoparticles 51.
  • the anode terminal 33 of the light emitting element 3 is connected on the anode electrode 23A.
  • the anode electrode 23A also has the function of the connection layer 24.
  • the anode electrode 23A since the anode electrode 23A includes the plurality of conductive nanoparticles 51, when the anode electrode 23A and the light emitting element 3 are connected, the conductive nanoparticles 51 are sintered at a low temperature. be able to. As a result, residual stress at the connection portion between the light emitting element 3 and the anode electrode 23A can be suppressed. Further, since the anode electrode 23A also serves as the connection layer 24, the display device 1A can reduce the number of stacked array substrates 2 as compared with the first embodiment.
  • connection method between the anode electrode 23A and the light emitting element 3 and the patterning method of the anode electrode 23A can be adopted as the connection method between the anode electrode 23A and the light emitting element 3 and the patterning method of the anode electrode 23A.
  • FIG. 12 is a sectional view showing the display device according to the third embodiment.
  • the display device 1B of the third embodiment is different from the above-described embodiment in the configuration including the reflective layer 28.
  • the reflective layer 28 is provided so as to face the side surface of the light emitting element 3, and includes a plurality of conductive nanoparticles 51.
  • the element insulating film 97 is provided with a through hole 97a in a region overlapping the light emitting element 3.
  • the light emitting element 3 is arranged on the connection layer 24 while being surrounded by the inner wall of the through hole 97a.
  • the reflective layer 28 is provided along the inner wall of the through hole 97a.
  • the lower end of the reflective layer 28 is electrically connected to the anode electrode 23 via the connecting layer 24.
  • the upper end of the reflective layer 28 is separated from the cathode electrode 22.
  • the area of the opening OP for mounting the light emitting element 3 is a region surrounded by the lower end of the reflective layer 28.
  • a reflective layer insulating film 98 is provided inside the through hole 97a.
  • the reflective layer insulating film 98 covers the side surface of the light emitting element 3 and also covers the reflective layer 28.
  • the cathode electrode 22 is provided so as to cover the element insulating film 97, the reflective layer insulating film 98, and the light emitting element 3, and is electrically connected to the cathode terminal 32.
  • the reflective layer insulating film 98 is also provided between the upper end of the reflective layer 28 and the cathode electrode 22.
  • the reflective layer 28 is formed of a plurality of glossy conductive nanoparticles 51. Further, the reflective layer 28 is provided so as to be inclined with respect to the normal line direction of the substrate 21. Accordingly, the reflection layer 28 reflects the light emitted in the lateral direction (side surface direction) of the light emitted from the light emitting element 3, and emits the reflected light in the direction along the normal direction of the substrate 21. As a result, the display device 1B can improve the efficiency of extracting light from the light emitting element 3.
  • the reflective layer 28 may be provided so as to surround the periphery of the light emitting element 3, or may be provided so as to face a part of the side surface of the light emitting element 3. Further, the configuration of the second embodiment can be applied to the display device 1B.
  • FIG. 13 is a sectional view showing the display device according to the fourth embodiment.
  • the element insulating film 97 is provided so that the upper surface of the element insulating film 97 and the upper surface of the cathode terminal 32 form the same surface, but the present invention is not limited to this. ..
  • the height of the element insulating film 97 is lower than the height of the light emitting element 3.
  • the element insulating film 97 covers the anode electrode 23 and the connection layer 24. Further, the element insulating film 97 is provided so as to cover a part of the side surface of the light emitting element 3, and at least covers the side surface of the anode terminal 33.
  • the cathode electrode 22 covers the upper surface of the element insulating film 97, the cathode terminal 32 of the light emitting element 3 and a part of the side surface of the light emitting element 3.
  • the element insulating film 97 can ensure the insulation of the anode electrode 23 in the adjacent sub-pixels 49. In addition, the element insulating film 97 can secure the connection strength between the light emitting element 3 and the anode electrode 23. It is also possible to apply the configuration of the second embodiment to the display device 1C.
  • the portions described as the anode terminal 33 and the cathode terminal 32 are not limited to the description in the specification but may be reversed depending on the connection direction of the light emitting element 3 and the voltage application direction.
  • You may. 5, 11, 12 and the like show a configuration in which one electrode of the light emitting element 3 is on the lower side and the other electrode is on the upper side, but both of them are on the lower side, that is, the array substrate 2
  • the configuration may be on the side facing the surface.
  • Display device 2 Array substrate 3, 3R, 3G, 3B Light emitting element 12 Driving circuit 21 Substrate 22 Cathode electrode 23, 23A Anode electrode 24 Connection layer 27 Terminal part 28 Reflective layer 31 Semiconductor layer 32 Cathode terminal 33 Anode terminal 49 Subpixel 51 Conductive nanoparticles 60 Cathode wiring 100, 200 Film forming device 210 Driving IC DRT drive transistor BCT light emission control transistor IST initialization transistor CCT correction transistor SST write transistor Pix pixel RST reset transistor BG light emission control scan line SG write control scan line RG reset control scan line IG initialization control scan line CG correction control scan line

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