WO2020174735A1 - データ転送システムにおけるメモリカード、データ記録装置、システムホスト、及びメモリカード判別方法 - Google Patents

データ転送システムにおけるメモリカード、データ記録装置、システムホスト、及びメモリカード判別方法 Download PDF

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Publication number
WO2020174735A1
WO2020174735A1 PCT/JP2019/038565 JP2019038565W WO2020174735A1 WO 2020174735 A1 WO2020174735 A1 WO 2020174735A1 JP 2019038565 W JP2019038565 W JP 2019038565W WO 2020174735 A1 WO2020174735 A1 WO 2020174735A1
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WIPO (PCT)
Prior art keywords
unit
interface
memory card
memory
identifier
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Ceased
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PCT/JP2019/038565
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English (en)
French (fr)
Japanese (ja)
Inventor
山下　英明
大塚　健
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to JP2021501544A priority Critical patent/JPWO2020174735A1/ja
Publication of WO2020174735A1 publication Critical patent/WO2020174735A1/ja
Priority to US17/378,068 priority patent/US11809340B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Definitions

  • the present disclosure relates to a memory card, a data recording device, a system host, and a memory card discrimination method in a data transfer system for connecting a system host and a memory card by an adapter to transfer data.
  • the data transfer method of the memory card is shifting from the parallel data transfer method to the differential serial transfer method with the increase in the transfer speed of the flash memory.
  • a transfer method a PCI Express (registered trademark) (hereinafter referred to as a high-speed serial interface) is used.
  • PCIe PCIe are used in various electronic devices such as personal computers.
  • PCIe is also used in a system configuration in which a video server is a system host and a memory card is a local device.
  • a system that uses the local bus on the system host side as an external interface and logically maps it in physically different signals, and uses an external device such as an adapter to convert the external interface to the protocol of the local bus on the system host side is often used.
  • an external device such as an adapter to convert the external interface to the protocol of the local bus on the system host side
  • a chip integrated unit
  • JP, 2015-29352 A Japanese Patent Laid-Open No. 2009-282851 JP, 2009-087124, A JP-A-2015-180980 Japanese Patent Laid-Open No. 2009-070255 JP, 2013-127745, A
  • the present disclosure provides a memory card, a data recording device, a system host, and a memory card discriminating method for executing data transfer that reduces control parts and minimizes speed reduction and realizes cost reduction.
  • the memory card includes two external interfaces, a first interface unit and a second interface unit, which are connected to the system host, a memory unit, and an additional information registration unit.
  • the first interface unit controls an external device by an interface of a physical signal common to the local bus of the system host.
  • the second interface unit is an interface different from the local bus.
  • the memory unit includes a first identifier storage unit that stores the identifier of the memory unit, a flash memory that stores user data, and a memory that controls the first identifier storage unit and the flash memory via the first interface unit. And a control unit.
  • the additional information registration unit stores a second identifier storage unit that stores the same identifier as the memory unit and the additional information, and stores the identifier and the additional information in the second identifier storage unit via the second interface unit.
  • An additional information notification unit for notifying the system host.
  • the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first identifier storage unit and the second identifier storage unit.
  • a data recording device includes a cable for communicating with a system host a first data signal for high-speed data communication and a second data signal for standard data communication whose communication speed is slower than that of high-speed data communication.
  • a data recording device to be connected which includes an adapter and a memory card.
  • the adapter includes a first adapter interface unit that communicates a first data signal of the system host to the memory card, and a second adapter interface unit that communicates a second data signal of the system host to the memory card. It has an interface conversion part including.
  • the memory card communicates the first data signal and the second data signal of the adapter, and includes a memory unit and an additional information registration unit.
  • the first adapter interface unit is compatible with a plurality of types of communication protocols, and communicates with one selected communication protocol.
  • One communication protocol is a physical signal common to the local bus of the system host.
  • the interface controls external devices.
  • the second adapter interface unit specifies the type of the communication protocol in the first adapter interface unit immediately after the connection, makes the first adapter interface unit communicable with the communication protocol, and after making the communication possible. Communicate with a communication protocol different from the communication protocol in the first adapter interface unit.
  • the memory unit controls the first identifier storage unit that stores the identifier of the memory unit, the flash memory that stores the user data, and the first identifier storage unit and the flash memory via the first memory interface unit. And a memory control unit.
  • the additional information registration unit stores a second identifier storage unit that stores the same identifier as the memory unit and additional information, and stores the identifier and the additional information in the second identifier storage unit via the second memory interface unit.
  • the system host associates the memory unit and the additional information registration unit with the identifiers stored in the first identifier storage unit and the second identifier storage unit. ..
  • a system host includes a first interface connected to a first interface unit of a memory card, a second interface connected to a second interface unit of a memory card, and an identifier. And a corresponding part.
  • the first interface is an interface for a physical signal common to the local bus, and acquires an identifier and reads/writes user data via the first interface unit of the memory card.
  • the second interface controls the memory card by an interface different from the interface for the physical signal common to the local bus, and the first interface unit of the memory card is controlled via the second interface unit of the memory card.
  • An identifier that is the same as the identifier that is obtained through is acquired.
  • the identifier corresponding unit associates the first interface unit of the memory card with the second interface unit of the memory card when the memory card is connected.
  • a system host includes a first interface connected to a first interface unit of a memory card via a first interface unit of an adapter and a second interface of a memory card.
  • the unit is provided with a second interface connected via the second interface unit of the adapter, and an identifier corresponding unit.
  • the first interface is an interface for a physical signal common to the local bus, and acquires an identifier and reads/writes user data via the first interface unit of the memory card.
  • the second interface controls the memory card by an interface different from the interface for the physical signal common to the local bus, and the first interface unit of the memory card is controlled via the second interface unit of the memory card.
  • An identifier that is the same as the identifier that is obtained through is acquired.
  • the identifier corresponding unit associates the first interface unit of the memory card with the second interface unit of the memory card when the memory card is connected.
  • a memory card identification method includes a step of storing an identifier of a memory unit in a memory unit of a memory card, a step of storing an identifier of the additional information registration unit in an additional information registration unit of the memory card, and an identifier of the memory unit.
  • the memory card, the data recording device, and the system host for data transfer according to the present disclosure are connected to the memory card equivalently to the local bus on the system host side, thereby reducing control components and minimizing speed reduction. And at the same time realize cost reduction.
  • FIG. 1 is a schematic block diagram of a data transfer system according to a first embodiment.
  • FIG. 10 is a diagram showing that the system host recognizes that the first interface unit and the second interface unit logically exist in plurality.
  • FIG. 1 is a diagram of a stack of device drivers of a system host, showing a software configuration using a personal computer (PC) equipped with Windows (registered trademark) which is an operating system of Microsoft (registered trademark) as a system host as an example. is there.
  • FIG. 3 is a diagram of a stack of device drivers of a system host in the data transfer system according to the first embodiment, in a personal computer (PC) equipped with Windows (registered trademark) which is an operating system of Microsoft (registered trademark) company as a system host.
  • PC personal computer
  • Windows registered trademark
  • FIG. 4 is a sequence diagram illustrating the operation of each block of the data transfer system according to the first embodiment.
  • FIG. 6 is a schematic block diagram of a data transfer system according to a second embodiment.
  • FIG. 9 is a schematic block diagram of a data transfer system according to a third embodiment.
  • FIG. 10 is a schematic block diagram of a data transfer system according to a fourth embodiment. It is a block diagram of a memory card having two communication paths (a first communication path and a second communication path).
  • FIG. 9 is a sequence diagram illustrating an operation of each block of the memory card shown in FIG. 8 and the system host.
  • FIG. 1 It is a block diagram explaining the further prior art data transfer system which transmits/receives the data in a memory card to/from the system host represented by a personal computer. It is a sequence diagram explaining operation
  • a conventional memory card has a plurality of communication paths, and one communication path identifies the physical communication method of the memory card. Furthermore, after the connection of the other communication path is completed, the communication path for identifying the memory card can be used for simple data communication in parallel with the data transfer of the other communication path. A conventional technique will be described with reference to the block diagrams of FIGS. 8 and 10.
  • the memory card 19 shown in FIG. 8 has two communication paths (a first communication path 44 and a second communication path 46).
  • the first communication path 44 is a communication path for performing main high-speed transfer (high-speed data communication), and the second communication path 46 is communication for identifying the physical communication method of the first communication path 44. It is a route.
  • the memory card 19 includes a flash memory 26, a memory control unit 24, and a first interface unit 22.
  • the flash memory 26 is a non-volatile memory that keeps written data even when the power is turned off.
  • the memory control unit 24 performs initialization of the flash memory 26 and control of writing and reading of data.
  • the first interface unit 22 is an interface unit corresponding to a physical signal and a logical protocol of the first communication path 44. It is desirable that the first interface unit 22 perform high-speed data communication.
  • the memory card 19 includes a card identification information notification unit 27, a second interface unit 30, and an additional information notification unit 32.
  • the card identification information notification unit 27 is a notification unit that notifies the physical communication method of the first communication path 44.
  • the second interface unit 30 is an interface unit that converts a physical signal of the second communication path 46, and the additional information notifying unit 32, after the connection of the first communication path 44 is completed, the second interface unit 30. As a result, the card identification information notification unit 27 is changed to notify the additional information of the memory card 19 via the second communication path 46.
  • the additional information is, for example, information indicating access restriction of user data to the memory card 19.
  • the second interface unit 30 may perform standard data communication.
  • FIG. 9 is a sequence diagram for explaining the operation of each block of the memory card 19 shown in FIG. 8 and the system host 4 (not shown).
  • the system host 4 reads the card identification information from the card identification information notification unit 27 (S102), and acquires the card identification information from the card identification information notification unit 27 (S104).
  • the system host 4 activates the memory function of the memory control unit 24, initializes the memory control unit 24, and the like, and then puts the communication control unit in a communicable state through the first communication path 44 (S106). ..
  • the system host 4 records the data in the flash memory 26 and reads the data from the flash memory 26 by performing memory read/write control on the memory control unit 24 (S108). Further, the system host 4 requests additional information from the additional information notifying unit 32 (S110), and acquires additional information from the additional information notifying unit 32 (S112).
  • FIG. 10 is a block diagram illustrating a further conventional data transfer system 502 that transmits/receives the data in the memory card 120 to/from the system host 4 represented by a personal computer.
  • the data transfer system 502 shown in FIG. 10 includes a system host 4, an adapter 110, and a memory card 120.
  • the adapter 110 converts data for each interface between the system host 4 and the memory card 120 and provides a data read/write function to each.
  • the interface conversion unit 112 in the adapter 110 is an interface conversion unit that converts the protocol of the memory card 120 according to the interface with the system host 4.
  • the integration unit 113 of the adapter 110 is an integration unit that integrates and controls two communication paths of the memory card 120, the first communication path 44 and the second communication path 46. In this way, the data transfer system 502 shown in FIG. 10 supports data read/write by combining two communication paths in the adapter 110 and integrating them into one protocol for the system host 4. doing.
  • FIG. 11 is a sequence diagram illustrating the operation of each block of the data transfer system 502 shown in FIG. Of each block of the data transfer system 502, a processing sequence among the system host 4, the integration unit 113 (in the adapter 110), the additional information notification unit 32 (in the memory card 120), and the memory control unit 24 will be described. ..
  • the system host 4 makes a request to read additional information to the integration unit 113 (S202), and in response to this, the integration unit 113 makes a request to read additional information to the additional information notification unit 32 (S204).
  • the additional information notification unit 32 notifies the system host 4 of the additional information via the integration unit 113 (S206) (S208).
  • the system host 4 records and reads data in the flash memory 26 by performing memory read/write control on the memory control unit 24 (S212) via the integration unit 113 (S210) (S214). ).
  • the embodiment solves the above-mentioned problems, and by connecting up to a memory card equivalently to the local bus on the system host side, the control parts are reduced to minimize the speed reduction and realize the cost reduction.
  • FIG. 1 is a schematic block diagram of a data transfer system 2 according to the first embodiment. The configuration will be described focusing on the difference from the data transfer system 502 shown in FIG.
  • the data transfer system 2 shown in FIG. 1 performs high-speed data communication between the system host 4 and the hot-swappable memory card 20 via the adapter 10 that does not include the integration unit 113.
  • the main purpose of the reduction of the integration unit 113 is to reduce the speed and to realize the cost reduction.
  • the system host 4 has two external interfaces, a first interface and a second interface.
  • a local bus (first bus 40, second bus 42) is provided on the system host 4 side, and the local bus is a communication path (first communication path 44, second communication path 46) in the memory card 20.
  • the interface conversion unit 12 of the adapter 10 is provided with a first interface unit 16 for the first bus 40 and a second interface unit 18 for the second bus 42.
  • a protocol conversion unit 14 for protocol conversion between the second bus 42 and the second communication path 46 is provided in the adapter 10.
  • the protocol conversion unit 14 converts the data signal for the second interface unit 30 of the memory card 20 in the second interface unit 18 and transmits the data signal to the second interface unit 30 of the memory card 20.
  • a USB 3.1/Thunderbolt that performs high-speed data communication is assumed as the first bus 40, and a USB 2 that performs standard data communication that is a communication at a slower communication speed than the high-speed data communication is assumed as the second bus 42.
  • the first bus 40 and the second bus 42 may be SATA Express (SerialATA Express), OCuLink (Optical copper Link), RS-232C, RS-442, I2C, etc., respectively. That is, it is sufficient if the bus is composed of two different buses.
  • the first interface unit 16 is compatible with a plurality of types of communication protocols, and communicates with one selected communication protocol, and the one communication protocol of the system host 4 is used.
  • An external device can be controlled by a physical signal interface common to the local bus.
  • the second interface unit 18 specifies the type of the communication protocol in the first interface unit 16 immediately after the connection, makes the first interface unit 16 communicable with the communication protocol, and after making the communication possible, , An interface capable of performing communication using a communication protocol different from that of the first interface unit 16.
  • the first identifier storage unit 28 is an identifier storage unit that stores an identifier notified to the system host 4 via the first communication path 44, and the second identifier storage unit 34 is connected via the second communication path 46. It is an identifier storage unit that stores an identifier to be notified.
  • the first interface unit 22 of the memory card 20 controls an external device by an interface of a physical signal common to the local bus of the system host, and the second interface unit 30 of the memory card 20 connects to the local bus. May be different interfaces.
  • the first interface unit 22, the memory control unit 24, the flash memory 26, and the first identifier storage unit 28 in the memory card 20 as shown in FIG. 1 form a memory unit 29.
  • the second interface unit 30, the additional information notification unit 32, and the second identifier storage unit 34 in the memory card 20 form an additional information registration unit 35.
  • the additional information is, for example, information indicating access restriction of user data to the memory card 20.
  • the memory card 20 and the adapter 10 can realize a configuration in which a plurality of blocks are connected by a daisy chain.
  • the (lower) adapter 10 having the same function is connected to the (upper) adapter 10
  • the (lower) adapter 10 has the same function as the (upper) memory card 20.
  • a configuration example in which the (lower) memory card 20 is connected is realized.
  • the system host 4 has an identifier corresponding unit 8 that determines the identifier in the memory card 20.
  • the system host 4 logically has only a plurality of first interface units 16 and 22 and second interface units 18 and 30. recognize. That is, the system host 4 cannot grasp which first interface unit 16 or 22 is associated with which second interface unit 18 or 30.
  • the adapter 10 and the memory card 20 connected to the system host 4 by an interface cable and a daisy chain have a plurality of first interface units 16 and 22 and a first communication path 44, and a plurality of second interfaces.
  • the units 18 and 30 and the second communication path 46 are present, they are attached to the first interface unit 22 for the system host 4, the first interface unit driver 58, and the second interface unit driver 60.
  • the association between the memory control unit 24 and the additional information notification unit 32 attached to the second interface unit 30 is unknown. Therefore, the system host 4 has a disadvantage that it cannot properly use the additional information of each memory card.
  • FIG. 3 is a diagram of a stack of device drivers of the system host 4 in the data transfer system 2 according to the first embodiment.
  • FIG. 3 is a diagram showing a software configuration of a personal computer (PC) equipped with Windows (registered trademark) which is an operating system of Microsoft (registered trademark) as a system host.
  • the application 50 is software that includes a user interface and can be operated by the user, and corresponds to, for example, an explorer for file operations, an editing application for editing video, and the like.
  • the service 52 is software that operates between the application 50 and a software group that operates in a kernel space having a high processing priority.
  • the service 52 also provides a function of passing processing to software in the kernel space and a function common to a plurality of applications by performing an intermediate process as needed in response to an access from the application 50.
  • the service 52 has a function of bundling (associating) identifiers in the same memory card 20 (identifiers in the first identifier storage unit 28 and identifiers in the second identifier storage unit 34). provide.
  • the application 50 and the service 52 generally operate in a mode in the user space, and the processing priority is set lower than that in the kernel space.
  • the operating system (OS) 54 included in the kernel space provides the application 50 with basic functions.
  • the filter driver 56 is located between the operating system (OS) 54 and the software group closer to the hardware, performs a part of the processing from the user space, and then processes the lower software group. Hand over.
  • the filter driver 56 corresponds to the flash memory 26 based on the association information of the identifiers (first identifier and second identifier) in the same memory card 20 from the service 52. It has a function to hold additional information.
  • the kernel space further includes a first interface driver 58 and a second interface driver 60, which are a software group for controlling hardware.
  • the first interface unit driver 58 is a device driver that controls the first interface unit 16 of the adapter 10
  • the second interface unit driver 60 is a device driver that controls the second interface unit 18 of the adapter 10. Is.
  • the number of these drivers (58, 60) increases as the number of connected adapters 10 increases. For example, when two adapters 10 are connected, there are two first interface driver 58 and two second interface driver 60.
  • the interface cable 41 physically connects the system host 4 and the adapter 10.
  • the adapter 10 is a Thunderbolt (registered trademark) device, it is connected by a Thunderbolt-compatible USB-C cable.
  • Thunderbolt registered trademark
  • the interface cable 41 is used because the stack diagram in FIG. 3 is intended to explain the configuration of the software module. Is simply expressed as one block.
  • the first interface unit 16 and the second interface unit 18 of the adapter 10 are connected via the interface cable 41. Further, here, the first interface unit 16 of the adapter 10 and the first interface unit 22 of the memory card 20 are logically equivalent when viewed from the system host 4 side, and therefore the system host 4 loads the memory card 20. It can be controlled appropriately.
  • the relationship between the second interface unit 18 of the adapter 10 and the second interface unit 30 of the memory card 20 is the same.
  • the first interface unit 22 preferably performs high-speed data communication, and the second interface unit 30 may perform standard data communication.
  • FIG. 4 is a sequence diagram illustrating the operation of each block of the data transfer system 2 according to the first embodiment. The flow of processing in the data transfer system 2 will be described using the sequence diagram shown in FIG.
  • the module shown in FIG. 4 corresponds to the stack diagram of the device driver shown in FIG.
  • the first interface unit 16 of the adapter 10 When the memory card 20 is inserted into the adapter 10, the first interface unit 16 of the adapter 10 first turns on the power to the memory card 20, and the memory card 20 is inserted. A notification is sent from 16 to the first interface driver 58 (S02).
  • the first interface unit driver 58 initializes the device via the first interface unit 22 of the memory card 20, and notifies the OS 54 that the memory card 20 has been inserted (S04).
  • the OS 54 notifies the service 52 that the insertion of the memory card 20 has been detected, as an event (S06).
  • the notification to the service 52 by an event is shown as an example, but the service 52 mainly makes an inquiry to the memory card 20 at regular time intervals via the first interface driver 58. By performing (polling), the insertion of the memory card 20 may be detected.
  • the service 52 which has received the notification of the detection of the insertion of the memory card 20 from the first interface unit 16 of the adapter 10 sends an identifier read request to the first interface unit driver 58 (S08) and receives the request.
  • the first interface unit driver 58 sends an identifier read request to the first interface unit 16 of the adapter 10 (S10).
  • the first interface unit 16 of the adapter 10 uses the first communication path 44 and the identifier in the first identifier storage unit 28 obtained via the first interface unit 22 of the memory card 20 as the first Is sent to the interface driver 58 (S12), and the first interface driver 58 sends the identifier to the service 52 (S14).
  • the second interface unit 18 of the adapter 10 when the second interface unit 18 of the adapter 10 notifies the second interface unit driver 60 that the memory card 20 has been inserted (S16), the insertion is detected.
  • the interface driver 60 of No. 2 notifies the OS 54, and the OS 54 notifies the service 52 (S18, S20).
  • the service 52 that has received the notification of the detection of the insertion of the memory card 20 sends an identifier read request to the second interface driver 60 (S22), and the second interface driver 60 that has received the request sends the identifier.
  • the read request is sent to the second interface unit 18 of the adapter 10 (S24).
  • the second interface unit 18 of the adapter 10 uses the second communication path 46 and the identifier in the second identifier storage unit 34 obtained via the second interface unit 30 of the memory card 20 as the second Is sent to the interface driver 60 (S26), and the second interface driver 60 sends the identifier to the service 52 (S28).
  • the service 52 includes the identifier in the first identifier storage unit 28 obtained by the first interface unit 16 of the adapter 10 and the adapter 10 by the identifier corresponding unit 8 attached to the CPU 6 which is the central processing unit of the system host 4.
  • the identifiers in the second identifier storage unit 34 obtained by the second interface unit 18 are associated (S30). That is, the service 52 determines by the identifier correspondence unit 8 whether or not both identifiers are obtained from the same memory card 20, and associates them.
  • the service 52 issues an additional information read request for reading the additional information stored in the additional information notification unit 32 attached to the second interface unit 30 of the memory card 20 to the filter driver. 56 (S32).
  • the additional information read request sent to the filter driver 56 is sent to the second interface unit 18 of the adapter 10 via the second interface driver 60 (S34) (S36).
  • the second interface unit 18 of the adapter 10 uses the second communication path 46 and the additional information in the additional information notification unit 32 obtained via the second interface unit 30 of the memory card 20 as the second additional information.
  • the additional interface information is sent to the interface driver 60 (S38), and the second interface driver 60 sends the additional information to the filter driver 56 (S40).
  • the additional information is held by the filter driver 56 and then sent to the service 52 (S42).
  • the application 50 When the application 50 accesses the flash memory 26, the application 50 first issues a memory status confirmation request to the OS 54 (S44). At this time, since the filter driver 56 holds the memory status information as the additional information of the flash memory 26, the OS 54 issues a request for additional information to the filter driver 56 (S46). The OS 54 acquires the additional information of the flash memory 26 (S48) and returns the memory status information to the application 50 (S50). Based on the returned memory status information, the memory read/write control is performed by the application 50 by the OS 54 (S52), the first interface driver 58 (S54), and the first interface unit 16 (S56) of the adapter 10. ) And read/write data from/to the flash memory 26. The result of the data read/write is returned to the application 50 via the first interface unit 16 of the adapter 10 (S58).
  • the memory card 20 has the two external interfaces of the first interface section 22 and the second interface section 30 which are connected to the system host 4, and the memory section 29. And the additional information registration unit 35.
  • the first interface unit 22 controls an external device with an interface of a physical signal common to the local bus of the system host 4, and the second interface unit 30 is an interface different from the local bus.
  • the memory unit 29 includes a first identifier storage unit 28 that stores the identifier of the memory unit 29, a flash memory 26 that stores user data, and a first identifier storage unit 28 and a flash via the first interface unit 22. It has a memory control unit 24 for controlling the memory 26.
  • the additional information registration unit 35 stores a second identifier storage unit 34 that stores the same identifier as the memory unit 29, and an identifier in the second identifier storage unit 34 that stores additional information and that stores the additional information via the second interface unit 30. And an additional information notifying unit 32 for notifying the system host 4 of the additional information.
  • the system host 4 associates the memory unit 29 with the additional information registration unit 35 with the identifiers stored in the first identifier storage unit 28 and the second identifier storage unit 34. I do.
  • the adapter 10 is connected to the system host 4 by an interface cable 41 that communicates a first data signal for high speed data communication and a second data signal for standard data communication, and transmits the first data signal of the system host 4 to the system host 4.
  • the interface conversion unit 12 includes a first interface unit 16 for communicating with the memory card and a second interface unit 18 for communicating a second data signal of the system host 4 with the memory card 20.
  • the first interface unit 16 is compatible with a plurality of types of communication protocols, communicates with one selected communication protocol, and one communication protocol is local to the system host 4. Controls external devices with a physical signal interface common to the bus.
  • the second interface unit 18 specifies the type of communication protocol in the first interface unit 16 immediately after the connection, makes the first interface unit 16 communicable with the communication protocol, and after making the communication possible, This is an interface for performing communication using a communication protocol different from that of the interface unit 16 of No. 1.
  • FIG. 5 is a schematic block diagram of the data transfer system 102 according to the second embodiment.
  • the data transfer system 102 according to the second embodiment shown in FIG. 5 has substantially the same configuration as the data transfer system 2 according to the first embodiment shown in FIG.
  • the configuration of the adapter 10A of the data transfer system 102 is different from that of the adapter 10 of the data transfer system 2.
  • the system host 4 and the adapter 10A and the adapter 10A and the adapter 10A connected by a daisy chain are connected only by the first bus 40. It That is, although one local bus (first bus 40) is provided on the system host 4 side, the local bus logically has two communication paths (first communication path 44, second communication path 44 and second communication path 44) in the memory card 20. Communication path 46) is included. Therefore, the adapter 10A includes only the first interface unit 16 corresponding to the first bus 40.
  • FIG. 6 is a schematic block diagram of the data transfer system 202 according to the third embodiment.
  • the data transfer system 202 according to the third embodiment shown in FIG. 6 also differs from the data transfer system 102 according to the second embodiment shown in FIG. 5 in the configurations of the system host 4A, the adapter 11, and the memory card 21.
  • the system host 4A and the interface conversion unit 12 of the adapter 11 are provided with Bus number setting units 7 and 13, respectively.
  • the Bus number setting units 7 and 13 assign a unique Bus number to each bus (and communication path) according to a predetermined logic.
  • the memory card 21 in the data transfer system 202 according to the third embodiment does not include the first identifier storage unit or the second identifier storage unit.
  • the system host 4A of the data transfer system 202 uses the flash number 26 and the flash memory 26 in the same memory card 21 according to the bus number assignment logic for each bus in the bus number setting units 7 and 13.
  • the corresponding additional information (in the additional information notification unit 32) is linked.
  • FIG. 7 is a schematic block diagram of the data transfer system 302 according to the fourth embodiment.
  • the data transfer system 302 according to the fourth embodiment shown in FIG. 7 also has substantially the same configuration as the data transfer system 2 according to the first embodiment shown in FIG.
  • the data recording device in which the adapter 10 and the memory card 20 in the data transfer system 2 according to the first embodiment shown in FIG. 70 is formed.
  • the control components are reduced and the speed reduction is minimized. Cost reduction can be realized.
  • Embodiments 1 to 4 have been described as examples of the technology disclosed in the present application. However, the technique in the present disclosure is not limited to this, and is also applicable to the embodiment in which changes, replacements, additions, omissions, etc. are appropriately made. Further, it is also possible to combine the constituent elements described in the first to fourth embodiments to form a new embodiment.
  • the present disclosure can be used in a PCIe-compatible information processing device.
  • Second interface Unit 19 20, 21, 120 memory card 22 first interface unit 24 memory control unit 26 flash memory 28 first identifier storage unit 29 memory unit 30 second interface unit 32 additional information notification unit 34 second identifier storage Unit 35 Additional information registration unit 40 First bus 41 Interface cable 42 Second bus 44 First communication path 46 Second communication path 50 Application 52 Service 54 Operating system (OS) 56 Filter Driver 58 First Interface Driver 60 Second Interface Driver 70 Data Recording Device

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PCT/JP2019/038565 2019-02-25 2019-09-30 データ転送システムにおけるメモリカード、データ記録装置、システムホスト、及びメモリカード判別方法 Ceased WO2020174735A1 (ja)

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