WO2020168849A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2020168849A1
WO2020168849A1 PCT/CN2020/070886 CN2020070886W WO2020168849A1 WO 2020168849 A1 WO2020168849 A1 WO 2020168849A1 CN 2020070886 W CN2020070886 W CN 2020070886W WO 2020168849 A1 WO2020168849 A1 WO 2020168849A1
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Prior art keywords
pixel
sub
row
gate line
pixel unit
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PCT/CN2020/070886
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English (en)
French (fr)
Inventor
袁粲
李永谦
李蒙
袁志东
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020560841A priority Critical patent/JP2022522313A/ja
Priority to EP20759625.5A priority patent/EP3929993B1/en
Priority to US16/767,296 priority patent/US11257432B2/en
Publication of WO2020168849A1 publication Critical patent/WO2020168849A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • the embodiments of the present disclosure relate to a display panel, a driving method thereof, and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • At least one embodiment of the present disclosure provides a display panel including a plurality of pixel units arranged in an array, and data lines and sensing lines connected to the pixel units, each pixel unit includes a plurality of sub-pixels; the same column of pixel units All the sub-pixels in are connected to the same data line, each column of pixel units are respectively connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines.
  • the display panel provided by at least one embodiment of the present disclosure further includes a gate line group connected to the sub-pixels, each row of pixel units is respectively connected to two gate line groups to receive scan driving signals, and any two adjacent ones Row pixel units share one gate line group, and the gate line group includes a first gate line and a second gate line.
  • the display panel includes M ⁇ N pixel units and N+1 rows of gate line groups, and each pixel unit includes a first sub-pixel, a second sub-pixel, and The third sub-pixel; the first sub-pixel in the pixel unit of the nth row and the mth column is respectively connected to the first gate line of the nth row, the second gate line of the nth row, the sensing line of the mth column, and the mth column The second sub-pixel in the pixel unit of the nth row and the mth column is connected to the first gate line of the n+1th row, the second gate line of the n+1th row, and the sense of the m+1th column.
  • the measurement line and the data line of the mth column are connected; the third sub-pixel in the pixel unit of the nth row and the mth column is connected to the first gate line of the nth row, the second gate line of the n+1th row, and the mth column respectively
  • the sensing line and the data line of the mth column are connected; M represents the number of pixel units in the column direction, N represents the number of pixel units in the row direction, 1 ⁇ n ⁇ N, 1 ⁇ m ⁇ M, and both M and N A positive integer greater than 1.
  • each sub-pixel includes a light-emitting device, a pixel drive circuit for driving the light-emitting device to emit light, and a sensing device for sensing the pixel drive circuit.
  • the pixel driving circuit includes a data writing sub-circuit and a driving sub-circuit; the driving sub-circuit and the data writing sub-circuit, the light-emitting device and the sensing circuit are connected, and are configured for control Driving current for driving the light-emitting device to emit light; the data writing sub-circuit is configured to receive the scan driving signal, and in response to the scan driving signal, write a data voltage into the driving sub-circuit; The test circuit is also connected to the drive sub-circuit, and is configured to receive the scan drive signal, and in response to the scan drive signal, write a reference voltage signal to the drive sub-circuit or read out the sensor from the drive sub-circuit. Measure the voltage signal.
  • the pixel driving circuit further includes a storage sub-circuit, the storage sub-circuit is connected to the light emitting device, and is configured to store the written data voltage and The reference voltage signal.
  • the sensing circuit includes a first transistor
  • the data writing sub-circuit includes a second transistor
  • the driving sub-circuit includes a driving transistor
  • the storage sub-circuit includes a driving transistor.
  • the circuit includes a storage capacitor; for the first sub-pixel in the pixel unit of the nth row and mth column, the gate of the first transistor is connected to the first gate line of the nth row, and the The first electrode is connected to the sensing line of the mth column; the gate of the second transistor is connected to the second gate line of the nth row, and the first electrode of the second transistor is connected to the mth row.
  • the gate of the first transistor is connected to the first gate line of the n+1th row, and the The first electrode of a transistor is connected to the sensing line of the m+1th column; the gate of the second transistor is connected to the second gate line of the n+1th row, and the first electrode of the second transistor One pole is connected to the data line in the mth column; for the third sub-pixel in the pixel unit in the nth row and mth column, the gate of the first transistor is connected to the second The gate line is connected, the first electrode of the first transistor is connected to the sensing line of the mth column; the gate of the second transistor is connected to the first gate line of the nth row, and the second The first electrode of the transistor is connected to the data line of the m-th column; for any sub-pixel, the second electrode of the first transistor is connected to the first end of the storage capacitor; the second electrode of the second transistor Connected
  • the first transistor, the second transistor, and the driving transistor are all N-type transistors, or all are P-type transistors.
  • the color of light emitted by the first sub-pixel in the pixel unit of the nth row is the same as that of the second sub-pixel in the pixel unit of the n+1th row.
  • the second sub-pixel in the pixel unit of the nth row has the same color as the light emitted by the first sub-pixel in the pixel unit of the n+1th row.
  • the color of light emitted by the third sub-pixel in each pixel unit is the same.
  • the colors of light emitted by the first sub-pixel, the second sub-pixel, and the third sub-pixel in each pixel unit are all different.
  • At least one embodiment of the present disclosure further provides a display device, comprising the display panel according to any one of claims 1-10.
  • the display device provided by at least one embodiment of the present disclosure further includes a source driving chip connected to the data line in the display panel to provide a data voltage, and the source driving chip is connected to the The sensing line in the display panel is connected to provide a reference voltage signal or receive a sensing voltage signal.
  • the display device provided by at least one embodiment of the present disclosure further includes a gate driving chip connected to the gate line group in the display panel and configured to direct the gate line group to the gate line group through the gate line group.
  • the pixel units in the display panel provide scan driving signals.
  • At least one embodiment of the present disclosure further provides a driving method of a display panel, including a display period and a blanking period for one frame, and the driving method includes: in the display period, the gate line group sequentially provides the Scan driving signals to the N rows of pixel units, so that the pixel drive circuits in the N rows of pixel units drive the light emitting devices in the N rows of pixel units to emit light; in the blanking period, the gate line The group provides the scan driving signal to the pixel unit of the ith row of the N rows of pixel units, so that the sensing circuit in the pixel unit of the ith row performs sensing; 1 ⁇ i ⁇ N.
  • the driving period of each row of pixel units in the N rows of pixel units includes a first time period, a second time period, and a third time period.
  • the scan driving signal of the first gate line of the n-1th row and the scan driving signal of the second gate line of the nth row are both high Level to write the data voltage into the third sub-pixel in the pixel unit of the n-1th row and mth column;
  • the scan driving signals of the first gate line in the nth row are both high levels to write the data voltage into the second sub-pixel in the pixel unit of the n-1th row and the mth column and the nth row the first sub-pixel in the m-column pixel unit;
  • the third time period the scan driving signals input by the first gate line in the n-1th row and the second gate line in the
  • the driving method provided by at least one embodiment of the present disclosure further includes: inputting a reference voltage signal to both the m-th column of sensing lines and the m+1-th column of sensing lines.
  • the driving period of each row of pixel units in the N rows of pixel units includes a fifth time period, a sixth time period, and a seventh time period.
  • Time period and eighth time period in the fifth time period, read the sensing voltage signal of the first sub-pixel in the pixel unit in the n-1th row and the mth column and the pixel unit in the n-2th row and the mth column
  • in the sixth time period read the sensing voltage signal of the third sub-pixel in the n-1th row and mth column pixel unit, so as to compare the n-1th row and mth column
  • the third sub-pixel in the pixel unit performs compensation
  • in the seventh time period the sensing voltage signal of the first sub-pixel in the
  • the third sub-pixel in the unit is compensated; 3 ⁇ n ⁇ N, and N is a positive integer greater than 3.
  • FIG. 1A is a schematic diagram of a pixel circuit
  • FIG. 1B shows a schematic structural diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 1C shows a schematic structural diagram of a sub-pixel provided by at least one embodiment of the present disclosure
  • FIG. 2 shows a circuit diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 3 shows a partial schematic diagram of a pixel unit shown in FIG. 2;
  • FIG. 4 shows a driving timing diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 5 shows a timing diagram of a display panel in a display period and a blanking period according to at least one embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • Pixel circuits in OLED display devices generally adopt a matrix driving method, and are divided into active matrix (Active Matrix) driving and passive matrix (Passive Matrix) driving according to whether switching elements are introduced in each pixel unit.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that the OLED emits light as needed.
  • the basic pixel circuit used in the AMOLED display device is usually a 2T1C pixel circuit, which uses two thin-film transistors (TFT) and a storage capacitor Cst to realize the function of driving the OLED to emit light.
  • FIG. 1A shows a schematic diagram of an externally compensated pixel circuit.
  • the pixel circuit includes a switching transistor T1, a driving transistor T3, a storage capacitor Cst, a sensing transistor T2, and an organic electroluminescence (EL) device (ie, an organic light emitting diode).
  • the sensing transistor T2 can implement a compensation function.
  • the gate of the switching transistor T1 is connected to the gate line to receive the scan driving signal G1; for example, the source of the switching transistor T1 is connected to the data line to receive the data signal Vdata; the drain of the switching transistor T1 is connected to the driving transistor T3
  • the gate of the drive transistor T3 is connected to the first voltage terminal to receive the first voltage Vdd (high voltage)
  • the source of the drive transistor T3 is connected to the positive terminal of the EL device
  • one end of the storage capacitor Cst is connected to the switching transistor
  • the drain of T1 and the gate of the driving transistor T3 are connected to the source of the driving transistor T3.
  • the negative terminal of the EL device is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the data signal Vdata input by the data driving circuit through the data line can charge the storage capacitor Cst through the switching transistor T1, thereby storing the data signal Vdata in the storage capacitor In Cst, and the stored data signal Vdata can control the conduction degree of the driving transistor T3, thereby controlling the current flowing through the driving transistor T3 to drive the OLED to emit light, that is, the current determines the gray scale of the pixel's light emission.
  • the first end of the sensing transistor T2 is connected to the source of the driving transistor T3, and the second end of the sensing transistor T2 is connected to a detection circuit (for example, including a resistor Rvc, a capacitor Cvc, and a mold Digital conversion (ADC), amplifier and other devices) are connected, and the gate of the sensing transistor T2 receives the compensation scanning signal G2. Therefore, after the compensation scan signal G2 is applied to turn on the driving transistor T3, the detection circuit is charged via the sensing transistor T2, so that the source potential of the driving transistor T3 changes.
  • a detection circuit for example, including a resistor Rvc, a capacitor Cvc, and a mold Digital conversion (ADC), amplifier and other devices
  • the driving transistor T3 When the voltage Vs of the source of the driving transistor T3 is equal to the difference between the gate voltage Vg of the driving transistor T3 and the threshold voltage Vth of the driving transistor T3, the driving transistor T3 is turned off. At this time, after the driving transistor T3 is turned off, the sensing voltage (ie, the source voltage Vb of the driving transistor T3 after the driving transistor T3 is turned off) can be obtained from the source of the driving transistor T3 through the turned-on sensing transistor T2.
  • the sensing voltage ie, the source voltage Vb of the driving transistor T3 after the driving transistor T3 is turned off
  • COF Chip On Film, flip-chip film
  • At least one embodiment of the present disclosure provides a display panel including a plurality of pixel units arranged in an array, and data lines and sensing lines connected to the pixel units, each pixel unit includes a plurality of sub-pixels; All sub-pixels are connected to the same data line, each column of pixel units is respectively connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines.
  • each column of pixel units are respectively connected to two sensing lines, and any two adjacent columns of pixel units share them
  • One sensing line reduces the number of data lines and sensing lines.
  • FIG. 1B shows a schematic structural diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel 110 includes a plurality of pixel units 10 arranged in an array, and data lines and sensing lines connected to the pixel units 10, such as data lines Dm and data lines Dm as shown in FIG. 1B. 1.
  • the sensing line Sm, the sensing line Sm+1 and the sensing line Sm+2, each pixel unit 10 includes 3 sub-pixels; for example, as shown in FIG. 1B, all the sub-pixels in the same column of pixel units 10 are The same data line is connected, each column of pixel units 10 is respectively connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines.
  • the sensing line is used to provide a sensing signal (for example, a reference voltage signal) or receive transmission of a sensing voltage signal.
  • m is an integer greater than or equal to 1.
  • each pixel unit 10 may also include 6, 9, or more sub-pixels, which is not limited in the embodiment of the present disclosure.
  • the pixel unit 10 in the mth column and the pixel unit 10 in the m+1th column are respectively. All the sub-pixels in the pixel unit 10 in the mth column are connected to the data line Dm, and the m+1th column All sub-pixels in the pixel unit 10 are connected to the data line Dm+1, so that the number of data lines in the display panel can be reduced; the pixel unit 10 in the mth column is connected to the sensing line Sm and the sensing line Sm+1, respectively.
  • the pixel unit 10 in the +1 column is respectively connected to the sensing line Sm+1 and the sensing line Sm+2. Therefore, it can be seen that the pixel unit 10 in the m-th column and the pixel unit 10 in the m+1-th column share the sensing line Sm+ 1. Thus, the number of sensing lines in the display panel can be reduced.
  • each pixel unit 10 includes a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13 is taken as an example to illustrate the difference between the embodiments of the present disclosure and the existing ones.
  • M represents the number of pixel units in the column direction
  • N represents the number of pixel units in the row direction
  • both M and N are positive integers greater than 1.
  • the first arrangement is Strip (strip) arrangement, that is, the first sub-pixel, the second sub-pixel and the second sub-pixel in the pixel unit.
  • the three sub-pixels are arranged side by side, the first sub-pixel, the second sub-pixel and the third sub-pixel in each column of pixel units are respectively connected to a data line, and all the sub-pixels in each column of pixel units share a sensing line,
  • the display panel adopts the first arrangement, and the number of data lines and sensing lines is 4 ⁇ M;
  • the second arrangement is Square (pin-shaped) arrangement, and each column of pixel units is connected to two Data lines, and all sub-pixels in each column of pixel units share one sensing line, the second arrangement is adopted for the display panel, and the number of data lines and sensing lines is 3 ⁇ M.
  • each column of pixel units 10 are respectively connected to two sensing lines, and any two adjacent columns of pixel units 10 are shared
  • the number of data lines and sensing lines in the display panel of the embodiment of the present disclosure is 2 ⁇ M+1.
  • the display panel provided by the embodiment of the present disclosure can greatly reduce the number of data lines and sensing lines, so that the COF is used to combine the source driving chip with the display panel.
  • the data line and the sensing line are connected, the hardware cost and bonding difficulty can be reduced, and the bonding yield can be improved.
  • the resolution of an 8K display panel is 7680 ⁇ 4320, that is, the display panel includes 7680 ⁇ 4320 pixel units 10.
  • the number of data lines and sensing lines in the display panel of the embodiment of the present disclosure is less than the number of data lines and sensing lines in the existing display panel, so that the data lines and sensing lines in the display panel The number of measurement lines is reduced.
  • COF is subsequently used to connect the source driver chip with the data lines and sensing lines in the display panel
  • the signal transmission lines that need to be designed on the circuit board and COF are also reduced accordingly, thereby reducing the circuit board and COF
  • the cost of hardware is high, and when COF is used for bonding, the difficulty of bonding will also be reduced, thereby increasing the bonding yield.
  • the display panel of the embodiment of the present disclosure The reduction in the number of data lines and sensing lines will also reduce the pins of the source driver chip required, thereby reducing the cost of the source driver chip.
  • each pixel unit 10 may also include multiple sub-pixels, for example, each pixel unit 10 may also include 4 sub-pixels and so on.
  • the display panel 110 further includes a gate line group connected to the sub-pixels; each row of pixel units 10 is respectively connected to two gate line groups, and any two adjacent rows of pixel units 10 share one of the gate lines.
  • the gate line group includes a first gate line and a second gate line, such as the first gate line G1_ ⁇ n-1>, the first gate line G1_ ⁇ n>, and the first gate line G1_ ⁇ n+ in FIG. 1B 1> and the first gate line G1_ ⁇ n+2>, the second gate line G2_ ⁇ n-1>, the second gate line G2_ ⁇ n>, the second gate line G2_ ⁇ n+1> and the second gate line G2_ ⁇ n+2>.
  • n is an integer greater than 2.
  • the first gate line G1_ ⁇ n-1> and the second gate line G2_ ⁇ n-1> form a gate line group
  • the first gate line G1_ ⁇ n> and the second gate line G2_ ⁇ n> form a gate line Group
  • the first gate line G1_ ⁇ n+1> and the second gate line G2_ ⁇ n+1> form a gate line group
  • the first gate line G1_ ⁇ n+2> and the second gate line G2_ ⁇ n+2> Form a grid line group.
  • the pixel units 10 in the n-1th row, the pixel units 10 in the n+1 row, and the pixel units 10 in the n+1th row are respectively connected with the pixel units 10 in the n-1th row.
  • the gate line group G1_ ⁇ n-1> and the second gate line G2_ ⁇ n-1> and the gate line group including the first gate line G1_ ⁇ n> and the second gate line G2_ ⁇ n> are connected.
  • the row of pixel units 10 are respectively connected to the gate line group including the first gate line G1_ ⁇ n> and the second gate line G2_ ⁇ n> and the first gate line G1_ ⁇ n+1> and the second gate line G2_ ⁇ n+1 > Is connected to the gate line group of >, the pixel unit 10 in the n+1th row is respectively connected to the gate line group including the first gate line G1_ ⁇ n+1> and the second gate line G2_ ⁇ n+1> and the gate line group including the first gate line G1_ ⁇ n+2> is connected to the gate line group of the second gate line G2_ ⁇ n+2>.
  • the pixel unit 10 in the nth row and the pixel unit 10 in the n-1th row share the first gate line G1_ ⁇ n> and the gate line group of the second gate line G2_ ⁇ n>
  • the pixel unit 10 of the nth row and the pixel unit 10 of the n+1th row share the first gate line G1_ ⁇ n+1> and the second gate line G2_ ⁇ n+1> grid line group.
  • the number of gate lines in the display panel 110 of the embodiment of the present disclosure is 2 ⁇ N+2. In some display panels, the number of gate lines is 2 ⁇ N. Therefore, there are two more gate lines in the display panel of the embodiment of the present disclosure than in the existing display panel, and the number of gate lines increases very little , which is basically negligible. Therefore, the embodiments of the present disclosure can reduce the number of data lines and sensing lines on the basis of basically not increasing gate lines, thereby simplifying the wiring design of the display panel.
  • each row of pixel units 10 is respectively connected to two gate line groups, and any two adjacent rows of pixel units
  • the connected gate line groups 10 are not shared. Therefore, when the display panel includes M ⁇ N pixel units 10, the number of gate lines in the display panel is 4 ⁇ N. If the display panel of the embodiment of the present disclosure adopts GOA (Gate Driver On Array (array substrate row drive) design, although the number of gate lines has increased, since the gate lines do not need to be bonded to the gate driving chip, the bonding difficulty of the display panel will not be affected.
  • GOA Gate Driver On Array
  • the display panel 110 includes M ⁇ N pixel units 10, and each pixel unit 10 includes a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13; the pixel unit in the nth row and mth column
  • the first sub-pixel 11 in 10 corresponds to the first gate line G1_ ⁇ n> in the nth row, the second gate line G2_ ⁇ n> in the nth row, the sensing line Sm in the mth column, and the data in the mth column.
  • Line Dm is connected; the second sub-pixel 12 in the pixel unit 10 in the nth row and mth column is connected to the first gate line G1_ ⁇ n+1> in the n+1th row and the second gate line G2_ in the n+1th row, respectively.
  • the sensing line Sm+1 in the m+1th column and the data line Dm in the mth column are connected; the third sub-pixel 13 in the pixel unit 10 in the nth row and mth column is connected to the The first gate line G1_ ⁇ n>, the second gate line G2_ ⁇ n+1> in the n+1th row, the sensing line Sm in the mth column, and the data line Dm in the mth column are connected; for example, M represents the column direction
  • N represents the number of pixel units in the row direction, 1 ⁇ n ⁇ N, 1 ⁇ m ⁇ M, and both M and N are positive integers greater than 1.
  • n and m are also positive integers.
  • the first sub-pixel 11 in the pixel unit 10 in the nth row and the second sub-pixel 12 in the pixel unit 10 in the n+1th row have the same color of light
  • the second sub-pixel 12 in the pixel unit 10 has the same color as the light emitted by the first sub-pixel 11 in the pixel unit 10 in the n+1 row; the light emitted by the third sub-pixel 13 in each pixel unit 10 is The colors are all the same.
  • the first sub-pixel 11 in the pixel unit 10 in the n-th row and the second sub-pixel 12 in the pixel unit 10 in the n-1th row share the same components including the first gate line G1_ ⁇ n> and the second gate line G2_ ⁇ n>
  • the gate line group, the second sub-pixel 12 in the pixel unit 10 in the nth row and the first sub-pixel 11 in the pixel unit 10 in the n+1th row share a first gate line G1_ ⁇ n+1> and a second gate line
  • the first sub-pixel 11 in the pixel unit 10 in the nth row is The second sub-pixel in the pixel unit 10 in the n-1th row needs to be displayed simultaneously, and the second sub-pixel in the pixel unit 10 in the nth row and the first sub-pixel in the pixel unit 10 in the n+1th row need to
  • the first sub-pixel 11 in the pixel unit 10 in the nth row needs to be
  • the color of the light emitted by the second sub-pixel 12 in the pixel unit 10 in the n+1th row is set to be the same, and the second sub-pixel 12 in the pixel unit 10 in the n+1 row is set to be the same as that in the pixel unit 10 in the n+1th row.
  • the colors of the light emitted by the first sub-pixels 11 are set to be the same.
  • the color of the light emitted by it is the same, and in the actual display process of the pixel unit 10, the third sub-pixel 13 is not displayed simultaneously with other sub-pixels.
  • the first sub-pixel 11 in the n-th row of pixel unit 10 is a green sub-pixel
  • the second sub-pixel 12 in the n-th row of pixel unit 10 is a red sub-pixel
  • the third sub-pixel in the n-th row of pixel unit 10 13 is a blue sub-pixel
  • the first sub-pixel 11 in the pixel unit 10 in the n+1th row is a red sub-pixel
  • the second sub-pixel 12 in the pixel unit 10 in the n+1-th row is a green sub-pixel.
  • the third sub-pixel in the pixel unit 10 of the +1 row is a blue sub-pixel.
  • the colors of the light emitted by the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 in each pixel unit 10 are all different.
  • the colors of the light emitted by the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 in the pixel unit 10 need to be set to be different, for example,
  • the colors of light emitted by one sub-pixel 11, second sub-pixel 12, and third sub-pixel 13 are red, green, and blue, respectively. It should be noted that the embodiment of the present disclosure does not limit this, and the specific setting of the color of each sub-pixel in each pixel unit is set according to the above description, which will not be repeated here.
  • FIG. 1C shows a schematic structural diagram of a sub-pixel provided by at least one embodiment of the present disclosure.
  • each sub-pixel includes a light emitting device L, a pixel driving circuit 410 for driving the light emitting device to emit light, and a sensing circuit 420 for sensing the pixel driving circuit 410.
  • the first sub-pixel 11 of the pixel unit of the n-th row is taken as an example for description, and the structures of other sub-pixels are similar to this, and will not be repeated.
  • the pixel driving circuit 410 includes a data writing sub-circuit 411 and a driving sub-circuit 412; in other examples, the pixel driving circuit 410 further includes a storage sub-circuit 413.
  • the pixel driving circuit 410 in the first sub-pixel 11 may drive the light emitting device L to emit light; in the blanking period of one frame, the sensing circuit 420 in the first sub-pixel 11 may The pixel driving circuit 410 is sensed, so that external compensation for the first sub-pixel 11 can be realized according to the sensing result.
  • the driving sub-circuit 412 and the data writing sub-circuit 411, the parasitic capacitance (not shown in the figure) or the storage sub-circuit 413, the light-emitting device L and the sensing circuit 420 are connected, and are configured to control the light-emitting device L for driving the light-emitting device L to emit light.
  • the drive current For example, in the light-emitting phase, the driving sub-circuit 412 may provide a driving current to the light-emitting device L to drive the light-emitting device L to emit light, and may emit light according to a desired "gray scale" (ie, data voltage).
  • the data writing sub-circuit 411 is also connected to a parasitic capacitance (not shown in the figure) or a storage sub-circuit 413, and is configured to receive a scan driving signal and write a data voltage to the driving sub-circuit 412 in response to the scan driving signal.
  • the data writing sub-circuit 411 is connected to the gate line G2_ ⁇ n> to receive a scan driving signal, and the data writing circuit 411 may be turned on in response to the scan driving signal.
  • the data writing sub-circuit 411 in the first sub-pixel 11 of the pixel unit in the nth row and mth column may also be connected to the data line Dm to receive the data voltage, and when the data writing subcircuit 411 is turned on The data voltage is written into the driving sub-circuit 412.
  • the data voltage received by the data writing sub-circuit 411 may be a compensated data voltage for the first sub-pixel 11 to emit light, or it may be a data voltage for other sub-pixels to emit light. The embodiment of the present disclosure does not limit this.
  • the sensing circuit 420 is also connected to a parasitic capacitance (not shown in the figure) or a storage sub-circuit 413 and the light emitting device L, and is configured to receive a scan driving signal, and in response to the scan driving signal, the reference voltage signal (for example, low Level) write to the driver sub-circuit 412 or read out the sensing voltage signal from the driver sub-circuit 412.
  • the sensing circuit 420 is connected to the gate line G1_ ⁇ n> to receive a scan driving signal, and the sensing circuit 420 may be driven in response to the scan driving signal. through.
  • the sensing circuit 420 in the first sub-pixel 11 of the pixel unit in the nth row and the mth column may also be connected to the sensing line Sm.
  • the sensing circuit 420 may pass through The reference voltage signal received by the sensing line Sm is written into the driving sub-circuit 412, or the sensing circuit 420 may also output the sensing voltage signal read from the driving sub-circuit 412 through the sensing line Sm.
  • the display panel 110 provided by the embodiment of the present disclosure may further include a sample-and-hold circuit S/H, an analog-to-digital conversion circuit ADC, a first switch K1, and a second switch K2.
  • a sample-and-hold circuit S/H an analog-to-digital conversion circuit ADC
  • a first switch K1 when the reference voltage signal needs to be written through the sensing line Sm, the first switch K1 is closed and the second switch K2 is opened.
  • the sensing voltage signal needs to be read through the sensing line Sm, the first switch K1 is opened and the second switch K2 is closed.
  • the sample and hold circuit S/H is configured to sample and hold the sensed voltage signal.
  • the analog-to-digital conversion circuit ADC is connected to the sample-and-hold circuit S/H, and is configured to perform analog-to-digital conversion (analog signal conversion into digital signal) of the sensed voltage signal after sampling and holding to facilitate subsequent further data processing. For example, by processing the sensed voltage signal, compensation information about the threshold voltage Vth and the current coefficient K in the driving sub-circuit 412 can be obtained.
  • the sensing voltage signal can be obtained by the sensing circuit 420, and further data processing of the sensing voltage signal can be performed to obtain compensation information about the threshold voltage Vth and the current coefficient K;
  • the light-emitting device L is driven again according to the compensation information obtained above, so as to complete the external compensation of the first sub-pixel 11 of the n-th row of pixel units.
  • the specific compensation method can refer to the method in this field, which will not be repeated here.
  • the storage sub-circuit 413 is also connected to the light emitting device L, and is configured to store the written data voltage and the reference voltage signal.
  • the storage sub-circuit 413 can simultaneously store the data voltage.
  • the storage sub-circuit 413 may simultaneously store the reference voltage signal.
  • FIG. 2 shows a circuit diagram of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 3 shows a partial schematic diagram of a pixel unit in FIG. 2.
  • each pixel unit 10 may be implemented as the circuit structure shown in FIG. 3.
  • the sensing circuit 420 may be implemented as a first transistor T1
  • the data writing sub-circuit 411 may be implemented as a second transistor T2
  • the driving sub-circuit 412 may be implemented as a driving transistor T3
  • the storage sub-circuit 413 may be implemented as a storage capacitor C.
  • the first sub-pixel 11 in the pixel unit 10 in the n-th row and m-th column is taken as an example to describe the transistors in the sub-pixel in detail.
  • the structure of the remaining sub-pixels is similar to the structure of the first sub-pixel 11 in the pixel unit 10 in the nth row and mth column, and will not be described again.
  • the gate of the first transistor T1 is connected to the first gate line G1_ ⁇ n> in the nth row, and the first electrode of the first transistor T1 Connected to the sensing line Sm in the mth column;
  • the gate of the second transistor T2 is connected to the second gate line G2_ ⁇ n> in the nth row, and the first electrode of the second transistor T2 is connected to the data line Dm in the mth column ;
  • the gate of the first transistor T1 is connected to the first gate line G1_ ⁇ n+1> in the n+1th row, and the first transistor T1
  • the first electrode is connected to the sensing line Sm+1 in the m+1th column;
  • the gate of the second transistor T2 is connected to the second gate line G2_ ⁇ n+1> in the n+1th row, and the second transistor T2
  • the first electrode of the first transistor T1 is connected to the sensing line Sm in the mth column; the gate of the second transistor T2 is connected to the first gate line G1_ ⁇ n> in the nth row, and the second transistor The first pole of T2 is connected to the data line Dm of the m-th column.
  • the second electrode of the first transistor T1 is connected to the first terminal N1 of the storage capacitor C; the second electrode of the second transistor T2 is connected to the second terminal N2 of the storage capacitor C; the gate of the driving transistor T3 is connected to The second electrode N2 of the second transistor T2 is connected, the first electrode of the driving transistor T3 is connected to the anode of the light emitting device L, and the second electrode of the driving transistor T3 is connected to the first voltage terminal VDD to receive the first voltage (for example, high voltage).
  • the first terminal N1 of the storage capacitor C is also connected to the anode of the light emitting device L, and the cathode of the light emitting device L is connected to the second voltage terminal Vss to receive the second voltage (for example, low level, less than the first voltage).
  • the first transistor T1, the second transistor T2 and the driving transistor T3 are all N-type transistors.
  • the first transistor T1, the second transistor T2 and the driving transistor T3 may also be P-type transistors.
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, the high level can be 5V, 10V or other suitable voltages), and multiple high levels can be the same or different.
  • the low level represents a lower voltage range (for example, the low level may adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels may be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • FIG. 1B and FIG. 2 only schematically show 3 rows and 2 columns of pixel units for description. More pixel units may also be included. The specific settings can be set according to actual conditions. The embodiments of the present disclosure There is no restriction on this.
  • FIG. 4 shows a driving timing diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the first sub-pixel 11 in the pixel unit 10 in the nth row and mth column is a green sub-pixel
  • the second sub-pixel 12 in the pixel unit 10 in the nth row and mth column is a red sub-pixel
  • the nth row and mth column are
  • the third sub-pixel 13 in the pixel unit 10 is a blue sub-pixel as an example to illustrate the specific working process of the display panel 110 shown in FIG. 2 during the display period.
  • the driving timing diagram shown in FIG. 4 is a timing diagram of the display panel 110 in the display period, and the signal input by the sensing line Sm is a reference voltage signal, such as a low level.
  • the scan driving signals input by the first gate line G1_ ⁇ n-1> in the n-1th row and the second gate line G2_ ⁇ n> in the nth row are both high level, which controls the The first transistor T1 and the second transistor T2 of the third sub-pixel 13 in the n-1 row of the pixel unit 10 are turned on.
  • the data voltage input by the data line Dm is that of the pixel unit 10 in the n-1th row and mth column.
  • the data voltage d1 required by the third sub-pixel 13 (that is, the blue sub-pixel B) is written to the second end N2 of the storage capacitor C of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column.
  • Input data voltage d1 since the sensing signal input from the sensing line Sm in the mth column is low level, it is used to input the data voltage d1 of the storage capacitor C of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column.
  • the anode of the light-emitting device L of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column is low.
  • the pixel unit 10 in the n-1th row and mth column The light emitting device L of the third sub-pixel 13 does not emit light.
  • the second transistor T1 in the first sub-pixel 11 in the pixel unit 10 in the nth row and the mth column responds to the scan driving signal input from the second gate line G2_ ⁇ n> in the nth row.
  • the third transistor T3 in the first sub-pixel 11 in the pixel unit 10 in the nth row and mth column is If the voltage of the gate N1 is higher than the voltage of the data voltage d1, the voltage of the data voltage d1 cannot reach the voltage that causes the light emitting device L to emit light.
  • the pixel unit in the nth row and the mth column The light-emitting device L in the first sub-pixel 11 in 10 does not emit light; if the first sub-pixel 11 in the nth row and mth column pixel unit 10 does not emit light in the previous frame, that is, the nth row and mth column pixel
  • the voltage of the gate N1 of the third transistor T3 in the first sub-pixel 11 in the unit 10 is 0, or the gate of the third transistor T3 in the first sub-pixel 11 in the nth row and mth column of the pixel unit 10
  • the voltage of N1 is less than the voltage of the data voltage d1, even if the light emitting device L in the first sub-pixel 11 in the pixel unit 10 in the nth row and the mth column emits light, due to the time when the data voltage d1 is written (that is, the first time period t1) ) Is extremely short, the human eye cannot perceive the light emitted, and immediately enters
  • the scan driving signals inputted by the second gate line G2_ ⁇ n> in the nth row and the first gate line G1_ ⁇ n> in the nth row are both at a high level to control the n-1th row
  • the first transistor T1 and the second transistor T2 of the second sub-pixel 12 in the pixel unit 10 are turned on, and the first transistor T1 and the second transistor T2 of the first sub-pixel 11 in the pixel unit 10 in the nth row are turned on.
  • the data voltage input by the data line Dm is the second sub-pixel 12 (ie, the green sub-pixel G) in the pixel unit 10 in the n-1th row and the mth column and the first sub-pixel in the pixel unit 10 in the nth row and mth column 11 (ie, the data voltage d2 required by the green sub-pixel G), the data voltage d2 is written to the second end N2 of the storage capacitor C of the second sub-pixel 12 in the pixel unit 10 in the n-1th row and the mth column.
  • the first transistor T1 of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column remains unchanged.
  • the light-emitting device L of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column still does not emit light.
  • the scan driving signals input by the first gate line G1_ ⁇ n-1> in the n-1th row and the second gate line G2_ ⁇ n> in the nth row are both low, so that the The first transistor T1 and the second transistor T2 of the third sub-pixel 13 in the pixel unit 10 in the n-1 row are both turned off, and the storage capacitor C of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column is The driving transistor T3 of the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column is turned on, so that the third sub-pixel 13 in the pixel unit 10 in the n-1th row and mth column is The light emitting device L emits corresponding "gray" light according to the data voltage stored in the storage capacitor C.
  • the scan driving signals input to the first gate line G1_ ⁇ n> in the nth row and the second gate line G2_ ⁇ n+1> in the n+1th row are both high level, which controls the pixel unit 10 in the nth row
  • the first transistor T1 and the second transistor T2 of the third sub-pixel 13 are turned on.
  • the data voltage input from the data line Dm is the third sub-pixel 13 (ie, the blue sub-pixel 13) in the pixel unit 10 in the nth row and mth column.
  • the scan driving signals input by the second gate line G2_ ⁇ n> of the nth row and the first gate line G1_ ⁇ n> of the nth row are both low, so that the n-1th row
  • the first transistor T1 and the second transistor T2 of the second sub-pixel 12 in the pixel unit 10 are turned off, and the first transistor T1 and the second transistor T2 of the first sub-pixel 11 in the pixel unit 10 in the nth row are turned off.
  • the driving transistor T3 of the second sub-pixel 12 in the pixel unit 10 in row n-1 and m column is turned on.
  • the light emitting device L of the second sub-pixel 12 in the pixel unit 10 in the n-1th row and the mth column emits corresponding “gray” light according to the data voltage stored in the storage capacitor C, and in the nth row and mth Under the action of the storage capacitor C of the first sub-pixel 11 in the column of pixel unit 10, the driving transistor T3 of the first sub-pixel 11 in the pixel unit 10 in the nth row and mth column is turned on, so that the nth row and mth column are turned on.
  • the light-emitting device L of the first sub-pixel 11 in the pixel unit 10 emits corresponding “gray-scale” light according to the data voltage stored in the storage capacitor C.
  • the scan driving signals input to the second gate line G2_ ⁇ n+1> in the n+1th row and the first gate line G1_ ⁇ n+1> in the n+1th row are both high, which controls the nth row
  • the first transistor T1 and the second transistor T2 of the second sub-pixel 12 in the pixel unit 10 are turned on, and the first transistor T1 and the second transistor T2 of the first sub-pixel 11 in the pixel unit 10 in the n+1th row are turned on,
  • the data voltage input from the data line Dm is the second sub-pixel 12 (ie, the red sub-pixel R) in the pixel unit 10 in the nth row and mth column and the first in the pixel unit 10 in the n+1th row and mth column.
  • the data voltage d4 required by the sub-pixel 11 (that is, the red sub-pixel R), since the sensing signals input from the sensing line Sm in the mth column and the sensing line Sm+1 in the m+1th column are both low level, this At this time, the light-emitting devices L of the second sub-pixel 12 in the pixel unit 10 in the nth row and mth column and the first sub-pixel 11 in the pixel unit 10 in the n+1th row and mth column do not emit light.
  • FIG. 5 there is shown a timing diagram of the display panel in the display period and the blanking period of the embodiment of the present disclosure.
  • the first sub-pixel 11 in the pixel unit 10 in the n-th row and m-th column is a green sub-pixel
  • the second sub-pixel 12 in the pixel unit 10 in the n-th row and m-th column is a red sub-pixel
  • the third sub-pixel 13 in the column pixel unit 10 is a blue sub-pixel as an example to illustrate the specific working process of the display panel 110 shown in FIG. 2 during the display period and the blanking period, where the display period includes the first period t1, the second time period t2, the third time period t3, and the fourth time period t4, the blanking period includes a fifth time period t5, a sixth time period t6, a seventh time period t7, and an eighth time period t8.
  • the scan driving signals input by the second gate line G2_ ⁇ n-1> in the n-1th row and the first gate line G1_ ⁇ n-1> in the n-1th row are both high Level, control the first transistor T1 and the second transistor T2 of the first sub-pixel 11 (ie, the red sub-pixel R ⁇ n-1>) in the pixel unit 10 in the n-1th row to turn on, and the pixel unit in the n-2th row
  • the first transistor T1 and the second transistor T2 of the second sub-pixel 12 in 10 ie, the red sub-pixel R ⁇ n-2>
  • the sensing line Sm in the m-th column is directed to the m-th row in the n-1th row.
  • the first terminal N1 of the storage capacitor C of the first sub-pixel 11 in the column pixel unit 10 writes a sensing signal (for example, a reference voltage signal Vref) or reads a sensing voltage signal sense1, and is input according to the m-th column data line Dm
  • a sensing signal for example, a reference voltage signal Vref
  • Vref reference voltage signal
  • the threshold voltage of the driving transistor T3 of the first sub-pixel 11 in the first sub-pixel 11; at the same time, the sensing line Sm+1 in the (m+1)th column is directed to the storage capacitor of the second sub-pixel 12 in the pixel unit 10 in the n-2th row and mth column
  • the first terminal N1 of C writes the reference voltage signal Vref or reads the sensing voltage signal sense2, according to the data voltage input from the data line Dm
  • the sixth time period t6 calculates the threshold voltage of the driving transistor T3 of the third sub-pixel 13 (ie, the blue sub-pixel B ⁇ n-1>) in the pixel unit 10 in the n-1th row and mth column
  • the seventh time period t7 calculate the threshold voltage of the driving transistor T3 of the first sub-pixel 11 (ie, the green sub-pixel G ⁇ n>) in the pixel unit 10 in the nth row and the mth column, and the n-1th row
  • the threshold voltage of the driving transistor T3 of the second sub-pixel 12 ie, the green sub-pixel G ⁇ n-1>
  • the pixel unit in the n-th row and the m-th column is calculated
  • the threshold voltage of the driving transistor T3 of the third sub-pixel 13 in 10 ie, the blue sub-pixel B ⁇ n>).
  • the threshold voltages of the sub-pixels in one or several rows of pixel units 10 are randomly calculated, so that during the subsequent display period, According to the calculated threshold voltage, the magnitude of the data voltage that needs to be input to the data line can be accurately determined, so that the external compensation of each sub-pixel can be realized and the display effect of the display panel can be improved.
  • the timing diagram of the display period in FIG. 5 is similar to the timing diagram shown in FIG. 4, and the specific working process of the display panel in the display period has been described above, which will not be repeated here.
  • each pixel unit includes a plurality of sub-pixels; the pixel units in the same column All sub-pixels are connected to the same data line, each column of pixel units is respectively connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines.
  • each column of pixel units is connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines, so that the data
  • the number of wires and sensing wires is reduced.
  • FIG. 6 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a display device 100 including the above-mentioned display panel 110.
  • the display device 100 further includes a source driver chip 140, the source driver chip 140 is connected to the data line DL in the display panel 110 to provide a data voltage d1/d2, the source driver chip 140 and the display
  • the sensing line SL of the panel 110 is connected to provide a sensing signal (for example, a reference voltage signal Vref) or to receive a sensing voltage signal s1/s2.
  • the source driver chip 140 is first fixed on the circuit board, and then one side of the COF is bonded to the data line DL and the sensing line SL in the display panel 110, and the other side of the COF is fixed to the source driver chip. 140's circuit board bonding.
  • the display device 100 further includes a gate driving chip 120.
  • the gate driving chip 120 is connected to the gate line group (for example, including the gate line GL) in the display panel 110, and is configured to connect to the pixel unit 10 in the display panel 110.
  • the display panel 110 is disposed in the display device 100 and is electrically connected to the gate driving chip 120, the timing controller 130 and the source driving chip 140.
  • the display panel 110 includes a pixel unit 10 defined according to the intersection of a plurality of gate lines GL and a plurality of data lines DL; a gate driving chip 120 is used to drive a plurality of gate lines GL; a source driving chip 140 is used to drive a plurality of data lines DL and multiple sensing lines SL;
  • the timing controller 130 is used to process the image data RGB input from the outside of the display device 100, provide the processed image data RGB to the source driving chip 140, and to the gate driving chip 120 and the source driving
  • the chip 140 outputs a scan control signal GCS and a data control signal DCS to control the gate driving chip 120 and the source driving chip 140.
  • the plurality of gate lines are correspondingly connected to the data writing circuit in the pixel driving circuit of each sub-pixel of each row of pixel units to provide scan driving signals, and the plurality of gate lines are also correspondingly connected to each row of pixel units.
  • the sensing circuit of the sub-pixel uses the scan driving signal as the sensing control signal.
  • the pixel unit 10 is disposed in the intersection area of the gate line GL and the data line DL.
  • each pixel unit 10 is connected to 4 gate lines GL (G2_ ⁇ N> to G1_ ⁇ n+1>) (respectively providing scan driving signals), one data line DL, and two sensing lines.
  • the first voltage line or the second voltage line may be replaced with a corresponding plate-shaped common electrode (such as a common anode or a common cathode). It should be noted that only a part of the pixel unit 10, the gate line GL, and the data line DL are shown in FIG. 6.
  • the data line DL of each column is connected to the data writing sub-circuit of each sub-pixel in the pixel circuit 10 of the current column to provide a data signal.
  • the gate driving chip 120 provides a plurality of gate signals to the plurality of gate lines GL according to the plurality of scan control signals GCS from the timing controller 130. These signals are provided to each pixel unit 10 through a plurality of gate lines GL.
  • the source driving chip 140 uses the reference gamma voltage to convert the digital image data RGB input from the timing controller 130 into data signals according to a plurality of data control signals DCS from the timing controller 130.
  • the source driver chip 140 provides converted and compensated data signals to a plurality of data lines DL.
  • the timing controller 130 processes externally input image data RGB to match the size and resolution of the display panel 110, and then provides the source driver chip 140 with the processed image data.
  • the timing controller 130 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from the outside of the display device.
  • the timing controller 130 provides the generated scan control signal GCS and the data control signal DCS to the gate driving chip 120 and the source driving chip 140, respectively, for controlling the gate driving chip 120 and the source driving chip 140.
  • the source driving chip 140 may be connected to a plurality of data lines DL to provide data signals d1/d2; at the same time, it may also be connected to a plurality of first voltage lines, a plurality of second voltage lines, and a plurality of sensing lines to respectively Provide a first voltage, a second voltage, and a reference voltage signal Vref.
  • the gate driving chip 120 and the source driving chip 140 may be implemented as semiconductor chips.
  • the display device 100 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may, for example, adopt existing conventional components, which will not be described in detail here.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a navigator, and so on.
  • the display device includes a display panel, and by arranging a plurality of pixel units arranged in an array and a data line and a sensing line connected to the pixel unit in the display panel, each pixel unit includes a plurality of sub-pixels; All sub-pixels in the same column of pixel units are connected to the same data line, each column of pixel units are respectively connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines.
  • each column of pixel units By connecting all sub-pixels in the same column of pixel units to the same data line, each column of pixel units is connected to two sensing lines, and any two adjacent columns of pixel units share one of the sensing lines, so that the data The number of wires and sensing wires is reduced.
  • COF is subsequently used to connect the source driver chip with the data wires and sensing wires in the display panel, the hardware cost and bonding difficulty can be reduced, and the bonding yield can be improved.
  • the embodiment of the present disclosure also provides a method for driving the display panel, which can be used to drive the display panel 110 provided by the embodiment of the present disclosure.
  • the driving method includes a display period and a blanking period for one frame.
  • the driving method includes:
  • the gate line group sequentially provides scan driving signals to the N rows of pixel units, so that the pixel driving circuits in the N rows of pixel units drive the light-emitting devices in the N rows of pixel units to emit light; in the blanking period, the gate The line group provides a scan driving signal to the pixel unit of the i-th row among the pixel units of the N row, so that the sensing circuit in the pixel unit of the i-th row performs sensing;
  • the driving period of each row of pixel units in the N rows of pixel units includes a first time period, a second time period, a third time period, and a fourth time period.
  • the scan driving signal of the first gate line of the n-1th row and the scan driving signal of the second gate line of the nth row are both at a high level to write the data voltage into the n-1th
  • the scan driving signal of the second gate line in the nth row and the scan driving signal of the first gate line in the nth row are both at a high level, so as to write the data voltage in the n-1th row (m)
  • the scan driving signals input by the first gate line in the n-1th row and the second gate line in the nth row are both low, so that the pixel unit in the mth column in the n-1th row
  • the three sub-pixels emit light; the scan driving signal of the first gate line in the nth row and the scan driving signal of the second gate line in the n+1th row are both at a high level to write the data voltage in the nth row and mth column
  • the scan driving signals inputted by the second gate line in the nth row and the first gate line in the nth row are both low level, so that the second sub in the pixel unit of the n-1th row and the mth column
  • the pixel and the first sub-pixel in the pixel unit of the nth row and the mth column emit light;
  • the scan driving signal of the second gate line in the n+1th row and the scan driving signal of the first gate line in the n+1th row are both high Level to write the data voltage into the second sub-pixel in the pixel unit in the nth row and mth column and the first sub-pixel in the pixel unit in the n+1th row and mth column.
  • a reference voltage signal (for example, a low level) is input to the sensing line of the mth column and the sensing line of the m+1th column.
  • the driving period of each row of pixel units in the N rows of pixel units includes a fifth period, a sixth period, a seventh period, and an eighth period.
  • the seventh time period read the sensing voltage signal of the first sub-pixel in the pixel unit of the nth row and the mth column and the sensing voltage signal of the second sub-pixel in the pixel unit of the n-1th row and mth column, To compensate the first sub-pixel in the pixel unit of the nth row and mth column and the second sub-pixel in the pixel unit of the n-1th row and mth column;
  • the sensing voltage signal of the third sub-pixel in the pixel unit in the nth row and mth column is read to compensate the third sub-pixel in the pixel unit in the nth row and mth column.
  • N is a positive integer greater than 3.

Abstract

一种显示面板、显示装置及显示面板的驱动方法。该显示面板(110)包括呈阵列排布的多个像素单元(10)以及与所述像素单元(10)连接的数据线和感测线，每个像素单元(10)包括多个子像素；同一列像素单元(10)中的所有子像素与同一根数据线连接，每列像素单元(10)分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。该显示面板可以减少数据线和感测线的数量，后续在采用COF将源极驱动芯片与显示面板中的数据线和感测线连接时，可以降低硬件成本和粘合难度，提高粘合良率。

Description

显示面板及其驱动方法、显示装置
本申请要求于2019年2月21日递交的中国专利申请第201910129993.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板及其驱动方法、显示装置。
背景技术
随着显示技术的不断发展，OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板由于其具有的低能耗、生产成本低、自发光、宽视角及响应速度快等优点，得到了人们广泛的关注。
发明内容
本公开至少一实施例提供一种显示面板，包括呈阵列排布的多个像素单元以及与所述像素单元连接的数据线和感测线，每个像素单元包括多个子像素；同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。
例如，本公开至少一实施例提供的显示面板，还包括与所述子像素连接的栅线组，每行像素单元分别与两个栅线组连接以接收扫描驱动信号，且任意相邻的两行像素单元共同其中一个栅线组，所述栅线组包括第一栅线和第二栅线。
例如，在本公开至少一实施例提供的显示面板中，所述显示面板包括M×N个像素单元和N+1行栅线组，每个像素单元包括第一子像素、第二子像素和第三子像素；第n行第m列像素单元中的第一子像素分别与第n行的第一栅线、第n行的第二栅线、第m列的感测线以及第m列的数据线连接；第n行第m列像素单元中的第二子像素分别与第n+1行的第一栅线、第n+1行的第二栅线、第m+1列的感测线以及第m列的数据线连接；第n行第m 列像素单元中的第三子像素分别与第n行的第一栅线、第n+1行的第二栅线、第m列的感测线以及第m列的数据线连接；M表示列方向上的像素单元数量，N表示行方向上的像素单元数量，1≤n≤N，1≤m≤M，且M和N均为大于1的正整数。
例如，在本公开至少一实施例提供的显示面板中，每个子像素均包括发光器件和用于驱动所述发光器件进行发光的像素驱动电路和用于对所述像素驱动电路进行感测的感测电路，所述像素驱动电路包括数据写入子电路和驱动子电路；所述驱动子电路和所述数据写入子电路、所述发光器件以及所述感测电路连接，被配置为控制用于驱动所述发光器件发光的驱动电流；所述数据写入子电路被配置为接收所述扫描驱动信号，并且响应于所述扫描驱动信号将数据电压写入所述驱动子电路；所述感测电路还和所述驱动子电路连接，被配置为接收所述扫描驱动信号，并且响应于所述扫描驱动信号将参考电压信号写入所述驱动子电路或者从所述驱动子电路读出感测电压信号。
例如，在本公开至少一实施例提供的显示面板中，所述像素驱动电路还包括存储子电路，所述存储子电路和所述发光器件连接，被配置为存储写入的所述数据电压和所述参考电压信号。
例如，在本公开至少一实施例提供的显示面板中，所述感测电路包括第一晶体管，所述数据写入子电路包括第二晶体管，所述驱动子电路包括驱动晶体管，所述存储子电路包括存储电容；针对所述第n行第m列像素单元中的第一子像素，所述第一晶体管的栅极与所述第n行的第一栅线连接，所述第一晶体管的第一极与所述第m列的感测线连接；所述第二晶体管的栅极与所述第n行的第二栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；针对所述第n行第m列像素单元中的第二子像素，所述第一晶体管的栅极与所述第n+1行的第一栅线连接，所述第一晶体管的第一极与所述第m+1列的感测线连接；所述第二晶体管的栅极与所述第n+1行的第二栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；针对所述第n行第m列像素单元中的第三子像素，所述第一晶体管的栅极与所述第n+1行的第二栅线连接，所述第一晶体管的第一极与所述第m列的感测线连接；所述第二晶体管的栅极与所述第n行的第一栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；针对任意子像素，所述第一晶体管的第二极与 所述存储电容的第一端连接；所述第二晶体管的第二极与所述存储电容的第二端连接；所述驱动晶体管的栅极与所述第二晶体管的第二极连接，所述驱动晶体管的第一极与所述发光器件的阳极连接，所述驱动晶体管的第二极与第一电压端连接以接收第一电压，所述存储电容的第一端还与所述发光器件的阳极连接，所述发光器件的阴极与第二电压端连接以接收第二电压。
例如，在本公开至少一实施例提供的显示面板中，所述第一晶体管、所述第二晶体管和所述驱动晶体管均为N型晶体管，或均为P型晶体管。
例如，在本公开至少一实施例提供的显示面板中，所述第n行像素单元中的第一子像素与所述第n+1行像素单元中的第二子像素发出的光的颜色相同，且所述第n行像素单元中的第二子像素与所述第n+1行像素单元中的第一子像素发出的光的颜色相同。
例如，在本公开至少一实施例提供的显示面板中，每个像素单元中的第三子像素发出的光的颜色均相同。
例如，在本公开至少一实施例提供的显示面板中，每个像素单元中的所述第一子像素、所述第二子像素和所述第三子像素发出的光的颜色均不同。
本公开至少一实施例还提供一种显示装置，包括如权利要求1-10任一所述的显示面板。
例如，本公开至少一实施例提供的显示装置，还包括源极驱动芯片，所述源极驱动芯片与所述显示面板中的数据线连接以提供数据电压，所述源极驱动芯片与所述显示面板中的感测线连接以提供参考电压信号或接收感测电压信号。
例如，本公开至少一实施例提供的显示装置，还包括栅极驱动芯片，所述栅极驱动芯片与所述显示面板中的栅线组连接，且配置为通过所述栅线组向所述显示面板中的像素单元提供扫描驱动信号。
本公开至少一实施例还提供一种显示面板的驱动方法，包括用于一帧的显示时段和消隐时段，所述驱动方法包括：在所述显示时段，所述栅线组依次提供所述扫描驱动信号至所述N行像素单元中，使得所述N行像素单元中的像素驱动电路分别驱动所述N行像素单元中的发光器件进行发光；在所述消隐时段，所述栅线组提供所述扫描驱动信号至所述N行像素单元中的第i行像素单元，使得所述第i行像素单元中的感测电路进行感测；1≤i≤N。
例如，在本公开至少一实施例提供的驱动方法中，在所述显示时段，所述N行像素单元中的每行像素单元的驱动周期包括第一时间段、第二时间段、第三时间段和第四时间段；在所述第一时间段，所述第n-1行的第一栅线的扫描驱动信号和所述第n行的第二栅线输入的扫描驱动信号均为高电平，以将数据电压写入所述第n-1行第m列像素单元中的第三子像素；在所述第二时间段，所述第n行的第二栅线的扫描驱动信号和所述第n行的第一栅线的扫描驱动信号均为高电平，以将所述数据电压写入第n-1行第m列像素单元中的第二子像素以及第n行第m列像素单元中的第一子像素；在所述第三时间段，所述第n-1行的第一栅线和所述第n行的第二栅线输入的扫描驱动信号均为低电平，使得所述第n-1行第m列像素单元中的第三子像素发光；所述第n行的第一栅线的扫描驱动信号和所述第n+1行的第二栅线的扫描驱动信号均为高电平，以将所述数据电压写入所述第n行第m列像素单元中的第三子像素；在所述第四时间段，所述第n行的第二栅线和所述第n行的第一栅线输入的扫描驱动信号均为低电平，使得所述第n-1行第m列像素单元中的第二子像素和所述第n行第m列像素单元中的第一子像素发光；所述第n+1行的第二栅线的扫描驱动信号和所述第n+1行的第一栅线的扫描驱动信号均为高电平，以将所述数据电压写入所述第n行第m列像素单元中的第二子像素以及第n+1行第m列像素单元中的第一子像素。
例如，本公开至少一实施例提供的驱动方法，还包括：向所述第m列感测线和所述第m+1列的感测线均输入参考电压信号。
例如，在本公开至少一实施例提供的驱动方法中，在所述消隐时段，所述N行像素单元中的每行像素单元的驱动周期包括第五时间段、第六时间段、第七时间段和第八时间段；在所述第五时间段，读取第n-1行第m列像素单元中的第一子像素的感测电压信号和第n-2行第m列像素单元中的第二子像素的感测电压信号，以对所述第n-1行第m列像素单元中的第一子像素和所述第n-2行第m列像素单元中的第二子像素进行补偿；在所述第六时间段，读取所述第n-1行第m列像素单元中的第三子像素的感测电压信号，以对所述第n-1行第m列像素单元中的第三子像素进行补偿；在所述第七时间段，读取所述第n行第m列像素单元中的第一子像素的感测电压信号以及所述第n-1行第m列像素单元中的第二子像素的感测电压信号，以对所述第n行第 m列像素单元中的第一子像素和所述第n-1行第m列像素单元中的第二子像素进行补偿；在所述第八时间段，读取所述第n行第m列像素单元中的第三子像素的感测电压信号，以对所述第n行第m列像素单元中的第三子像素进行补偿；3≤n≤N，且N为大于3的正整数。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种像素电路的示意图；
图1B示出了本公开至少一实施例提供的一种显示面板的结构示意图；
图1C示出了本公开至少一实施例提供的一种子像素的结构示意图；
图2示出了本公开至少一实施例提供的一种显示面板的电路图；
图3示出了图2所示的一个像素单元的局部示意图；
图4示出了本公开至少一实施例提供的一种显示面板的驱动时序图；
图5示出了本公开至少一实施例提供的一种显示面板在显示时段和消隐时段的时序图；以及
图6示出了本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现 该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix)驱动和无源矩阵(Passive Matrix)驱动。AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个薄膜晶体管(Thin-film transistor，TFT)和一个存储电容Cst来实现驱动OLED发光的功能。
在通常的OLED显示面板中，需要通过补偿技术来提高显示质量。在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。图1A示出了一种外部补偿的像素电路的示意图。如图1A所示，该像素电路包括开关晶体管T1、驱动晶体管T3、存储电容Cst、感测晶体管T2以及有机电致发光(EL)器件(即有机发光二极管)。例如，该感测晶体管T2可以实现补偿功能。例如，该开关晶体管T1的栅极连接栅线以接收扫描驱动信号G1；例如，该开关晶体管T1的源极连接到数据线以接收数据信号Vdata；该开关晶体管T1的漏极连接到驱动晶体管T3的栅极；驱动晶体管T3的漏极连接到第一电压端以接收第一电压Vdd(高电压)，驱动晶体管T3的源极连接到EL器件的正极端；存储电容Cst的一端连接到开关晶体管T1的漏极以及驱动晶体管T3的栅极，另一端连接到驱动晶体管T3的源极；EL器件的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。例如， 当通过栅线施加扫描信号G1以开启开关晶体管T1时，数据驱动电路通过数据线输入的数据信号Vdata可以通过开关晶体管T1对存储电容Cst充电，由此可以将数据信号Vdata存储在存储电容Cst中，且该存储的数据信号Vdata可以控制驱动晶体管T3的导通程度，由此可以控制流过驱动晶体管T3以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。
如图1A所示，感测晶体管T2的第一端连接到驱动晶体管T3的源极，感测晶体管T2的第二端经由感测线SL与检测电路(例如包括电阻Rvc、电容Cvc以及例如模数转换(ADC)、放大器等器件)连接，感测晶体管T2的栅极接收补偿扫描信号G2。由此当施加补偿扫描信号G2以使得驱动晶体管T3导通之后，经由感测晶体管T2对检测电路充电，使得驱动晶体管T3的源极电位改变。当驱动晶体管T3的源极的电压Vs等于驱动晶体管T3的栅极电压Vg与驱动晶体管T3的阈值电压Vth的差值时，驱动晶体管T3截止。此时，可以在驱动晶体管T3截止后，再经由导通的感测晶体管T2从驱动晶体管T3的源极获取感测电压(也即，驱动晶体管T3截止后的源极的电压Vb)。在获取驱动晶体管T3截止后的源极的电压Vb之后，则可以获取驱动晶体管的阈值电压Vth＝Vdata-Vb，由此可以基于每个像素电路中驱动晶体管的阈值电压针对每个像素电路建立(也即，确定)补偿数据，进而可以实现显示面板各个子像素的阈值电压补偿功能。
为了追求更好的显示效果，高分辨率的OLED显示面板应运而生，如8K显示面板等，在制作得到高分辨率的OLED显示面板后，还需要采用COF(Chip On Film，覆晶薄膜)将源极驱动芯片与显示面板中的数据线和感测线连接，具体地，例如将COF的一面与显示面板中的数据线和感测线粘合，COF的另一面与固定有源极驱动芯片的电路板粘合。
但是，在高分辨率的OLED显示面板中，数据线和感测的数量大幅度增加，为了将源极驱动芯片提供的信号输入至数据线和感测线，电路板和COF上需要设计的信号传输线也需要增加，使得硬件成本增高，且在采用COF进行粘合时，粘合的难度也会增加。
本公开至少一实施例提供一种显示面板，包括呈阵列排布的多个像素单元以及与像素单元连接的数据线和感测线，每个像素单元包括多个子像素；同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与 两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。
在本公开的实施例中，通过将同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线，使得数据线和感测线的数量减少，后续在采用COF将源极驱动芯片与显示面板中的数据线和感测线连接时，可以降低硬件成本和粘合难度，提高粘合良率。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细地说明。
本公开至少一实施例提供了一种显示面板，图1B示出了本公开至少一实施例提供的一种显示面板的结构示意图。
如图1B所示，该显示面板110包括呈阵列排布的多个像素单元10以及与像素单元10连接的数据线和感测线，如图1B中所示的数据线Dm、数据线Dm+1，感测线Sm、感测线Sm+1和感测线Sm+2，每个像素单元10包括3个子像素；例如，如图1B所示，同一列像素单元10中的所有子像素与同一根数据线连接，每列像素单元10分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。例如，该感测线用于提供感测信号(例如，参考电压信号)或接收感测电压信号的传输。例如，m为大于等于1的整数。
需要注意的是，每个像素单元10还可以包括6个、9个等更多个子像素，本公开的实施例对此不作限制。
如图1B所示，从左到右分别为第m列像素单元10和第m+1列像素单元10，第m列像素单元10中的所有子像素与数据线Dm连接，第m+1列像素单元10中的所有子像素与数据线Dm+1连接，从而可以减少显示面板中数据线的数量；第m列像素单元10分别与感测线Sm和感测线Sm+1连接，第m+1列像素单元10分别与感测线Sm+1和感测线Sm+2连接，因此，可以看出，第m列像素单元10和第m+1列像素单元10共用感测线Sm+1，从而可以减少显示面板中感测线的数量。
下面以显示面板包括M×N个像素单元10，且每个像素单元10包括第一子像素11、第二子像素12和第三子像素13的情况为例，说明本公开实施例与现有的显示面板中的数据线和感测线的数量的区别。例如，M表示列方向上的像素单元数量，N表示行方向上的像素单元数量，M、N均为大于1 的正整数。
现有的显示面板的像素单元中的子像素有两种排布方式，第一种排布方式为Strip(条形)排布，即像素单元中的第一子像素、第二子像素和第三子像素并排排列，每列像素单元中的第一子像素、第二子像素和第三子像素分别连接一根数据线，且每列像素单元中的所有子像素共用一根感测线，则采用第一种排布方式的显示面板，其数据线和感测线的数量为4×M根；第二种排布方式为Square(品字形)排布，每列像素单元分别连接两根数据线，且每列像素单元中的所有子像素共用一根感测线，则采用第二种排布方式的显示面板，其数据线和感测线的数量为3×M根。
在本公开实施例中，由于同一列像素单元10中的所有子像素与同一根数据线连接，每列像素单元10分别与两根感测线连接，且任意相邻的两列像素单元10共用其中一根感测线，则本公开实施例的显示面板中的数据线和感测线的数量为2×M+1根。
由于2×M+1<3×M<4×M，因此，本公开实施例提供的显示面板可以极大地减少数据线和感测线的数量，从而在采用COF将源驱动芯片与显示面板中的数据线和感测线连接时，可以降低硬件成本和粘合难度，提高粘合良率。
例如，8K显示面板的分辨率为7680×4320，即显示面板包括7680×4320个像素单元10，现有的采用第一种排布方式的显示面板，其数据线和感测线的数量为7680×4＝30720根，现有的采用第二种排布方式的显示面板，其数据线和感测线的数量为7680×3＝23040根，而本公开实施例的显示面板中的数据线和感测线的数量为7680×2+1＝15361根，可以看出，数据线和感测线的数量大幅度减少。
因此，可以看出，本公开实施例的显示面板中的数据线和感测线的数量，小于现有的显示面板中的数据线和感测线的数量，使得显示面板中的数据线和感测线的数量减少，当后续采用COF将源极驱动芯片与显示面板中的数据线和感测线连接时，电路板和COF上需要设计的信号传输线也相应减少，从而降低了电路板和COF的硬件成本，且在采用COF进行粘合时，粘合的难度也会降低，进而提高粘合良率。
此外，当显示面板中的数据线和感测线的数量较多时，所需的源极驱动 芯片的引脚也较多，使得源极驱动芯片的成本增加，因此，本公开实施例的显示面板中的数据线和感测线的数量减少，也会使得所需的源极驱动芯片的引脚减少，从而降低源极驱动芯片的成本。
需要说明的是，每个像素单元10中的子像素的数量不仅仅如图1B所示的3个，即第一子像素11、第二子像素12和第三子像素13，每个像素单元10还可以包括多个子像素，例如，每个像素单元10还可以包括4个子像素等。
在本公开一些实施例中，显示面板110还包括与子像素连接的栅线组；每行像素单元10分别与两个栅线组连接，且任意相邻的两行像素单元10共同其中一个栅线组，栅线组包括第一栅线和第二栅线，如图1B中的第一栅线G1_<n-1>、第一栅线G1_<n>、第一栅线G1_<n+1>和第一栅线G1_<n+2>，第二栅线G2_<n-1>、第二栅线G2_<n>、第二栅线G2_<n+1>和第二栅线G2_<n+2>。例如，在该示例中，n为大于2的整数。
其中，第一栅线G1_<n-1>和第二栅线G2_<n-1>组成一个栅线组，第一栅线G1_<n>和第二栅线G2_<n>组成一个栅线组，第一栅线G1_<n+1>和第二栅线G2_<n+1>组成一个栅线组，第一栅线G1_<n+2>和第二栅线G2_<n+2>组成一个栅线组。
如图1B所示，从上到下分别为第n-1行像素单元10、第n行像素单元10和第n+1行像素单元10，第n-1行像素单元10分别与包括第一栅线G1_<n-1>和第二栅线G2_<n-1>的栅线组以及包括第一栅线G1_<n>和第二栅线G2_<n>的栅线组连接，第n行像素单元10分别与包括第一栅线G1_<n>和第二栅线G2_<n>的栅线组以及包括第一栅线G1_<n+1>和第二栅线G2_<n+1>的栅线组连接，第n+1行像素单元10分别与包括第一栅线G1_<n+1>和第二栅线G2_<n+1>的栅线组以及包括第一栅线G1_<n+2>和第二栅线G2_<n+2>的栅线组连接，因此，可以看出，第n行像素单元10与第n-1行像素单元10共用包括第一栅线G1_<n>和第二栅线G2_<n>的栅线组，第n行像素单元10与第n+1行像素单元10共用包括第一栅线G1_<n+1>和第二栅线G2_<n+1>的栅线组。
当显示面板110包括M×N个像素单元10，即显示面板110的分辨率为M×N时，本公开实施例的显示面板110中的栅线的数量为2×N+2，而对于 现有的显示面板，其栅线的数量为2×N，因此，本公开实施例的显示面板中的栅线比现有的显示面板中的栅线多两根，栅线的数量增加的很少，基本上可忽略不计，因此，本公开实施例可以在基本不增加栅线的基础上，减小数据线和感测线的数量，从而可简化显示面板的布线设计。
当然，本公开的实施例的实施例对此不作限制，也可以将显示面板中的布线方式设计为：每行像素单元10分别与两个栅线组连接，且任意相邻的两行像素单元10连接的栅线组不共用，因此，当显示面板包括M×N个像素单元10时，显示面板中的栅线的数量为4×N，若本公开实施例的显示面板采用GOA(Gate Driver on Array，阵列基板行驱动)设计，虽然栅线的数量有所增加，但是由于栅线无需与栅极驱动芯片粘合，因此，也不会影响显示面板的粘合难度。
如图1B所示，显示面板110包括M×N个像素单元10，每个像素单元10包括第一子像素11、第二子像素12和第三子像素13；第n行第m列像素单元10中的第一子像素11分别与第n行的第一栅线G1_<n>、第n行的第二栅线G2_<n>、第m列的感测线Sm以及第m列的数据线Dm连接；第n行第m列像素单元10中的第二子像素12分别与第n+1行的第一栅线G1_<n+1>、第n+1行的第二栅线G2_<n+1>、第m+1列的感测线Sm+1以及第m列的数据线Dm连接；第n行第m列像素单元10中的第三子像素13分别与第n行的第一栅线G1_<n>、第n+1行的第二栅线G2_<n+1>、第m列的感测线Sm以及第m列的数据线Dm连接；例如，M表示列方向上的像素单元数量，N表示行方向上的像素单元数量，1≤n≤N，1≤m≤M，且M和N均为大于1的正整数。此外，n和m也为正整数。
例如，在本公开的一些实施例中，第n行像素单元10中的第一子像素11与第n+1行像素单元10中的第二子像素12发出的光的颜色相同，且第n行像素单元10中的第二子像素12与第n+1行像素单元10中的第一子像素11发出的光的颜色相同；每个像素单元10中的第三子像素13发出的光的颜色均相同。
由于第n行像素单元10中的第一子像素11与第n-1行像素单元10中的第二子像素12共用包括第一栅线G1_<n>和第二栅线G2_<n>的栅线组，第n行像素单元10中的第二子像素12与第n+1行像素单元10中的第一子像素 11共用包括第一栅线G1_<n+1>和第二栅线G2_<n+1>的栅线组，在像素单元10的实际显示过程中，为了保证像素单元10中的所有子像素都能正常显示，第n行像素单元10中的第一子像素11与第n-1行像素单元10中的第二子像素需要同时显示，第n行像素单元10中的第二子像素与第n+1行像素单元10中的第一子像素需要同时显示，且由于同一列像素单元10中的所有子像素与同一根数据线连接，数据线在同一时间段内只能输入一种数据电压，因此，需要将第n行像素单元10中的第一子像素11与第n+1行像素单元10中的第二子像素12发出的光的颜色设置成相同，以及将第n行像素单元10中的第二子像素12与第n+1行像素单元10中的第一子像素11发出的光的颜色设置成相同。
对于各个像素单元10中的第三子像素13，其发出的光的颜色均相同，且在像素单元10的实际显示过程中，第三子像素13不与其他子像素同时显示。
例如，第n行像素单元10中的第一子像素11为绿色子像素，第n行像素单元10中的第二子像素12为红色子像素，第n行像素单元10中的第三子像素13为蓝色子像素，则第n+1行像素单元10中的第一子像素11为红色子像素，第n+1行像素单元10中的第二子像素12为绿色子像素，第n+1行像素单元10中的第三子像素为蓝色子像素。
此外，每个像素单元10中的第一子像素11、第二子像素12和第三子像素13发出的光的颜色均不同。
为了保证像素单元10可以发出各种不同颜色的光线，需要将像素单元10中的第一子像素11、第二子像素12和第三子像素13发出的光的颜色设置成不同，例如，第一子像素11、第二子像素12和第三子像素13发出的光的颜色分别为红色、绿色和蓝色。需要注意的是，本公开的实施例对此不作限制，各个像素单元中各个子像素的颜色的具体的设置根据上面的描述设置，在此不再赘述。
图1C示出了本公开至少一实施例提供的一种子像素的结构示意图。
在本公开的实施例中，每个子像素均包括发光器件L，用于驱动发光器件进行发光的像素驱动电路410和用于对像素驱动电路410进行感测的感测电路420。例如，在本公开的实施例中，以第n行像素单元的第一子像素11 为例进行说明，其他子像素的结构与此类似，不再赘述。
例如，如图1C所示，在一些示例中，像素驱动电路410包括数据写入子电路411、驱动子电路412；在另一些示例中，该像素驱动电路410还包括存储子电路413。
例如，在一帧的显示时段中，第一子像素11中的像素驱动电路410可以驱动发光器件L进行发光；在一帧的消隐时段中，第一子像素11中的感测电路420可以对像素驱动电路410进行感测，从而可以根据感测结果实现对该第一子像素11的外部补偿。
例如，驱动子电路412和数据写入子电路411、寄生电容(图中未示出)或存储子电路413、发光器件L以及感测电路420连接，被配置为控制用于驱动发光器件L发光的驱动电流。例如，在发光阶段，驱动子电路412可以向发光器件L提供驱动电流以驱动发光器件L进行发光，且可以根据需要的“灰度”(即，数据电压)发光。
例如，数据写入子电路411还和寄生电容(图中未示出)或存储子电路413连接，被配置为接收扫描驱动信号，并且响应于扫描驱动信号将数据电压写入驱动子电路412。例如，数据写入子电路411和栅线G2_<n>连接以接收扫描驱动信号，数据写入电路411可以响应于该扫描驱动信号而导通。例如，第n行第m列像素单元的第一子像素11中的数据写入子电路411还可以和数据线Dm连接以接收数据电压，并且在该数据写入子电路411导通时将该数据电压写入驱动子电路412。例如，在不同的阶段，数据写入子电路411接收到的数据电压可以是用于该第一子像素11发光的、经过补偿的数据电压，也可以是用于其它子像素发光的数据电压，本公开的实施例对此不作限制。
例如，感测电路420还和寄生电容(图中未示出)或存储子电路413以及发光器件L连接，被配置为接收扫描驱动信号，并且响应于扫描驱动信号将参考电压信号(例如，低电平)写入驱动子电路412或者从驱动子电路412读出感测电压信号。例如，以第n行像素单元的第一子像素11为例进行说明，感测电路420和栅线G1_<n>连接以接收扫描驱动信号，感测电路420可以响应于该扫描驱动信号而导通。例如，第n行第m列像素单元的第一子像素11中的感测电路420还可以和感测线Sm连接，例如，在该感测电路420导通时，感测电路420可以将通过感测线Sm接收到的参考电压信号写入驱动 子电路412，或者感测电路420也可以将从驱动子电路412读出的感测电压信号通过感测线Sm输出。
例如，如图1C所示，本公开的实施例提供的显示面板110还可以包括采样保持电路S/H、模数转换电路ADC、第一开关K1以及第二开关K2。例如，当需要通过感测线Sm写入参考电压信号时，使得第一开关K1闭合，第二开关K2断开。又例如，当需要通过感测线Sm读出感测电压信号时，使得第一开关K1断开，第二开关K2闭合。
例如，采样保持电路S/H被配置为对感测电压信号进行采样与保持。模数转换电路ADC和采样保持电路S/H连接，且被配置为将采样与保持后的感测电压信号进行模数转换(模拟信号转换为数字信号)，以便于后续的进一步数据处理。例如，通过对该感测电压信号进行处理可以获得驱动子电路412中关于阈值电压Vth和电流系数K的补偿信息。例如，可以在某一帧的消隐时段中，通过感测电路420获得感测电压信号，并对该感测电压信号做进一步的数据处理获得关于阈值电压Vth和电流系数K的补偿信息；然后，在下一帧中的显示时段中，根据上述获得的补偿信息再对发光器件L进行驱动，从而完成第n行像素单元的第一子像素11的外部补偿。具体补偿方法可参考本领域的方法，在此不再赘述。
例如，如图1C所示，存储子电路413还和发光器件L连接，被配置为存储写入的数据电压和参考电压信号。例如，当通过数据写入子电路411将数据电压写入驱动子电路412时，该存储子电路413可以同时存储该数据电压。又例如，当通过感测电路420将参考电压信号写入驱动子电路412时，该存储子电路413可以同时存储该参考电压信号。
图2示出了本公开至少一实施例提供的一种显示面板的电路图，图3示出了图2中的一个像素单元的局部示意图。如图2B和图3所示，在本公开的一些实施例提供的显示面板110中，各个像素单元10可以实现为图3中所示的电路结构。
例如，感测电路420可以实现为第一晶体管T1、数据写入子电路411可以实现为第二晶体管T2、驱动子电路412可以实现为驱动晶体管T3，存储子电路413可以实现为存储电容C。下面以第n行第m列像素单元10中的第一子像素11为例，对子像素中的晶体管进行详细描述。其余各个子像素的 结构与第n行第m列像素单元10中的第一子像素11的结构类似，不再赘述。
例如，针对第n行第m列像素单元10中的第一子像素11，第一晶体管T1的栅极与第n行的第一栅线G1_<n>连接，第一晶体管T1的第一极与第m列的感测线Sm连接；第二晶体管T2的栅极与第n行的第二栅线G2_<n>连接，第二晶体管T2的第一极与第m列的数据线Dm连接；针对第n行第m列像素单元10中的第二子像素12，第一晶体管T1的栅极与第n+1行的第一栅线G1_<n+1>连接，第一晶体管T1的第一极与第m+1列的感测线Sm+1连接；第二晶体管T2的栅极与第n+1行的第二栅线G2_<n+1>连接，第二晶体管T2的第一极与第m列的数据线Dm连接；针对第n行第m列像素单元10中的第三子像素13，第一晶体管T1的栅极与第n+1行的第二栅线G2_<n+1>连接，第一晶体管T1的第一极与第m列的感测线Sm连接；第二晶体管T2的栅极与第n行的第一栅线G1_<n>连接，第二晶体管T2的第一极与第m列的数据线Dm连接。
针对任意子像素，第一晶体管T1的第二极与存储电容C的第一端N1连接；第二晶体管T2的第二极与存储电容C的第二端N2连接；驱动晶体管T3的栅极与第二晶体管T2的第二极N2连接，驱动晶体管T3的第一极与发光器件L的阳极连接，驱动晶体管T3的第二极与第一电压端VDD连接以接收第一电压(例如，高电平)，存储电容C的第一端N1还与发光器件L的阳极连接，发光器件L的阴极与第二电压端Vss连接以接收第二电压(例如，低电平，小于第一电压)。
例如，第一晶体管T1、第二晶体管T2和驱动晶体管T3均为N型晶体管。当然，第一晶体管T1、第二晶体管T2和驱动晶体管T3还可以是P型晶体管。
需要说明的是，在本公开的一些实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或 其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
需要注意的是，图1B和图2中仅示意性地示出了3行2列像素单元进行描述，还可以包括更多的像素单元，具体设置可根据实际情况进行设置，本公开的实施例对此不作限制。
图4示出了本公开至少一实施例提供的一种显示面板的驱动时序图。
下面以第n行第m列像素单元10中的第一子像素11为绿色子像素，第n行第m列像素单元10中的第二子像素12为红色子像素，第n行第m列像素单元10中的第三子像素13为蓝色子像素为例，说明图2所示的显示面板110在显示时段内的具体工作过程。
其中，图4所示的驱动时序图为显示面板110在显示时段的时序图，感测线Sm输入的信号为参考电压信号，例如低电平。
在第一时间段t1内，第n-1行的第一栅线G1_<n-1>和第n行的第二栅线G2_<n>输入的扫描驱动信号均为高电平，控制第n-1行像素单元10中的第三子像素13的第一晶体管T1和第二晶体管T2打开，此时，数据线Dm输入的数据电压是第n-1行第m列像素单元10中的第三子像素13(即蓝色子像素B)所需的数据电压d1，则向第n-1行第m列像素单元10中的第三子像素13的存储电容C的第二端N2写入数据电压d1，由于第m列感测线Sm输入的感测信号为低电平，用于对第n-1行第m列像素单元10中的第三子像素13的存储电容C的第一端N1进行复位，则第n-1行第m列像素单元10中的第三子像素13的发光器件L的阳极为低电平，此时，第n-1行第m列像素单元10中的第三子像素13的发光器件L不发光。
在该第一时间段t1，第n行第m列像素单元10中的第一子像素11中的第二晶体管T1响应于第n行的第二栅线G2_<n>输入的扫描驱动信号而导通，并将该数据电压d1写入存储电容C，即发光器件L的阳极N1的电压为数据电压d1的电压。例如，如果该第n行第m列像素单元10中的第一子像素11在上一帧中发光，第n行第m列像素单元10中的第一子像素11中的第三晶体管T3的栅极N1的电压若高于该数据电压d1的电压，该数据电压d1的电压达不到使得发光器件L发光的电压，因此，在该第一时间段t1，第n行第m列像素单元10中的第一子像素11中的发光器件L不发光；若该第n行第m列像素单元10中的第一子像素11在上一帧中不发光，即第n行第m列像素单元10中的第一子像素11中的第三晶体管T3的栅极N1的电压为0，或第n行第m列像素单元10中的第一子像素11中的第三晶体管T3的栅极N1的电压小于该数据电压d1的电压，即使第n行第m列像素单元10中的第一子像素11中的发光器件L发光，由于数据电压d1写入的时间(即第一时间段t1)极短，人眼不能察觉其发出的光，而且，马上进入第二时间段t2，如下面所述，在第二时间段t2写入的是控制该第n行第m列像素单元10中的第一子像素11的数据电压d2，从而将存储电容C中存储的数据电压更新为其需要的数据电压，因此不会对显示面板的显示造成影响。其他各个像素单元中的第一子像素11的情况与此类似，不再赘述。
在第二时间段t2内，第n行的第二栅线G2_<n>和第n行的第一栅线G1_<n>输入的扫描驱动信号均为高电平，控制第n-1行像素单元10中的第二子像素12的第一晶体管T1和第二晶体管T2打开，以及第n行像素单元10中的第一子像素11的第一晶体管T1和第二晶体管T2打开，此时，数据线Dm输入的数据电压是第n-1行第m列像素单元10中的第二子像素12(即绿色子像素G)以及第n行第m列像素单元10中的第一子像素11(即绿色子像素G)所需的数据电压d2，则分别向第n-1行第m列像素单元10中的第二子像素12的存储电容C的第二端N2写入数据电压d2，以及向第n行第m列像素单元10中的第一子像素11的存储电容C的第二端N2写入数据电压d2，且由于第m列感测线Sm和第m+1列的感测线Sm+1输入的感测信号均为低电平，此时，第n-1行第m列像素单元10中的第二子像素12以及第n行第m列像素单元10中的第一子像素11的发光器件L均不发光。
同时，由于第n行的第二栅线G2_<n>输入的扫描驱动信号为高电平，使得第n-1行第m列像素单元10中的第三子像素13的第一晶体管T1依旧处于打开状态，则第n-1行第m列像素单元10中的第三子像素13的发光器件L依旧不发光。
在第三时间段t3内，第n-1行的第一栅线G1_<n-1>和第n行的第二栅线G2_<n>输入的扫描驱动信号均为低电平，使得第n-1行像素单元10中的第三子像素13的第一晶体管T1和第二晶体管T2均关闭，在第n-1行第m列像素单元10中的第三子像素13的存储电容C的作用下，使得第n-1行第m列像素单元10中的第三子像素13的驱动晶体管T3打开，从而使得第n-1行第m列像素单元10中的第三子像素13的发光器件L根据存储电容C存储的数据电压发处相应“灰度”的光。
同时，第n行的第一栅线G1_<n>和第n+1行的第二栅线G2_<n+1>输入的扫描驱动信号均为高电平，控制第n行像素单元10中的第三子像素13的第一晶体管T1和第二晶体管T2打开，此时，数据线Dm输入的数据电压是第n行第m列像素单元10中的第三子像素13(即蓝色子像素B)所需的数据电压d3，由于第m列感测线Sm输入的感测信号为低电平，使得第n行第m列像素单元10中的第三子像素13的发光器件L不发光。
在第四时间段t4内，第n行的第二栅线G2_<n>和第n行的第一栅线G1_<n>输入的扫描驱动信号均为低电平，使得第n-1行像素单元10中的第二子像素12的第一晶体管T1和第二晶体管T2关闭，以及第n行像素单元10中的第一子像素11的第一晶体管T1和第二晶体管T2关闭，在第n-1行第m列像素单元10中的第二子像素12的存储电容C的作用下，使得第n-1行第m列像素单元10中的第二子像素12的驱动晶体管T3打开，从而使得第n-1行第m列像素单元10中的第二子像素12的发光器件L根据存储电容C中存储的数据电压发处相应“灰度”的光，以及在第n行第m列像素单元10中的第一子像素11的存储电容C的作用下，使得第n行第m列像素单元10中的第一子像素11的驱动晶体管T3打开，从而使得第n行第m列像素单元10中的第一子像素11的发光器件L根据存储电容C中存储的数据电压发处相应“灰度”的光。
同时，第n+1行的第二栅线G2_<n+1>和第n+1行的第一栅线G1_<n+1> 输入的扫描驱动信号均为高电平，控制第n行像素单元10中的第二子像素12的第一晶体管T1和第二晶体管T2打开，以及第n+1行像素单元10中的第一子像素11的第一晶体管T1和第二晶体管T2打开，此时，数据线Dm输入的数据电压是第n行第m列像素单元10中的第二子像素12(即红色子像素R)以及第n+1行第m列像素单元10中的第一子像素11(即红色子像素R)所需的数据电压d4，由于第m列感测线Sm和第m+1列的感测线Sm+1输入的感测信号均为低电平，此时，第n行第m列像素单元10中的第二子像素12和第n+1行第m列像素单元10中的第一子像素11的发光器件L均不发光。
需要说明的是，以上描述仅仅示出了第m列中的几个像素单元10的具体驱动方法，可以理解的是，对于显示面板中的其他像素单元10，对应参照上述的驱动方法即可。
参照图5，示出了本公开实施例的显示面板在显示时段和消隐时段的时序图。
下面还是以第n行第m列像素单元10中的第一子像素11为绿色子像素，第n行第m列像素单元10中的第二子像素12为红色子像素，第n行第m列像素单元10中的第三子像素13为蓝色子像素为例，说明图2所示的显示面板110在显示时段和消隐时段内的具体工作过程，其中，显示时段包括第一时间段t1、第二时间段t2、第三时间段t3和第四时间段t4，消隐时段包括第五时间段t5、第六时间段t6、第七时间段t7和第八时间段t8。
在第五时间段t5内，第n-1行的第二栅线G2_<n-1>和第n-1行的第一栅线G1_<n-1>输入的扫描驱动信号均为高电平，控制第n-1行像素单元10中的第一子像素11(即红色子像素R<n-1>)的第一晶体管T1和第二晶体管T2打开，以及第n-2行像素单元10中的第二子像素12(即红色子像素R<n-2>)的第一晶体管T1和第二晶体管T2打开，此时，第m列感测线Sm向第n-1行第m列像素单元10中的第一子像素11的存储电容C的第一端N1写入感测信号(例如，参考电压信号Vref)或读取感测电压信号sense1，根据第m列数据线Dm输入的数据电压以及第n-1行第m列像素单元10中的第一子像素11的发光器件L的发光亮度(例如，感测电压信号)，计算第n-1行第m列像素单元10中的第一子像素11的驱动晶体管T3的阈值电压；同时， 第m+1列感测线Sm+1向第n-2行第m列像素单元10中的第二子像素12的存储电容C的第一端N1写入参考电压信号Vref或读取感测电压信号sense2，根据第m列数据线Dm输入的数据电压以及第n-2行第m列像素单元10中的第二子像素12的发光器件L的发光亮度(感测电压信号)，计算第n-2行第m列像素单元10中的第二子像素12的驱动晶体管T3的阈值电压。
相应的，在第六时间段t6内，计算第n-1行第m列像素单元10中的第三子像素13(即蓝色子像素B<n-1>)的驱动晶体管T3的阈值电压；在第七时间段t7内，计算第n行第m列像素单元10中的第一子像素11(即绿色子像素G<n>)的驱动晶体管T3的阈值电压，以及第n-1行第m列像素单元10中的第二子像素12(即绿色子像素G<n-1>)的驱动晶体管T3的阈值电压；在第八时间段t8内，计算第n行第m列像素单元10中的第三子像素13(即蓝色子像素B<n>)的驱动晶体管T3的阈值电压。
在实际工作过程中，由于消隐时段的时长较短，因此，在每次的消隐时段内，随机计算一行或几行像素单元10中的子像素的阈值电压，以便后续在显示时段内，能够根据计算得到的阈值电压，精确确定数据线需要输入的数据电压的大小，从而可以实现各个子像素的外部补偿，提高显示面板的显示效果。
图5中的显示时段的时序图与图4所示的时序图类似，上面已经描述了显示时段内显示面板的具体工作过程，在此不再赘述。
在本公开实施例中，通过在显示面板中设置呈阵列排布的多个像素单元以及与像素单元连接的数据线和感测线，每个像素单元包括多个子像素；同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。通过将同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线，使得数据线和感测线的数量减少，后续在采用COF将源极驱动芯片与显示面板中的数据线和感测线连接时，可以降低硬件成本和粘合难度，提高粘合良率。
图6示出了本公开至少一实施例提供的一种显示装置的示意图。本公开实施例提供了一种显示装置100，包括上述的显示面板110。
例如，如图6所示，该显示装置100还包括源极驱动芯片140，源极驱 动芯片140与显示面板110中的数据线DL连接以提供数据电压d1/d2，源极驱动芯片140与显示面板110的感测线SL连接以提供感测信号(例如，参考电压信号Vref)或接收感测电压信号s1/s2。
具体地，是先将源极驱动芯片140固定在电路板上，再将COF的一面与显示面板110中的数据线DL和感测线SL粘合，COF的另一面与固定有源极驱动芯片140的电路板粘合。
例如，该显示装置100还包括栅极驱动芯片120，栅极驱动芯片120与显示面板110中的栅线组(例如，包括栅线GL)连接，且配置为向显示面板110中的像素单元10提供扫描驱动信号G1/G2。
如图6所示显示面板110设置在显示装置100中，并与栅极驱动芯片120、定时控制器130和源极驱动芯片140电连接。该显示面板110包括根据多条栅线GL和多条数据线DL交叉限定的像素单元10；栅极驱动芯片120用于驱动多条栅线GL；源极驱动芯片140用于驱动多条数据线DL和多条感测线SL；定时控制器130用于处理从显示装置100外部输入的图像数据RGB、向源极驱动芯片140提供处理的图像数据RGB以及向栅极驱动芯片120和源极驱动芯片140输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动芯片120和源极驱动芯片140进行控制。
例如，该多条栅线对应连接到每行像素单元的各个子像素的像素驱动电路中的数据写入电路以提供扫描驱动信号，并且该多条栅线还对应连接到每行像素单元的各个子像素的感测电路以将扫描驱动信号作为感测控制信号。
例如，像素单元10设置在栅线GL和数据线DL的交叉区域。例如，如图6所示，每个像素单元10连接到4条栅线GL(G2_<N>至G1_<n+1>)(分别提供扫描驱动信号)、一条数据线DL、2条感测线SL、用于提供第二电压Vss的第二电压线以及用于提供第一电压VDD的第一电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图6中仅示出了部分的像素单元10、栅线GL、数据线DL。
例如，每一列的数据线DL和本列像素电路10中的各个子像素的数据写入子电路连接以提供数据信号。
例如，栅极驱动芯片120根据源自定时控制器130的多个扫描控制信号 GCS向多个栅线GL提供多个选通信号。这些信号通过多个栅线GL提供给每个像素单元10。
例如，源极驱动芯片140使用参考伽玛电压根据源自定时控制器130的多个数据控制信号DCS将从定时控制器130输入的数字图像数据RGB转换成数据信号。源极驱动芯片140向多条数据线DL提供转换以及补偿后的数据信号。
例如，定时控制器130对外部输入的图像数据RGB进行处理以匹配显示面板110的大小和分辨率，然后向源极驱动芯片140提供处理的图像数据。定时控制器130使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器130分别向栅极驱动芯片120和源极驱动芯片140提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动芯片120和源极驱动芯片140的控制。
例如，源极驱动芯片140可以与多条数据线DL连接，以提供数据信号d1/d2；同时还可以与多条第一电压线、多条第二电压线和多条感测线连接以分别提供第一电压、第二电压和参考电压信号Vref。
例如，栅极驱动芯片120和源极驱动芯片140可以实现为半导体芯片。该显示装置100还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
关于显示面板的具体描述可以参照上述实施例中的的描述，本公开实施例对此不再赘述。
在实际应用中，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
在本公开实施例中，显示装置包括显示面板，通过在显示面板中设置呈阵列排布的多个像素单元以及与像素单元连接的数据线和感测线，每个像素单元包括多个子像素；同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。通过将同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线，使得数据线和感测线的数量减少，后续在采用COF将源极驱动 芯片与显示面板中的数据线和感测线连接时，可以降低硬件成本和粘合难度，提高粘合良率。
本公开的实施例还提供一种显示面板的驱动方法，可以用于驱动本公开的实施例提供的显示面板110。例如，在图1B所示的示例中，该驱动方法包括用于一帧的显示时段和消隐时段。该驱动方法包括：
在所述显示时段，栅线组依次提供扫描驱动信号至N行像素单元中，使得N行像素单元中的像素驱动电路分别驱动N行像素单元中的发光器件进行发光；在消隐时段，栅线组提供扫描驱动信号至N行像素单元中的第i行像素单元，使得第i行像素单元中的感测电路进行感测；
例如，1≤i≤N。
例如，在一些实例中，在显示时段，N行像素单元中的每行像素单元的驱动周期包括第一时间段、第二时间段、第三时间段和第四时间段。
在第一时间段，第n-1行的第一栅线的扫描驱动信号和第n行的第二栅线输入的扫描驱动信号均为高电平，以将数据电压写入第n-1行第m列像素单元中的第三子像素；
在第二时间段，第n行的第二栅线的扫描驱动信号和第n行的第一栅线的扫描驱动信号均为高电平，以将数据电压写入第n-1行第m列像素单元中的第二子像素以及第n行第m列像素单元中的第一子像素；
在第三时间段，第n-1行的第一栅线和第n行的第二栅线输入的扫描驱动信号均为低电平，使得第n-1行第m列像素单元中的第三子像素发光；第n行的第一栅线的扫描驱动信号和第n+1行的第二栅线的扫描驱动信号均为高电平，以将数据电压写入第n行第m列像素单元中的第三子像素；
在第四时间段，第n行的第二栅线和第n行的第一栅线输入的扫描驱动信号均为低电平，使得第n-1行第m列像素单元中的第二子像素和第n行第m列像素单元中的第一子像素发光；第n+1行的第二栅线的扫描驱动信号和第n+1行的第一栅线的扫描驱动信号均为高电平，以将数据电压写入第n行第m列像素单元中的第二子像素以及第n+1行第m列像素单元中的第一子像素。
例如，在上述第一时间段至第四时间段中，向第m列感测线和第m+1列的感测线输入参考电压信号(例如，低电平)。
例如，在消隐时段，N行像素单元中的每行像素单元的驱动周期包括第五时间段、第六时间段、第七时间段和第八时间段。
在第五时间段，读取第n-1行第m列像素单元中的第一子像素的感测电压信号和第n-2行第m列像素单元中的第二子像素的感测电压信号，以对第n-1行第m列像素单元中的第一子像素和第n-2行第m列像素单元中的第二子像素进行补偿；
在第六时间段，读取第n-1行第m列像素单元中的第三子像素的感测电压信号，以对第n-1行第m列像素单元中的第三子像素进行补偿；
在第七时间段，读取第n行第m列像素单元中的第一子像素的感测电压信号以及第n-1行第m列像素单元中的第二子像素的感测电压信号，以对第n行第m列像素单元中的第一子像素和第n-1行第m列像素单元中的第二子像素进行补偿；
在第八时间段，读取第n行第m列像素单元中的第三子像素的感测电压信号，以对第n行第m列像素单元中的第三子像素进行补偿。
例如，在该示例中，3≤n≤N，且N为大于3的正整数。
需要说明的是，上述各个阶段的具体实现过程可参考图4和图5的相关描述，在此不再赘述。
关于显示面板的驱动方法的技术效果可以参考本公开的实施例中提供的显示面板的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (17)

  1. 一种显示面板，包括呈阵列排布的多个像素单元以及与所述像素单元连接的数据线和感测线，每个像素单元包括多个子像素；
    其中，同一列像素单元中的所有子像素与同一根数据线连接，每列像素单元分别与两根感测线连接，且任意相邻的两列像素单元共用其中一根感测线。
  2. 根据权利要求1所述的显示面板，还包括与所述子像素连接的栅线组，
    其中，每行像素单元分别与两个栅线组连接以接收扫描驱动信号，且任意相邻的两行像素单元共同其中一个栅线组，所述栅线组包括第一栅线和第二栅线。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板包括M×N个像素单元和N+1行栅线组，每个像素单元包括第一子像素、第二子像素和第三子像素；
    第n行第m列像素单元中的第一子像素分别与第n行的第一栅线、第n行的第二栅线、第m列的感测线以及第m列的数据线连接；
    第n行第m列像素单元中的第二子像素分别与第n+1行的第一栅线、第n+1行的第二栅线、第m+1列的感测线以及第m列的数据线连接；
    第n行第m列像素单元中的第三子像素分别与第n行的第一栅线、第n+1行的第二栅线、第m列的感测线以及第m列的数据线连接；
    其中，M表示列方向上的像素单元数量，N表示行方向上的像素单元数量，1≤n≤N，1≤m≤M，且M和N均为大于1的正整数。
  4. 根据权利要求3所述的显示面板，其中，每个子像素均包括发光器件和用于驱动所述发光器件进行发光的像素驱动电路和用于对所述像素驱动电路进行感测的感测电路，
    其中，所述像素驱动电路包括数据写入子电路和驱动子电路；
    所述驱动子电路和所述数据写入子电路、所述发光器件以及所述感测电路连接，被配置为控制用于驱动所述发光器件发光的驱动电流；
    所述数据写入子电路被配置为接收所述扫描驱动信号，并且响应于所述扫描驱动信号将数据电压写入所述驱动子电路；
    所述感测电路还和所述驱动子电路连接，被配置为接收所述扫描驱动信号，并且响应于所述扫描驱动信号将参考电压信号写入所述驱动子电路或者从所述驱动子电路读出感测电压信号。
  5. 根据权利要求4所述的显示面板，其中，所述像素驱动电路还包括存储子电路，其中，所述存储子电路和所述发光器件连接，被配置为存储写入的所述数据电压和所述参考电压信号。
  6. 根据权利要求5所述的显示面板，其中，所述感测电路包括第一晶体管，所述数据写入子电路包括第二晶体管，所述驱动子电路包括驱动晶体管，所述存储子电路包括存储电容；
    其中，针对所述第n行第m列像素单元中的第一子像素，所述第一晶体管的栅极与所述第n行的第一栅线连接，所述第一晶体管的第一极与所述第m列的感测线连接；所述第二晶体管的栅极与所述第n行的第二栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；
    针对所述第n行第m列像素单元中的第二子像素，所述第一晶体管的栅极与所述第n+1行的第一栅线连接，所述第一晶体管的第一极与所述第m+1列的感测线连接；所述第二晶体管的栅极与所述第n+1行的第二栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；
    针对所述第n行第m列像素单元中的第三子像素，所述第一晶体管的栅极与所述第n+1行的第二栅线连接，所述第一晶体管的第一极与所述第m列的感测线连接；所述第二晶体管的栅极与所述第n行的第一栅线连接，所述第二晶体管的第一极与所述第m列的数据线连接；
    针对任意子像素，所述第一晶体管的第二极与所述存储电容的第一端连接；所述第二晶体管的第二极与所述存储电容的第二端连接；所述驱动晶体管的栅极与所述第二晶体管的第二极连接，所述驱动晶体管的第一极与所述发光器件的阳极连接，所述驱动晶体管的第二极与第一电压端连接以接收第一电压，所述存储电容的第一端还与所述发光器件的阳极连接，所述发光器件的阴极与第二电压端连接以接收第二电压。
  7. 根据权利要求6所述的显示面板，其中，所述第一晶体管、所述第二晶体管和所述驱动晶体管均为N型晶体管，或均为P型晶体管。
  8. 根据权利要求3-7任一所述的显示面板，其中，所述第n行像素单元 中的第一子像素与所述第n+1行像素单元中的第二子像素发出的光的颜色相同，且所述第n行像素单元中的第二子像素与所述第n+1行像素单元中的第一子像素发出的光的颜色相同。
  9. 根据权利要求3-8任一所述的显示面板，其中，每个像素单元中的第三子像素发出的光的颜色均相同。
  10. 根据权利要求3-9任一所述的显示面板，其中，每个像素单元中的所述第一子像素、所述第二子像素和所述第三子像素发出的光的颜色均不同。
  11. 一种显示装置，包括如权利要求1-10任一所述的显示面板。
  12. 根据权利要求11所述的显示装置，还包括源极驱动芯片，其中，所述源极驱动芯片与所述显示面板中的数据线连接以提供数据电压，所述源极驱动芯片与所述显示面板中的感测线连接以提供参考电压信号或接收感测电压信号。
  13. 根据权利要求11所述的显示装置，还包括栅极驱动芯片，其中，所述栅极驱动芯片与所述显示面板中的栅线组连接，且配置为通过所述栅线组向所述显示面板中的像素单元提供扫描驱动信号。
  14. 一种如权利要求3所述的显示面板的驱动方法，包括用于一帧的显示时段和消隐时段，所述驱动方法包括：
    在所述显示时段，所述栅线组依次提供所述扫描驱动信号至所述N行像素单元中，使得所述N行像素单元中的像素驱动电路分别驱动所述N行像素单元中的发光器件进行发光；
    在所述消隐时段，所述栅线组提供所述扫描驱动信号至所述N行像素单元中的第i行像素单元，使得所述第i行像素单元中的感测电路进行感测；
    其中，1≤i≤N。
  15. 根据权利要求14所述的显示面板的驱动方法，其中，在所述显示时段，所述N行像素单元中的每行像素单元的驱动周期包括第一时间段、第二时间段、第三时间段和第四时间段；其中，
    在所述第一时间段，所述第n-1行的第一栅线的扫描驱动信号和所述第n行的第二栅线输入的扫描驱动信号均为高电平，以将数据电压写入所述第n-1行第m列像素单元中的第三子像素；
    在所述第二时间段，所述第n行的第二栅线的扫描驱动信号和所述第n 行的第一栅线的扫描驱动信号均为高电平，以将所述数据电压写入第n-1行第m列像素单元中的第二子像素以及第n行第m列像素单元中的第一子像素；
    在所述第三时间段，所述第n-1行的第一栅线和所述第n行的第二栅线输入的扫描驱动信号均为低电平，使得所述第n-1行第m列像素单元中的第三子像素发光；所述第n行的第一栅线的扫描驱动信号和所述第n+1行的第二栅线的扫描驱动信号均为高电平，以将所述数据电压写入所述第n行第m列像素单元中的第三子像素；
    在所述第四时间段，所述第n行的第二栅线和所述第n行的第一栅线输入的扫描驱动信号均为低电平，使得所述第n-1行第m列像素单元中的第二子像素和所述第n行第m列像素单元中的第一子像素发光；所述第n+1行的第二栅线的扫描驱动信号和所述第n+1行的第一栅线的扫描驱动信号均为高电平，以将所述数据电压写入所述第n行第m列像素单元中的第二子像素以及第n+1行第m列像素单元中的第一子像素。
  16. 根据权利要求15所述的显示面板的驱动方法，还包括：
    向所述第m列感测线和所述第m+1列的感测线均输入参考电压信号。
  17. 根据权利要求14-16任一所述的显示面板的驱动方法，其中，在所述消隐时段，所述N行像素单元中的每行像素单元的驱动周期包括第五时间段、第六时间段、第七时间段和第八时间段；其中，
    在所述第五时间段，读取第n-1行第m列像素单元中的第一子像素的感测电压信号和第n-2行第m列像素单元中的第二子像素的感测电压信号，以对所述第n-1行第m列像素单元中的第一子像素和所述第n-2行第m列像素单元中的第二子像素进行补偿；
    在所述第六时间段，读取所述第n-1行第m列像素单元中的第三子像素的感测电压信号，以对所述第n-1行第m列像素单元中的第三子像素进行补偿；
    在所述第七时间段，读取所述第n行第m列像素单元中的第一子像素的感测电压信号以及所述第n-1行第m列像素单元中的第二子像素的感测电压信号，以对所述第n行第m列像素单元中的第一子像素和所述第n-1行第m列像素单元中的第二子像素进行补偿；
    在所述第八时间段，读取所述第n行第m列像素单元中的第三子像素的感测电压信号，以对所述第n行第m列像素单元中的第三子像素进行补偿；
    其中，3≤n≤N，且N为大于3的正整数。
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