WO2020164220A1 - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

Info

Publication number
WO2020164220A1
WO2020164220A1 PCT/CN2019/094671 CN2019094671W WO2020164220A1 WO 2020164220 A1 WO2020164220 A1 WO 2020164220A1 CN 2019094671 W CN2019094671 W CN 2019094671W WO 2020164220 A1 WO2020164220 A1 WO 2020164220A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film
film layer
amorphous silicon
electrical
Prior art date
Application number
PCT/CN2019/094671
Other languages
English (en)
French (fr)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020164220A1 publication Critical patent/WO2020164220A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to the field of liquid crystal display technology, and in particular to a thin film transistor and a manufacturing method thereof, which are used to effectively improve the utilization rate of the panel.
  • Liquid crystal display is composed of color filter substrate (Color Filter Substrate), thin film transistor array substrate (TFT array substrate) and a liquid crystal layer located between the two substrates.
  • color filter substrate Color Filter Substrate
  • TFT array substrate thin film transistor array substrate
  • liquid crystal layer located between the two substrates.
  • the panel utilization rate (UPS: Usage Per Sheet) of large-size panels is limited by the limit of the factory process, resulting in low utilization rate.
  • the film Thickness and electrical properties show an increasing trend, so the utilization rate of the panel cannot be improved, and the economic cutting rate cannot be achieved, and thus the cost cannot be effectively reduced, and the market share of the product is reduced.
  • FIG. 1 it is a schematic diagram of a film formation guarantee area and an electrical film formation guarantee area of a thin film transistor in the prior art
  • the glass size of the thin film transistor As shown in area A of Figure 1, it is the glass size of the thin film transistor. The larger the glass substrate size, the larger the glass size. As shown in area B of Figure 1, it is the film formation guarantee area of thin film transistors. The larger the size of the glass substrate, the poorer the uniformity of the film formation of the panel. The film thickness of the edge cannot be effectively guaranteed. The film formation guarantee area will be The compression is reduced, and the relevant components used in the process need to be designed in this area. As shown in area B of Figure 1, it is the area to ensure the electrical film formation of thin film transistors.
  • the panel industry compresses the size of the non-filming guarantee area by compressing the process tolerance, or even sacrificing test blocking or machine modification, thereby increasing the utilization rate of the panel.
  • the method of compressing the process tolerance and sacrificing test blocking is all There are many potential risks, the product quality cannot be effectively guaranteed, and the risk of defective rate is high; the machine modification method is effective, but the modification cost is expensive, and the available film formation guarantee area is limited.
  • a thin film transistor including:
  • a semiconductor substrate including a non-electric film-forming area and an electrical film-forming area
  • a gate electrode disposed on the semiconductor substrate
  • a gate insulating layer disposed on the gate electrode
  • a second amorphous silicon film layer disposed on the first amorphous silicon film layer
  • the thickness of the first amorphous silicon film layer corresponding to the non-electric film forming region is smaller than the thickness of the first amorphous silicon film layer corresponding to the electrical film forming region.
  • the gate insulating layer is a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer.
  • the transparent conductive film is connected to the gate electrode through the contact hole.
  • the material of the transparent conductive film is indium tin oxide or zinc aluminum oxide.
  • the present disclosure also provides a thin film transistor, including:
  • a semiconductor substrate including a non-electric film-forming area and an electrical film-forming area
  • a gate electrode disposed on the semiconductor substrate
  • a gate insulating layer disposed on the gate electrode
  • a second amorphous silicon film layer disposed on the first amorphous silicon film layer
  • a depth length of the channel portion corresponding to the non-electric film forming region is smaller than a depth length of the channel portion corresponding to the non-electric film forming region.
  • the gate insulating layer is a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer.
  • the transparent conductive film is connected to the gate electrode through the contact hole.
  • the material of the transparent conductive film is indium tin oxide or zinc aluminum oxide.
  • the present disclosure provides another method for manufacturing a thin film transistor, including:
  • a second photoresist pattern is formed on the metal film layer, the metal film layer not covered by the second photoresist pattern is etched by a first wet etching method, and then a first dry etching method is used to remove
  • the metal film layer is intended to be the second photoresist pattern of a channel part;
  • a second wet etching method is used to remove the metal film layer of the channel part, and then a second dry etching method is used to remove part of the first amorphous layer that is not covered by the remaining second photoresist pattern.
  • the etching performed in the electrical film-forming region lasts for a second etching time, and the first etching time and the second etching time are different;
  • a transparent conductive film is formed on the semiconductor substrate, and the transparent conductive film is selectively etched using a fourth photoresist pattern as a shield to form a pixel electrode by patterning, and the fourth photoresist pattern is removed.
  • the first amorphous silicon film layer corresponding to the non-electric film-forming region has a thickness smaller than that of the first amorphous silicon film layer corresponding to the electric film-forming region One thickness.
  • a depth length of the channel portion corresponding to the non-electric film forming region is smaller than a depth length of the channel portion corresponding to the non-electric film forming region.
  • the first etching time is greater than the second etching time.
  • the step of forming the gate electrode on the semiconductor substrate includes: depositing a first metal layer on a semiconductor substrate, forming a first photoresist pattern on the first metal On the layer, the first metal layer that is not covered by the first photoresist pattern is etched to form the gate electrode.
  • the step of forming the first photoresist pattern on the first metal layer includes: coating a photoresist on the first metal layer, and using a mask to align the The photoresist is exposed and developed to form the first photoresist pattern.
  • an etching rate of the second dry etching method in the non-electric film forming region is greater than an etching rate of the second dry etching method in the electrical film forming region .
  • the first dry etching method and the second dry etching method are respectively an oxygen plasma ashing etching method.
  • a film thickness of the second photoresist pattern corresponding to the non-electric film-forming region is smaller than a film thickness of the second photoresist pattern corresponding to the electrical film-forming region Film thickness.
  • the gate insulating layer is a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer.
  • the transparent conductive film is connected to the gate electrode through the contact hole.
  • the material of the transparent conductive film is indium tin oxide or zinc aluminum oxide.
  • the thin film transistor provided by the present disclosure and the manufacturing method thereof, because the electrical uniformity of the glass substrate is proportional to the width-to-length ratio (W/L) of the glass substrate, and the electrical uniformity of the glass substrate is proportional to the first amorphous silicon film layer.
  • the thickness of the thin film transistor is proportional to the thickness of the non-electric film formation area (that is, the non-film formation guarantee area of the existing glass substrate).
  • the area of the non-electric film-forming area is converted into an electrical film-forming area with sufficient electrical uniformity as a compensation means for increasing the width of the glass substrate, so that the first non-electric film-forming area corresponding to the non-electric film
  • the thickness of the crystalline silicon film layer is smaller than the thickness of the first amorphous silicon film layer corresponding to the electrical film formation region; or the non-electric film formation region can be adjusted relative to the electrical film formation region during the process
  • the thickness of the second photoresist pattern of the region is such that a depth length of the channel portion corresponding to the non-electric film-forming region after etching is smaller than that of the non-electric film-forming region.
  • a depth length of the channel portion, and the depth length of the channel portion is the length of the glass substrate of the thin film transistor, so that the depth length of the channel portion of the non-electric film-forming region is smaller than that of the electrical film-forming region
  • the depth of the channel part improves the electrical uniformity of the non-electric film-forming area to improve the electrical uniformity of the entire panel, thereby reducing the size of the non-electric film-forming area, thereby increasing the utilization rate of the glass substrate. Realize the production of large-size panels.
  • FIG. 1 is a schematic diagram of a film formation guarantee area and an electrical film formation guarantee area of a thin film transistor in the prior art
  • FIG. 2 is a schematic diagram of the structure of the disclosed thin film transistor
  • FIG. 3 is a process flow diagram of a method for manufacturing a thin film transistor according to the disclosure.
  • 4A-4F are the process flow diagrams of the manufacturing method of the disclosed thin film transistor
  • FIG. 5 is a schematic flow chart of the method for manufacturing a thin film transistor according to the disclosure.
  • the large size of the glass substrate for thin film transistors results in that the film thickness at the edge of the glass substrate cannot be effectively guaranteed.
  • the film thickness and electrical non-guaranteed area of the large plate edge of the glass substrate cannot be used, resulting in an unavailability of the glass substrate.
  • the defects that have been effectively improved are improved as follows.
  • the present disclosure provides a thin film transistor, which includes: a semiconductor substrate 101, including a non-electric film-forming region and an electrical film-forming region; a gate electrode 102, disposed on the semiconductor substrate 101; a gate insulating layer 103, disposed on the gate electrode; a first amorphous silicon film layer 10, disposed on the gate insulating layer 103; a first Two amorphous silicon film layers 105 are disposed on the first amorphous silicon film layer 104; a metal film layer 106 is disposed on the second amorphous silicon film layer 105, and the metal film layer 106 includes a The channel portion 107 extends to the bottom of the second amorphous silicon film layer 105; a passivation layer 108 is disposed on the metal film layer 106, and the passivation layer 108 includes a plurality of contact holes 109 to expose the corresponding Part of the metal film layer 106; a plurality of transparent conductive films 110 are
  • the thin film transistor includes: a semiconductor substrate 101 including a non-electric film-forming region and an electrical film-forming region; a gate electrode 102 disposed on the semiconductor substrate 101; A gate insulating layer 103 is disposed on the gate electrode; a first amorphous silicon film layer 10 is disposed on the gate insulating layer 103; a second amorphous silicon film layer 105 is disposed on the first On an amorphous silicon film layer 104; a metal film layer 106 disposed on the second amorphous silicon film layer 105, the metal film layer 106 includes a channel portion 107 extending to the second amorphous silicon film The bottom of the layer 105; a passivation layer 108 is disposed on the metal film layer 106, the passivation layer 108 includes a plurality of contact holes 109 to expose the corresponding part of the metal film layer 106; a plurality of transparent The conductive film 110 is disposed on the passivation layer 108, and each transparent conductive film 110 is electrically
  • the process flow diagram and the improved process flow diagram of the method for manufacturing a thin film transistor of the present disclosure are improved from the prior art of the Four Mask Process of the half tone light process technology. As explained below, it is a rationalization technology for the islanding process of the semiconductor layer containing the channel and the source and drain wiring process by using a photomask using halftone exposure technology.
  • the first mask is used to make the gate; the second mask is used to make the channel layer, source and drain; the third mask is used to make the passivation layer/protective layer The contact window opening; and the fourth photomask is used to make the pixel electrode, especially, the second photomask usually uses a half-tone photomask to make the channel layer and the source and drain at the same time.
  • step S01 Provide a semiconductor substrate including a non-electric film-forming region and an electrical film-forming region. Using a sputtering device or other film forming device, chromium, molybdenum, tantalum, aluminum, copper or their alloys or their laminated structure are coated on a surface of a semiconductor substrate 101 as a first metal layer.
  • the bottom 101 may be a glass substrate, and the semiconductor substrate 101 includes a non-electric film forming area (not shown) and an electrical film forming area (not shown).
  • step S02 forming a gate electrode on the semiconductor substrate.
  • a photoresist is coated on one surface of the first metal layer, and a first photoresist pattern (not shown) is selectively formed using a first photomask.
  • the step of forming the first photoresist pattern on the first metal layer includes: coating a photoresist (not shown) on the first metal layer, and applying a mask to the photoresist The resist is exposed and developed to form the first photoresist pattern.
  • the first metal layer is etched using the first photoresist pattern as a shield, and the photoresist is removed to form the gate electrode 102 shown in FIG. 2 which also serves as a scan line.
  • the film thickness of the gate electrode 102 is generally set in the range of 0.1 to 0.3 ⁇ m.
  • steps S03 to S06 forming a gate insulating layer on the gate electrode; forming a first amorphous silicon film layer on the gate insulating layer; forming a second amorphous silicon film layer on the gate insulating layer On the first amorphous silicon film layer; forming a metal film layer on the second amorphous silicon film layer.
  • a sputtering device or the like is used for coating such as chromium, molybdenum, tantalum, aluminum, copper or their alloys or their laminated structure as the metal film layer 106.
  • the thickness of the metal film layer 106 is generally about 0.3 ⁇ m.
  • the gate insulating layer 103 is a silicon nitride layer or a silicon oxide layer, or a mixture of a silicon nitride layer and a silicon oxide layer.
  • step S07 forming a second photoresist pattern on the metal film layer, etching the metal film layer not covered by the second photoresist pattern by a first wet etching method, and then using a first The second photoresist pattern of the metal film layer intended to be a channel portion is removed by dry etching. As shown in FIGS.
  • a second mask (not shown) that adjusts the transmitted exposure energy with a slit pattern, a dot pattern, etc., or a second mask that uses a semi-transmissive film to adjust the transmitted exposure energy, is formed with a A second photoresist pattern 201 of the exposed part, the fully exposed part, and the halftone exposed part, the second photoresist pattern 201 is formed on the metal film layer 106.
  • a first wet etching method is used to etch the metal film layer 106 not covered by the second photoresist pattern 201 to form source and drain wirings. .
  • a first dry etching method (such as an ashing method such as oxygen plasma) is used to remove the second photoresist pattern 106 on the metal film layer 106 that is intended to be a channel portion 107.
  • step S08 remove the metal film layer of the channel part by a second wet etching method, and then remove part of the metal film layer that is not covered by the remaining second photoresist pattern by a second dry etching method.
  • the second photoresist pattern 201 with the reduced film thickness is used as a shield, and the channel portion 107 and the parts not covered by the remaining second photoresist pattern 201 are etched again by a second wet etching method.
  • the metal film layer 106 is further removed by a second dry etching method to remove part of the first amorphous silicon film layer 104 and the second amorphous silicon film layer 104 that are not covered by the remaining second photoresist pattern 201
  • the silicon film layer 105 that is, after the metal film layer 106, the second amorphous silicon film layer 105, and the first amorphous silicon film layer 104 are etched again, the second amorphous silicon film between the source and drain wirings is removed
  • the layer 105 makes the first amorphous silicon film layer 104 in the non-electric film forming area have a suitable thickness T1, and the first amorphous silicon film layer 104 in the electrical film forming area has a thickness T2, And T1 ⁇ T2, the electrical uniformity of the edge area of the semiconductor substrate 101 (that is, the non-electric film-forming area) is improved, so that the non-electric film-forming area of the edge area of the semiconductor substrate 101 becomes the
  • the electrical film-forming area reduces the size of the
  • the electrical uniformity of the thin film transistor is proportional to the thickness of the first amorphous silicon film layer
  • the electrical uniformity of the glass substrate is proportional to the thickness of the first amorphous silicon film layer
  • the A proper thickness of the first amorphous silicon film layer 104 is left in the film region, and the etching time for the first amorphous silicon film layer 104 in the non-electric film forming region will be reduced.
  • the second dry etching The etching time for the non-electric film-forming area and the second dry etching method for the electrical film-forming area are different.
  • the etching performed by the second dry etching method in the non-electric film forming area lasts for a first etching time, and the etching performed by the second dry etching method in the electrical film forming area continues A second etching time, where the first etching time and the second etching time are different.
  • the first etching time is greater than the second etching time.
  • an etching rate of the second dry etching method in the non-electric film forming area is greater than an etching rate of the second dry etching method in the electrical film forming area, In this way, under the same etching time, the thickness of the first amorphous silicon film layer 104 in the non-electric film forming region can be made smaller than the thickness of the first amorphous silicon film layer 104 in the electrical film forming region.
  • a film thickness of the second photoresist pattern corresponding to the non-electric film-forming region is smaller than that of the second photoresist corresponding to the electrical film-forming region A film thickness of the pattern.
  • the remaining thickness (residual film amount) of the second photoresist pattern is different.
  • the depth length of the channel portion in different regions is different, and the second photoresist pattern is thicker. The area will cause the depth length of the channel part to be small, and the thin area of the second photoresist pattern will cause the depth length of the channel part to be larger, so that after etching, it corresponds to all of the non-electric film forming area.
  • a depth length of the channel portion is smaller than a depth length of the channel portion corresponding to the non-electric film-forming region, and the depth length of the channel portion is the length of the glass substrate of the thin film transistor, so that the non-electric film forming region
  • the depth length of the channel portion of the film region is smaller than the depth length of the channel portion of the electrical film formation region, which improves the electrical uniformity of the non-electric film formation region.
  • step S09 remove the remaining second photoresist pattern, and form a passivation layer 108 on the metal film layer, using a third photoresist pattern for making To reach the gate electrode 102 and the contact hole 109 of the metal film layer 106, the first amorphous silicon film layer 104 and the second amorphous silicon film layer 105 in the contact hole 109 are etched to make the The gate electrode 102 and the metal film layer 106 are partially exposed.
  • step S10 a transparent conductive film 110 is formed on the semiconductor substrate, and the transparent conductive film 110 is selectively etched using a fourth photoresist pattern as a shield to form a pixel electrode by patterning, and remove the first Four photoresist patterns.
  • the transparent conductive film is connected to the gate electrode through the contact hole.
  • the material of the transparent conductive film is indium tin oxide or zinc aluminum oxide.
  • the thickness of the first amorphous silicon film layer of the thin film transistor is adjusted to make the original
  • the area of the non-electric film-forming area is converted into an electrical film-forming area with sufficient electrical uniformity as a compensation means for increasing the width of the glass substrate, so that the second corresponding to the non-electric film-forming area
  • the thickness of an amorphous silicon film layer is smaller than the thickness of the first amorphous silicon film layer corresponding to the electrical film forming area; or by adjusting the non-electric film forming area relative to the electrical film forming area during the process
  • the thickness of the second photoresist pattern in the film formation region is such that the channel portion corresponding to the non-electric film formation region after etching has a depth smaller than that of the non-electric film formation region
  • a depth length of the channel portion, and the depth length of the channel portion is the length of the glass substrate of the thin film transistor, so that the depth length of the channel portion

Abstract

本揭示提供一种薄膜晶体管，包括：依序层迭设置的一半导体衬底、一栅电极、一闸极绝缘层、一第一非晶硅膜层、一第二非晶硅膜层、一金属膜层、一钝化层、一透明导电膜，半导体衬底，包括一非电性成膜区与一电性成膜区，对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度，使非电性成膜区可作为电性成膜区利用，提升非电性成膜区的电性均匀度，来提升整个面板的电性的均匀性，减小非电性成膜区域的大小，进而提升玻璃基板的利用率。还提供所述薄膜晶体管的制作方法。

Description

薄膜晶体管及其制作方法 技术领域
本揭示涉及液晶显示技术领域，尤其涉及一种薄膜晶体管及其制作方法，用于有效的提高面板利用率。
 背景技术
液晶显示器(Liquid Crystal Display, LCD)是由彩色滤光基板(Color Filter Substrate)、薄膜晶体管数组基板(TFT array substrate)以及位于两基板之间的液晶层所组成。近年来，由于液晶电视的需求增加，使得液晶显示器逐渐朝着大尺寸面板的方向发展。
而大尺寸面板的面板利用率（UPS：Usage Per Sheet）由于受到工厂制程的极限限制，导致利用率不高，尤其对于大尺寸面板的生产线，由于各现有制程的均匀度差，故而导致膜厚及电性呈现增长趋势，故而面板的利用率无法得到提高，进而无法实现经济切割率，进而无法有效降低成本，也就降低了产品的市场占有率。
如图1所示，为现有技术的薄膜晶体管的成膜保证区与电性成膜保证区示意图；
如图1的 A 区域所示，为薄膜晶体管的玻璃尺寸，玻璃基板尺寸越大，玻璃的尺寸越大米。如图1的 B 区域所示，为薄膜晶体管的成膜保证区，玻璃基板尺寸越大，导致面板的成膜的均匀度差，边缘的膜厚无法有效保证，所述成膜保证区域会被压缩减少，制程所使用相关组件需要设计在此区域内。如图1的 B 区域所示，为薄膜晶体管的电性成膜保证区域，玻璃基板尺寸越大，导致面板的成膜的均匀度差，边缘的膜厚无法有效保证，尤其由于半导体的特性较敏感，半导体成膜保证区域会被严重压缩，所使用相关开关设计必须要在此区域内。
目前面板产业皆通过压缩制程宽容度、甚至牺牲测试拦捡或者进行机台改造来压缩非成膜保证区域的大小，进而提高面板的利用率，压缩制程宽容度及牺牲测试拦捡的方式，都存在着很多潜在风险，产品品质无法有效的保证，且不良率风险很高；机台改造的方式行之有效，但改造费用昂贵，且可得回的成膜保证区域有限。
因此，有必要提供一种薄膜晶体管的制作方法，有效的增加电性成膜保证区域，从而增加面板的有效利用率，实现最经济切割，可以实现较大面板的制作。
 技术问题
现有的薄膜晶体管制作方法中玻璃基板尺寸越大，导致面板的成膜的均匀度差，边缘的膜厚无法有效保证，即产生玻璃基板的面板利用率低的技术问题。
 技术解决方案
为了解决上述技术问题，本揭示提供一种薄膜晶体管，包括：
一半导体衬底，包括一非电性成膜区与一电性成膜区；
一栅电极，设置于所述半导体衬底上；
一闸极绝缘层，设置于所述栅电极上；
一第一非晶硅膜层，设置于所述闸极绝缘层上；
一第二非晶硅膜层，设置于所述第一非晶硅膜层上；
一金属膜层，设置于所述第二非晶硅膜层上，所述金属膜层包括一通道部分延伸至所述第二非晶硅膜层底部；
一钝化层，设置于所述金属膜层上，所述钝化层包括多个接触孔，以暴露出对应部分的所述金属膜层；
一透明导电膜，设置于所述钝化层上，每一透明导电膜经由所述接触孔与对应的该所述金属膜层电性连接；
其中对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度。
根据本文描述的一实施例，所述闸极绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
根据本文描述的一实施例，所述透明导电膜通过所述接触孔与所述栅电极连接。
根据本文描述的一实施例，所述透明导电膜的材料为氧化铟锡或氧化锌铝。
为了解决上述技术问题，本揭示另提供一种薄膜晶体管，包括：
一半导体衬底，包括一非电性成膜区与一电性成膜区；
一栅电极，设置于所述半导体衬底上；
一闸极绝缘层，设置于所述栅电极上；
一第一非晶硅膜层，设置于所述闸极绝缘层上；
一第二非晶硅膜层，设置于所述第一非晶硅膜层上；
一金属膜层，设置于所述第二非晶硅膜层上，所述金属膜层包括一通道部分延伸至所述第二非晶硅膜层底部；
一钝化层，设置于所述金属膜层上，所述钝化层包括多个接触孔，以暴露出对应部分的所述金属膜层；
一透明导电膜，设置于所述钝化层上，所述透明导电膜经由所述接触孔与对应的该所述金属膜层电性连接；
其中对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区所述通道部分的一纵深长度。
根据本文描述的一实施例，所述闸极绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
根据本文描述的一实施例，所述透明导电膜通过所述接触孔与所述栅电极连接。
根据本文描述的一实施例，所述透明导电膜的材料为氧化铟锡或氧化锌铝。
为了解决上述技术问题，本揭示另提供一薄膜晶体管的制作方法，包括：
提供包括一非电性成膜区与一电性成膜区的一半导体衬底；
形成一栅电极于所述半导体衬底上；
形成一闸极绝缘层于所述栅电极上；
形成一第一非晶硅膜层于所述闸极绝缘层上；
形成一第二非晶硅膜层于所述第一非晶硅膜层上；
形成一金属膜层于所述第二非晶硅膜层上；
形成一第二光阻图案于所述金属膜层上，以一第一湿式蚀刻方式蚀刻未被所述第二光阻图案覆盖的所述金属膜层，再使用一第一干式蚀刻方式除去所述金属膜层预定作为一通道部分的所述第二光阻图案；
以一第二湿式蚀刻方式除去所述通道部分的所述金属膜层，再以一第二干式蚀刻方式除去部分的未被剩余的所述第二光阻图案覆盖的所述第一非晶硅膜层及所述第二非晶硅膜层，其中所述第二干式蚀刻方式于所述非电性成膜区所进行的蚀刻持续一第一蚀刻时间，所述第二干式蚀刻方式于所述电性成膜区所进行的蚀刻持续一第二蚀刻时间，所述第一蚀刻时间和所述第二蚀刻时间不相同；
移除剩余的所述第二光阻图案，并在所述金属膜层上形成一钝化层，使用一第三光阻图案制作用以到达所述栅电极及所述金属膜层之接触孔，蚀刻接触孔内的所述第一非晶硅膜层和所述第二非晶硅膜层，使所述栅电极和所述金属膜层局部露出；
在所述半导体衬底上形成一透明导电膜，使用一第四光阻图案为屏蔽选择性蚀刻所述透明导电膜，以图案化形成像素电极，并除去所述第四光阻图案。
根据本文描述的一实施例，对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度。
根据本文描述的一实施例，对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区所述通道部分的一纵深长度。
根据本文描述的一实施例，所述第一蚀刻时间大于所述第二蚀刻时间。
根据本文描述的一实施例，形成所述栅电极于所述半导体衬底上的步骤包括：在一半导体衬底上沉积一第一金属层，形成一第一光阻图案于所述第一金属层上，蚀刻未被所述第一光阻图案遮盖的所述第一金属层，以形成所述栅电极。
根据本文描述的一实施例，形成所述第一光阻图案于所述第一金属层上的步骤包括：在所述第一金属层上涂覆一光刻胶，利用一掩膜板对所述光刻胶进行曝光，显影后形成所述第一光阻图案。
根据本文描述的一实施例，所述第二干式蚀刻方式于所述非电性成膜区的一蚀刻速率大于所述第二干式蚀刻方式于所述电性成膜区的一蚀刻速率。
根据本文描述的一实施例，所述第一干式蚀刻方式及所述第二干式蚀刻方式分别为一氧气等离子体灰化蚀刻法。
根据本文描述的一实施例，对应于所述非电性成膜区的所述第二光阻图案的一膜厚度小于对应于所述电性成膜区的所述第二光阻图案的一膜厚度。
根据本文描述的一实施例，所述闸极绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
根据本文描述的一实施例，所述透明导电膜通过所述接触孔与所述栅电极连接。
根据本文描述的一实施例，所述透明导电膜的材料为氧化铟锡或氧化锌铝。
 有益效果
本揭示提供的薄膜晶体管及其制作方法，由于玻璃基板的电性均匀度与玻璃基板的宽长比(W/L)成正比，而玻璃基板的电性均匀度与第一非晶硅膜层的厚度成正比，通过提升非电性成膜区(即现有玻璃基板的非成膜保证区域)的膜厚特性，调整薄膜晶体管的第一非晶硅膜层的厚度，使原本为非电性成膜区的区域转换为具有足够电性均匀度的电性成膜区，来做为增加玻璃基板的宽度的补偿手段，使对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度；或者通过调整制程中所述非电性成膜区相对于所述电性成膜区的所述第二光阻图案的一膜厚度的方式，使蚀刻后对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区的所述通道部分的一纵深长度，而所述通道部分的纵深长度为薄膜晶体管的玻璃基板的长度，从而使得非电性成膜区的所述通道部分的纵深长度小于电性成膜区的所述通道部分的纵深长度，提升非电性成膜区的电性均匀度，来提升整个面板的电性的均匀性，进而减小非电性成膜区域的大小，进而提升玻璃基板的利用率，实现大尺寸面板的制作。
 附图说明
图1为现有技术的薄膜晶体管的成膜保证区与电性成膜保证区示意图；
图2为本揭示薄膜晶体管结构示意图；
图3为本揭示薄膜晶体管制作方法的工艺流程图；
图4A-4F为本揭示薄膜晶体管制作方法的工艺流程图；
图5为本揭示薄膜晶体管制作方法的流程示意图。
 本发明的实施方式
下面结合附图详细本揭示实施例的实现过程。
针对薄膜晶体管的玻璃基板尺寸较大，导致玻璃基板边缘的膜厚不能得到有效的保证，玻璃基板的大板边缘的膜厚及电性不保证区域不能够使用，导致了玻璃基板的利用率无法得到有效提高的缺陷进行以下改进。
如图2至图4A-4F及图5所示，本揭示提供一种薄膜晶体管，其包括：一半导体衬底101，包括一非电性成膜区与一电性成膜区；一栅电极102，设置于所述半导体衬底101上；一闸极绝缘层103，设置于所述栅电极上；一第一非晶硅膜层10，设置于所述闸极绝缘层103上；一第二非晶硅膜层105，设置于所述第一非晶硅膜层104上；一金属膜层106，设置于所述第二非晶硅膜层105上，所述金属膜层106包括一通道部分107延伸至所述第二非晶硅膜层105底部；一钝化层108，设置于所述金属膜层106上，所述钝化层108包括多个接触孔109，以暴露出对应部分的所述金属膜层106；多个一透明导电膜110，设置于所述钝化层108上，每一透明导电膜110经由所述接触孔109与对应的该所述金属膜层106电性连接；其中对应于所述非电性成膜区的所述第一非晶硅膜层104一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层104一厚度。
在不同实施例中，所述薄膜晶体管包括：一半导体衬底101，包括一非电性成膜区与一电性成膜区；一栅电极102，设置于所述半导体衬底101上；一闸极绝缘层103，设置于所述栅电极上；一第一非晶硅膜层10，设置于所述闸极绝缘层103上；一第二非晶硅膜层105，设置于所述第一非晶硅膜层104上；一金属膜层106，设置于所述第二非晶硅膜层105上，所述金属膜层106包括一通道部分107延伸至所述第二非晶硅膜层105底部；一钝化层108，设置于所述金属膜层106上，所述钝化层108包括多个接触孔109，以暴露出对应部分的所述金属膜层106；多个一透明导电膜110，设置于所述钝化层108上，每一透明导电膜110经由所述接触孔109与对应的该所述金属膜层106电性连接；其中对应于所述非电性成膜区的所述通道部分107一纵深长度小于对应于所述非电性成膜区所述通道部分107的一纵深长度。
如图2至图4A-4F所示，为本揭示薄膜晶体管制作方法的流程示意图及改进工艺流程图。本揭示的薄膜晶体管制作方法改良自半色调(half tone)光制程技术之四道光罩制程(Four Mask Process)的现有技术。如下文说明，系藉由半色调曝光技术利用一片光罩进行包含通道之半导体层之岛化制程和源极、汲极配线制程的合理化技术。四道光罩制程中，第一道光罩是用来制作闸极；第二道光罩是用来制作通道层与源极、汲极；第三道光罩是用来制作钝化层/保护层中的接触窗开口；且第四道光罩是用来制作像素电极，特别是，第二道光罩通常会采用半调式光罩，以同时制作通道层与源极、汲极。
如图2至图4A-4F及图5所示，首先，步骤S01：提供包括一非电性成膜区与一电性成膜区的一半导体衬底。使用溅镀装置等制膜装置，将铬、钼、钽、铝、铜或其合金或其层迭结构被覆于一半导体衬底101之一表面上，作为一第一金属层，所述半导体衬底101可以为一玻璃基板，并且所述半导体衬底101包括一非电性成膜区(未图示)与一电性成膜区(未图示)。接着，步骤S02：形成一栅电极于所述半导体衬底上。在第一金属层之一表面上涂布光阻，使用第一光罩选择性形成第一光阻图案(未图示)。而形成所述第一光阻图案于所述第一金属层上的步骤包括：在所述第一金属层上涂覆一光刻胶(未图示)，利用一掩膜板对所述光刻胶进行曝光，显影后形成所述第一光阻图案。
然后，将第一光阻图案作为屏蔽进行所述第一金属层的蚀刻，除去光阻，而形成图2所示的兼作为扫描线的栅电极102。栅电极102的膜厚一般设于0.1~0.3 μm之范围。
接着，步骤S03~S06：形成一闸极绝缘层于所述栅电极上；形成一第一非晶硅膜层于所述闸极绝缘层上；形成一第二非晶硅膜层于所述第一非晶硅膜层上；形成一金属膜层于所述第二非晶硅膜层上。使用电浆CVD装置或溅镀装置等制膜装置，将作为一闸极绝缘层103之第一氮化硅膜、作为晶体管之通道之几乎不含杂质之第一非晶硅膜层104(a－Si)、以及作为薄膜晶体管之源极、汲极之掺杂N型杂质之第二非晶硅膜层105(N＋a－Si)的三薄膜，分别以例如0.3－0.2－0.05 μm之膜厚沉积。再使用溅镀装置等被覆例如铬、钼、钽、铝、铜或其合金或其层迭结构，作为金属膜层106。金属膜层106的膜厚一般亦约为0.3μm。并且优选地，所述闸极绝缘层103为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
接着，步骤S07：形成一第二光阻图案于所述金属膜层上，以一第一湿式蚀刻方式蚀刻未被所述第二光阻图案覆盖的所述金属膜层，再使用一第一干式蚀刻方式除去所述金属膜层预定作为一通道部分的所述第二光阻图案。如图4A-4B所示利用以缝隙图案、点图案等调整透射之曝光能量的第二光罩(未图示)或利用以半透射膜调整透射之曝光能量的第二光罩，形成具有未曝光部分、完全曝光部分以及半色调曝光部分的一第二光阻图案201，所述第二光阻图案201形成于所述金属膜层106上。如图4C所示以第二光阻图案201为屏蔽，采用一第一湿式蚀刻方式蚀刻未被所述第二光阻图案201覆盖的所述金属膜层106而形成源极、汲极配线。之后，如图4D所示利用一第一干式蚀刻方式(如氧气电浆等灰化方式)，除去所述金属膜层106上预定作为一通道部分107的所述第二光阻图案106。
然后，步骤S08：以一第二湿式蚀刻方式除去所述通道部分的所述金属膜层，再以一第二干式蚀刻方式除去部分的未被剩余的所述第二光阻图案覆盖的所述第一非晶硅膜层及所述第二非晶硅膜层。如图4E所示将膜厚减少之所述第二光阻图案201作为屏蔽，以一第二湿式蚀刻方式再次蚀刻所述通道部分107以及未被剩余的所述第二光阻图案201覆盖的所述金属膜层106，再以一第二干式蚀刻方式除去部分的未被剩余的所述第二光阻图案201覆盖的所述第一非晶硅膜层104及所述第二非晶硅膜层105，即再次蚀刻所述金属膜层106、第二非晶硅膜层105以及第一非晶硅膜层104后，除去源极、汲极配线间之第二非晶硅膜层105，使所述非电性成膜区的第一非晶硅膜层104具有一适合的厚度T1，而所述电性成膜区的第一非晶硅膜层104具有一厚度T2，而T1<T2，使半导体衬底101边缘区域(即非所述电性成膜区)的电性均匀度提高，从而使半导体衬底101边缘区域的非所述电性成膜区成为所述电性成膜区，通过减少非电性成膜区(即现有玻璃基板的非成膜保证区域)的大小，增加所述半导体衬底101的可利用率。
由于薄膜晶体管的电性均匀度与第一非晶硅膜层的厚度成正比，而玻璃基板的电性均匀度与第一非晶硅膜层的厚度成正比，为了在所述非电性成膜区留下合适的第一非晶硅膜层104的厚度，对在所述非电性成膜区的第一非晶硅膜层104的蚀刻时间将会减少，所述第二干式蚀刻方式对于所述非电性成膜区与所述第二干式蚀刻方式对于所述电性成膜区所持续的蚀刻时间并不相同。即所述第二干式蚀刻方式于所述非电性成膜区所进行的蚀刻持续一第一蚀刻时间，所述第二干式蚀刻方式于所述电性成膜区所进行的蚀刻持续一第二蚀刻时间，所述第一蚀刻时间和所述第二蚀刻时间不相同。优选地，所述第一蚀刻时间大于所述第二蚀刻时间。
此外在不同实施例中，所述第二干式蚀刻方式于所述非电性成膜区的一蚀刻速率大于所述第二干式蚀刻方式于所述电性成膜区的一蚀刻速率，如此在相同蚀刻时间下，亦可达到使所述非电性成膜区的第一非晶硅膜层104的厚度小于所述电性成膜区的第一非晶硅膜层104的厚度。
须注意的是，在不同实施例中，对应于所述非电性成膜区的所述第二光阻图案的一膜厚度小于对应于所述电性成膜区的所述第二光阻图案的一膜厚度。利用所述第二光阻图案残留的厚度（残膜量）有差异，经过所述第一干式蚀刻方式后不同区域的所述通道部分的纵深长度不同，所述第二光阻图案厚的区域会造成所述通道部分的纵深长度较小，所述第二光阻图案薄的区域会造成所述通道部分的纵深长度较大，使蚀刻后对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区的所述通道部分的一纵深长度，而所述通道部分的纵深长度为薄膜晶体管的玻璃基板的长度，从而使得非电性成膜区的所述通道部分的纵深长度小于电性成膜区的所述通道部分的纵深长度，提升非电性成膜区的电性均匀度。
其后如图2及图5所示，步骤S09：移除剩余的所述第二光阻图案，并在所述金属膜层上形成一钝化层108，使用一第三光阻图案制作用以到达所述栅电极102及所述金属膜层106之接触孔109，蚀刻接触孔109内的所述第一非晶硅膜层104和所述第二非晶硅膜层105，使所述栅电极102和所述金属膜层106局部露出。然后，步骤S10：在所述半导体衬底上形成一透明导电膜110，使用一第四光阻图案为屏蔽选择性蚀刻所述透明导电膜110，以图案化形成像素电极，并除去所述第四光阻图案。
在优选实施例中所述透明导电膜通过所述接触孔与所述栅电极连接。并且所述透明导电膜的材料为氧化铟锡或氧化锌铝。本揭示提供的薄膜晶体管的制作方法及薄膜晶体管，由于玻璃基板的电性均匀度与玻璃基板的宽长比(W/L)成正比，而玻璃基板的电性均匀度与第一非晶硅膜层的厚度成反比，通过提升非电性成膜区(即现有玻璃基板的非成膜保证区域)的膜厚特性，调整薄膜晶体管的第一非晶硅膜层的厚度，使原本为非电性成膜区的区域转换为具有足够电性均匀度的电性成膜区，来做为增加玻璃基板的宽度的补偿手段，使对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度；或者通过调整制程中所述非电性成膜区相对于所述电性成膜区的所述第二光阻图案的一膜厚度的方式，使蚀刻后对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区的所述通道部分的一纵深长度，而所述通道部分的纵深长度为薄膜晶体管的玻璃基板的长度，从而使得非电性成膜区的所述通道部分的纵深长度小于电性成膜区的所述通道部分的纵深长度，提升非电性成膜区的电性均匀度，来提升整个面板的电性的均匀性，进而减小非电性成膜区域的大小，进而提升玻璃基板的利用率，实现大尺寸面板的制作。
以上所述是本揭示的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本揭示的保护范围。

Claims (10)

  1. 一种薄膜晶体管，其包括：
    一半导体衬底，包括一非电性成膜区与一电性成膜区；
    一栅电极，设置于所述半导体衬底上；
    一闸极绝缘层，设置于所述栅电极上；
    一第一非晶硅膜层，设置于所述闸极绝缘层上；
    一第二非晶硅膜层，设置于所述第一非晶硅膜层上；
    一金属膜层，设置于所述第二非晶硅膜层上，所述金属膜层包括一通道部分延伸至所述第二非晶硅膜层底部；
    一钝化层，设置于所述金属膜层上，所述钝化层包括多个接触孔，以暴露出对应部分的所述金属膜层；及
    一透明导电膜，设置于所述钝化层上，所述透明导电膜经由所述接触孔与对应的该所述金属膜层电性连接；
    其中对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度。
  2. 根据权利要求1所述的薄膜晶体管，其中所述闸极绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
  3. 根据权利要求1所述的薄膜晶体管，其中所述透明导电膜通过所述接触孔与所述栅电极连接。
  4. 根据权利要求1所述的薄膜晶体管，其中所述透明导电膜的材料为氧化铟锡或氧化锌铝。
  5. 一种薄膜晶体管，其包括：
    一半导体衬底，包括一非电性成膜区与一电性成膜区；
    一栅电极，设置于所述半导体衬底上；
    一闸极绝缘层，设置于所述栅电极上；
    一第一非晶硅膜层，设置于所述闸极绝缘层上；
    一第二非晶硅膜层，设置于所述第一非晶硅膜层上；
    一金属膜层，设置于所述第二非晶硅膜层上，所述金属膜层包括一通道部分延伸至所述第二非晶硅膜层底部；
    一钝化层，设置于所述金属膜层上，所述钝化层包括多个接触孔，以暴露出对应部分的所述金属膜层；及
    一透明导电膜，设置于所述钝化层上，所述透明导电膜经由所述接触孔与对应的该所述金属膜层电性连接；
    其中对应于所述非电性成膜区的所述通道部分一纵深长度小于对应于所述非电性成膜区所述通道部分的一纵深长度。
  6. 根据权利要求5所述的薄膜晶体管，其中所述闸极绝缘层为氮化硅层或者氧化硅层，或者氮化硅层和氧化硅层的混合。
  7. 根据权利要求5所述的薄膜晶体管，其中所述透明导电膜通过所述接触孔与所述栅电极连接。
  8. 根据权利要求5所述的薄膜晶体管，其中所述透明导电膜的材料为氧化铟锡或氧化锌铝。
  9. 一种薄膜晶体管的制作方法，其包括步骤：
    提供包括一非电性成膜区与一电性成膜区的一半导体衬底；
    形成一栅电极于所述半导体衬底上；
    形成一闸极绝缘层于所述栅电极上；
    形成一第一非晶硅膜层于所述闸极绝缘层上；
    形成一第二非晶硅膜层于所述第一非晶硅膜层上；
    形成一金属膜层于所述第二非晶硅膜层上；
    形成一第二光阻图案于所述金属膜层上，以一第一湿式蚀刻方式蚀刻未被所述第二光阻图案覆盖的所述金属膜层，再使用一第一干式蚀刻方式除去所述金属膜层预定作为一通道部分的所述第二光阻图案；
    以一第二湿式蚀刻方式除去所述信道部分的所述金属膜层，再以一第二干式蚀刻方式除去部分的未被剩余的所述第二光阻图案覆盖的所述第一非晶硅膜层及所述第二非晶硅膜层，其中所述第二干式蚀刻方式于所述非电性成膜区所进行的蚀刻持续一第一蚀刻时间，所述第二干式蚀刻方式于所述电性成膜区所进行的蚀刻持续一第二蚀刻时间，所述第一蚀刻时间和所述第二蚀刻时间不相同；
    移除剩余的所述第二光阻图案，并在所述金属膜层上形成一钝化层，使用一第三光阻图案制作用以到达所述栅电极及所述金属膜层之接触孔，蚀刻接触孔内的所述第一非晶硅膜层和所述第二非晶硅膜层，使所述栅电极和所述金属膜层局部露出；及
    在所述半导体衬底上形成一透明导电膜，使用一第四光阻图案为屏蔽选择性蚀刻所述透明导电膜，以图案化形成像素电极，并除去所述第四光阻图案；
    其中对应于所述非电性成膜区的所述第一非晶硅膜层一厚度小于对应于所述电性成膜区的所述第一非晶硅膜层一厚度。
  10. 根据权利要求9所述的薄膜晶体管的制作方法，其中对应于所述非电性成膜区的所述第二光阻图案的一膜厚度小于对应于所述电性成膜区的所述第二光阻图案的一膜厚度。
PCT/CN2019/094671 2019-02-13 2019-07-04 薄膜晶体管及其制作方法 WO2020164220A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910117376.3A CN109920855B (zh) 2019-02-13 2019-02-13 薄膜晶体管及其制作方法
CN201910117376.3 2019-02-13

Publications (1)

Publication Number Publication Date
WO2020164220A1 true WO2020164220A1 (zh) 2020-08-20

Family

ID=66961667

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/094671 WO2020164220A1 (zh) 2019-02-13 2019-07-04 薄膜晶体管及其制作方法

Country Status (2)

Country Link
CN (1) CN109920855B (zh)
WO (1) WO2020164220A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814455A (zh) * 2009-02-19 2010-08-25 乐金显示有限公司 制造阵列基板的方法
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板
CN107275334A (zh) * 2016-04-08 2017-10-20 群创光电股份有限公司 显示设备
CN107887420A (zh) * 2017-10-25 2018-04-06 上海中航光电子有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550625B (zh) * 2018-04-18 2021-04-02 Tcl华星光电技术有限公司 一种薄膜晶体管及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814455A (zh) * 2009-02-19 2010-08-25 乐金显示有限公司 制造阵列基板的方法
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板
CN107275334A (zh) * 2016-04-08 2017-10-20 群创光电股份有限公司 显示设备
CN107887420A (zh) * 2017-10-25 2018-04-06 上海中航光电子有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Also Published As

Publication number Publication date
CN109920855A (zh) 2019-06-21
CN109920855B (zh) 2020-11-03

Similar Documents

Publication Publication Date Title
US5886761A (en) Process for producing actively addressing substrate, and liquid crystal display
US7666695B2 (en) Array substrates of liquid crystal display and fabrication method thereof
US7115913B2 (en) Array substrate used for a display device and a method of making the same
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
KR20190131582A (ko) Tft 기판의 제조 방법 및 tft 기판
WO2013123786A1 (zh) 薄膜晶体管阵列基板及其制作方法
US7575945B2 (en) Method of forming a metal line and method of manufacturing a display substrate by using the same including etching and undercutting the channel layer
US6335781B2 (en) Method for manufacturing an LCD in which a photoresist layer is at least 1.2 times thicker than the passivation layer
KR100336881B1 (ko) 박막트랜지스터액정표시소자의제조방법
US10497724B2 (en) Manufacturing method of a thin film transistor and manufacturing method of an array substrate
WO2020164220A1 (zh) 薄膜晶体管及其制作方法
JPH1082997A (ja) アクティブマトリクス液晶表示装置の製造方法及びアクティブマトリクス液晶表示装置
TW200939482A (en) Thin film transistor and semiconductor device
KR100707024B1 (ko) 박막트랜지스터 액정표시장치의 어레이 기판 제조방법
KR100603852B1 (ko) 회절 노광 기술을 이용한 액정 표시 장치 제조 방법
JPH06230425A (ja) 液晶表示装置及びその製造方法
KR101002470B1 (ko) 액정표시장치 제조방법
KR100289650B1 (ko) 박막 트랜지스터 액정표시소자의 제조방법
KR100707016B1 (ko) 박막 트랜지스터 액정표시장치의 제조방법
KR100259610B1 (ko) 액정표시장치 및 그 제조방법
KR20000003179A (ko) 액정표시소자의 데이터 라인 형성방법
JPH11119251A (ja) アクティブマトリックス基板の製造方法
KR100242946B1 (ko) 박막트랜지스터 및 그 제조방법
KR20040046384A (ko) 액정표시장치 및 그 제조방법
KR20020057025A (ko) 박막 트랜지스터 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19915442

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19915442

Country of ref document: EP

Kind code of ref document: A1