WO2020164193A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2020164193A1
WO2020164193A1 PCT/CN2019/085727 CN2019085727W WO2020164193A1 WO 2020164193 A1 WO2020164193 A1 WO 2020164193A1 CN 2019085727 W CN2019085727 W CN 2019085727W WO 2020164193 A1 WO2020164193 A1 WO 2020164193A1
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WIPO (PCT)
Prior art keywords
transistor
node
electrically connected
level
signal
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PCT/CN2019/085727
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English (en)
French (fr)
Inventor
薛炎
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020164193A1 publication Critical patent/WO2020164193A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA full English name: Gate Driver on Array, full Chinese name: integrated gate drive circuit
  • GOA full English name: Gate Driver on Array, full Chinese name: integrated gate drive circuit
  • the production process reduces product costs in two aspects.
  • the signal delay of the scan signal output by the existing GOA circuit is relatively large, which is likely to cause incorrect charging, and then cause abnormal display of the display panel.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the scan signal output by the existing GOA circuit has a relatively large signal delay, which is likely to cause incorrect charging, and thereby cause abnormal display of the display panel.
  • the embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: a pull-up control module, a downstream module, a first pull-up module, a second pull-up module, and feedback Module, pull-down module, pull-down control module, first bootstrap capacitor and second bootstrap capacitor;
  • the pull-up control module is connected to the upper-level transmission signal and the first clock signal, and is electrically connected to the first node and the second node, and is used to transfer the last one under the control of the first clock signal. Output level-by-level transmission signals to the first node and the second node;
  • the download module is connected to a second clock signal, and is electrically connected to the first node, for outputting a transmission signal of the current stage under the control of the potential of the first node;
  • the first pull-up module is connected to the second clock signal and is electrically connected to the first node for outputting a scan signal of the current level under the control of the potential of the first node;
  • the second pull-up module is connected to a third clock signal, and is electrically connected to the third node and the first node, for outputting the third clock signal under the control of the potential of the first node To the third node;
  • the feedback module is electrically connected to the current-level transmission signal, the current-level scanning signal, and the second node, and is used to combine the current-level scanning signal under the control of the current-level transmission signal The potential is fed back to the second node;
  • the pull-down module is connected to the next-level transmission signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node, the second node, and the first node A three-node for outputting the first DC low-level signal to the first node and the second node under the control of the next-level transmission signal, and at the next-level Outputting the second DC low-level signal to the third node under the control of the transmission signal;
  • the pull-down control module accesses a DC high-level signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node and the second node ,
  • the current-level transmission signal and the current-level scanning signal are used to pull down the potential of the first node, the second node, and the current-level transmission signal to the first The potential of the DC low-level signal, and pulling down the potential of the current-level scanning signal to the potential of the second DC low-level signal;
  • the first end of the first bootstrap capacitor is electrically connected to the first node, and the second end of the first bootstrap capacitor is electrically connected to the scan signal of the current stage;
  • a first end of the second bootstrap capacitor is electrically connected to the first node, and a second end of the second bootstrap capacitor is electrically connected to the third node;
  • the pull-up control module includes: a first transistor and a second transistor;
  • the gates of the first transistor and the second transistor are both electrically connected to the first clock signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the first The drain of a transistor and the source of the second transistor are both electrically connected to the second node, and the drain of the second transistor is electrically connected to the first node;
  • the download module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second clock signal, and the drain of the third transistor is electrically connected to the Describe the transmission signal at this level.
  • the first pull-up module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the scan signal at this level.
  • the second pull-up module includes: a fifth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the third clock signal, and the drain of the fifth transistor is electrically connected to the The third node.
  • the feedback module includes: a sixth transistor
  • the gate of the sixth transistor is electrically connected to the current-level transmission signal, the source of the sixth transistor is electrically connected to the current-level scan signal, and the gate of the sixth transistor is electrically connected At the second node.
  • the pull-down module includes: a seventh transistor, an eighth transistor, and a ninth transistor;
  • the gate of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor are all electrically connected to the next-level transmission signal, and the source of the seventh transistor is electrically connected Connected to the second DC low-level signal, the source of the eighth transistor is electrically connected to the first DC low-level signal, the drain of the eighth transistor and the ninth transistor The sources are electrically connected to the second node, and the drain of the ninth transistor is electrically connected to the first node.
  • the pull-down control module includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor , The seventeenth transistor and the eighteenth transistor;
  • the source of the twelfth transistor, the source of the fourteenth transistor, and the gate of the fourteenth transistor are all electrically connected to the DC high-level signal;
  • the source of the eleventh transistor, the source of the thirteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are all electrically connected to the first direct current Low-level signal
  • the source of the seventeenth transistor and the source of the eighteenth transistor are both electrically connected to the second DC low-level signal;
  • the gate of the tenth transistor, the gate of the eleventh transistor, the drain of the twelfth transistor, the drain of the thirteenth transistor, the gate of the sixteenth transistor, the The gate of the seventeenth transistor and the gate of the eighteenth transistor are electrically connected;
  • the drain of the tenth transistor, the gate of the thirteenth transistor, and the gate of the fifteenth transistor are all electrically connected to the first node;
  • the source of the tenth transistor and the drain of the eleventh transistor are both electrically connected to the second node;
  • the gate of the twelfth transistor, the drain of the fourteenth transistor, and the drain of the fifteenth transistor are all electrically connected;
  • the drain of the sixteenth transistor is electrically connected to the current stage for signal transmission; the drain of the seventeenth transistor and the drain of the eighteenth transistor are both electrically connected to the current stage of scanning signal.
  • the potential of the second DC low-level signal is greater than the potential of the first DC low-level signal.
  • An embodiment of the present application also provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: a pull-up control module, a downstream module, a first pull-up module, a second pull-up module, A feedback module, a pull-down module, a pull-down control module, a first bootstrap capacitor, and a second bootstrap capacitor;
  • the pull-up control module is connected to the upper-level transmission signal and the first clock signal, and is electrically connected to the first node and the second node, and is used to transfer the last one under the control of the first clock signal. Output level-by-level transmission signals to the first node and the second node;
  • the download module is connected to a second clock signal, and is electrically connected to the first node, for outputting a transmission signal of the current stage under the control of the potential of the first node;
  • the first pull-up module is connected to the second clock signal and is electrically connected to the first node for outputting a scan signal of the current level under the control of the potential of the first node;
  • the second pull-up module is connected to a third clock signal, and is electrically connected to the third node and the first node, for outputting the third clock signal under the control of the potential of the first node To the third node;
  • the feedback module is electrically connected to the current-level transmission signal, the current-level scanning signal, and the second node, and is used to combine the current-level scanning signal under the control of the current-level transmission signal The potential is fed back to the second node;
  • the pull-down module is connected to the next-level transmission signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node, the second node, and the first node A three-node for outputting the first DC low-level signal to the first node and the second node under the control of the next-level transmission signal, and at the next-level Outputting the second DC low-level signal to the third node under the control of the transmission signal;
  • the pull-down control module accesses a DC high-level signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node and the second node ,
  • the current-level transmission signal and the current-level scanning signal are used to pull down the potential of the first node, the second node, and the current-level transmission signal to the first The potential of the DC low-level signal, and pulling down the potential of the current-level scanning signal to the potential of the second DC low-level signal;
  • the first end of the first bootstrap capacitor is electrically connected to the first node, and the second end of the first bootstrap capacitor is electrically connected to the scan signal of the current stage;
  • the first terminal of the second bootstrap capacitor is electrically connected to the first node, and the second terminal of the second bootstrap capacitor is electrically connected to the third node.
  • the pull-up control module includes: a first transistor and a second transistor;
  • the gates of the first transistor and the second transistor are both electrically connected to the first clock signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the first The drain of a transistor and the source of the second transistor are both electrically connected to the second node, and the drain of the second transistor is electrically connected to the first node.
  • the download module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second clock signal, and the drain of the third transistor is electrically connected to the Describe the transmission signal at this level.
  • the first pull-up module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the scan signal at this level.
  • the second pull-up module includes: a fifth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the third clock signal, and the drain of the fifth transistor is electrically connected to the The third node.
  • the feedback module includes: a sixth transistor
  • the gate of the sixth transistor is electrically connected to the current-level transmission signal, the source of the sixth transistor is electrically connected to the current-level scan signal, and the gate of the sixth transistor is electrically connected At the second node.
  • the pull-down module includes: a seventh transistor, an eighth transistor, and a ninth transistor;
  • the gate of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor are all electrically connected to the next-level transmission signal, and the source of the seventh transistor is electrically connected Connected to the second DC low-level signal, the source of the eighth transistor is electrically connected to the first DC low-level signal, the drain of the eighth transistor and the ninth transistor The sources are electrically connected to the second node, and the drain of the ninth transistor is electrically connected to the first node.
  • the pull-down control module includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor , The seventeenth transistor and the eighteenth transistor;
  • the source of the twelfth transistor, the source of the fourteenth transistor, and the gate of the fourteenth transistor are all electrically connected to the DC high-level signal;
  • the source of the eleventh transistor, the source of the thirteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are all electrically connected to the first direct current Low-level signal
  • the source of the seventeenth transistor and the source of the eighteenth transistor are both electrically connected to the second DC low-level signal;
  • the gate of the tenth transistor, the gate of the eleventh transistor, the drain of the twelfth transistor, the drain of the thirteenth transistor, the gate of the sixteenth transistor, the The gate of the seventeenth transistor and the gate of the eighteenth transistor are electrically connected;
  • the drain of the tenth transistor, the gate of the thirteenth transistor, and the gate of the fifteenth transistor are all electrically connected to the first node;
  • the source of the tenth transistor and the drain of the eleventh transistor are both electrically connected to the second node;
  • the gate of the twelfth transistor, the drain of the fourteenth transistor, and the drain of the fifteenth transistor are all electrically connected;
  • the drain of the sixteenth transistor is electrically connected to the current stage for signal transmission; the drain of the seventeenth transistor and the drain of the eighteenth transistor are both electrically connected to the current stage of scanning signal.
  • the potential of the second DC low-level signal is greater than the potential of the first DC low-level signal.
  • An embodiment of the present application also provides a display panel, which includes a GOA circuit.
  • the GOA circuit includes: multi-level cascaded GOA units.
  • Each level of GOA unit includes: a pull-up control module, a downstream module, and a first upper A pull module, a second pull module, a feedback module, a pull module, a pull control module, a first bootstrap capacitor, and a second bootstrap capacitor;
  • the pull-up control module is connected to the upper-level transmission signal and the first clock signal, and is electrically connected to the first node and the second node, and is used to transfer the last one under the control of the first clock signal. Output level-by-level transmission signals to the first node and the second node;
  • the download module is connected to a second clock signal, and is electrically connected to the first node, for outputting a transmission signal of the current stage under the control of the potential of the first node;
  • the first pull-up module is connected to the second clock signal and is electrically connected to the first node for outputting a scan signal of the current level under the control of the potential of the first node;
  • the second pull-up module is connected to a third clock signal, and is electrically connected to the third node and the first node, for outputting the third clock signal under the control of the potential of the first node To the third node;
  • the feedback module is electrically connected to the current-level transmission signal, the current-level scanning signal, and the second node, and is used to combine the current-level scanning signal under the control of the current-level transmission signal The potential is fed back to the second node;
  • the pull-down module is connected to the next-level transmission signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node, the second node, and the first node A three-node for outputting the first DC low-level signal to the first node and the second node under the control of the next-level transmission signal, and at the next-level Outputting the second DC low-level signal to the third node under the control of the transmission signal;
  • the pull-down control module accesses a DC high-level signal, the first DC low-level signal, and the second DC low-level signal, and is electrically connected to the first node and the second node ,
  • the current-level transmission signal and the current-level scanning signal are used to pull down the potential of the first node, the second node, and the current-level transmission signal to the first The potential of the DC low-level signal, and pulling down the potential of the current-level scanning signal to the potential of the second DC low-level signal;
  • the first end of the first bootstrap capacitor is electrically connected to the first node, and the second end of the first bootstrap capacitor is electrically connected to the scan signal of the current stage;
  • the first terminal of the second bootstrap capacitor is electrically connected to the first node, and the second terminal of the second bootstrap capacitor is electrically connected to the third node.
  • the pull-up control module includes: a first transistor and a second transistor;
  • the gates of the first transistor and the second transistor are both electrically connected to the first clock signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the first The drain of a transistor and the source of the second transistor are both electrically connected to the second node, and the drain of the second transistor is electrically connected to the first node.
  • the download module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the second clock signal, and the drain of the third transistor is electrically connected to the Describe the transmission signal at this level.
  • the first pull-up module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the scan signal at this level.
  • the potential of the first node is pulled up multiple times by setting the first bootstrap capacitor and the second bootstrap capacitor, so that the potential of the first node is compared with that in the conventional GOA circuit.
  • the potential of the first node is high, which can significantly reduce the fall time of the scanning signal, prevent the risk of incorrect charging caused by the increase in the resolution of the display panel, and thereby improve the display quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of this application;
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application;
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit provided by the embodiment of the present application includes multi-stage cascaded GOA units.
  • Figure 1 takes the cascaded level n-1 GOA unit, n level GOA unit, and n+1 level GOA unit as examples.
  • the scan signal output by the n-th GOA unit is at a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel, and perform a data signal on the pixel electrode in each pixel.
  • the n-th level transmission signal is used to control the work of the n+1-th level GOA unit; when the n+1-th level GOA unit is working, the scan signal output by the n+1-th level GOA unit is high, and the nth level The scanning signal output by the GOA unit is low.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA unit includes: a pull-up control module 101, a download module 102, a first pull-up module 103, a second pull-up module 104, a feedback module 105, a pull-down module 106, a pull-down control module 107, and a A bootstrap capacitor Cbt1 and a second bootstrap capacitor Cbt2.
  • the pull-up control module 101 is connected to the upper-level transmission signal Count(n-1) and the first clock signal CK1, and is electrically connected to the first node Q and the second node N, for the Under the control of the signal CK1, the upper level transmission signal Count(n-1) is output to the first node Q and the second node N.
  • the download module 102 is connected to the second clock signal CK2, and is electrically connected to the first node Q, and is used for outputting the current stage transmission signal Count(n) under the control of the potential of the first node Q.
  • the first pull-up module 103 is connected to the second clock signal CK2 and is electrically connected to the first node Q for outputting the scan signal G(n) of the current level under the control of the potential of the first node Q.
  • the second pull-up module 104 is connected to the third clock signal CK3, and is electrically connected to the third node M and the first node Q, for outputting the third clock signal CK3 under the control of the potential of the first node Q To the third node M.
  • the feedback module 105 is electrically connected to the current level transmission signal Count(n), the current level scanning signal G(n) and the second node N, and is used to transfer the current level under the control of the current level transmission signal Count(n) The potential of the stage scan signal G(n) is fed back to the second node N.
  • the pull-down module 106 is connected to the next-level transmission signal Count(n+1), the first DC low-level signal VGL1, and the second DC low-level signal VGL2, and is electrically connected to the first node Q and the first node Q
  • the second node N and the third node M are used to output the first DC low-level signal VGL1 to the first node Q and the second node N under the control of the next-level transmission signal Count(n+1), and to The second DC low-level signal VGL2 is output to the third node M under the control of the first-level transmission signal Count(n+1).
  • the pull-down control module 107 accesses the DC high-level signal VGH, the first DC low-level signal VGL1, and the second DC low-level signal VGL2, and is electrically connected to the first node Q, the second node N, and the local The level-level transmission signal Count(n) and the current level scan signal G(n) are used to pull down the potential of the first node Q, the second node N, and the current level transmission signal Count(n) to the first The potential of the DC low-level signal VGL1, and the potential of the scanning signal G(n) of this level is pulled down to the potential of the second DC low-level signal VGL2.
  • the first end of the first bootstrap capacitor Cbt1 is electrically connected to the first node Q, and the second end of the first bootstrap capacitor Cbt1 is electrically connected to the scan signal G(n) of the current stage.
  • the first terminal of the second bootstrap capacitor Cbt2 is electrically connected to the first node Q, and the second terminal of the second bootstrap capacitor Cbt2 is electrically connected to the third node M.
  • the pull-up control module 101 includes: a first transistor T1 and a second transistor T2.
  • the gates of the first transistor T1 and the second transistor T2 are both electrically connected to the first clock signal CK1, the source of the first transistor T1 is electrically connected to the upper-level transmission signal Count(n-1), and the first transistor
  • the drain of T1 and the source of the second transistor T2 are both electrically connected to the second node N, and the drain of the second transistor T2 is electrically connected to the first node Q.
  • the download module 102 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the first node Q, the source of the third transistor T3 is electrically connected to the second clock signal CK2, and the drain of the third transistor T3 is electrically connected to the current stage transmission signal Count (N).
  • the first pull-up module 103 includes: a fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the first node Q
  • the source of the fourth transistor T4 is electrically connected to the second clock signal CK2
  • the drain of the fourth transistor T4 is electrically connected to the scan signal G( n).
  • the second pull-up module 104 includes: a fifth transistor T5.
  • the gate of the fifth transistor T5 is electrically connected to the first node Q
  • the source of the fifth transistor T5 is electrically connected to the third clock signal CK3
  • the drain of the fifth transistor T5 is electrically connected to the third node M.
  • the feedback module 105 includes: a sixth transistor T6.
  • the gate of the sixth transistor T6 is electrically connected to the transmission signal Count(n) of the current stage, the source of the sixth transistor T6 is electrically connected to the scan signal G(n) of the current stage, and the gate of the sixth transistor T6 is electrically connected Connected to the second node N.
  • the pull-down module 106 includes: a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the gate of the seventh transistor T7, the gate of the eighth transistor T8, and the gate of the ninth transistor T9 are all electrically connected to the next stage transmission signal Count (n+1), and the source of the seventh transistor T7 is electrically connected Connected to the second DC low-level signal VGL2, the source of the eighth transistor T8 is electrically connected to the first DC low-level signal VGL1, the drain of the eighth transistor T8 and the source of the ninth transistor T9 are electrically equal Connected to the second node N, the drain of the ninth transistor T9 is electrically connected to the first node Q.
  • the pull-down control module 107 includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor.
  • the source of the twelfth transistor T12, the source of the fourteenth transistor T14, and the gate of the fourteenth transistor T14 are all electrically connected to the DC high-level signal VGH; the source of the eleventh transistor T11, the source of the thirteenth transistor T14 The source of the transistor T13, the source of the fifteenth transistor T15, and the source of the sixteenth transistor T16 are all electrically connected to the first DC low-level signal VGL1. The source of the seventeenth transistor T17 and the source of the eighteenth transistor T18 are both electrically connected to the second direct current low level signal VGL2.
  • the drain of the tenth transistor T10, the gate of the thirteenth transistor T13, and the gate of the fifteenth transistor T15 are all electrically connected to the first node Q.
  • the source of the tenth transistor T10 and the drain of the eleventh transistor T11 are both electrically connected to the second node N.
  • the gate of the twelfth transistor T12, the drain of the fourteenth transistor T14, and the drain of the fifteenth transistor T15 are all electrically connected; the drain of the sixteenth transistor T16 is electrically connected to the transmission signal Count( n).
  • the drain of the seventeenth transistor T17 and the drain of the eighteenth transistor T18 are both electrically connected to the scan signal G(n) of this stage.
  • the GOA circuit provided in the embodiment of this application has a first bootstrap capacitor Cbt1 and a second bootstrap capacitor Cbt2 to the first
  • the potential of the node Q is pulled up multiple times, so that the potential of the first node Q is higher than that of the first node Q in the traditional GOA circuit, which can significantly reduce the fall time of the scan signal and prevent the resolution of the display panel Increase the risk of incorrect charging.
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the first DC low-level signal VGL1 and the second DC low-level signal VGL2 are DC power supplies.
  • the potential of the second direct current low level signal VGL2 is greater than the potential of the first direct current low level signal VGL1.
  • the voltage of the second DC low level signal VGL2 can be set to -10V
  • the voltage of the second DC low level signal VGL2 can be set to -6V
  • the voltage of the DC high level signal VGH can be set to +24V.
  • the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are all AC power sources.
  • the maximum voltage of the first clock signal CK1, the second timing signal, and the third clock signal CK3 can be set to +24V
  • the minimum voltage of the first clock signal CK1, the second timing signal, and the third clock signal CK3 can be set For -10V.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a low level
  • the third clock signal CK3 is at a low level
  • the upper-level transmission signal Count(n-1) is High potential
  • the next level transmission signal Count (n+1) is low potential.
  • the first clock signal CK1 is at a high potential
  • the first transistor T1 and the second transistor T2 are turned on.
  • the upper-level transmission signal Count(n-1) is first output to the second node N through the first transistor T1, and then through the first transistor T1.
  • the two transistors T2 are output to the first node Q. That is, at this time, the potential of the first node Q is raised to a high potential.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the fifteenth transistor T15 are turned on.
  • the first DC low level signal VGL1 is output through the thirteenth transistor T13 and the fifteenth transistor T15, so that the tenth transistor T10, the eleventh transistor T11, the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T15
  • the eight transistor T18 is off.
  • the second clock signal CK2 outputs the current stage pass signal Count(n) via the third transistor T3, the second clock signal CK2 outputs the current stage scan signal G(n) via the fourth transistor T4, and the third clock signal CK3 outputs the current stage scan signal G(n) via the fifth transistor.
  • T5 is output to the third node M. Since the second clock signal CK2 and the third clock signal CK3 are low, that is, in the first time period t1, the transmission signal Count(n) of this stage is low, and the scanning signal G(n) of this stage is low. , The potential of the third node M is low.
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a high level
  • the third clock signal CK3 is at a low level
  • the upper-level transfer signal Count(n-1) is at a low level.
  • the next level transmission signal Count (n+1) is low.
  • the first clock signal CK1 is at a low level, the first transistor T1 and the second transistor T2 are turned off.
  • the potential of the first node Q first maintains the high potential during the first time period t1. That is, at this time, the third transistor T3 is turned on, and the second clock signal CK2 is output to the second end of the first bootstrap capacitor Cbt1. Due to the capacitive coupling effect, the potential of the first end of the first capacitor also changes accordingly. That is, the potential of the first node Q continues to rise.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the fifteenth transistor T15 are turned on.
  • the first DC low level signal VGL1 is output through the thirteenth transistor T13 and the fifteenth transistor T15, so that the tenth transistor T10, the eleventh transistor T11, the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T15
  • the eight transistor T18 is off.
  • the second clock signal CK2 outputs the current stage pass signal Count(n) via the third transistor T3, the second clock signal CK2 outputs the current stage scan signal G(n) via the fourth transistor T4, and the third clock signal CK3 outputs the current stage scan signal G(n) via the fifth transistor.
  • T5 is output to the third node M.
  • the third clock signal CK3 is at a low potential, that is, in the second time period t2, the transmission signal Count(n) of the current stage is at a high potential, and the scan signal G(n) of the current stage It is a high potential, and the potential of the third node M is still a low potential.
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a high level
  • the third clock signal CK3 is at a high level
  • the upper level transmission signal Count(n-1) is at a low level.
  • the next level transmission signal Count (n+1) is low.
  • the first clock signal CK1 is at a low level, the first transistor T1 and the second transistor T2 are turned off.
  • the potential of the first node Q first maintains the high potential during the second time period t2. That is, at this time, the third transistor T3 is turned on, and the second clock signal CK2 is output to the second end of the first bootstrap capacitor Cbt1. That is, at this time, the potential of the first node Q is still the potential in the second time period t2.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the fifteenth transistor T15 are turned on.
  • the first DC low level signal VGL1 is output through the thirteenth transistor T13 and the fifteenth transistor T15, so that the tenth transistor T10, the eleventh transistor T11, the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T15
  • the eight transistor T18 is off.
  • the second clock signal CK2 outputs the current stage pass signal Count(n) via the third transistor T3, the second clock signal CK2 outputs the current stage scan signal G(n) via the fourth transistor T4, and the third clock signal CK3 outputs the current stage scan signal G(n) via the fifth transistor.
  • T5 is output to the third node M.
  • the third clock signal CK3 is at a high potential, that is, in the third time period t3, the transmission signal Count(n) of the current stage is at a high potential, and the scan signal G(n) of the current stage At a high potential, the third clock signal CK3 is output to the second end of the second bootstrap capacitor. Due to the capacitive coupling effect, the potential of the first terminal of the second bootstrap capacitor Cbt2 also changes accordingly. That is, the potential of the first node Q continues to rise.
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a low level
  • the third clock signal CK3 is at a high level
  • the upper-level transmission signal Count(n-1) is at a low level.
  • the next level transmission signal Count (n+1) is low.
  • the first clock signal CK1 is at a low level, the first transistor T1 and the second transistor T2 are turned off.
  • the potential of the first node Q first maintains the high potential during the third time period t3.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the fifteenth transistor T15 are turned on.
  • the first DC low level signal VGL1 is output through the thirteenth transistor T13 and the fifteenth transistor T15, so that the tenth transistor T10, the eleventh transistor T11, the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T15
  • the eight transistor T18 is off.
  • the second clock signal CK2 outputs the current stage pass signal Count(n) via the third transistor T3, the second clock signal CK2 outputs the current stage scan signal G(n) via the fourth transistor T4, and the third clock signal CK3 outputs the current stage scan signal G(n) via the fifth transistor.
  • T5 is output to the third node M.
  • the transmission signal Count(n) of the current level is at a low level
  • the scan signal G(n) of the current level At a low potential, the potential of the third node M is still at a high potential.
  • the second clock signal CK2 is output to the second end of the first bootstrap capacitor Cbt1 through the fourth transistor T4. Due to the capacitive coupling effect, the potential of the first terminal of the first bootstrap capacitor Cbt1 also changes accordingly. That is, the potential of the first node Q is pulled down.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a low level
  • the third clock signal CK3 is at a low level
  • the upper-level transfer signal Count(n-1) is at a low level.
  • the next level transmission signal Count (n+1) is high.
  • the first clock signal CK1 is at a high potential
  • the first transistor T1 and the second transistor T2 are turned on.
  • the upper-level transmission signal Count(n-1) is first output to the second node N through the first transistor T1, and then through the first transistor T1.
  • the two transistors T2 are output to the first node Q. That is, at this time, the potential of the first node Q is pulled down.
  • the fifteenth transistor T15 is turned off, so that the tenth transistor T10, the eleventh transistor T11, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned on.
  • the first DC low level signal VGL1 is output to the first node Q through the eleventh transistor T11 and the tenth transistor T10, and the potential of the first node Q is pulled down.
  • the first DC low-level signal VGL1 is output to the current stage transmission signal Count(n) through the sixteenth transistor T16, and the current stage transmission signal Count(n) is pulled low.
  • the second DC low level signal VGL2 is output to the scan signal G(n) of the current stage through the seventeenth transistor T17 and the eighteenth transistor T18, and the scan signal G(n) of the current stage is pulled low.
  • next-stage transmission signal Count(n+1) is at a high potential
  • the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on.
  • the second clock signal CK2 is output to the third node M through the seventh transistor T7, and the potential of the third node M is pulled low.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein, the structure and principle of the GOA circuit 200 are similar to the above-mentioned GOA circuit, and will not be repeated here.

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Abstract

一种GOA电路(200)及显示面板，通过设置第一自举电容(Cbt1)以及第二自举电容(Cbt2)对第一节点(Q)的电位进行多次上拉，使得第一节点(Q)的电位相较于传统GOA电路中的第一节点的电位高，从而能够显著减少扫描信号(G(n))的下降时间，防止因显示面板的解析度提高造成的错充风险，进而提高显示面板显示质量。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。然而，现有的GOA电路输出的扫描信号的信号延时较大，容易造成错充，进而导致显示面板显示异常。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的GOA电路输出的扫描信号的信号延时较大，容易造成错充，进而导致显示面板显示异常的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点；
所述上拉控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点；
所述下传模块包括：第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述第一上拉模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第二上拉模块包括：第五晶体管；
所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三时钟信号，所述第五晶体管的漏极电性连接于所述第三节点。
在本申请所述的GOA电路中，所述反馈模块包括：第六晶体管；
所述第六晶体管的栅极电性连接于所述本级级传信号，所述第六晶体管的源极电性连接于所述本级扫描信号，所述第六晶体管的栅极电性连接于所述第二节点。
在本申请所述的GOA电路中，所述下拉模块包括：第七晶体管、第八晶体管以及第九晶体管；
所述第七晶体管的栅极、所述第八晶体管的栅极以及所述第九晶体管的栅极均电性连接于所述下一级级传信号，所述第七晶体管的源极电性连接于所述第二直流低电平信号，所述第八晶体管的源极电性连接于所述第一直流低电平信号，所述第八晶体管的漏极以及所述第九晶体管的源极均电性连接于所述第二节点，所述第九晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述下拉控制模块包括：第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管以及第十八晶体管；
所述第十二晶体管的源极、所述第十四晶体管的源极以及所述第十四晶体管的栅极均电性连接与所述直流高电平信号；
所述第十一晶体管的源极、所述第十三晶体管的源极，所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一直流低电平信号；
所述第十七晶体管的源极以及所述第十八晶体管的源极均电性连接于所述第二直流低电平信号；
所述第十晶体管的栅极、所述第十一晶体管的栅极、所述第十二晶体管的漏极、所述第十三晶体管的漏极、所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十八晶体管的栅极均电性连接；
所述第十晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的栅极均电性连接于所述第一节点；
所述第十晶体管的源极以及所述第十一晶体管的漏极均电性连接于所述第二节点；
所述第十二晶体管的栅极、所述第十四晶体管的漏极以及所述第十五晶体管的漏极均电性连接；
所述第十六晶体管的漏极电性连接于所述本级级传信号；所述第十七晶体管的漏极以及所述第十八晶体管的漏极均电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第二直流低电平信号的电位大于所述第一直流低电平信号的电位。
本申请实施例还提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点。
在本申请所述的GOA电路中，所述上拉控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述下传模块包括：第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述第一上拉模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第二上拉模块包括：第五晶体管；
所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三时钟信号，所述第五晶体管的漏极电性连接于所述第三节点。
在本申请所述的GOA电路中，所述反馈模块包括：第六晶体管；
所述第六晶体管的栅极电性连接于所述本级级传信号，所述第六晶体管的源极电性连接于所述本级扫描信号，所述第六晶体管的栅极电性连接于所述第二节点。
在本申请所述的GOA电路中，所述下拉模块包括：第七晶体管、第八晶体管以及第九晶体管；
所述第七晶体管的栅极、所述第八晶体管的栅极以及所述第九晶体管的栅极均电性连接于所述下一级级传信号，所述第七晶体管的源极电性连接于所述第二直流低电平信号，所述第八晶体管的源极电性连接于所述第一直流低电平信号，所述第八晶体管的漏极以及所述第九晶体管的源极均电性连接于所述第二节点，所述第九晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述下拉控制模块包括：第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管以及第十八晶体管；
所述第十二晶体管的源极、所述第十四晶体管的源极以及所述第十四晶体管的栅极均电性连接与所述直流高电平信号；
所述第十一晶体管的源极、所述第十三晶体管的源极，所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一直流低电平信号；
所述第十七晶体管的源极以及所述第十八晶体管的源极均电性连接于所述第二直流低电平信号；
所述第十晶体管的栅极、所述第十一晶体管的栅极、所述第十二晶体管的漏极、所述第十三晶体管的漏极、所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十八晶体管的栅极均电性连接；
所述第十晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的栅极均电性连接于所述第一节点；
所述第十晶体管的源极以及所述第十一晶体管的漏极均电性连接于所述第二节点；
所述第十二晶体管的栅极、所述第十四晶体管的漏极以及所述第十五晶体管的漏极均电性连接；
所述第十六晶体管的漏极电性连接于所述本级级传信号；所述第十七晶体管的漏极以及所述第十八晶体管的漏极均电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第二直流低电平信号的电位大于所述第一直流低电平信号的电位。
本申请实施例还提供一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点。
在本申请所述的显示面板中，所述上拉控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点。
在本申请所述的显示面板中，所述下传模块包括：第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的显示面板中，所述第一上拉模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过设置第一自举电容以及第二自举电容对第一节点的电位进行多次上拉，使得第一节点的电位相较于传统GOA电路中的第一节点的电位高，从而能够显著减少扫描信号的下降时间，防止因显示面板的解析度提高造成的错充风险，进而提高显示面板显示质量。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为本申请实施例提供的GOA电路中一GOA单元的电路示意图；
图3为本申请实施例提供的GOA电路中一GOA单元的信号时序图；
图4为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路包括多级级联的GOA单元。其中，图1以级联的第n-1级GOA单元、第n级GOA单元和第n+1级GOA单元为例。
当第n级GOA单元工作时，第n级GOA单元输出的扫描信号为高电位，用于打开显示面板中一行中每个像素的晶体管开关，并通过数据信号对每个像素中的像素电极进行充电；第n级级传信号用于控制第n+1级GOA单元的工作；当第n+1级GOA单元工作时，第n+1级GOA单元输出的扫描信号为高电位，同时第n级GOA单元输出的扫描信号为低电位。
进一步的，请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的电路示意图。如图2所示，该GOA单元包括：上拉控制模块101、下传模块102、第一上拉模块103、第二上拉模块104、反馈模块105、下拉模块106、下拉控制模块107、第一自举电容Cbt1以及第二自举电容Cbt2。
其中，所上拉控制模块101接入上一级级传信号Count（n-1）以及第一时钟信号CK1，并电性连接于第一节点Q以及第二节点N，用于在第一时钟信号CK1的控制下将上一级级传信号Count（n-1）输出至第一节点Q以及第二节点N。
其中，下传模块102接入第二时钟信号CK2，并电性连接于第一节点Q，用于在第一节点Q的电位控制下输出本级级传信号Count（n）。
其中，第一上拉模块103接入第二时钟信号CK2，并电性连接于第一节点Q，用于在第一节点Q的电位控制下输出本级扫描信号G（n）。
其中，第二上拉模块104接入第三时钟信号CK3，并电性连接于第三节点M以及第一节点Q，用于在第一节点Q的电位控制下，将第三时钟信号CK3输出至第三节点M。
其中，反馈模块105电性连接于本级级传信号Count（n）、本级扫描信号G（n）以及第二节点N，用于在本级级传信号Count（n）的控制下将本级扫描信号G（n）的电位反馈至第二节点N。
其中，下拉模块106接入下一级级传信号Count（n+1）、第一直流低电平信号VGL1以及第二直流低电平信号VGL2，并电性连接于第一节点Q、第二节点N以及第三节点M，用于在下一级级传信号Count（n+1）的控制下将第一直流低电平信号VGL1输出至第一节点Q以及第二节点N，以及在下一级级传信号Count（n+1）的控制下将第二直流低电平信号VGL2输出至第三节点M。
其中，下拉控制模块107接入直流高电平信号VGH、第一直流低电平信号VGL1以及第二直流低电平信号VGL2，并电性连接于第一节点Q、第二节点N、本级级传信号Count（n）以及本级扫描信号G（n），用于将第一节点Q的电位、第二节点N的电位以及本级级传信号Count（n）的电位下拉至第一直流低电平信号VGL1的电位，以及将本级扫描信号G（n）的电位下拉至第二直流低电平信号VGL2的电位。
其中，第一自举电容Cbt1的第一端电性连接于第一节点Q，第一自举电容Cbt1的第二端电性连接于本级扫描信号G（n）。
其中，第二自举电容Cbt2的第一端电性连接于第一节点Q，第二自举电容Cbt2的第二端电性连接于第三节点M。
在一些实施例中，上拉控制模块101包括：第一晶体管T1以及第二晶体管T2。第一晶体管T1以及第二晶体管T2的栅极均电性连接于第一时钟信号CK1，第一晶体管T1的源极电性连接于上一级级传信号Count（n-1），第一晶体管T1的漏极以及第二晶体管T2的源极均电性连接于第二节点N，第二晶体管T2的漏极电性连接于第一节点Q。
在一些实施例中，下传模块102包括：第三晶体管T3。第三晶体管T3的栅极电性连接于第一节点Q，第三晶体管T3的源极电性连接于第二时钟信号CK2，第三晶体管T3的漏极电性连接于本级级传信号Count（n）。
在一些实施例中，第一上拉模块103包括：第四晶体管T4。第四晶体管T4的栅极电性连接于第一节点Q，第四晶体管T4的源极电性连接于第二时钟信号CK2，第四晶体管T4的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，第二上拉模块104包括：第五晶体管T5。第五晶体管T5的栅极电性连接于第一节点Q，第五晶体管T5的源极电性连接于第三时钟信号CK3，第五晶体管T5的漏极电性连接于第三节点M。
在一些实施例中，反馈模块105包括：第六晶体管T6。第六晶体管T6的栅极电性连接于本级级传信号Count（n），第六晶体管T6的源极电性连接于本级扫描信号G（n），第六晶体管T6的栅极电性连接于第二节点N。
在一些实施例中，下拉模块106包括：第七晶体管T7、第八晶体管T8以及第九晶体管T9。第七晶体管T7的栅极、第八晶体管T8的栅极以及第九晶体管T9的栅极均电性连接于下一级级传信号Count（n+1），第七晶体管T7的源极电性连接于第二直流低电平信号VGL2，第八晶体管T8的源极电性连接于第一直流低电平信号VGL1，第八晶体管T8的漏极以及第九晶体管T9的源极均电性连接于第二节点N，第九晶体管T9的漏极电性连接于第一节点Q。
在一些实施例中，下拉控制模块107包括：第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18。
第十二晶体管T12的源极、第十四晶体管T14的源极以及第十四晶体管T14的栅极均电性连接与直流高电平信号VGH；第十一晶体管T11的源极、第十三晶体管T13的源极，第十五晶体管T15的源极以及第十六晶体管T16的源极均电性连接于第一直流低电平信号VGL1。第十七晶体管T17的源极以及第十八晶体管T18的源极均电性连接于第二直流低电平信号VGL2。第十晶体管T10的栅极、第十一晶体管T11的栅极、第十二晶体管T12的漏极、第十三晶体管T13的漏极、第十六晶体管T16的栅极、第十七晶体管T17的栅极以及第十八晶体管T18的栅极均电性连接。第十晶体管T10的漏极、第十三晶体管T13的栅极以及第十五晶体管T15的栅极均电性连接于第一节点Q。第十晶体管T10的源极以及第十一晶体管T11的漏极均电性连接于第二节点N。第十二晶体管T12的栅极、第十四晶体管T14的漏极以及第十五晶体管T15的漏极均电性连接；第十六晶体管T16的漏极电性连接于本级级传信号Count（n）。第十七晶体管T17的漏极以及第十八晶体管T18的漏极均电性连接于本级扫描信号G（n）。
需要说明的是，本申请实施例提供的GOA电路与现有的GOA电路的区别在于：本申请实施例提供的GOA电路，通过设置第一自举电容Cbt1以及第二自举电容Cbt2对第一节点Q的电位进行多次上拉，使得第一节点Q的电位相较于传统GOA电路中的第一节点Q的电位高，从而能够显著减少扫描信号的下降时间，防止因显示面板的解析度提高造成的错充风险。
请结合图2、图3，图3为本申请实施例提供的GOA电路中一GOA单元的信号时序图。
其中，第一直流低电平信号VGL1和第二直流低电平信号VGL2为直流电源。第二直流低电平信号VGL2的电位大于第一直流低电平信号VGL1的电位。例如，第二直流低电平信号VGL2的电压可以设置为-10V，第二直流低电平信号VGL2的的电压可以设置为-6V，直流高电平信号VGH的电压可以设置为+24V。
其中，第一时钟信号CK1、第二时钟信号CK2以及第三时钟信号CK3均为交流电源。例如，第一时钟信号CK1、第二时序信号以及第三时钟信号CK3的电压最大值可以设置为+24V，第一时钟信号CK1、第二时序信号以及第三时钟信号CK3的电压最小值可以设置为-10V。
具体的，在第一时间段t1，第一时钟信号CK1为高电位，第二时钟信号CK2为低电位，第三时钟信号CK3为低电位，上一级级传信号Count（n-1）为高电位，下一级级传信号Count（n+1）为低电位。
由于第一时钟信号CK1为高电位，使得第一晶体管T1以及第二晶体管T2打开，上一级级传信号Count（n-1）先经第一晶体管T1输出至第二节点N，再经第二晶体管T2输出至第一节点Q。也即，此时，第一节点Q的电位被抬升至高电位。
由于第一节点Q的电位被抬升至高电位，使得第三晶体管T3、第四晶体管T4、第五晶体管T5、第十三晶体管T13以及第十五晶体管T15打开。第一直流低电平信号VGL1经第十三晶体管T13以及第十五晶体管T15输出，从而使得第十晶体管T10、第十一晶体管T11、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18关闭。
由于下一级级传信号Count（n+1）为低电位，使得第七晶体管T7、第八晶体管T8以及第九晶体管T9关闭。第二时钟信号CK2经第三晶体管T3输出本级级传信号Count（n），第二时钟信号CK2经第四晶体管T4输出本级扫描信号G（n），第三时钟信号CK3经第五晶体管T5输出至第三节点M。由于第二时钟信号CK2以及第三时钟信号CK3为低电位，也即，在第一时间段t1，本级级传信号Count（n）为低电位，本级扫描信号G（n）为低电位，第三节点M的电位为低电位。
在第二时间段t2，第一时钟信号CK1为低电位，第二时钟信号CK2为高电位，第三时钟信号CK3为低电位，上一级级传信号Count（n-1）为低电位，下一级级传信号Count（n+1）为低电位。
由于第一时钟信号CK1为低电位，使得第一晶体管T1以及第二晶体管T2关闭。另外，由于第一自举电容Cbt1以及第二自举电容Cbt2的存储作用，使得第一节点Q的电位先保持第一时间段t1时的高电位。也即，此时，第三晶体管T3打开，第二时钟信号CK2输出至第一自举电容Cbt1的第二端。由于电容耦合效应，使得第一电容的第一端的电位也相应发生变换。也即，第一节点Q的电位继续上升。
由于第一节点Q的电位继续上升，使得第三晶体管T3、第四晶体管T4、第五晶体管T5、第十三晶体管T13以及第十五晶体管T15打开。第一直流低电平信号VGL1经第十三晶体管T13以及第十五晶体管T15输出，从而使得第十晶体管T10、第十一晶体管T11、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18关闭。
由于下一级级传信号Count（n+1）为低电位，使得第七晶体管T7、第八晶体管T8以及第九晶体管T9关闭。第二时钟信号CK2经第三晶体管T3输出本级级传信号Count（n），第二时钟信号CK2经第四晶体管T4输出本级扫描信号G（n），第三时钟信号CK3经第五晶体管T5输出至第三节点M。由于第二时钟信号CK2为高电位，第三时钟信号CK3为低电位，也即，在第二时间段t2，本级级传信号Count（n）为高电位，本级扫描信号G（n）为高电位，第三节点M的电位仍为低电位。
在第三时间段t3，第一时钟信号CK1为低电位，第二时钟信号CK2为高电位，第三时钟信号CK3为高电位，上一级级传信号Count（n-1）为低电位，下一级级传信号Count（n+1）为低电位。
由于第一时钟信号CK1为低电位，使得第一晶体管T1以及第二晶体管T2关闭。另外，由于第一自举电容Cbt1以及第二自举电容Cbt2的存储作用，使得第一节点Q的电位先保持第二时间段t2时的高电位。也即，此时，第三晶体管T3打开，第二时钟信号CK2输出至第一自举电容Cbt1的第二端。也即，此时，第一节点Q的电位仍旧为第二时间段t2时的电位。
由于第一节点Q的电位仍旧为第二时间段t2时的电位，使得第三晶体管T3、第四晶体管T4、第五晶体管T5、第十三晶体管T13以及第十五晶体管T15打开。第一直流低电平信号VGL1经第十三晶体管T13以及第十五晶体管T15输出，从而使得第十晶体管T10、第十一晶体管T11、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18关闭。
由于下一级级传信号Count（n+1）为低电位，使得第七晶体管T7、第八晶体管T8以及第九晶体管T9关闭。第二时钟信号CK2经第三晶体管T3输出本级级传信号Count（n），第二时钟信号CK2经第四晶体管T4输出本级扫描信号G（n），第三时钟信号CK3经第五晶体管T5输出至第三节点M。由于第二时钟信号CK2为高电位，第三时钟信号CK3为高电位，也即，在第三时间段t3，本级级传信号Count（n）为高电位，本级扫描信号G（n）为高电位，第三时钟信号CK3输出至第二自举电容的第二端。由于电容耦合效应，使得第二自举电容Cbt2的第一端的电位也相应发生变换。也即，第一节点Q的电位继续上升。
在第四时间段t4，第一时钟信号CK1为低电位，第二时钟信号CK2为低电位，第三时钟信号CK3为高电位，上一级级传信号Count（n-1）为低电位，下一级级传信号Count（n+1）为低电位。
由于第一时钟信号CK1为低电位，使得第一晶体管T1以及第二晶体管T2关闭。另外，由于第一自举电容Cbt1以及第二自举电容Cbt2的存储作用，使得第一节点Q的电位先保持第三时间段t3时的高电位。
由于第一节点Q的电位先为第三时间段t3时的电位，使得第三晶体管T3、第四晶体管T4、第五晶体管T5、第十三晶体管T13以及第十五晶体管T15打开。第一直流低电平信号VGL1经第十三晶体管T13以及第十五晶体管T15输出，从而使得第十晶体管T10、第十一晶体管T11、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18关闭。
由于下一级级传信号Count（n+1）为低电位，使得第七晶体管T7、第八晶体管T8以及第九晶体管T9关闭。第二时钟信号CK2经第三晶体管T3输出本级级传信号Count（n），第二时钟信号CK2经第四晶体管T4输出本级扫描信号G（n），第三时钟信号CK3经第五晶体管T5输出至第三节点M。由于第二时钟信号CK2为低电位，第三时钟信号CK3为高电位，也即，在第四时间段t4，本级级传信号Count（n）为低电位，本级扫描信号G（n）为低电位，第三节点M的电位仍为高电位。另外，第二时钟信号CK2经第四晶体管T4输出至第一自举电容Cbt1的第二端。由于电容耦合效应，使得第一自举电容Cbt1的第一端的电位也相应发生变换。也即，第一节点Q的电位被拉低。
在第五时间段t5，第一时钟信号CK1为高电位，第二时钟信号CK2为低电位，第三时钟信号CK3为低电位，上一级级传信号Count（n-1）为低电位，下一级级传信号Count（n+1）为高电位。
由于第一时钟信号CK1为高电位，使得第一晶体管T1以及第二晶体管T2打开，上一级级传信号Count（n-1）先经第一晶体管T1输出至第二节点N，再经第二晶体管T2输出至第一节点Q。也即，此时，第一节点Q的电位被拉低。
由于第一节点Q的电位被拉低，也即，此时，第一节点Q的电位为低电位，使得第三晶体管T3、第四晶体管T4、第五晶体管T5、第十三晶体管T13以及第十五晶体管T15关闭，进而使得第十晶体管T10、第十一晶体管T11、第十六晶体管T16、第十七晶体管T17以及第十八晶体管T18打开。第一直流低电平信号VGL1经第十一晶体管T11以及第十晶体管T10输出至第一节点Q，第一节点Q的电位被拉低。第一直流低电平信号VGL1经第十六晶体管T16输出至本级级传信号Count（n），本级级传信号Count（n）被拉低。第二直流低电平信号VGL2经第十七晶体管T17以及第十八晶体管T18输出至本级扫描信号G（n），本级扫描信号G（n）被拉低。
由于下一级级传信号Count（n+1）为高电位，使得第七晶体管T7、第八晶体管T8以及第九晶体管T9打开。第二时钟信号CK2经第七晶体管T7输出至第三节点M，第三节点M的电位被拉低。
请参阅图4，图4为本申请实施例提供的显示面板的结构示意图。如图4所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路的结构和原理类似，这里不再赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
    所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
    所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
    所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
    所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
    所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
    所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
    所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点；
    所述上拉控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点；
    所述下传模块包括：第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
  2. 根据权利要求1所述的GOA电路，其中，所述第一上拉模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
  3. 根据权利要求1所述的GOA电路，其中，所述第二上拉模块包括：第五晶体管；
    所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三时钟信号，所述第五晶体管的漏极电性连接于所述第三节点。
  4. 根据权利要求1所述的GOA电路，其中，所述反馈模块包括：第六晶体管；
    所述第六晶体管的栅极电性连接于所述本级级传信号，所述第六晶体管的源极电性连接于所述本级扫描信号，所述第六晶体管的栅极电性连接于所述第二节点。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括：第七晶体管、第八晶体管以及第九晶体管；
    所述第七晶体管的栅极、所述第八晶体管的栅极以及所述第九晶体管的栅极均电性连接于所述下一级级传信号，所述第七晶体管的源极电性连接于所述第二直流低电平信号，所述第八晶体管的源极电性连接于所述第一直流低电平信号，所述第八晶体管的漏极以及所述第九晶体管的源极均电性连接于所述第二节点，所述第九晶体管的漏极电性连接于所述第一节点。
  6. 根据权利1所述的GOA电路，其中，所述下拉控制模块包括：第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管以及第十八晶体管；
    所述第十二晶体管的源极、所述第十四晶体管的源极以及所述第十四晶体管的栅极均电性连接与所述直流高电平信号；
    所述第十一晶体管的源极、所述第十三晶体管的源极，所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一直流低电平信号；
    所述第十七晶体管的源极以及所述第十八晶体管的源极均电性连接于所述第二直流低电平信号；
    所述第十晶体管的栅极、所述第十一晶体管的栅极、所述第十二晶体管的漏极、所述第十三晶体管的漏极、所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十八晶体管的栅极均电性连接；
    所述第十晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的栅极均电性连接于所述第一节点；
    所述第十晶体管的源极以及所述第十一晶体管的漏极均电性连接于所述第二节点；
    所述第十二晶体管的栅极、所述第十四晶体管的漏极以及所述第十五晶体管的漏极均电性连接；
    所述第十六晶体管的漏极电性连接于所述本级级传信号；所述第十七晶体管的漏极以及所述第十八晶体管的漏极均电性连接于所述本级扫描信号。
  7. 根据权利要求1所述的GOA电路，其中，所述第二直流低电平信号的电位大于所述第一直流低电平信号的电位。
  8. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
    所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
    所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
    所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
    所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
    所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
    所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
    所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点。
  9. 根据权利要求8所述的GOA电路，其中，所述上拉控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点。
  10. 根据权利要求8所述的GOA电路，其中，所述下传模块包括：第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
  11. 根据权利要求8所述的GOA电路，其中，所述第一上拉模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
  12. 根据权利要求8所述的GOA电路，其中，所述第二上拉模块包括：第五晶体管；
    所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三时钟信号，所述第五晶体管的漏极电性连接于所述第三节点。
  13. 根据权利要求8所述的GOA电路，其中，所述反馈模块包括：第六晶体管；
    所述第六晶体管的栅极电性连接于所述本级级传信号，所述第六晶体管的源极电性连接于所述本级扫描信号，所述第六晶体管的栅极电性连接于所述第二节点。
  14. 根据权利要求8所述的GOA电路，其中，所述下拉模块包括：第七晶体管、第八晶体管以及第九晶体管；
    所述第七晶体管的栅极、所述第八晶体管的栅极以及所述第九晶体管的栅极均电性连接于所述下一级级传信号，所述第七晶体管的源极电性连接于所述第二直流低电平信号，所述第八晶体管的源极电性连接于所述第一直流低电平信号，所述第八晶体管的漏极以及所述第九晶体管的源极均电性连接于所述第二节点，所述第九晶体管的漏极电性连接于所述第一节点。
  15. 根据权利8所述的GOA电路，其中，所述下拉控制模块包括：第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管以及第十八晶体管；
    所述第十二晶体管的源极、所述第十四晶体管的源极以及所述第十四晶体管的栅极均电性连接与所述直流高电平信号；
    所述第十一晶体管的源极、所述第十三晶体管的源极，所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一直流低电平信号；
    所述第十七晶体管的源极以及所述第十八晶体管的源极均电性连接于所述第二直流低电平信号；
    所述第十晶体管的栅极、所述第十一晶体管的栅极、所述第十二晶体管的漏极、所述第十三晶体管的漏极、所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十八晶体管的栅极均电性连接；
    所述第十晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的栅极均电性连接于所述第一节点；
    所述第十晶体管的源极以及所述第十一晶体管的漏极均电性连接于所述第二节点；
    所述第十二晶体管的栅极、所述第十四晶体管的漏极以及所述第十五晶体管的漏极均电性连接；
    所述第十六晶体管的漏极电性连接于所述本级级传信号；所述第十七晶体管的漏极以及所述第十八晶体管的漏极均电性连接于所述本级扫描信号。
  16. 根据权利要求8所述的GOA电路，其中，所述第二直流低电平信号的电位大于所述第一直流低电平信号的电位。
  17. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、下传模块、第一上拉模块、第二上拉模块、反馈模块、下拉模块、下拉控制模块、第一自举电容以及第二自举电容；
    所述上拉控制模块接入上一级级传信号以及第一时钟信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点以及所述第二节点；
    所述下传模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第一上拉模块接入所述第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述第二上拉模块接入第三时钟信号，并电性连接于第三节点以及所述第一节点，用于在所述第一节点的电位控制下，将所述第三时钟信号输出至所述第三节点；
    所述反馈模块电性连接于所述本级级传信号、所述本级扫描信号以及所述第二节点，用于在所述本级级传信号的控制下将所述本级扫描信号的电位反馈至所述第二节点；
    所述下拉模块接入下一级级传信号、第一直流低电平信号以及第二直流低电平信号，并电性连接于所述第一节点、所述第二节点以及所述第三节点，用于在所述下一级级传信号的控制下将所述第一直流低电平信号输出至所述第一节点以及所述第二节点，以及在所述下一级级传信号的控制下将所述第二直流低电平信号输出至所述第三节点；
    所述下拉控制模块接入直流高电平信号、所述第一直流低电平信号以及所述第二直流低电平信号，并电性连接于所述第一节点、所述第二节点、所述本级级传信号以及所述本级扫描信号，用于将所述第一节点的电位、所述第二节点的电位以及所述本级级传信号的电位下拉至所述第一直流低电平信号的电位，以及将所述本级扫描信号的电位下拉至所述第二直流低电平信号的电位；
    所述第一自举电容的第一端电性连接于所述第一节点，所述第一自举电容的第二端电性连接于所述本级扫描信号；
    所述第二自举电容的第一端电性连接于所述第一节点，所述第二自举电容的第二端电性连接于所述第三节点。
  18. 根据权利要求17所述的显示面板，其中，所述上拉控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管以及所述第二晶体管的栅极均电性连接于所述第一时钟信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极以及所述第二晶体管的源极均电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第一节点。
  19. 根据权利要求17所述的显示面板，其中，所述下传模块包括：第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第二时钟信号，所述第三晶体管的漏极电性连接于所述本级级传信号。
  20. 根据权利要求17所述的显示面板，其中，所述第一上拉模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级扫描信号。
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