WO2020155904A1 - 阵列基板及其控制方法、制造方法、显示面板、显示装置 - Google Patents

阵列基板及其控制方法、制造方法、显示面板、显示装置 Download PDF

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Publication number
WO2020155904A1
WO2020155904A1 PCT/CN2019/126336 CN2019126336W WO2020155904A1 WO 2020155904 A1 WO2020155904 A1 WO 2020155904A1 CN 2019126336 W CN2019126336 W CN 2019126336W WO 2020155904 A1 WO2020155904 A1 WO 2020155904A1
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transistor
substrate
substrate electrode
electrode
voltage
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PCT/CN2019/126336
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English (en)
French (fr)
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王丽
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京东方科技集团股份有限公司
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Priority to US16/905,851 priority Critical patent/US11605684B2/en
Publication of WO2020155904A1 publication Critical patent/WO2020155904A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate and its control method, manufacturing method, display panel, and display device.
  • a thin film transistor array For an actively driven display panel, a thin film transistor array (TFT) is usually arranged on the array substrate. Whether the TFT is in normal working condition is very important for the display effect. Among them, the threshold voltage of the TFT is an important factor that affects the working state of the TFT. However, in the prior art, once a TFT is manufactured, its threshold voltage is basically fixed, and it is difficult to adjust its threshold voltage subsequently.
  • an array substrate including:
  • a first transistor arranged in the display area of the array substrate
  • a second transistor provided in the non-display area of the array substrate.
  • a substrate electrode, the substrate electrode is arranged on a side of at least one of the first transistor and the second transistor away from the light emitting direction,
  • the substrate electrode is used to adjust the threshold voltage of at least one of the first transistor and the second transistor.
  • the absolute value of the threshold voltage of the first transistor is not equal to the absolute value of the threshold voltage of the second transistor.
  • the substrate electrode includes:
  • a first substrate electrode provided on a side of the first transistor away from the light emitting direction
  • the first substrate electrode is connected to a first regulating voltage
  • the second substrate electrode is connected to a second regulating voltage
  • the first regulating voltage and the second regulating voltage have different values.
  • the first regulation voltage is related to the threshold voltage of the first transistor
  • the second regulation voltage is related to the threshold voltage of the second transistor
  • the first substrate electrode is a planar electrode, the number of the first transistors is multiple, and the projections of the plurality of first transistors on the plane where the first substrate electrode is located are all located on the first substrate electrode.
  • the number of the first transistors is multiple, and the projections of the plurality of first transistors on the plane where the first substrate electrode is located are all located on the first substrate electrode.
  • the second substrate electrode is a planar electrode, the number of the second transistors is multiple, and the projections of the plurality of second transistors in the plane where the second substrate electrode is located are all located on the second substrate electrode Inside.
  • the number of the first substrate electrodes is multiple, the plurality of first substrate electrodes are arranged in an array, the number of the first transistors is multiple, and the number of the first transistor arrays is multiple.
  • the projections of the plurality of first transistors in the plane where the first substrate electrode is located are located in the plurality of first substrate electrodes in a one-to-one correspondence; and/or,
  • the number of the second substrate electrodes is multiple, the plurality of second substrate electrodes are arranged in an array, the number of the second transistors is multiple, and the number of the second transistor arrays is multiple.
  • the projections of the second transistors on the plane where the second substrate electrodes are located are located in the plurality of second substrate electrodes in a one-to-one correspondence.
  • the first transistor includes a gate, and a projection of the gate of the first transistor in a plane where the first substrate electrode is located is in the first substrate electrode; and/or,
  • the second transistor includes a gate, and a projection of the gate of the second transistor in a plane where the second substrate electrode is located is in the second substrate electrode.
  • the array substrate includes a base substrate and a buffer layer provided on the base substrate, each of the first transistor and the second transistor includes an active layer, and the active layer Located on the side of the buffer layer away from the base substrate,
  • the first substrate electrode and the second substrate electrode are both located on a side of the buffer layer close to the substrate substrate.
  • a part of the buffer layer is located between the first substrate electrode and the second substrate electrode, so that there is an open circuit between the first substrate electrode and the second substrate electrode.
  • each of the first transistor and the second transistor includes an active layer, and the active layer of each of the first transistor and the second transistor is in the plane of the substrate electrode The projection of is located in the substrate electrode, so that the substrate electrode can prevent light incident from the back of the array substrate from irradiating the active layer.
  • the array substrate further includes a light-shielding layer, wherein the light-shielding layer is used to prevent light incident from the back of the array substrate from irradiating the active of each of the first transistor and the second transistor.
  • Layer wherein the substrate electrode and the light shielding layer are located in the same layer.
  • a display panel including the array substrate as described above.
  • a display device including the array substrate as described above.
  • a driving voltage is provided to the first transistor and the second transistor, and when the substrate electrode is provided on the side of one of the first transistor and the second transistor away from the light emission direction, the driving is set The voltage is equal to the target threshold voltage of one of the first transistor and the second transistor that is not provided with the substrate electrode, and an adjustment voltage is provided to the substrate electrode so that the first transistor and the One of the second transistors provided with the substrate electrode operates at its target threshold voltage; the case where the substrate electrode is provided on both sides of the first transistor and the second transistor away from the light emission direction
  • a first adjusted voltage is provided to the substrate electrode disposed on the side of the first transistor away from the light-emitting direction to make the first transistor work at its target threshold voltage, and to The substrate electrode on the side of the second transistor away from the light emitting direction provides a second regulating voltage to make the second transistor work under its target threshold voltage.
  • the value of the first regulation voltage is different from the value of the second regulation voltage.
  • a method for manufacturing an array substrate including:
  • the substrate electrode is located on a side of at least one of the first transistor and the second transistor away from the light emitting direction, and is used to adjust the threshold of at least one of the first transistor and the second transistor Voltage.
  • the forming the substrate electrode on the substrate substrate includes:
  • a light shielding layer is formed on the base substrate, and the light shielding layer is used to shield light incident from the back of the array substrate to prevent the light from irradiating the active layer in the first transistor and the second transistor ;
  • the substrate electrode is formed in the light shielding layer through a patterning process.
  • the forming the substrate electrode on the substrate substrate includes:
  • a light shielding layer and a substrate electrode are formed in the metal thin film through a patterning process; the light shielding layer is used to shield light incident from the back of the array substrate to prevent the light from irradiating the first transistor and the second transistor The active layer in.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the structure of an array substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic plan view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic flowchart of a method for controlling an array substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the disclosure.
  • an array substrate which can solve the problem caused by the difference in threshold voltage to a certain extent.
  • the array substrate may include a first transistor 11 provided in the display area 10 of the array substrate and a second transistor 21 provided in the non-display area 20 of the array substrate; the array substrate may also include a substrate Bottom electrode 31/32.
  • the substrate electrode 31 is arranged on the side of the first transistor 11 away from the light emitting direction, and is used to adjust the threshold voltage of the first transistor 11; as shown in FIG. 2, the substrate The electrode 32 is arranged on the side of the second transistor 21 away from the light emitting direction, and is used to adjust the threshold voltage of the second transistor 21.
  • the display area 10 may refer to a pixel area of an array substrate
  • the non-display area 20 may refer to a GOA area (Gate Driver on Array) of the array substrate.
  • the threshold voltage of the transistor at the corresponding position of the substrate electrode 31/32 can be adjusted based on the principle of the contrast effect, so that the transistor can work In an ideal state.
  • the so-called offset effect can be understood as follows: When the transistor is working, after the channel (inversion layer) appears in the active layer, although the thickness of the depletion layer under the channel reaches the maximum (at this time, even if the gate voltage increases Large, the thickness of the depletion layer will not increase), but the contrast voltage (that is, the adjustment voltage applied to the substrate electrode 31/32) is the reverse voltage directly applied between the source and the substrate , It can further broaden the thickness of the depletion layer of the field induction junction, and cause the space charge surface density in it to increase, thereby increasing the threshold voltage of the transistor.
  • the substrate electrode is provided on the side of the transistor away from the light emission direction, so that the substrate electrode can be used to adjust the threshold voltage of the transistor above it based on the principle of the contrast effect. In this way, even if the transistor's own manufacturing process causes its threshold voltage to deviate, it can be adjusted through the substrate electrode to make it work in an ideal state.
  • the absolute value of the threshold voltage Vth of a generally larger TFT is obviously greater than the absolute value of the Vth of a smaller TFT.
  • the size of the TFT is usually smaller than that of the TFT located in the GOA area, which makes the threshold voltage of the two differ greatly. The problem caused by this is that the process control is difficult, and the Vth requirement of the pixel circuit and the GOA circuit cannot be taken into account at the same time, resulting in poor circuit function or even failure.
  • the threshold voltages of the two are very different. The problem is that process control is difficult, and the Vth requirements of the Pixel circuit and the GOA circuit cannot be taken into account at the same time, resulting in poor circuit function or even failure.
  • the array substrate includes a first substrate electrode 31 disposed on a side of the first transistor 11 away from the light emitting direction, and a first substrate electrode 31 disposed on the first transistor 11
  • the second substrate electrode 32 on one side of the two transistors 21 away from the light emitting direction.
  • the first substrate electrode 31 is used to adjust the threshold voltage of the first transistor 11;
  • the second substrate electrode 32 is used to adjust the threshold voltage of the second transistor 21.
  • the first substrate electrode 31 and the second substrate electrode 32 are open circuit, that is, the design is disconnected between the two, so that they can be connected to different regulating voltages, so that the first transistor 11 and the second The transistor 21 performs threshold voltage adjustment.
  • the first transistor 11 may be a driving transistor of a Pixel circuit
  • the second transistor 21 may be a driving transistor of a GOA circuit.
  • the threshold voltages of the first transistor 11 and the second transistor 21 can be adjusted by supplying voltage to the substrate electrode, so that the threshold voltage can be adjusted according to requirements.
  • Adjust the Vth value of the TFT device in the pixel area and the GOA area so that the Pixel circuit and the GOA circuit are in their respective suitable working conditions, which solves the problem of the threshold voltage mismatch between the small-size TFT and the large-size TFT, which is conducive to process control. It also solves the problem of inconsistency between the optimal operating point (such as the ideal threshold voltage Vth) of the Pixel circuit and the GOA circuit.
  • the substrate electrode 31 in the display area and the substrate electrode 32 in the non-display area in the array substrate need to be designed to be disconnected to provide voltages respectively.
  • the substrate electrode 31 can be connected to a first regulating voltage
  • the substrate electrode 32 can be connected to a second regulating voltage
  • the first regulating voltage and the second regulating voltage have different values.
  • the first regulation voltage is related to the threshold voltage of the first transistor 11
  • the second regulation voltage is related to the threshold voltage of the second transistor 21.
  • the substrate electrode 31 in the display area and the substrate electrode 32 in the non-display area respectively lead out signal lines to connect to external circuits, such as pins of an external drive chip IC or flexible circuit board FPC (refer to FIG. 3).
  • the threshold voltages of the TFTs in these two areas are adjusted to appropriate values to satisfy the normal operation of the circuit.
  • the array substrate includes a base substrate 111, a first base electrode 31, a buffer layer 112, an active layer 113, a gate insulating layer 114, and a gate set from bottom to top.
  • the active layer 113, the gate insulating layer 114, the gate 115, the interlayer dielectric layer 116 and the source and drain 117 constitute the first transistor 11, and the first substrate electrode 31 is located away from the light emitting direction of the first transistor 11
  • One side is connected to an external circuit through a via 311 so as to be provided with a regulated voltage.
  • the second substrate electrode 32 is connected to an external circuit through a via 321 to be provided with a regulated voltage, as shown in FIG. 2 and FIG. 4.
  • the projection of the gate 115 of the first transistor 11 in the plane of the substrate electrode 31 is located in the substrate electrode 31.
  • the projection of the gate of the second transistor 21 in the plane of the substrate electrode 32 is located in the substrate electrode 32. In this way, it is advantageous to adjust the threshold voltage of the first transistor based on the contrast effect.
  • the projected area of the substrate electrode on the base substrate may be larger than the projected area of the gate of the transistor on the base substrate.
  • the projections of the active layer, source and drain of the transistor on the base substrate can all fall within the projections of the base electrode on the base substrate.
  • a part of the buffer layer 112 is located between the substrate electrode 31 and the substrate electrode 32, so that the substrate electrode 31 and the substrate electrode 32 are between open circuit.
  • the substrate electrode 31/32 can also be used as a light shielding layer of the array substrate.
  • the projection of the active layer of each of the first transistor 11 and the second transistor 21 in the plane of the substrate electrode is located in the substrate electrode, so that the substrate electrode 31/32
  • the light incident from the back of the array substrate can be prevented from irradiating the active layer, so as to prevent the active layer from generating photo-generated carriers due to illumination, which affects device performance.
  • the light-shielding layer is usually made of metal, such as metal molybdenum (Mo). In this way, the use of metal materials to make the substrate electrode and the light-shielding layer at the same time can save materials and processes. It can also achieve the two effects of shading and threshold voltage adjustment at the same time. .
  • the array substrate may further include a light shielding layer for shielding light incident from the back of the array substrate to prevent it from irradiating the active layer of the first transistor and the second transistor, Prevent the active layer from generating photo-generated carriers due to light, which affects device performance.
  • the substrate electrode 31/32 and the light shielding layer may be located in the same layer. In this way, the substrate electrode and the light shielding layer are in the same layer, which can reduce the overall thickness of the array substrate.
  • the substrate electrode and the light-shielding layer can be manufactured through a patterning process.
  • the expression "located on the same layer” can include that two film layers, components or elements can be formed by a patterning process, or that the surfaces of the two film layers, components or elements close to the base substrate are both the same Layer contact, etc.
  • the first substrate electrode 31 is directly arranged on the base substrate 111, and usually the light-shielding layer is also directly arranged on the base substrate 111. In this way, the light-shielding layer can be used to simultaneously fabricate the substrate. An electrode, thereby obtaining a first substrate electrode 31 that also has a light-shielding effect. The same is true for the second substrate electrode 32.
  • the first substrate electrode 31 and the second substrate electrode 32 are planar; the number of the first transistors 11 is multiple, and the plurality of first transistors 11 are on the first substrate.
  • the projections in the plane where the bottom electrode 31 is located are all located in the first substrate electrode 31, and/or, the number of the second transistors 21 is multiple, and the multiple second transistors 21 are on the second substrate electrode.
  • the projections in the plane 32 are all located in the second substrate electrode 32.
  • planar first substrate electrode 31 adjusts the threshold voltage of the first transistor 11, it can be adjusted with reference to the average value or the center point value of the threshold voltage difference of each first transistor 11, thereby ensuring As a whole, each first transistor 11 can be in the best working state as much as possible; in the same way, the planar second substrate electrode 32 can also adjust the threshold voltage of the second transistor 21 in this way.
  • the number of the first substrate electrode 31 and the number of the second substrate electrode 32 is multiple, and the plurality of the first substrate electrodes 31 are arranged in an array; the first transistor 11 The number is multiple and arranged in an array, the projections of the multiple first transistors 11 in the plane where the first substrate electrode is located are located in the multiple first substrate electrodes 31 in a one-to-one correspondence, and/or, The number of the second transistors 21 is multiple, and the projections of the multiple second transistors 21 on the plane where the second substrate electrode is located are located in the multiple second substrate electrodes 32 in a one-to-one correspondence.
  • each substrate electrode can be provided with a corresponding regulating voltage, so that each transistor works in an optimal state.
  • the substrate electrode does not necessarily have a light-shielding function, and whether it needs to have a light-shielding function is determined according to product requirements. When the light-shielding function needs to be realized at the same time, such The design makes the two processes compatible.
  • the substrate electrode can not only be used as a light-shielding layer, for a dual-gate TFT, the substrate electrode can also be used as the bottom gate of a dual-gate TFT; or the substrate electrode can also be directly used as a signal wiring Use; these specific embodiments all belong to the protection scope of the present disclosure, and are not required and limited here.
  • the substrate electrodes added in the embodiments of the present disclosure may also be compatible with existing processes, for example, may be integrated with optical fingerprint recognition technology.
  • the optical fingerprint identification technology usually requires an optical sensor to be placed on the back of the screen. To meet the identification requirements of the sensor, a number of arrays of light-transmitting holes need to be formed on the screen to collect fingerprint information. At the same time, in order to prevent stray light from entering If the image is blurred, it is necessary to perform shading treatment in other positions. At this time, the substrate electrode can play such a shading function.
  • the substrate electrode can also protect the TFT from light injection affecting the performance of the TFT.
  • the design of the substrate electrode of the present disclosure is not only compatible with fingerprint recognition technology, but also compatible with infrared sensing, facial recognition and other technologies. These compatible designs belong to the protection scope of the present disclosure, and no rigid requirements are made here.
  • a display panel which can solve the problem caused by the difference in threshold voltage to a certain extent.
  • the display panel includes any embodiment or arrangement or combination of the above-mentioned array substrate.
  • the substrate electrode is provided on the side of the transistor away from the light emitting direction, so that the substrate electrode can be used to adjust the threshold voltage of the transistor above it based on the principle of the contrast effect. In this way, even if the transistor's own manufacturing process causes its threshold voltage to deviate, it can be adjusted through the substrate electrode to make it work in an ideal state.
  • a display device which can solve the problem caused by the difference in threshold voltage to a certain extent.
  • the display device includes any embodiment or arrangement and combination of the above-mentioned array substrate.
  • the display device in this embodiment may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc.
  • the substrate electrode is arranged on the side of the transistor away from the light emitting direction, so that the substrate electrode can be used to adjust the threshold voltage of the transistor above it based on the principle of the contrast effect;
  • the manufacturing process leads to deviations in the threshold voltage, which can also be adjusted by the substrate electrode to make it work in an ideal state.
  • the fourth aspect of the embodiments of the present disclosure proposes a control method of the array substrate, which can solve the problem caused by the difference in threshold voltage to a certain extent.
  • control method of the array substrate includes:
  • Step 41 Determine the target threshold voltage of the first transistor and the second transistor
  • Step 42 Provide a drive voltage to the first transistor and the second transistor, and set the drive when the substrate electrode is provided on one side of the first transistor and the second transistor away from the light emission direction
  • the voltage is equal to the target threshold voltage of one of the first transistor and the second transistor where the substrate electrode is not provided, and the substrate electrode is provided with an adjusted voltage so that the first transistor and the second transistor
  • One of the substrate electrodes is set to work at its target threshold voltage; in the case where the substrate electrodes are both provided on the side of the first transistor and the second transistor away from the light emission direction, according to the driving voltage , Provide a first regulated voltage to the substrate electrode on the side of the first transistor away from the light-emitting direction to make the first transistor work at its target threshold voltage, and provide the substrate electrode on the side of the second transistor away from the light-emitting direction with a first adjustment voltage.
  • the bottom electrode provides a second regulated voltage to make the second transistor work at its target threshold voltage.
  • the value of the first regulation voltage is different from the value of the second regulation voltage.
  • the first transistor is a driving transistor of a Pixel circuit
  • the second transistor is a driving transistor of a GOA circuit. Since the size (for example, the aspect ratio) of the first transistor is different from the size (for example, the aspect ratio) of the second transistor, the target threshold voltages of the first transistor and the second transistor are different.
  • the substrate electrode is provided on the side of the second transistor away from the light-emitting direction (the substrate electrode is not provided on the side of the first transistor away from the light-emitting direction)
  • the driving voltage may be set equal to the target threshold voltage of the first transistor
  • the substrate electrode may be provided with an adjustment voltage.
  • the value of the adjustment voltage at this time may be equal to the target threshold voltage of the second transistor The absolute value of the difference from the driving voltage, so that the second transistor can operate at its target threshold voltage.
  • the driving voltage may be set equal to the first transistor
  • the value of the first regulation voltage may be equal to zero, so that the first transistor operates under its target threshold voltage
  • the value of the second regulation voltage may be equal to the value of the second transistor
  • the driving voltage may be set to be equal to the average value of the target threshold voltage of the first transistor and the target threshold voltage of the second transistor.
  • the value of the first regulation voltage may be equal to the value of the first transistor.
  • the absolute value of the difference between the target threshold voltage of a transistor and the driving voltage, so that the first transistor operates under its target threshold voltage; the value of the second regulation voltage may be equal to the target threshold of the second transistor.
  • the control method of the array substrate provided by the embodiment of the present disclosure is to provide a substrate electrode on the side of the transistor away from the light emitting direction, and use the substrate electrode to adjust the threshold voltage of the transistor above it based on the principle of the contrast effect.
  • the manufacturing process leads to deviations in the threshold voltage, which can also be adjusted by the substrate electrode to make it work in an ideal state.
  • the determination of the adjustment voltage can be calculated by first inputting a preset detection voltage to the transistor and collecting the corresponding electrical signal to calculate the threshold voltage offset, and then calculating the adjustment voltage, and then adjusting the voltage Input to the corresponding substrate electrode.
  • the working state of the transistor can be detected at any time and the adjustment voltage can be dynamically adjusted. In other words, the adjustment voltage can be changed with the working state of the transistor and can be adjusted according to specific conditions.
  • a method for manufacturing the array substrate is proposed, which can solve the problem caused by the difference in threshold voltage to a certain extent.
  • the manufacturing method of the array substrate includes:
  • Step 51 forming a substrate electrode on the substrate substrate
  • Step 52 forming a first transistor in the display area, and forming a second transistor in the non-display area;
  • the substrate electrode is located on a side of at least one of the first transistor and the second transistor away from the light emitting direction, and is used to adjust the threshold of at least one of the first transistor and the second transistor Voltage.
  • the substrate electrode is provided on the side of the transistor away from the light emitting direction, so that the substrate electrode can be used to adjust the threshold voltage of the transistor above it based on the principle of the contrast effect. In this way, even if the transistor's own manufacturing process causes its threshold voltage to deviate, it can be adjusted through the substrate electrode to make it work in an ideal state.
  • the forming the substrate electrode on the base substrate includes: forming a light shielding layer on the base substrate, and the light shielding layer is used to shield light incident from the back of the array substrate to Preventing it from irradiating the active layers in the first transistor and the second transistor; and forming the substrate electrode in the light shielding layer through a patterning process.
  • the use of the light-shielding layer to fabricate the substrate electrode allows the substrate electrode to adjust the threshold voltage of the transistor and achieve the light-shielding effect, achieving two goals with one stone.
  • forming a substrate electrode on a base substrate includes: forming a metal film on the base substrate; and forming a light-shielding layer and a substrate electrode in the metal film through a patterning process;
  • the light shielding layer is used for shielding light incident from the back of the array substrate to prevent it from irradiating the active layers in the first transistor and the second transistor.
  • the substrate electrode itself is located on the side of the transistor away from the light emitting direction. If the substrate electrode has a light-shielding effect, the finished substrate electrode can replace the light-shielding layer, that is, the two can be the same object.
  • the patterning process suitable for the classic mask process usually includes photoresist coating, exposure, development, etching, photoresist stripping and other processes. Sometimes the pattern can be made without the traditional patterning process, such as the use of lift-off technology. In reality, there are situations where there is no need to use masks for composition, for example, printing, printing, and other other composition methods can be used. In other words, any process that can form a desired pattern can be called a patterning process.
  • layer formation operations include, but are not limited to (chemical phase, physical phase) deposition film formation, (magnetron) sputtering film formation, and those skilled in the art can understand that after forming each layer, Corresponding patterns can be further formed on it as required, which will not be repeated in this disclosure.
  • the source and drain electrodes and the active layer are in different layers, the thickness of the substrate is large and the manufacturing process is complicated.
  • the source electrode, drain electrode, data line and active layer can be prepared in the same layer by doping copper nitride, thereby reducing the thickness of the array substrate and simplifying the manufacture of the array substrate Craft.

Abstract

本公开公开了一种阵列基板、显示面板、显示装置以及所述阵列基板的控制方法和制造方法。所述阵列基板包括：设置在所述阵列基板的显示区域的第一晶体管；设置在所述阵列基板的非显示区域的第二晶体管；和衬底电极，所述衬底电极设置在所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，其中，所述衬底电极用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。

Description

阵列基板及其控制方法、制造方法、显示面板、显示装置
相关申请的交叉引用
本公开要求于2019年1月28日递交中国专利局的、申请号为201910080652.3的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板及其控制方法、制造方法、显示面板、显示装置。
背景技术
对于有源驱动的显示面板而言，其阵列基板上通常设置有薄膜晶体管阵列(TFT)。TFT是否处于正常工作状态，对于显示效果十分重要。其中，TFT的阈值电压就是影响TFT工作状态的一个重要因素。但是，现有技术中，TFT一旦制成，其阈值电压就基本固定，后续难以对其阈值电压进行调节。
发明内容
在一个方面，提供一种阵列基板，包括：
设置在所述阵列基板的显示区域的第一晶体管；
设置在所述阵列基板的非显示区域的第二晶体管；和
衬底电极，所述衬底电极设置在所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，
其中，所述衬底电极用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。
可选地，所述第一晶体管的阈值电压的绝对值不等于所述第二晶体管的阈值电压的绝对值。
可选地，所述衬底电极包括：
设置在所述第一晶体管远离出光方向一侧的第一衬底电极；和
设置在所述第二晶体管远离出光方向一侧的第二衬底电极，
其中，所述第一衬底电极与第二衬底电极之间为开路。
可选地，所述第一衬底电极接入第一调节电压，所述第二衬底电极接入第二调节电压，所述第一调节电压与所述第二调节电压具有不同的值。
可选地，所述第一调节电压与所述第一晶体管的阈值电压相关，所述第二调节电压与所述第二晶体管的阈值电压相关。
可选地，所述第一衬底电极为面状电极，所述第一晶体管的数量为多个，多个所述第一晶体管在第一衬底电极所在平面内的投影均位于所述第一衬底电极内；和/或，
所述第二衬底电极为面状电极，所述第二晶体管的数量为多个，多个所述第二晶体管在第二衬底电极所在平面内的投影均位于所述第二衬底电极内。
可选地，所述第一衬底电极的数量为多个，多个所述第一衬底电极阵列排布，所述第一晶体管的数量为多个，多个所述第一晶体管阵列排布，多个所述第一晶体管在第一衬底电极所在平面内的投影一一对应地位于多个所述第一衬底电极内；和/或，
所述第二衬底电极的数量为多个，多个所述第二衬底电极阵列排布，所述第二晶体管的数量为多个，多个所述第二晶体管阵列排布，多个所述第二晶体管在第二衬底电极所在平面内的投影一一对应地位于多个所述第二衬底电极内。
可选地，所述第一晶体管包括栅极，所述第一晶体管的栅极在第一衬底电极所在平面内的投影位于所述第一衬底电极内；和/或，
所述第二晶体管包括栅极，所述第二晶体管的栅极在第二衬底电极所在平面内的投影位于所述第二衬底电极内。
可选地，所述阵列基板包括衬底基板和设置在所述衬底基板上的缓冲层，所述第一晶体管和所述第二晶体管中的每一个包括有源层，所述有源层位于所述缓冲层远离所述衬底基板的一侧，
其中，所述第一衬底电极和所述第二衬底电极均位于所述缓冲层靠近所述衬底基板的一侧。
可选地，所述缓冲层的一部分位于所述第一衬底电极与所述第二衬底电极之间，以使得所述第一衬底电极与第二衬底电极之间为开路。
可选地，所述第一晶体管和所述第二晶体管中的每一个包括有源层，所述第一晶体管和所述第二晶体管中的每一个的有源层在衬底电极所在平面内的投影位于所述衬 底电极内，使得所述衬底电极能够阻止从所述阵列基板背面入射的光线照射所述有源层。
可选地，所述阵列基板还包括遮光层，其中，所述遮光层用于阻止从所述阵列基板背面入射的光线照射所述第一晶体管和所述第二晶体管中的每一个的有源层，其中，所述衬底电极与所述遮光层位于同一层。
在另一个方面，提供一种显示面板，包括如前所述的阵列基板。
在又一个方面，提供一种显示装置，包括如前所述的阵列基板。
在再一个方面，提供一种如前所述的阵列基板的控制方法，包括：
确定所述第一晶体管和所述第二晶体管的目标阈值电压；
向所述第一晶体管和第二晶体管提供驱动电压，在所述第一晶体管和所述第二晶体管中的一个的远离出光方向一侧设置有所述衬底电极的情况下，设置所述驱动电压等于所述第一晶体管和所述第二晶体管中的未设置有所述衬底电极的一个的目标阈值电压，并向所述衬底电极提供调节电压以使所述第一晶体管和所述第二晶体管中的设置有所述衬底电极的一个工作在其目标阈值电压下；在所述第一晶体管和所述第二晶体管的远离出光方向一侧均设置有所述衬底电极的情况下，根据所述驱动电压，向设置在所述第一晶体管远离出光方向一侧的衬底电极提供第一调节电压以使所述第一晶体管工作在其目标阈值电压下，并向设置在所述第二晶体管远离出光方向一侧的衬底电极提供第二调节电压以使所述第二晶体管工作在其目标阈值电压下。
可选地，所述第一调节电压的值不同于所述第二调节电压的值。
在又再一个方面，提供一种阵列基板的制造方法，包括：
在衬底基板上形成衬底电极；
在显示区域形成第一晶体管，在非显示区域形成第二晶体管；
其中，所述衬底电极位于所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。
可选地，所述在衬底基板上形成衬底电极包括：
在所述衬底基板上形成遮光层，所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止所述光线照射所述第一晶体管和所述第二晶体管中的有源层；和
通过构图工艺在所述遮光层中形成所述衬底电极。
可选地，所述在衬底基板上形成衬底电极包括：
在衬底基板上形成金属薄膜；和
通过一次构图工艺在所述金属薄膜中形成遮光层和衬底电极；所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止所述光线照射所述第一晶体管和第二晶体管中的有源层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例提供的阵列基板的结构示意图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3为本公开实施例提供的阵列基板的平面示意图；
图4为本公开实施例提供的阵列基板的结构示意图；
图5为本公开实施例提供的阵列基板的结构示意图；
图6为本公开实施例提供的阵列基板的控制方法的流程示意图；以及
图7为本公开实施例提供的阵列基板的制造方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相 连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例的第一个方面，提出了一种阵列基板，能够在一定程度上解决阈值电压差异带来的问题。
参照图1和图2，所述阵列基板可以包括设置在阵列基板的显示区域10的第一晶体管11和设置在阵列基板的非显示区域20的第二晶体管21；所述阵列基板还可以包括衬底电极31/32。如图1所示，所述衬底电极31设置在所述第一晶体管11的远离出光方向一侧，用于调整所述第一晶体管11的阈值电压；如图2所示，所述衬底电极32设置在所述第二晶体管21的远离出光方向一侧，用于调整所述第二晶体管21的阈值电压。可选的，所述显示区域10可以指阵列基板的像素区，所述非显示区域20可以指阵列基板的GOA区(Gate Driver onArray，阵列基板栅极驱动技术)。
所述阵列基板中的晶体管在工作时，通过对衬底电极31/32施加一定的调节电压，从而能够基于衬偏效应原理调整衬底电极31/32对应位置的晶体管的阈值电压，使晶体管工作在理想状态。
所谓衬偏效应可以做如下理解：晶体管工作时，在有源层中出现沟道(反型层)以后，虽然沟道下面的耗尽层厚度达到了最大(这时，栅极电压即使再增大，耗尽层厚度也不会再增大)，但是，衬偏电压(即施加在衬底电极31/32上的调节电压)是直接加在源极和衬底基板之间的反向电压，它可以使场感应结的耗尽层厚度进一步展宽，并引起其中的空间电荷面密度增加，从而使晶体管的阈值电压升高。
在本公开实施例提供的阵列基板中，通过在晶体管远离出光方向一侧设置衬底电极，从而能够基于衬偏效应原理利用所述衬底电极调节其上方的晶体管的阈值电压。这样，即使晶体管本身的制作工艺导致其阈值电压出现偏差，也可以通过衬底电极进行调整，使其工作在理想状态。
在显示面板的制作工艺中，在相同的工艺与制程条件下，一般尺寸较大的TFT的阈值电压Vth的绝对值明显比尺寸较小的TFT的Vth的绝对值更大，而位于显示区域的TFT的尺寸通常较位于GOA区域的TFT的尺寸更小，使得二者的阈值电压差异很大。这样导致的问题是工艺管控困难，无法同时兼顾像素(Pixel)电路和GOA电路的Vth的要求，造成电路功能不良，甚至失效。
特别地，在低温多晶硅有机发光二极管(LTPS OLED)显示屏设计中，通常Pixel电路中采用尺寸较小的TFT(例如，沟道的宽长比W/L＝3μm/3μm)，GOA电路中使用尺寸较大的TFT来带动负载(例如，沟道的宽长比W/L＝80μm/3μm)。这样，在相同的工艺与制程条件下，二者的阈值电压差异很大，导致的问题是工艺管控困难，无法同时兼顾Pixel电路和GOA电路的Vth的要求，造成电路功能不良，甚至失效。
因此，作为本公开的一个实施例，结合图3和图4所示，所述阵列基板包括设置在所述第一晶体管11远离出光方向一侧的第一衬底电极31以及设置在所述第二晶体管21远离出光方向一侧的第二衬底电极32。所述第一衬底电极31用于调整所述第一晶体管11的阈值电压；所述第二衬底电极32用于调整所述第二晶体管21的阈值电压。所述第一衬底电极31与第二衬底电极32之间为开路，即二者之间断开设计，使得二者可以接入不同的调节电压，从而能够分别对第一晶体管11和第二晶体管21进行阈值电压调节。
例如，所述第一晶体管11可以为Pixel电路的驱动晶体管，所述第二晶体管21可以为GOA电路的驱动晶体管。
这样，通过分别设置第一衬底电极31和第二衬底电极32，使得第一晶体管11和第二晶体管21的阈值电压均可通过对衬底电极提供电压而进行凋节，从而可以根据需求调整像素区和GOA区的TFT器件的Vth值，使Pixel电路和GOA电路都处于各自适合的工作状态，解决了小尺寸TFT与大尺寸TFT的阈值电压不匹配的问题，有利于工艺管控，同时也解决了Pixel电路与GOA电路的最佳工作点(例如理想阈值电压Vth)不一致的问题。
如图3和图4所示，所述阵列基板中显示区域的衬底电极31与非显示区域的衬底电极32需断开设计，以分别提供电压。也就是说，所述衬底电极31可以接入第一调节电压，所述衬底电极32可以接入第二调节电压，所述第一调节电压与所述第二调节电压具有不同的值。例如，所述第一调节电压与所述第一晶体管11的阈值电压相关，所述第二调节电压与所述第二晶体管21的阈值电压相关。显示区域的衬底电极31和非显示区域的衬底电极32分别引出信号线接入外部电路，例如外部驱动芯片IC或柔性电路板FPC的引脚上(参照图3)。通过设置Pixel区与GOA区的衬底电极不同的电压，将这两个区域TFT的阈值电压调节到适当的值，满足电路正常工作。
如图5所示，以显示区域为例，所述阵列基板包括由下至上设置的衬底基板111、第一衬底电极31、缓冲层112、有源层113、栅极绝缘层114、栅极115、层间介电层116和源漏极117。其中，有源层113、栅极绝缘层114、栅极115、层间介电层116和源漏极117构成第一晶体管11，所述第一衬底电极31位于第一晶体管11远离出光方向一侧并通过过孔311与外部电路连接从而被提供调节电压。同理，所述第二衬底电极32则通过过孔321与外部电路连接从而被提供调节电压，参考图2和图4所示。
例如，参照图5，所述第一晶体管11的栅极115在衬底电极31所在平面内的投影位于所述衬底电极31内。类似地，参照图4，所述第二晶体管21的栅极在衬底电极32所在平面内的投影位于所述衬底电极32内。这样，有利于基于衬偏效应调节第一晶体管的阈值电压。
需要说明的是，在本公开的实施例中，衬底电极在衬底基板上的投影的面积可以大于晶体管的栅极在衬底基板上的投影的面积。例如，晶体管的有源层、源极和漏极在衬底基板上的投影均可以落入衬底电极在衬底基板上的投影内。
结合参照图4和图5，所述缓冲层112的一部分位于所述衬底电极31与所述衬底电极32之间，以使得所述衬底电极31与所述衬底电极32之间为开路。
作为本公开的一个可选实施方式，所述衬底电极31/32还可以用作阵列基板的遮光层。例如，所述第一晶体管11和所述第二晶体管21中的每一个的有源层在衬底电极所在平面内的投影均位于所述衬底电极内，使得所述衬底电极31/32能够阻止从所述阵列基板背面入射的光线照射所述有源层，从而防止有源层因光照产生光生载流子，影响器件性能。遮光层通常采用金属制作，例如金属钼(Mo)等，这样，利用金属材料同时制作出衬底电极和遮光层，能够节省材料和工艺，还能同时实现遮光和阈值电压调节两个效果，一举两得。
可选地，所述阵列基板还可以包括遮光层，所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止其照射所述第一晶体管和第二晶体管中的有源层，防止有源层因光照产生光生载流子，影响器件性能。例如，所述衬底电极31/32可以与所述遮光层位于同一层，这样，衬底电极与遮光层共层，可以减小阵列基板的整体厚度。例如，所述衬底电极和所述遮光层可以通过一次构图工艺制得。
需要说明的是，在本文中，表述“位于同一层”可以包括两个膜层、部件或元件可以通过一次构图工艺形成，或者两个膜层、部件或元件靠近衬底基板的表面均与同一层接触等情况。
在本公开的实施例中，所述第一衬底电极31直接设置在衬底基板111上，而通常遮光层也是直接设置在衬底基板111上，这样，就可以利用遮光层同时制作衬底电极，从而得到同时具有遮光作用的第一衬底电极31。第二衬底电极32同理。
作为一个可选实施例，所述第一衬底电极31和第二衬底电极32为面状；所述第一晶体管11的数量为多个，多个所述第一晶体管11在第一衬底电极31所在平面内的投影均位于所述第一衬底电极31内，和/或，所述第二晶体管21的数量为多个，多个所述第二晶体管21在第二衬底电极32所在平面内的投影均位于所述第二衬底电极32内。
这样，面状的所述第一衬底电极31在对第一晶体管11的阈值电压进行调节时，可以参照各第一晶体管11的阈值电压差值的均值或中心点值来进行调节，从而保证整体上各第一晶体管11都能尽量处于最佳工作状态；同理，面状的所述第二衬底电极32也可以如此调节第二晶体管21的阈值电压。
作为另一个可选实施例，所述第一衬底电极31和第二衬底电极32的数量均为多个，多个所述第一衬底电极31排列为阵列；所述第一晶体管11的数量为多个且排列为阵列，多个所述第一晶体管11在第一衬底电极所在平面内的投影一一对应地位于多个所述第一衬底电极31内，和/或，所述第二晶体管21的数量为多个，多个所述第二晶体管21在第二衬底电极所在平面内的投影一一对应地位于多个所述第二衬底电极32内。
这样，由于每个晶体管都对应一个衬底电极，因此可以给每个衬底电极提供对应的调节电压，使得每个晶体管均工作在最佳状态下。
还需要说明的是，在本公开的实施例中，所述衬底电极并不一定必须具备遮光作用，是否需要具备遮光功能具体的需要根据产品需求进行确定，在需要同时实现遮光作用时，这样的设计使得二者在工艺上可以兼容。此外，所述衬底电极也不仅仅可以做遮光层，对于双栅TFT而言，所述衬底电极也可以作为双栅TFT的底栅；或者所述衬底电极还能直接作为信号走线进行使用；这些具体的实施例都属于本公开的保护范围，在此不作要求与限制。
此外，本公开实施例中增加设置的衬底电极还可以与现有工艺可以兼容，如可以与光学指纹识别技术集成。
所述光学指纹识别技术，通常需要在屏幕背面放置光学传感器，为满足传感器的识别要求，需要在屏幕上形成若干阵列的透光孔，用以采集指纹信息，与此同时，为了防止杂散光进入造成成像模糊，需要在其它位置做遮光处理，此时的衬底电极则能起到这样的遮光作用。
同时，衬底电极在屏蔽杂散光的作用之外，还可以保护TFT以免光注入影响TFT性能。
此外，本公开的衬底电极的设计，不仅可以兼容指纹识别技术，还可以与红外传感、面部识别等技术兼容，这些兼容设计均属于本公开的保护范围，在此不做硬性要求。
本公开实施例的第二个方面，提出了一种显示面板，能够在一定程度上解决阈值电压差异带来的问题。
所述显示面板包括如前所述的阵列基板的任一实施例或实施例的排列、组合。
本公开实施例提供的显示面板，通过在晶体管远离出光方向一侧设置衬底电极，从而能够基于衬偏效应原理利用所述衬底电极调节其上方的晶体管的阈值电压。这样，即使晶体管本身的制作工艺导致其阈值电压出现偏差，也可以通过衬底电极进行调整，使其工作在理想状态。
本公开实施例的第三个方面，提出了一种显示装置，能够在一定程度上解决阈值电压差异带来的问题。
所述显示装置包括如前所述的阵列基板的任一实施例或实施例的排列、组合。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的显示装置，通过在晶体管远离出光方向一侧设置衬底电极，从而能够基于衬偏效应原理利用所述衬底电极调节其上方的晶体管的阈值电压；这样，即使晶体管本身的制作工艺导致其阈值电压出现偏差，也可以通过衬底电极进行调整，使其工作在理想状态。
本公开实施例的第四个方面，提出了一种所述阵列基板的控制方法，能够在一定程度上解决阈值电压差异带来的问题。
如图6所示，所述阵列基板的控制方法包括：
步骤41：确定所述第一晶体管和所述第二晶体管的目标阈值电压；
步骤42：向所述第一晶体管和第二晶体管提供驱动电压，在所述第一晶体管和第二晶体管中的一个远离出光方向一侧设置有所述衬底电极的情况下，设置所述驱动电压等于所述第一晶体管和第二晶体管中的未设置所述衬底电极的一个的目标阈值电压，并向所述衬底电极提供调节电压以使所述第一晶体管和第二晶体管中的设置所述衬底电极的一个工作在其目标阈值电压下；在所述第一晶体管和所述第二晶体管远离出光方向一侧均设置有所述衬底电极的情况下，根据所述驱动电压，向所述第一晶体管远离出光方向一侧的衬底电极提供第一调节电压以使所述第一晶体管工作在其目标阈值电压下，并向所述第二晶体管远离出光方向一侧的衬底电极提供第二调节电压以使所述第二晶体管工作在其目标阈值电压下。
在本公开的实施例中，所述第一调节电压的值不同于所述第二调节电压的值。
例如，所述第一晶体管为Pixel电路的驱动晶体管，所述第二晶体管为GOA电路的驱动晶体管。由于第一晶体管的尺寸(例如宽长比)不同于第二晶体管的尺寸(例如宽长比)，所以所述第一晶体管和所述第二晶体管的目标阈值电压不同。
例如，在上述步骤42中，在所述第二晶体管的远离出光方向一侧设置有所述衬底电极(所述第一晶体管的远离出光方向一侧未设置有所述衬底电极)的情况下，可以设置所述驱动电压等于所述第一晶体管的目标阈值电压，并向所述衬底电极提供调节电压，例如，此时的调节电压的值可以等于所述第二晶体管的目标阈值电压与所述驱动电压的差的绝对值，以使所述第二晶体管可以工作在其目标阈值电压下。
再例如，在上述步骤42中，在所述第一晶体管和所述第二晶体管远离出光方向一侧均设置有所述衬底电极的情况下，可以设置所述驱动电压等于所述第一晶体管的目标阈值电压，此时，所述第一调节电压的值可以等于零，以使得所述第一晶体管工作在其目标阈值电压下；所述第二调节电压的值可以等于所述第二晶体管的目标阈值电压与所述驱动电压的差的绝对值，以使所述第二晶体管可以工作在其目标阈值电压下。可选地，可以设置所述驱动电压等于所述第一晶体管的目标阈值电压和所述第二晶体管的目标阈值电压的平均值，此时，所述第一调节电压的值可以等于所述第一晶体管的目标阈值电压与所述驱动电压的差的绝对值，以使得所述第一晶体管工作在其目标 阈值电压下；所述第二调节电压的值可以等于所述第二晶体管的目标阈值电压与所述驱动电压的差的绝对值，以使所述第二晶体管可以工作在其目标阈值电压下。
本公开实施例提供的阵列基板的控制方法，通过在晶体管远离出光方向一侧设置衬底电极，并基于衬偏效应原理利用所述衬底电极调节其上方的晶体管的阈值电压，即使晶体管本身的制作工艺导致其阈值电压出现偏差，也可以通过衬底电极进行调整，使其工作在理想状态。
需要说明的是，这里，所述调节电压的确定，可以通过先向晶体管输入预设检测电压并采集相应的电信号来计算得到其阈值电压的偏移量，然后计算调节电压，再将调节电压输入到对应的衬底电极中。此外，在调节过程中还可以随时检测晶体管的工作状态并动态调整调节电压，换言之，调节电压可以是随晶体管的工作状态而变化的，可以根据具体情况进行调整。
本公开实施例的第五个方面，提出了一种所述阵列基板的制造方法，能够在一定程度上解决阈值电压差异带来的问题。
如图7所示，所述阵列基板的制造方法包括：
步骤51：在衬底基板上形成衬底电极；
步骤52：在显示区域形成第一晶体管，在非显示区域形成第二晶体管；
其中，所述衬底电极位于所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。
本公开实施例提供的阵列基板的制造方法，通过在晶体管远离出光方向一侧设置衬底电极，从而能够基于衬偏效应原理利用所述衬底电极调节其上方的晶体管的阈值电压。这样，即使晶体管本身的制作工艺导致其阈值电压出现偏差，也可以通过衬底电极进行调整，使其工作在理想状态。
作为本公开的一个实施例，所述在衬底基板上形成衬底电极包括：在所述衬底基板上形成遮光层，所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止其照射所述第一晶体管和第二晶体管中的有源层；以及，通过构图工艺在所述遮光层中形成所述衬底电极。这样，利用遮光层制作衬底电极，可以使衬底电极既可调节晶体管的阈值电压又可以实现遮光效果，一举两得。
作为本公开的另一个实施例，在衬底基板上形成衬底电极，包括：在衬底基板上形成金属薄膜；以及，通过一次构图工艺在所述金属薄膜中形成遮光层和衬底电极； 所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止其照射所述第一晶体管和第二晶体管中的有源层。
实际上，衬底电极本身就位于晶体管远离出光方向一侧，如果衬底电极具有遮光作用，则制作完成的衬底电极就能代替遮光层工作，亦即，二者可以是同一对象。
需要说明的是，形成薄膜通常有沉积、涂敷、溅射等多种方式。适用于经典掩膜版(mask)过程的构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。有时候不需要传统的构图工艺即可制作图案，比如利用离地剥离技术。现实中存在无需采用mask进行构图的情况，比如可以为打印、印刷等更多其他的构图方式。换言之，只要可以形成所需的图案的工艺都可以称为构图工艺。
需要说明的是，上述形成层的操作，包括但不仅限于(化学相、物理相)沉积成膜、(磁控)溅射成膜，并且本领域技术人员可以理解，在形成每个层之后，可以根据需要在其上进一步形成相应的图案，本公开对此不再赘述。
以上结合附图详细说明了本公开的技术方案，考虑到现有技术中，源漏极和有源层处于不同层，使得基板厚度较大，制作工艺复杂。通过本申请的技术方案，可以通过对氮化铜进行掺杂处理，将源极、漏极、数据线和有源层制备在同一层中，从而减小阵列基板的厚度，简化阵列基板的制作工艺。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开中，术语“第一”、“第二”、“第三”、“第四”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
所属领域的普通技术人员应当理解：以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种阵列基板，包括：
    设置在所述阵列基板的显示区域的第一晶体管；
    设置在所述阵列基板的非显示区域的第二晶体管；和
    衬底电极，所述衬底电极设置在所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，
    其中，所述衬底电极用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。
  2. 根据权利要求1所述的阵列基板，其中，所述第一晶体管的阈值电压的绝对值不等于所述第二晶体管的阈值电压的绝对值。
  3. 根据权利要求2所述的阵列基板，其中，所述衬底电极包括：
    设置在所述第一晶体管远离出光方向一侧的第一衬底电极；和
    设置在所述第二晶体管远离出光方向一侧的第二衬底电极，
    其中，所述第一衬底电极与第二衬底电极之间为开路。
  4. 根据权利要求3所述的阵列基板，其中，所述第一衬底电极接入第一调节电压，所述第二衬底电极接入第二调节电压，所述第一调节电压与所述第二调节电压具有不同的值。
  5. 根据权利要求4所述的阵列基板，其中，所述第一调节电压与所述第一晶体管的阈值电压相关，所述第二调节电压与所述第二晶体管的阈值电压相关。
  6. 根据权利要求3-5中任一项所述的阵列基板，其中，所述第一衬底电极为面状电极，所述第一晶体管的数量为多个，多个所述第一晶体管在第一衬底电极所在平面内的投影均位于所述第一衬底电极内；和/或，
    所述第二衬底电极为面状电极，所述第二晶体管的数量为多个，多个所述第二晶体管在第二衬底电极所在平面内的投影均位于所述第二衬底电极内。
  7. 根据权利要求3-5中任一项所述的阵列基板，其中，所述第一衬底电极的数量为多个，多个所述第一衬底电极阵列排布，所述第一晶体管的数量为多个，多个所述第一晶体管阵列排布，多个所述第一晶体管在第一衬底电极所在平面内的投影一一对应地位于多个所述第一衬底电极内；和/或，
    所述第二衬底电极的数量为多个，多个所述第二衬底电极阵列排布，所述第二晶体管的数量为多个，多个所述第二晶体管阵列排布，多个所述第二晶体管在第二衬底电极所在平面内的投影一一对应地位于多个所述第二衬底电极内。
  8. 根据权利要求3-5中任一项所述的阵列基板，其中，所述第一晶体管包括栅极，所述第一晶体管的栅极在第一衬底电极所在平面内的投影位于所述第一衬底电极内；和/或，
    所述第二晶体管包括栅极，所述第二晶体管的栅极在第二衬底电极所在平面内的投影位于所述第二衬底电极内。
  9. 根据权利要求3-5中任一项所述的阵列基板，其中，所述阵列基板包括衬底基板和设置在所述衬底基板上的缓冲层，所述第一晶体管和所述第二晶体管中的每一个包括有源层，所述有源层位于所述缓冲层远离所述衬底基板的一侧，
    其中，所述第一衬底电极和所述第二衬底电极均位于所述缓冲层靠近所述衬底基板的一侧。
  10. 根据权利要求9所述的阵列基板，其中，所述缓冲层的一部分位于所述第一衬底电极与所述第二衬底电极之间，以使得所述第一衬底电极与第二衬底电极之间为开路。
  11. 根据权利要求1-5中任一项所述的阵列基板，其中，所述第一晶体管和所述第二晶体管中的每一个包括有源层，所述第一晶体管和所述第二晶体管中的每一个的有源层在衬底电极所在平面内的投影位于所述衬底电极内，使得所述衬底电极能够阻止从所述阵列基板背面入射的光线照射所述有源层。
  12. 根据权利要求1-5中任一项所述的阵列基板，还包括遮光层，其中，所述遮光层用于阻止从所述阵列基板背面入射的光线照射所述第一晶体管和所述第二晶体管中的每一个的有源层，
    其中，所述衬底电极与所述遮光层位于同一层。
  13. 一种显示面板，包括如权利要求1-12中任一项所述的阵列基板。
  14. 一种显示装置，包括如权利要求1-12中任一项所述的阵列基板。
  15. 一种如权利要求1-12中任一项所述的阵列基板的控制方法，包括：
    确定所述第一晶体管和所述第二晶体管的目标阈值电压；
    向所述第一晶体管和第二晶体管提供驱动电压，在所述第一晶体管和所述第二晶体管中的一个的远离出光方向一侧设置有所述衬底电极的情况下，设置所述驱动电压等于所述第一晶体管和所述第二晶体管中的未设置有所述衬底电极的一个的目标阈值电压，并向所述衬底电极提供调节电压以使所述第一晶体管和所述第二晶体管中的设置有所述衬底电极的一个工作在其目标阈值电压下；在所述第一晶体管和所述第二晶体管的远离出光方向一侧均设置有所述衬底电极的情况下，根据所述驱动电压，向设置在所述第一晶体管远离出光方向一侧的衬底电极提供第一调节电压以使所述第一晶体管工作在其目标阈值电压下，并向设置在所述第二晶体管远离出光方向一侧的衬底电极提供第二调节电压以使所述第二晶体管工作在其目标阈值电压下。
  16. 一种阵列基板的制造方法，包括：
    在衬底基板上形成衬底电极；
    在显示区域形成第一晶体管，在非显示区域形成第二晶体管；
    其中，所述衬底电极位于所述第一晶体管和所述第二晶体管中的至少一个的远离出光方向一侧，用于调整所述第一晶体管和所述第二晶体管中的至少一个的阈值电压。
  17. 根据权利要求16所述的制造方法，其中，所述在衬底基板上形成衬底电极包括：
    在所述衬底基板上形成遮光层，所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止所述光线照射所述第一晶体管和所述第二晶体管中的有源层；和
    通过构图工艺在所述遮光层中形成所述衬底电极。
  18. 根据权利要求16所述的制造方法，其中，所述在衬底基板上形成衬底电极包括：
    在衬底基板上形成金属薄膜；和
    通过一次构图工艺在所述金属薄膜中形成遮光层和衬底电极；所述遮光层用于遮挡从所述阵列基板背面入射的光线，以防止所述光线照射所述第一晶体管和第二晶体管中的有源层。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109768053B (zh) * 2019-01-28 2021-12-28 京东方科技集团股份有限公司 阵列基板及其控制方法、制造方法、显示面板、显示装置
CN110347285A (zh) * 2019-06-25 2019-10-18 武汉华星光电技术有限公司 一种显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020065A1 (en) * 2001-07-27 2003-01-30 Semiconductor Energy Semiconductor device
JP2003280034A (ja) * 2002-03-20 2003-10-02 Sharp Corp Ｔｆｔ基板およびそれを用いる液晶表示装置
CN101414436A (zh) * 2007-10-17 2009-04-22 索尼株式会社 存储元件和显示装置
CN102315278A (zh) * 2010-07-07 2012-01-11 三星移动显示器株式会社 双栅薄膜晶体管及包括双栅薄膜晶体管的oled显示装置
CN104425545A (zh) * 2013-09-10 2015-03-18 群创光电股份有限公司 显示装置
CN105785635A (zh) * 2016-01-29 2016-07-20 上海天马微电子有限公司 半反半透式阵列基板、制作方法、显示面板和显示装置
CN109768053A (zh) * 2019-01-28 2019-05-17 京东方科技集团股份有限公司 阵列基板及其控制方法、制造方法、显示面板、显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560402B1 (ko) * 2003-11-04 2006-03-14 엘지.필립스 엘시디 주식회사 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법
KR101496148B1 (ko) * 2008-05-15 2015-02-27 삼성전자주식회사 반도체소자 및 그 제조방법
JP6198434B2 (ja) * 2013-04-11 2017-09-20 株式会社半導体エネルギー研究所 表示装置及び電子機器
KR20150066365A (ko) * 2013-12-06 2015-06-16 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN105572955A (zh) * 2016-02-24 2016-05-11 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、触控面板
CN106024811B (zh) * 2016-07-14 2018-11-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示器件
CN106847834B (zh) * 2017-03-30 2019-05-10 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN106920804B (zh) 2017-04-28 2020-03-24 厦门天马微电子有限公司 一种阵列基板、其驱动方法、显示面板及显示装置
CN107092117B (zh) 2017-06-29 2019-11-12 京东方科技集团股份有限公司 显示面板及提高显示面板显示质量的方法
KR102434909B1 (ko) 2017-08-04 2022-08-19 엘지디스플레이 주식회사 박막 트랜지스터, 그의 제조방법, 및 그를 포함한 표시장치
CN107978610B (zh) 2017-11-30 2020-04-24 上海天马微电子有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制造方法
US10326420B1 (en) * 2018-03-21 2019-06-18 Globalfoundries Inc. Receiver circuits for millimeter wave devices
US10818697B2 (en) * 2018-08-06 2020-10-27 Sharp Kabushiki Kaisha Semiconductor device, display device, and method of producing semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020065A1 (en) * 2001-07-27 2003-01-30 Semiconductor Energy Semiconductor device
JP2003280034A (ja) * 2002-03-20 2003-10-02 Sharp Corp Ｔｆｔ基板およびそれを用いる液晶表示装置
CN101414436A (zh) * 2007-10-17 2009-04-22 索尼株式会社 存储元件和显示装置
CN102315278A (zh) * 2010-07-07 2012-01-11 三星移动显示器株式会社 双栅薄膜晶体管及包括双栅薄膜晶体管的oled显示装置
CN104425545A (zh) * 2013-09-10 2015-03-18 群创光电股份有限公司 显示装置
CN105785635A (zh) * 2016-01-29 2016-07-20 上海天马微电子有限公司 半反半透式阵列基板、制作方法、显示面板和显示装置
CN109768053A (zh) * 2019-01-28 2019-05-17 京东方科技集团股份有限公司 阵列基板及其控制方法、制造方法、显示面板、显示装置

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