WO2020151132A1 - 一种半导体器件的制备方法及系统 - Google Patents

一种半导体器件的制备方法及系统 Download PDF

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Publication number
WO2020151132A1
WO2020151132A1 PCT/CN2019/086766 CN2019086766W WO2020151132A1 WO 2020151132 A1 WO2020151132 A1 WO 2020151132A1 CN 2019086766 W CN2019086766 W CN 2019086766W WO 2020151132 A1 WO2020151132 A1 WO 2020151132A1
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Prior art keywords
layer
oxide
polysilicon layer
etching solution
hydrofluoric acid
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PCT/CN2019/086766
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English (en)
French (fr)
Inventor
蒙元明
闫宇
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/620,503 priority Critical patent/US11087982B2/en
Publication of WO2020151132A1 publication Critical patent/WO2020151132A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/483—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using coherent light, UV to IR, e.g. lasers
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B1/00—Single-crystal growth directly from the solid state
    • C30B1/02—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Definitions

  • This application relates to the field of semiconductor device preparation, and in particular to a method and system for preparing a semiconductor device.
  • silicon materials especially polycrystalline, are playing an increasingly important role in the semiconductor field based on characteristics such as doping.
  • the prior art generally processes amorphous silicon to obtain a polysilicon layer. At this time, there are protrusions on the surface of the polysilicon layer. These protrusions cause the surface of the polysilicon layer to be rough, and the roughness is generally between 10 nm and 20 nm. Roughness will reduce the breakdown electric field and the sudden increase in leakage current, the surface roughness will double, and the leakage current will increase by two orders of magnitude.
  • the existing polysilicon layer has the technical problem of rough surface.
  • the present application provides a method and system for manufacturing a semiconductor device to alleviate the technical problem of surface roughness existing in the existing polysilicon layer.
  • the embodiment of the application provides a method for manufacturing a semiconductor device, which includes:
  • a functional layer is prepared on the surface of the polysilicon layer obtained by etching to obtain a semiconductor device.
  • the forming an oxide layer on the surface of the polysilicon layer includes: using a chemical vapor deposition method to deposit an oxide on the surface of the polysilicon layer to form the oxide layer.
  • the depositing oxide on the surface of the polysilicon layer includes: depositing silicon oxide on the surface of the polysilicon layer.
  • the growing a polysilicon layer on the device layer includes: forming an amorphous silicon layer on the device layer, and processing the amorphous silicon layer by an excimer laser annealing method to form the polysilicon layer.
  • the forming an oxide layer on the surface of the polysilicon layer includes: forming an oxide layer with a thickness of 20 nanometers on the surface of the polysilicon layer.
  • the using a buffered oxide etching solution to etch the oxide layer includes: configuring a buffered oxide etching solution, and immersing the device layer on which the oxide layer is formed.
  • the buffer oxide etching solution is taken out after a preset period of time.
  • the configuring the buffered oxide etching solution includes: configuring the hydrofluoric acid buffered etching solution.
  • the configuration of the hydrofluoric acid buffered etching solution includes: mixing hydrofluoric acid, ammonium fluoride, and water to obtain the hydrofluoric acid buffered etching solution.
  • the mixing of hydrofluoric acid, ammonium fluoride and water to obtain the hydrofluoric acid buffer etching solution includes: mixing a hydrofluoric acid aqueous solution with a molar ratio of 40% and a molar ratio of 50 % Ammonium fluoride aqueous solution is mixed in a volume ratio of 1:7 to the hydrofluoric acid buffered etching solution.
  • the immersing the device layer formed with the oxide layer in the buffer oxide etching solution for a preset period of time and then taking it out includes: removing the device layer formed with the oxide layer Soak in the buffer oxide etching solution for 2 seconds and then take it out.
  • This application provides a semiconductor device manufacturing system, which includes:
  • the growth component is used to grow a polysilicon layer on the device layer
  • the etching component is used to use a buffered oxide etching solution to etch the oxide layer;
  • the component is prepared for preparing a functional layer on the surface of the polysilicon layer obtained by etching to obtain a semiconductor device.
  • the growth member includes:
  • Amorphous silicon module used to form an amorphous silicon layer on the device layer
  • the polysilicon module is used to process the amorphous silicon layer to form the polysilicon layer.
  • the oxide member is used to deposit an oxide on the surface of the polysilicon layer using a chemical vapor deposition method to form the oxide layer, and the oxide layer covers the polysilicon layer Protrusions on the surface.
  • the oxide member is used to deposit silicon oxide on the surface of the polysilicon layer.
  • the oxide member is used to form an oxide layer with a thickness of 20 nanometers on the surface of the polysilicon layer.
  • the oxide member is used to form an oxide layer with a thickness greater than 20 nanometers on the surface of the polysilicon layer.
  • the etching member includes:
  • the immersion module is used to immerse the device layer formed with the oxide layer in the buffer oxide etching solution, and take it out after a preset period of time.
  • the configuration module is used to configure a hydrofluoric acid buffer etching solution.
  • the configuration module is used to mix hydrofluoric acid, ammonium fluoride and water to obtain the hydrofluoric acid buffered etching solution.
  • the configuration module is used to mix a hydrofluoric acid aqueous solution with a molar ratio of 40% and an ammonium fluoride aqueous solution with a molar ratio of 50% in a volume ratio of 1:7, to The hydrofluoric acid buffered etching solution.
  • This application provides a new method and system for manufacturing a semiconductor device, which includes growing a polysilicon layer on a device layer, forming an oxide layer on the surface of the polysilicon layer, and the oxide layer covers the surface of the polysilicon layer.
  • Protrusions use a buffered oxide etching solution to etch the oxide layer; prepare a functional layer on the surface of the etched polysilicon layer to obtain a semiconductor device; based on this, the present application first applies the polysilicon layer after the polysilicon layer is obtained.
  • a protective oxide layer is formed on the surface, and then a buffer oxide etching solution is used to etch and protect the oxide film and the protrusions on the polysilicon layer surface based on its controllability, thereby reducing the protrusions on the polysilicon layer surface. It can also well protect the surface of the polysilicon layer, alleviating the technical problem of rough surface of the existing polysilicon layer.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a manufacturing process of a semiconductor device provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a semiconductor device manufacturing system provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a semiconductor device provided by an embodiment of the application.
  • the embodiments of the present application can alleviate this problem.
  • the manufacturing method of the semiconductor device includes:
  • Step 1 A polysilicon layer is grown on the device layer.
  • this step includes:
  • an amorphous silicon layer S2 is formed on the device layer
  • the amorphous silicon layer S2 is processed by a process such as an excimer laser annealing method ELA to form the polysilicon layer S3.
  • Step 2 An oxide layer is formed on the surface of the polysilicon layer.
  • this step includes:
  • an oxide is deposited on the surface of the polysilicon layer to form the oxide layer S4, and the oxide layer S4 covers the surface of the polysilicon layer S3 The protrusion S31.
  • the oxide layer S4 formed by CVD is dense and relatively dense, so that the uniformity of the etching speed can be maintained during the etching process.
  • depositing oxide on the surface of the polysilicon layer includes: depositing silicon oxide on the surface of the polysilicon layer. This is because silicon oxide has a relatively low cost and is easy to etch.
  • the forming an oxide layer on the surface of the polysilicon layer includes: forming an oxide layer with a thickness of 20 nanometers on the surface of the polysilicon layer. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • the forming an oxide layer on the surface of the polysilicon layer includes: forming an oxide layer with a thickness greater than 20 nanometers on the surface of the polysilicon layer. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • Step 3 Use a buffered oxide etching solution to etch the oxide layer.
  • this step includes:
  • the oxide layer S4 is safely etched away, exposing the polysilicon layer S3', and the protrusions S31 on the surface of the polysilicon layer S3' will be greatly reduced.
  • the configuring the buffered oxide etching solution includes: configuring the hydrofluoric acid buffered etching solution.
  • the configuration of the hydrofluoric acid buffered etching solution includes: mixing hydrofluoric acid, ammonium fluoride, and water to obtain the hydrofluoric acid buffered etching solution.
  • Hydrofluoric acid HF is the main etching solution
  • ammonium fluoride NH4F is used as a buffer.
  • NH4F is used to fix the [H+] concentration to maintain a certain etching rate.
  • the mixing of hydrofluoric acid, ammonium fluoride and water to obtain the hydrofluoric acid buffer etching solution includes: mixing a hydrofluoric acid aqueous solution with a molar ratio of 40% and a molar ratio of 50%
  • the ammonium fluoride aqueous solution is mixed in a volume ratio of 1:7 to the hydrofluoric acid buffered etching solution.
  • the etching rate of the hydrofluoric acid buffer etching solution with this ratio is 10 nanometers/sec, and the etching rate is moderate.
  • the immersing the device layer on which the oxide layer is formed in the buffer oxide etching solution for a preset period of time and then taking it out includes: placing the device layer on which the oxide layer is formed on Soak in the buffer oxide etching solution for 2 seconds and then take it out.
  • Step 4 A functional layer is prepared on the surface of the polysilicon layer obtained by etching to obtain a semiconductor device.
  • this step includes:
  • a functional layer S5 such as an insulating layer and a gate metal layer, is prepared on the surface of the polysilicon layer S3' obtained by etching to obtain a semiconductor device, such as an OLED.
  • an embodiment of the present application provides a semiconductor device manufacturing system for executing the manufacturing method shown in FIG. 1, and the manufacturing system includes:
  • the growth member 31 is used to grow a polysilicon layer on the device layer.
  • the growth member 31 includes:
  • a module to provide a device layer that needs to grow a polysilicon layer as shown in (1) in Figure 2, such as a glass substrate S1, etc.;
  • Amorphous silicon module used to form an amorphous silicon layer S2 on the device layer, as shown in Figure 2 (2);
  • the amorphous silicon layer S2 is processed by processes such as the excimer laser annealing method ELA, and as shown in (3) in FIG. 2, the polysilicon layer S3 is formed.
  • the oxide member 32 is used to form an oxide layer on the surface of the polysilicon layer.
  • the oxide member 32 is used to deposit an oxide on the surface of the polysilicon layer by CVD using a chemical vapor deposition method to form the oxide layer S4, as shown in (4) in FIG. 2,
  • the oxide layer S4 covers the protrusions 31 on the surface of the polysilicon layer S3.
  • the oxide layer S4 formed by CVD is dense and relatively dense, so that the uniformity of the etching speed can be maintained during the etching process.
  • the oxide member 32 is used to deposit silicon oxide on the surface of the polysilicon layer. This is because silicon oxide has a relatively low cost and is easy to etch.
  • the oxide member 32 is used to form an oxide layer with a thickness of 20 nanometers on the surface of the polysilicon layer. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • the oxide member 32 is used to form an oxide layer with a thickness greater than 20 nanometers on the surface of the polysilicon layer. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • the etching member 33 is used to use a buffered oxide etching solution to etch the oxide layer.
  • the etching member 33 includes:
  • the immersion module is used to immerse the device layer S1 on which the oxide layer S4 is formed in the buffer oxide etching solution A, as shown in (5) in FIG. 2, and the result is as shown in FIG. After the structure layer shown in (6), take it out.
  • the oxide layer S4 is safely etched away, exposing the polysilicon layer S3', and the protrusions 31 on the surface of the polysilicon layer S3' will be greatly reduced.
  • the configuration module is used to configure a hydrofluoric acid buffer etching solution.
  • the configuration module is used to mix hydrofluoric acid, ammonium fluoride and water to obtain the hydrofluoric acid buffered etching solution.
  • Hydrofluoric acid HF is the main etching solution
  • ammonium fluoride NH4F is used as a buffer.
  • NH4F is used to fix the hydrogen ion H+ concentration to maintain a certain etching rate.
  • the configuration module is used to mix a 40% molar ratio of hydrofluoric acid aqueous solution and a 50% molar ratio of ammonium fluoride aqueous solution in a volume ratio of 1:7 to mix the hydrogen Fluoric acid buffered etching solution.
  • the etching rate of the hydrofluoric acid buffer etching solution with this ratio is 10 nanometers/sec, and the etching speed is moderate.
  • the immersion module is used to: immerse the device layer formed with the oxide layer in the buffer oxide etching solution for 2 seconds and then take it out.
  • the preparation member 34 is used to prepare a functional layer on the surface of the polysilicon layer obtained by etching to obtain a semiconductor device.
  • the preparation member 34 is used to: after obtaining the polysilicon layer S3' as shown in (6) in FIG. 2, use a neutral solution such as water to clean the surface of the polysilicon layer S3' to remove excess hydrogen.
  • Fluoric acid buffer etching solution as shown in Figure 2 (7), a functional layer S5, such as an insulating layer and a gate metal layer, is prepared on the surface of the polysilicon layer S3' obtained by etching to obtain a semiconductor device, such as an OLED.
  • an embodiment of the present application provides a semiconductor device obtained by the manufacturing method shown in FIG. 1.
  • the semiconductor device 4 includes:
  • the device layer 41 such as a glass substrate S1, etc.
  • the polysilicon layer 42 is formed on the device layer 41, and the polysilicon layer 42 is obtained by etching the oxide layer formed on the surface of the polysilicon layer 42 using a buffered oxide etching solution;
  • the functional layer 43 is formed on the polysilicon layer 42, such as an insulating layer and a gate metal layer, to obtain a semiconductor device, such as an OLED.
  • the polysilicon layer 42 is formed by processing the amorphous silicon layer by a process such as an excimer laser annealing method ELA.
  • the oxide layer formed on the surface of the polysilicon layer 42 is formed by depositing an oxide on the surface of the polysilicon layer using chemical vapor deposition method CVD, and the oxide layer covers the polysilicon layer. Protrusions 31 on the surface of the layer.
  • the oxide layer S4 formed by CVD is dense and relatively dense, so that the uniformity of the etching speed can be maintained during the etching process.
  • the oxide layer is silicon oxide. This is because silicon oxide has a relatively low cost and is easy to etch.
  • the thickness of the oxide layer is 20 nanometers. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • the thickness of the oxide layer is greater than 20 nanometers. This is because 20 nanometer protrusions may appear on the surface of the polysilicon layer, so that the protrusions can be completely covered.
  • the polysilicon layer 42 is obtained by immersing the device layer formed with the oxide layer in the buffer oxide etching solution A for a preset period of time t and then taking it out.
  • the buffered oxide etching solution includes: a hydrofluoric acid buffered etching solution.
  • the hydrofluoric acid buffered etching solution includes: hydrofluoric acid, ammonium fluoride and water are mixed to obtain the hydrofluoric acid buffered etching solution.
  • Hydrofluoric acid HF is the main etching solution, and ammonium fluoride NH4F is used as a buffer.
  • NH4F is used to fix the [H+] concentration to maintain a certain etching rate.
  • the hydrofluoric acid buffered etching solution comprises: a hydrofluoric acid aqueous solution with a molar ratio of 40% and an ammonium fluoride aqueous solution with a molar ratio of 50% in a volume ratio of 1:7. Mix to the hydrofluoric acid buffered etching solution.
  • the etching rate of the hydrofluoric acid buffer etching solution with this ratio is 10 nanometers/sec, and the etching rate is moderate.
  • the polysilicon layer 42 is a device layer on which the oxide layer is formed, soaked in the buffer oxide etching solution for 2 seconds, and then taken out.
  • Step 4 A functional layer is prepared on the surface of the polysilicon layer obtained by etching to obtain a semiconductor device.
  • This application provides a new method and system for manufacturing a semiconductor device, which includes growing a polysilicon layer on a device layer, forming an oxide layer on the surface of the polysilicon layer, and the oxide layer covers the surface of the polysilicon layer.
  • Protrusions use a buffered oxide etching solution to etch the oxide layer; prepare a functional layer on the surface of the etched polysilicon layer to obtain a semiconductor device; based on this, the present application first applies the polysilicon layer after the polysilicon layer is obtained.
  • a protective oxide layer is formed on the surface, and then a buffer oxide etching solution is used to etch and protect the oxide film and the protrusions on the polysilicon layer surface based on its controllability, thereby reducing the protrusions on the polysilicon layer surface. It can also well protect the surface of the polysilicon layer, alleviating the technical problem of rough surface of the existing polysilicon layer.

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Abstract

本申请提供一种半导体器件的制备方法及系统，在得到多晶硅层后，先在多晶硅层表面上形成一道保护作用的氧化物层，然后利用缓冲氧化物刻蚀液，基于其可控性，蚀刻保护氧化膜和多晶硅层表面上的突起，从而起到降低多晶硅层表面突起的作用，同时也能很好的保护好多晶硅层表面，缓解了现有多晶硅层存在的表面粗糙的技术问题。

Description

一种半导体器件的制备方法及系统 技术领域
本申请涉及半导体器件制备领域，尤其涉及一种半导体器件的制备方法及系统。
 背景技术
随着技术发展，硅材料，尤其是多晶，基于掺杂等特性，在半导体领域内的作用越来越大。
现有技术一般是对非晶硅进行处理之后，得到多晶硅层，此时多晶硅层的表面存在突起，这些突起导致多晶硅层表面粗糙，其粗糙度一般在10纳米至20纳米之间，多晶硅的表面粗糙度会降低击穿电场与漏电流突增，表面粗糙度增加一倍，漏电流增加两个数量级。
即现有多晶硅层存在表面粗糙的技术问题。
 技术问题
本申请提供一种半导体器件的制备方法及系统，以缓解现有多晶硅层存在的表面粗糙的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种半导体器件的制备方法，其包括：
在器件层上生长多晶硅层；
在所述多晶硅层表面上形成氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起；
使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；
在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
在本申请的制备方法中，所述在所述多晶硅层表面上形成氧化物层包括：采用化学气相沉积法，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层。
在本申请的制备方法中，所述在所述多晶硅层表面上沉积氧化物包括：在所述多晶硅层表面上沉积氧化硅。
在本申请的制备方法中，所述在所器件层上生长多晶硅层包括：在器件层形成非晶硅层，采用准分子激光退火法处理所述非晶硅层，形成所述多晶硅层。
在本申请的制备方法中，所述在所述多晶硅层表面上形成氧化物层包括：在所述多晶硅层表面上形成20纳米厚度的氧化物层。
在本申请的制备方法中，所述使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀包括：配置缓冲氧化物刻蚀液，将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中预设时长后取出。
在本申请的制备方法中，所述配置缓冲氧化物刻蚀液包括：配置氢氟酸缓冲刻蚀液。
在本申请的制备方法中，所述配置氢氟酸缓冲刻蚀液包括：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。
在本申请的制备方法中，所述将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液包括：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。
在本申请的制备方法中，所述将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中预设时长后取出包括：将形成有所述氧化物层的器件层在所述缓冲氧化物刻蚀液中浸泡2秒后取出。
本申请提供一种半导体器件的制备系统，其包括：
生长构件，用于在器件层上生长多晶硅层；
氧化物构件，用于在所述多晶硅层表面上形成氧化物层；
蚀刻构件，用于使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；
制备构件，用于在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
在本申请的制备系统中，所述生长构件包括：
提供模块，用于提供一个需要生长多晶硅层的器件层；
非晶硅模块，用于在器件层形成非晶硅层；
多晶硅模块，用于处理所述非晶硅层，形成所述多晶硅层。
在本申请的制备系统中，所述氧化物构件用于：采用化学气相沉积法，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起。
在本申请的制备系统中，所述氧化物构件用于：在所述多晶硅层表面上沉积氧化硅。
在本申请的制备系统中，所述氧化物构件用于：在所述多晶硅层表面上形成20纳米厚度的氧化物层。
在本申请的制备系统中，所述氧化物构件用于：在所述多晶硅层表面上形成大于20纳米厚度的氧化物层。
在本申请的制备系统中，所述蚀刻构件包括：
配置模块，用于配置缓冲氧化物刻蚀液；
浸泡模块，用于将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中，预设时长后取出。
在本申请的制备系统中，所述配置模块用于：配置氢氟酸缓冲刻蚀液。
在本申请的制备系统中，所述配置模块用于：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。
在本申请的制备系统中，所述配置模块用于：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。
 有益效果
本申请提供一种新的半导体器件的制备方法及系统，其包括在器件层上生长多晶硅层，在所述多晶硅层表面上形成氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起，使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件；基于此，本申请在得到多晶硅层后，先在多晶硅层表面上形成一道保护作用的氧化物层，然后利用缓冲氧化物刻蚀液，基于其可控性，蚀刻保护氧化膜和多晶硅层表面上的突起，从而起到降低多晶硅层表面突起的作用，同时也能很好的保护好多晶硅层表面，缓解了现有多晶硅层存在的表面粗糙的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的半导体器件制备方法的流程图。
图2为本申请实施例提供的半导体器件制备过程的示意图。
图3为本申请实施例提供的半导体器件制备系统的示意图。
图4为本申请实施例提供的半导体器件的示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有多晶硅层存在的表面粗糙的技术问题，本申请实施例可以缓解这个问题。
如图1所示，本申请实施例提供的半导体器件的制备方法包括：
步骤1、在器件层上生长多晶硅层。
在一种实施例中，本步骤包括：
如图2中（1）所示，提供一个需要生长多晶硅层的器件层，例如玻璃基板S1等；
如图2中（2）所示，在器件层形成非晶硅层S2；
如图2中（3）所示，采用准分子激光退火法ELA等工艺处理所述非晶硅层S2，形成所述多晶硅层S3。
步骤2、在所述多晶硅层表面上形成氧化物层。
在一种实施例中，本步骤包括：
如图2中（4）所示，采用化学气相沉积法CVD，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层S4，所述氧化物层S4覆盖所述多晶硅层S3表面上的突起S31。采用CVD所形成的氧化物层S4致密，并且密度较好，这样就可以在蚀刻的过程中，保持蚀刻速度的均一性。
在一种实施例中，在所述多晶硅层表面上沉积氧化物包括：在所述多晶硅层表面上沉积氧化硅。这是因为氧化硅的成本比较低，且容易蚀刻。
在一种实施例中，所述在所述多晶硅层表面上形成氧化物层包括：在所述多晶硅层表面上形成20纳米厚度的氧化物层。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
在一种实施例中，所述在所述多晶硅层表面上形成氧化物层包括：在所述多晶硅层表面上形成大于20纳米厚度的氧化物层。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
步骤3、使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀。
在一种实施例中，本步骤包括：
配置缓冲氧化物刻蚀液A；
如图2中（5）所示，将形成有所述氧化物层S4的器件层S1浸泡在所述缓冲氧化物刻蚀液A中预设时长t后，得到如图2中（6）所示的结构层之后，取出。
如图2中（6）所示，蚀刻处理后，氧化物层S4被安全蚀刻掉，露出多晶硅层S3’，同时多晶硅层S3’表面的突起S31将大大减少。
在一种实施例中，所述配置缓冲氧化物刻蚀液包括：配置氢氟酸缓冲刻蚀液。
在一种实施例中，所述配置氢氟酸缓冲刻蚀液包括：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。氢氟酸HF为主要的蚀刻液，氟化铵NH4F则作为缓冲剂使用，利用NH4F固定〔H+〕的浓度，使之保持一定的蚀刻率。
在一种实施例中，所述将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液包括：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。该配比的氢氟酸缓冲刻蚀液的蚀刻速度为10纳米/秒，蚀刻速度适中。
在一种实施例中，所述将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中预设时长后取出包括：将形成有所述氧化物层的器件层在所述缓冲氧化物刻蚀液中浸泡2秒后取出。
步骤4、在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
在一种实施例中，本步骤包括：
在得到如图2中（6）所示的多晶硅层S3’后，使用水等中性溶液对多晶硅层S3’表面进行清洗，去除多余的氢氟酸缓冲刻蚀液；
如图2中（7）所示，在腐蚀得到的多晶硅层S3’表面上制备功能层S5，如绝缘层和栅极金属层等，得到半导体器件，如OLED等。
在一种实施例中，如图3所示，本申请实施例提供了一种半导体器件的制备系统，用于执行图1所示的制备方法，该制备系统包括：
生长构件31，用于在器件层上生长多晶硅层。
在一种实施例中，生长构件31包括：
提供模块，用于提供一个需要生长多晶硅层的器件层，如图2中（1）所示，例如玻璃基板S1等；
非晶硅模块，用于在器件层形成非晶硅层S2，如图2中（2）所示；
多晶硅模块，采用准分子激光退火法ELA等工艺处理所述非晶硅层S2，如图2中（3）所示，形成所述多晶硅层S3。
氧化物构件32，用于在所述多晶硅层表面上形成氧化物层。
在一种实施例中，氧化物构件32用于：采用化学气相沉积法CVD，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层S4，如图2中（4）所示，所述氧化物层S4覆盖所述多晶硅层S3表面上的突起31。采用CVD所形成的氧化物层S4致密，并且密度较好，这样就可以在蚀刻的过程中，保持蚀刻速度的均一性。
在一种实施例中，氧化物构件32用于：在所述多晶硅层表面上沉积氧化硅。这是因为氧化硅的成本比较低，且容易蚀刻。
在一种实施例中，氧化物构件32用于：在所述多晶硅层表面上形成20纳米厚度的氧化物层。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
在一种实施例中，氧化物构件32用于：在所述多晶硅层表面上形成大于20纳米厚度的氧化物层。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
蚀刻构件33，用于使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀。
在一种实施例中，蚀刻构件33包括：
配置模块，用于配置缓冲氧化物刻蚀液A；
浸泡模块，用于将形成有所述氧化物层S4的器件层S1浸泡在所述缓冲氧化物刻蚀液A中，如图2中（5）所示，预设时长t后得到如图2中（6）所示的结构层之后，取出。
如图2中（6）所示，蚀刻处理后，氧化物层S4被安全蚀刻掉，露出多晶硅层S3’，同时多晶硅层S3’表面的突起31将大大减少。
在一种实施例中，配置模块用于：配置氢氟酸缓冲刻蚀液。
在一种实施例中，配置模块用于：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。氢氟酸HF为主要的蚀刻液，氟化铵NH4F则作为缓冲剂使用，利用NH4F固定氢离子H+的浓度，使之保持一定的蚀刻率。
在一种实施例中，配置模块用于：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。该配比的氢氟酸缓冲刻蚀液的蚀刻率为10纳米/秒，蚀刻速度适中。
在一种实施例中，浸泡模块用于：将形成有所述氧化物层的器件层在所述缓冲氧化物刻蚀液中浸泡2秒后取出。
制备构件34，用于在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
在一种实施例中，制备构件34用于：在得到如图2中（6）所示的多晶硅层S3’后，使用水等中性溶液对多晶硅层S3’表面进行清洗，去除多余的氢氟酸缓冲刻蚀液；如图2中（7）所示，在腐蚀得到的多晶硅层S3’表面上制备功能层S5，如绝缘层和栅极金属层等，得到半导体器件，如OLED等。
在一种实施例中，如图4所示，本申请实施例提供了一种半导体器件，通过图1所示的制备方法得到，该半导体器件4包括：
器件层41，例如玻璃基板S1等；
多晶硅层42，形成于所述器件层41之上，所述多晶硅层42为使用缓冲氧化物刻蚀液，对形成于多晶硅层42表面上的氧化物层进行腐蚀后得到的；
功能层43，形成于所述多晶硅层42之上，例如绝缘层和栅极金属层等，进而得到半导体器件，如OLED等。
在一种实施例中，多晶硅层42是采用准分子激光退火法ELA等工艺处理非晶硅层形成的。
在一种实施例中，形成于多晶硅层42表面上的氧化物层为：采用化学气相沉积法CVD，在所述多晶硅层表面上沉积氧化物所形成的，所述氧化物层覆盖所述多晶硅层表面上的突起31。采用CVD所形成的氧化物层S4致密，并且密度较好，这样就可以在蚀刻的过程中，保持蚀刻速度的均一性。
在一种实施例中，所述氧化物层为氧化硅。这是因为氧化硅的成本比较低，且容易蚀刻。
在一种实施例中，所述氧化物层为的厚度为20纳米。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
在一种实施例中，所述氧化物层为的厚度大于20纳米。这是因为多晶硅层表面可能会出现20纳米的突起，这样就可以完全覆盖突起。
在一种实施例中，多晶硅层42为形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液A中预设时长t后取出得到的。
在一种实施例中，所述缓冲氧化物刻蚀液包括：氢氟酸缓冲刻蚀液。
在一种实施例中，所述氢氟酸缓冲刻蚀液包括：氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。氢氟酸HF为主要的蚀刻液，氟化铵NH4F则作为缓冲剂使用，利用NH4F固定〔H+〕的浓度，使之保持一定的蚀刻率。
在一种实施例中，所述氢氟酸缓冲刻蚀液包括：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。该配比的氢氟酸缓冲刻蚀液的蚀刻速度为10纳米/秒，蚀刻速度适中。
在一种实施例中，多晶硅层42为形成有所述氧化物层的器件层在所述缓冲氧化物刻蚀液中浸泡2秒后取出。
步骤4、在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
根据上述实施例可知：
本申请提供一种新的半导体器件的制备方法及系统，其包括在器件层上生长多晶硅层，在所述多晶硅层表面上形成氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起，使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件；基于此，本申请在得到多晶硅层后，先在多晶硅层表面上形成一道保护作用的氧化物层，然后利用缓冲氧化物刻蚀液，基于其可控性，蚀刻保护氧化膜和多晶硅层表面上的突起，从而起到降低多晶硅层表面突起的作用，同时也能很好的保护好多晶硅层表面，缓解了现有多晶硅层存在的表面粗糙的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种半导体器件的制备方法，其包括：
    在器件层上生长多晶硅层；
    在所述多晶硅层表面上形成氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起；
    使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；
    在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
  2. 根据权利要求1所述的制备方法，其中，所述在所述多晶硅层表面上形成氧化物层包括：采用化学气相沉积法，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层。
  3. 根据权利要求2所述的制备方法，其中，所述在所述多晶硅层表面上沉积氧化物包括：在所述多晶硅层表面上沉积氧化硅。
  4. 根据权利要求1所述的制备方法，其中，所述在所器件层上生长多晶硅层包括：在器件层形成非晶硅层，采用准分子激光退火法处理所述非晶硅层，形成所述多晶硅层。
  5. 根据权利要求4所述的制备方法，其中，所述在所述多晶硅层表面上形成氧化物层包括：在所述多晶硅层表面上形成20纳米厚度的氧化物层。
  6. 根据权利要求1所述的制备方法，其中，所述使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀包括：配置缓冲氧化物刻蚀液，将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中预设时长后取出。
  7. 根据权利要求6所述的制备方法，其中，所述配置缓冲氧化物刻蚀液包括：配置氢氟酸缓冲刻蚀液。
  8. 根据权利要求7所述的制备方法，其中，所述配置氢氟酸缓冲刻蚀液包括：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。
  9. 根据权利要求8所述的制备方法，其中，所述将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液包括：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。
  10. 根据权利要求9所述的制备方法，其中，所述将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中预设时长后取出包括：将形成有所述氧化物层的器件层在所述缓冲氧化物刻蚀液中浸泡2秒后取出。
  11. 一种半导体器件的制备系统，其包括：
    生长构件，用于在器件层上生长多晶硅层；
    氧化物构件，用于在所述多晶硅层表面上形成氧化物层；
    蚀刻构件，用于使用缓冲氧化物刻蚀液，对所述氧化物层进行腐蚀；
    制备构件，用于在腐蚀得到的多晶硅层表面上制备功能层，得到半导体器件。
  12. 根据权利要求11所述的制备系统，其中，所述生长构件包括：
    提供模块，用于提供一个需要生长多晶硅层的器件层；
    非晶硅模块，用于在器件层形成非晶硅层；
    多晶硅模块，用于处理所述非晶硅层，形成所述多晶硅层。
  13. 根据权利要求11所述的制备系统，其中，所述氧化物构件用于：采用化学气相沉积法，在所述多晶硅层表面上沉积氧化物，形成所述氧化物层，所述氧化物层覆盖所述多晶硅层表面上的突起。
  14. 根据权利要求13所述的制备系统，其中，所述氧化物构件用于：在所述多晶硅层表面上沉积氧化硅。
  15. 根据权利要求13所述的制备系统，其中，所述氧化物构件用于：在所述多晶硅层表面上形成20纳米厚度的氧化物层。
  16. 根据权利要求13所述的制备系统，其中，所述氧化物构件用于：在所述多晶硅层表面上形成大于20纳米厚度的氧化物层。
  17. 根据权利要求11所述的制备系统，其中，所述蚀刻构件包括：
    配置模块，用于配置缓冲氧化物刻蚀液；
    浸泡模块，用于将形成有所述氧化物层的器件层浸泡在所述缓冲氧化物刻蚀液中，预设时长后取出。
  18. 根据权利要求17所述的制备系统，其中，所述配置模块用于：配置氢氟酸缓冲刻蚀液。
  19. 根据权利要求18所述的制备系统，其中，所述配置模块用于：将氢氟酸、氟化铵与水混合得到所述氢氟酸缓冲刻蚀液。
  20. 根据权利要求19所述的制备系统，其中，所述配置模块用于：将摩尔比为40%的氢氟酸水溶液、与摩尔比为50%的氟化铵水溶液，按体积比为1：7进行混合，到所述氢氟酸缓冲刻蚀液。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163935A (ja) * 1988-12-16 1990-06-25 Fujitsu Ltd 半導体装置の製造方法
CN1334312A (zh) * 2000-07-25 2002-02-06 关东化学株式会社 多晶硅膜表面处理溶液和采用该溶液的多晶硅膜表面处理方法
CN1487344A (zh) * 2002-08-23 2004-04-07 ͳ�����ɷ����޹�˾ 制造液晶显示器的方法以及形成复晶硅层的方法
CN1540719A (zh) * 2003-04-23 2004-10-27 友达光电股份有限公司 低温多晶硅薄膜的制造方法及低温多晶硅薄膜晶体管
CN102651311A (zh) * 2011-12-20 2012-08-29 京东方科技集团股份有限公司 一种低温多晶硅薄膜的制备方法及低温多晶硅薄膜
CN102655089A (zh) * 2011-11-18 2012-09-05 京东方科技集团股份有限公司 一种低温多晶硅薄膜的制作方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2715919B2 (ja) * 1994-07-19 1998-02-18 日本電気株式会社 薄膜トランジスタｃｍｏｓ回路
CN101657887B (zh) * 2007-04-13 2012-02-01 大金工业株式会社 蚀刻液

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163935A (ja) * 1988-12-16 1990-06-25 Fujitsu Ltd 半導体装置の製造方法
CN1334312A (zh) * 2000-07-25 2002-02-06 关东化学株式会社 多晶硅膜表面处理溶液和采用该溶液的多晶硅膜表面处理方法
CN1487344A (zh) * 2002-08-23 2004-04-07 ͳ�����ɷ����޹�˾ 制造液晶显示器的方法以及形成复晶硅层的方法
CN1540719A (zh) * 2003-04-23 2004-10-27 友达光电股份有限公司 低温多晶硅薄膜的制造方法及低温多晶硅薄膜晶体管
CN102655089A (zh) * 2011-11-18 2012-09-05 京东方科技集团股份有限公司 一种低温多晶硅薄膜的制作方法
CN102651311A (zh) * 2011-12-20 2012-08-29 京东方科技集团股份有限公司 一种低温多晶硅薄膜的制备方法及低温多晶硅薄膜

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