WO2020147637A1 - Circuit de génération de tension de référence et alimentation électrique à découpage - Google Patents

Circuit de génération de tension de référence et alimentation électrique à découpage Download PDF

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Publication number
WO2020147637A1
WO2020147637A1 PCT/CN2020/071078 CN2020071078W WO2020147637A1 WO 2020147637 A1 WO2020147637 A1 WO 2020147637A1 CN 2020071078 W CN2020071078 W CN 2020071078W WO 2020147637 A1 WO2020147637 A1 WO 2020147637A1
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Prior art keywords
output
conversion circuit
input terminal
pmos transistor
reference voltage
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PCT/CN2020/071078
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English (en)
Chinese (zh)
Inventor
张海军
张启帆
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上海艾为电子技术股份有限公司
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Publication of WO2020147637A1 publication Critical patent/WO2020147637A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/471—Indexing scheme relating to amplifiers the voltage being sensed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the technical field of switching power supplies, in particular to a reference voltage generating circuit and a switching power supply.
  • Class AB audio power amplifiers are widely used in portable electronic products because of their good linearity, sound quality, and simple design structure.
  • the switching power supply has the advantages of high working efficiency and low heat generation, usually the power supply of the output stage of the class AB audio power amplifier is provided by the switching power supply.
  • the present invention provides a reference voltage generating circuit and a switching power supply to solve the problems of high power consumption and low efficiency of the class AB audio power amplifier.
  • the first aspect of the present invention discloses a reference voltage generation circuit, which is characterized in that it is used to provide a reference voltage for the switching power supply of the output stage of the class AB audio power amplifier;
  • the reference voltage generation circuit includes: a sampling circuit, an input conversion circuit, Bias conversion circuit and sum module; among them:
  • the first input terminal and the second input terminal of the sampling circuit are respectively used as the first input terminal and the second input terminal of the reference voltage generating circuit, respectively receiving the output stage of the first operational amplifier in the class AB audio power amplifier
  • the potential sampling values of VOP1 and the output stage VON1, or the potential sampling values of the output stage VOP and the output stage VON of the AB audio power amplifier are respectively received;
  • the input terminal of the bias conversion circuit serves as the third input terminal of the reference voltage generating circuit, and is connected to a fixed bias voltage
  • the first output terminal of the sampling circuit is connected to the first input terminal of the input conversion circuit; the second output terminal of the sampling circuit is connected to the second input terminal of the input conversion circuit;
  • the output terminal of the input conversion circuit, the output terminal of the bias conversion circuit, and the input terminal of the summation module are all connected, and the output terminal of the summation module serves as the output terminal of the reference voltage generating circuit.
  • the first output terminal of the sampling circuit outputs the output stage VOP1 or the potential sampling value of the output stage VOP, and the second output terminal of the sampling circuit outputs the output stage VON1 or the output stage VON potential sampling value;
  • the input conversion circuit is used to convert and sum the sampled values of the received potentials, and output an input current signal through its own output terminal;
  • the bias conversion circuit is used to convert the fixed bias voltage and output a bias current signal through its own output terminal;
  • the summation module is used to sum the input current signal and the bias current signal, and output the voltage value corresponding to the summed current as a reference voltage signal.
  • the input conversion circuit includes: a first conversion circuit and a second conversion circuit; wherein:
  • the input terminal of the first conversion circuit is used as the first input terminal of the input conversion circuit, and is used to receive the output stage VOP1 or the potential sampling value of the output stage VOP, convert it into a first current signal and pass it through itself Output terminal for output;
  • the input terminal of the second conversion circuit is used as the second input terminal of the input conversion circuit, and is used to receive the output stage VON1 or the potential sampling value of the output stage VON, convert it into a second current signal and pass it through itself Output terminal for output;
  • the output terminal of the first conversion circuit is connected to the output terminal of the second conversion circuit, and the connection point serves as the output terminal of the input conversion circuit.
  • the first conversion circuit includes: a first comparator, a first NMOS transistor, a first resistor, a first PMOS transistor, and a second PMOS transistor; wherein:
  • the non-inverting input terminal of the first comparator serves as the input terminal of the first conversion circuit; the inverting input terminal of the first comparator is connected to the source of the first NMOS transistor, and the connection point is connected to one end of the first resistor Connected; the other end of the first resistor is grounded;
  • the output terminal of the first comparator is connected to the gate of the first NMOS transistor
  • the gate of the first PMOS transistor is connected to its drain, and the connection point is connected to the drain of the first NMOS transistor;
  • the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to a power source;
  • the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor; the drain of the second PMOS transistor serves as the output terminal of the first conversion circuit.
  • the second conversion circuit includes: a second comparator, a second NMOS transistor, a second resistor, a third PMOS transistor, and a fourth PMOS transistor; wherein:
  • the non-inverting input terminal of the second comparator is used as the input terminal of the second conversion circuit; the inverting input terminal of the second comparator is connected to the source of the second NMOS transistor, and the connection point is with one end of the second resistor Connected; the other end of the second resistor is grounded;
  • the output terminal of the second comparator is connected to the gate of the second NMOS transistor
  • the gate of the third PMOS transistor is connected to its drain, and the connection point is connected to the drain of the second NMOS transistor;
  • the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to a power source;
  • the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor; the drain of the fourth PMOS transistor serves as the output terminal of the second conversion circuit.
  • the bias conversion circuit includes: a third comparator, a third NMOS transistor, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor; wherein:
  • the non-inverting input terminal of the third comparator serves as the input terminal of the bias conversion circuit; the inverting input terminal of the third comparator is connected to the source of the third NMOS transistor, and the connection point is connected to one end of the third resistor Connected; the other end of the third resistor is grounded;
  • the output terminal of the third comparator is connected to the gate of the third NOMS transistor
  • the gate of the fifth PMOS transistor is connected to its drain, and the connection point is connected to the drain of the third NOMS transistor;
  • the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to a power source;
  • the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor; the drain of the sixth PMOS transistor is used as the output terminal of the bias conversion circuit.
  • the summation module includes a summation resistor, wherein: one end of the summation resistor serves as an input end of the summation module and an output end of the summation module, and the summation resistance The other end is grounded.
  • a second aspect of the present invention discloses a switching power supply, which is characterized in that it is used to provide a supply voltage for the output stage of a class AB audio power amplifier, and includes: a main circuit, and a reference voltage generator as described in any one of the first aspects Circuit; where:
  • the reference voltage supply end of the main circuit is connected to the output end of the reference voltage generation circuit; the input end of the main circuit is used as the input end of the switching power supply; the output end of the main circuit is used as the switching power supply The output terminal.
  • the main circuit is configured to receive the reference voltage signal output by the reference voltage generating circuit, and obtain at least one control signal after conversion, and the at least one control signal is used to control the input terminal and the output terminal of the main circuit Between on and off and voltage conversion.
  • the main circuit is any one of BUCK topology, BOOST topology, and BUCK_BOOST topology.
  • the BOOST topology includes:
  • the non-inverting input terminal is used as an error amplifier of the control terminal of the BOOST topology, and the inverting input terminal of the error amplifier receives a feedback voltage signal;
  • a pulse width modulation comparator whose positive input terminal is connected to the output terminal of the error amplifier; the negative input terminal of the pulse width modulation comparator receives a slope compensation voltage signal;
  • the input terminal of the switch tube driving unit is connected with the output terminal of the pulse width modulation comparator, the first output terminal of the switch driving unit is connected with the control terminal of the first power tube, and the second output terminal of the switch tube driving unit Connected to the control end of the second power tube;
  • the second end of the first power tube and the second end of the second power tube are connected to one end of the inductor
  • the other end of the inductor is used as the input end of the BOOST topology
  • the first end of the first power tube is used as the output end of the BOOST topology; the first end of the second power tube is grounded.
  • the first power tube is a PMOS power tube; the second power tube is an NMOS power tube.
  • the first ends of the first power tube and the second power tube are both source electrodes, and the second ends of the first power tube and the second power tube are both drain electrodes.
  • the control ends of the first power tube and the second power tube are both grids.
  • the present invention uses a sampling circuit to sample the potentials of the two output stages of the first operational amplifier of the class AB audio power amplifier or the two output stages of the class AB audio power amplifier;
  • the input conversion circuit converts and sums the potentials collected by the two input terminals of the acquisition circuit to obtain an input current signal, and converts the fixed bias voltage through a bias conversion circuit to obtain a bias current signal; and then through a summation module
  • the input current signal and the bias current signal are summed and converted into a reference voltage signal; thus, the reference voltage signal can follow the two output stages of the first operational amplifier of the class AB audio power amplifier or the class AB audio
  • the potential of the two output stages of the power amplifier changes, so that the output voltage of the switching power supply changes with the two output stages of the first operational amplifier of the class AB audio power amplifier or the class AB audio power amplifier.
  • the potentials of the two output stages change, thereby reducing the conduction loss on the power tube of the power stage and improving the efficiency of the system.
  • FIG. 1 is a schematic diagram of a reference voltage generating circuit disclosed in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an input conversion circuit in a reference voltage generating circuit disclosed in another embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a first conversion circuit in an input conversion circuit disclosed in another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a second conversion circuit in the input conversion circuit disclosed in another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a bias conversion circuit 300 in a reference voltage generation circuit disclosed in an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of a switching power supply disclosed in an embodiment of the present invention.
  • an embodiment of the present invention provides a reference voltage generating circuit for providing a reference voltage for the switching power supply of the output stage of the class AB audio power amplifier, as shown in Figure 1
  • the specific structure includes: a sampling circuit 100, an input conversion circuit 200, a bias conversion circuit 300, and a summation module 400; among them:
  • the first input terminal and the second input terminal of the sampling circuit 100 are used as the first input terminal and the second input terminal of the reference voltage generating circuit, respectively, for receiving the output of the first operational amplifier in the class AB audio power amplifier.
  • the input terminal of the bias conversion circuit 300 is used as the third input terminal of the reference voltage generating circuit for connecting a fixed bias voltage DV.
  • the first output terminal of the sampling circuit 100 is connected to the first input terminal of the input conversion circuit 200; the second output terminal of the sampling circuit 100 is connected to the second input terminal of the input conversion circuit 200.
  • the first output terminal of the sampling circuit 100 outputs the sampled value of the potential of VOP1/VOP, and the second output terminal outputs the sampled value of the potential of VON1/VON.
  • the input conversion circuit 200 is configured to convert and sum the sampled values of the received potentials to obtain the input current signal I3, and output the input current signal I3 to the summation module 400.
  • the output terminal of the input conversion circuit 200, the output terminal of the bias conversion circuit 300, and the input terminal of the summation module 400 are all connected, and the output terminal of the summation module 400 serves as the output terminal of the reference voltage generating circuit.
  • the bias conversion circuit 300 is configured to receive the fixed bias voltage DV and perform conversion to obtain the bias current signal I4, and output the bias current signal I4 to the summation module 400.
  • the summation module 400 is used to sum the input current signal I3 and the bias current signal I4, and output the voltage value corresponding to the summed current.
  • the summing module 400 includes a summing resistor Rt.
  • One end of the summing resistor Rt is connected to the input conversion circuit 200 and the bias conversion circuit 300, and the other end is grounded, where: the input current signal I3 and the bias current signal I4 pass through
  • the summing resistor Rt flows into the ground, and the end of the summing resistor Rt connected to the input conversion circuit 200 and the bias conversion circuit 300 is the output end of the reference voltage generation circuit.
  • the specific working principle of the reference voltage generating circuit is:
  • the first input terminal and the second input terminal of the sampling circuit 100 respectively receive the sampled values of the potentials of the output stage VOP1 and the output stage VON1 of the first operational amplifier in the class AB audio power amplifier, or sample the class AB audio power amplifier respectively The sampling value of the potential of the output stage VOP and the output stage VON.
  • the input conversion circuit 200 converts and sums the sampled values of the potentials received at the two input ends of the sampling circuit 100 to obtain the input current signal I3; the bias conversion circuit 300 converts the fixed bias voltage DV received at its input ends to obtain the bias current Signal I4.
  • the current flowing through the summing resistor Rt is the sum of the currents output by the input conversion circuit 200 and the bias conversion circuit 300, that is, the summing resistor Rt will The input current signal I3 and the bias current signal I4 are added together.
  • the summing resistor Rt converts the current signal into a voltage signal, and one end of the summing resistor is the output terminal of the reference voltage generating circuit, and the other end is grounded Therefore, the potential of the reference voltage signal VREF_IS output by the reference voltage generating circuit is the divided voltage of the summing resistor Rt.
  • the present invention samples the potentials of the two output stages of the first operational amplifier of the class AB audio power amplifier or the two output stages of the class AB audio power amplifier through a sampling circuit, and then uses a summing resistor ,
  • the input conversion circuit and the bias conversion circuit make the reference voltage change with the potential changes of the two output stages of the first operational amplifier of the class AB audio power amplifier or the two output stages of the class AB audio power amplifier, thereby making
  • the output voltage of the switching power supply changes with the potential changes of the two output stages of the first operational amplifier of the class AB audio power amplifier or the two output stages of the class AB audio power amplifier, thereby reducing the power of the power stage
  • the conduction loss on the tube improves the efficiency of the system.
  • an implementation of the input conversion circuit 200 includes: a first conversion circuit 210 and a second conversion circuit 220; wherein:
  • the input terminal of the first conversion circuit 210 serves as the first input terminal of the input conversion circuit 200, and receives the output stage VOP1 or the sampled value of the potential of the output stage VOP; the input terminal of the second conversion circuit 220 serves as the second input of the input conversion circuit 200 The terminal receives the sampled value of the potential of the output stage VON1 or the output stage VIN.
  • the output terminal of the first conversion circuit 210 is connected to the output terminal of the second conversion circuit 220, and the connection point serves as the output terminal of the input conversion circuit 200. Specifically, the first conversion circuit 210 outputs the first current signal I1, the second conversion circuit 220 outputs the second current signal I2, and is input to the conversion circuit 200.
  • the externally provided input current signal I3 is the first current signal I1 and the second current signal. The sum of I2.
  • the first conversion circuit 210 converts the sample value of the potential received by the first input terminal of the input conversion circuit 200 to obtain the first current signal I1; the second conversion circuit 220 inputs the sample value of the potential received by the second input terminal of the input conversion circuit 200 The second current signal I2 is obtained by conversion.
  • the input conversion circuit 200 sums the first current signal I1 and the second current signal I2 to output the input current signal I3.
  • this embodiment only takes a specific implementation of the first conversion circuit 210 and the second conversion circuit 220 as an example for description.
  • the other embodiments have the same working principles as this embodiment, and you can refer to this embodiment. The working principle is not repeated here.
  • an implementation of the first conversion circuit 210 includes: a first comparator 211, a first NMOS transistor M1, a first resistor R1, a first PMOS transistor P1 and second PMOS transistor P2; among them:
  • the non-inverting input terminal of the first comparator 211 is used as the input terminal of the first conversion circuit 210; the inverting input terminal of the first comparator 211 is connected to the source of the first NMOS transistor M1, and the connection point is connected to one end of the first resistor R1 ; The other end of the first resistor R1 is grounded.
  • the output terminal of the first comparator 211 is connected to the gate of the first NMOS transistor M1.
  • the gate of the first PMOS transistor P1 is connected to its drain, and the connection point is connected to the drain of the first NMOS transistor M1; the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power terminal.
  • the gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor; the drain of the second PMOS transistor serves as the output terminal of the first conversion circuit 210.
  • the first input terminal of the sampling circuit 100 receives the potential sampling value of the output stage VOP1, that is, the potential of the non-inverting input terminal of the first comparator 211 is the potential sampling value of the output stage VOP1, then when the potential of the output stage VOP1 is high, Since the inverting input terminal of the first comparator 211 is grounded through the first resistor R1, that is, the potential of the inverting input terminal of the first comparator 211 is 0, so the potential of the non-inverting input terminal of the first comparator 211 is that of the output stage VOP1 The potential sampling value is greater than the potential of the inverting input terminal of the first comparator 211, so the output terminal of the first comparator 211 outputs a high-level first control signal.
  • the first NMOS transistor M1 When the gate of the first NMOS transistor M1 receives a high-level first control signal, the first NMOS transistor is turned on; and because the gate of the first PMOS transistor P1 is connected to its drain, that is, the first NMOS transistor After M1 is turned on, the potential of the gate and drain of the first PMOS transistor P1 is 0, that is, low level, so the first PMOS transistor P1 is turned on, so the first resistor R1, the first NMOS transistor M1 and the first A current flows through the PMOS transistor P1.
  • the ratio of the current in the second PMOS transistor P2 to the current in the first PMOS transistor P1 is equal to the ratio of the sizes of the second PMOS transistor P2 to the first PMOS transistor P1, and the ratio between the two can be based on actual conditions. The requirements are determined, and there are no restrictions here.
  • the potential of the inverting input terminal of the first comparator 211 is the divided voltage of the first resistor R1, so that when the output stage VOP1 is at a high level, the first conversion circuit 210 can be maintained. It is in the on state, so it is necessary to ensure that after the first conversion circuit 210 is turned on, the voltage division of the first resistor R1 is less than the potential of the output stage VOP1.
  • the first conversion circuit 210 When the potential of the output stage VOP1 is low, the first conversion circuit 210 is not turned on.
  • the working principle is basically the same as the above working principle. It only needs to ensure that after the first conversion circuit 210 is turned on, the voltage division of the first resistor R1 is less than the output stage VOP The potential is sufficient, so I won’t repeat them here.
  • this embodiment only provides a specific implementation of the first conversion circuit 210. In practical applications, it can also be implemented in a circuit structure or chip composed of other discrete devices, as long as it can implement other aspects of the above-mentioned working principle. The implementation modes are all within the protection scope of this application.
  • an implementation of the second conversion circuit 220 includes: a second comparator 221, a second NMOS transistor M2, a second resistor R2, a third PMOS transistor P3 and fourth PMOS transistor P4; among them:
  • the non-inverting input terminal of the second comparator 221 is used as the input terminal of the second conversion circuit 220; the inverting input terminal of the second comparator 221 is connected to the source of the second NMOS transistor M2, and the connection point is connected to one end of the second resistor R2 ; The other end of the second resistor R2 is grounded.
  • the output terminal of the second comparator 221 is connected to the gate of the second NMOS transistor M2.
  • the gate of the third PMOS transistor P3 is connected to its drain, and the connection point is connected to the drain of the second NOMS transistor M2.
  • the source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are both connected to the power supply; the gate of the fourth PMOS transistor P4 is connected to the gate of the third PMOS transistor P3; the drain of the fourth PMOS transistor P4 As the output terminal of the second conversion circuit 220.
  • the working principle of the second conversion circuit 220 is basically the same as the working principle of the first conversion circuit 210, and will not be repeated here.
  • an implementation manner of the bias conversion circuit 300 includes: a third comparator 310, a third NMOS transistor M3, a third resistor R3, and a fifth PMOS transistor P5 and sixth PMOS transistor P6; among them:
  • the non-inverting input terminal of the third comparator 310 is used as the input terminal of the bias conversion circuit 300; the inverting input terminal of the third comparator 310 is connected to the source of the third NMOS transistor M3, and the connection point is connected to one end of the third resistor R3 ; The other end of the third resistor R3 is grounded.
  • the output terminal of the third comparator 310 is connected to the gate of the third NMOS transistor M3.
  • the gate of the fifth PMOS transistor P5 is connected to its drain, and the connection point is connected to the drain of the third NMOS transistor M3.
  • the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to the power source.
  • the gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor serves as the output terminal of the bias conversion circuit 300.
  • the working principle of the bias conversion circuit 300 is basically the same as the working principle of the first conversion circuit 210, and will not be repeated here.
  • the present invention also provides a switching power supply, as shown in FIG. 6, the specific structure includes: a main circuit 520 and the reference voltage generating circuit 510 disclosed in any of the above embodiments, wherein:
  • the reference voltage control terminal of the main circuit 520 is connected to the output terminal of the reference voltage generating circuit 510; the input terminal of the main circuit 520 serves as the input terminal of the switching power supply; the output terminal of the main circuit 520 serves as the output terminal of the switching power supply.
  • the main circuit 520 receives the reference voltage signal VREF_IS output by the reference voltage generating circuit 510 through its reference voltage control terminal; then the main circuit 520 converts the reference voltage signal VREF_IS to obtain at least one control signal, and the at least one control signal is used It controls the on-off and voltage conversion between the input terminal and the output terminal of the main circuit 520.
  • the main circuit is any one of BUCK topology, BOOST topology and BUCK_BOOST topology.
  • this embodiment only takes one implementation manner of the main circuit 520 as an example, that is, BOOST topology, for specific description, and other implementation manners of the main circuit 520 will not be described in detail here, but other aspects of the main circuit 520
  • the implementation manners are also within the protection scope of this application.
  • the specific structure of the BOOST topology, as shown in Fig. 6, includes: an error amplifier 521, a pulse width modulation comparator 522, and a switch tube driving unit 523; among them:
  • the non-inverting input terminal of the error amplifier 521 serves as the reference voltage supply terminal of the BOOST topology; the inverting input terminal of the error amplifier receives the feedback voltage signal.
  • One end of the fourth resistor R4 is connected to one end of the fifth resistor R5, and the connection point outputs a feedback voltage signal; the other end of the fifth resistor R5 is grounded.
  • the positive input terminal of the pulse width modulation comparator 522, the output terminal of the error amplifier 521, the output terminal of the clamp module 524, and the output terminal of the loop compensation capacitor 525 are all connected; the negative input terminal of the pulse width modulation comparator 522 receives slope compensation Voltage signal.
  • the sampling module 526 is connected to the current production module 527, and the connection point outputs a slope compensation voltage signal.
  • the input terminal of the switching tube driving unit 523 is connected with the output terminal of the pulse width modulation comparator 522; the first output terminal HSG of the switching tube driving unit 523 is connected with the control terminal of the first power tube Mp; the second output terminal of the switching tube driving unit 523 is connected The output terminal LSG is connected to the control terminal of the second power tube Mn.
  • the second end of the first power tube Mp, the second end of the second power tube Mn and one end of the inductor L are connected together, and the other end of the inductor is used as the input end of the BOOST topology; the first end of the first power tube Mp is used as The output end of the BOOST topology; the first end of the second power tube Mn is grounded.
  • the first power tube Mp is a PMOS power tube
  • the second power tube Mn is an NMOS power tube
  • the first ends of the first power tube Mp and the second power tube Mn are both sources, the first power The second ends of the tube Mp and the second power tube Mn are both drains, and the control ends of the first power tube Mp and the second power tube Mn are both gates.
  • the other end of the fourth resistor R4, one end of the capacitor C and one end of the sixth resistor R6 are connected, and the connection point is connected to the first end of the first power tube; the other end of the capacitor C is grounded, and the other end of the sixth resistor R6 is grounded.
  • the error amplifier 521 When the potential of the reference voltage signal VREF_IS output by the reference voltage generating circuit 510 is greater than the reference voltage VFB, the error amplifier 521 amplifies the difference between the potential of the reference voltage signal and the reference voltage VFB, and outputs the error amplification signal COMP, due to the potential of the reference voltage signal VREF_IS It is greater than the reference voltage VFB, so the clamping module 524 will not clamp the potential of the error amplification signal COMP.
  • the potential of the error amplification signal COMP is greater than the slope compensation voltage VSLOPE, so the potential of the drive signal output by the pulse width modulation comparator 522 is at a high level; the input terminal of the switch drive unit 523 receives a high level drive signal, and drives The first power tube Mp is turned on, and the second power tube Mn is turned off.
  • the error amplifier 521 When the potential of the reference voltage signal VREF_IS output by the reference voltage generating circuit 510 is less than the reference voltage VFB, the error amplifier 521 amplifies the potential difference between the reference voltage VFB and the reference voltage signal, and outputs the error amplification signal COMP, due to the potential of the reference voltage signal VREF_IS It is less than the reference voltage VFB, so the clamping module 524 clamps the potential of the error amplification signal COMP at a low level.
  • the potential of the error amplifier COMP is less than the slope compensation voltage VSLOPE, so the potential of the drive signal output by the pulse width modulation comparator 522 is low level; the input terminal of the switch drive unit 523 receives the low level drive signal, turning off the first A power tube Mp turns on the second power tube Mn.
  • the driving signals are only distinguished by high-level and low-level, so that different driving signals can control the switch tube driving unit 523 to complete different operations. This is not a limitation; in actual applications, as long as it can Other solutions for realizing the above working principle are all within the protection scope of this application.
  • the ratio of the reference voltage VFB to the output voltage VOUT of the BOOST topology is equal to the resistance of the fifth resistor R5 to the fourth resistor R4
  • the output voltage VOUT of the switching power supply is closer to the reference voltage. Therefore, when the potential of the reference voltage signal output by the reference voltage generating circuit 510 changes, after the above working process, the switch The output voltage VOUT of the power supply also changes and is closer to the changed reference voltage, that is, the output voltage VOUT of the switching power supply changes with the potential change of the reference voltage signal output by the reference voltage generating circuit 510. Also, because the reference voltage signal output by 510 changes with the fluctuation of the input/output signal of the class AB audio power amplifier, the output voltage VOUT of the switching power supply can follow the fluctuation of the input/output signal of the class AB audio power amplifier.
  • the output voltage VOUT provided by the switching power supply will also change accordingly, which can minimize the voltage drop on the output stage PMOS power tube and NMOS power tube, thereby reducing the corresponding The conduction loss on the power tube improves the system efficiency.

Abstract

Un circuit de génération de tension de référence (510) et une alimentation électrique à découpage, comprenant : un premier circuit de conversion (210), un second circuit de conversion (220), un circuit de conversion de polarisation (300), et une résistance de sommation (400). Un circuit d'échantillonnage (100) est utilisé pour échantillonner des potentiels de deux étages de sortie (VOP1, VON1) d'un premier amplificateur opérationnel d'un amplificateur de puissance audio de classe AB, ou pour échantillonner des potentiels de deux étages de sortie (VOP, VON) de l'amplificateur de puissance audio de classe AB. De plus, une résistance de sommation (Rt), un circuit de conversion d'entrée (200) et le circuit de conversion de polarisation (300) sont utilisés, de telle sorte qu'une tension de référence (VREF_IS) change avec des changements des potentiels des deux étages de sortie (VOP1, VON1) du premier amplificateur opérationnel de l'amplificateur de puissance audio de classe AB, ou avec des changements des potentiels des deux étages de sortie (VOP, VON) du changement d'amplificateur de puissance audio de classe AB. En conséquence, une tension de sortie (VOUT) d'une alimentation électrique à découpage change avec des changements des potentiels des deux étages de sortie (VOP1, VON1) du premier amplificateur opérationnel de l'amplificateur de puissance audio de classe AB, ou avec des changements des potentiels des deux étages de sortie (VOP, VON) de l'amplificateur de puissance audio de classe AB, ce qui permet de réduire les pertes de conduction au niveau des étages de puissance d'un tube de puissance et d'améliorer l'efficacité du système.
PCT/CN2020/071078 2019-01-14 2020-01-09 Circuit de génération de tension de référence et alimentation électrique à découpage WO2020147637A1 (fr)

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