WO2020140785A1 - Tem样品制备方法 - Google Patents

Tem样品制备方法 Download PDF

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Publication number
WO2020140785A1
WO2020140785A1 PCT/CN2019/127439 CN2019127439W WO2020140785A1 WO 2020140785 A1 WO2020140785 A1 WO 2020140785A1 CN 2019127439 W CN2019127439 W CN 2019127439W WO 2020140785 A1 WO2020140785 A1 WO 2020140785A1
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tem sample
substrate
tested
defect
planar tem
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English (en)
French (fr)
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李晓丽
王金成
王佳龙
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
    • G01N23/2202—Preparing specimens therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q

Definitions

  • the invention relates to the field of semiconductors, in particular to a method for preparing TEM samples.
  • a semiconductor device In the manufacturing process of a semiconductor device, it usually includes the steps of well implantation, ion advancement, and annealing of the semiconductor substrate, which easily disturbs the internal lattice arrangement of the semiconductor substrate and causes defects. At the same time, as the size of semiconductor devices becomes smaller and smaller, the integration of semiconductor devices becomes higher and higher, and defects have an increasing impact on the yield and reliability of the devices. Therefore, in the failure analysis of semiconductor devices, finding the location of the semiconductor substrate defect and obtaining the relevant information of the defect can reverse the process that caused the defect, so that the relevant process can be improved to avoid subsequent type defects, improve product yield and Device reliability.
  • defect information there are two methods for obtaining defect information: one is to chemically etch the semiconductor substrate and observe it with SEM (scanning electron microscopy) to determine whether there is a defect on the semiconductor substrate and the approximate location of the defect , But the specific location and morphology of the defect cannot be known; the other is to prepare a planar TEM (Transmission, Electron, Microscope, transmission electron microscope) sample and observe it with TEM, you can obtain the planar position and planar morphology of the defect, but you can not know the semiconductor Defect information in the thickness direction of the substrate, such as the depth information of the defect, thus limits the failure analysis of the semiconductor device.
  • SEM scanning electron microscopy
  • a TEM sample preparation method is provided.
  • a TEM sample preparation method including:
  • the target position is located in the planar TEM sample
  • the thickness of the adhesive glue is less than or equal to 50 ⁇ m
  • FIGS. 2a to 2e are schematic structural diagrams corresponding to each step of preparing a planar TEM sample in an embodiment of this application;
  • FIG. 3a is a top view of a planar TEM sample and a conductive pad after being pasted in an embodiment of this application;
  • 3b is a side cross-sectional view of a planar TEM sample and a conductive gasket after being pasted in an embodiment of this application;
  • FIG. 4 is a schematic structural diagram of a cross-sectional TEM sample in an embodiment of this application.
  • FIG. 6 is a scanning electron micrograph of a section of the plane TEM sample of FIG. 5 cut to form a section TEM sample.
  • TEM sample preparation methods include:
  • Step S100 Determine the target position where the defect exists on the semiconductor substrate and thin the semiconductor substrate from the back of the semiconductor substrate to prepare a planar TEM sample, and the target position is located in the planar TEM sample.
  • the longitudinal direction of the semiconductor substrate 100 is defined as the X axis
  • the width direction of the semiconductor substrate 100 is defined as the Y axis
  • the thickness direction of the semiconductor substrate 100 is defined as the Z axis.
  • the target position 110 where the defect exists on the semiconductor substrate 100 is first determined.
  • the target position 110 is a two-dimensional coordinate in a two-dimensional plane formed by the X-axis and the Y-axis, that is, only the X-axis and Y-axis
  • the target position 110 is located in the two-dimensional plane formed by the axis, and the target position 110 does not include the Z-axis coordinate of the defect. Since observation with a scanner can only obtain planar image information, the target position 110 is actually the projection position of the defect on the observation surface of the semiconductor substrate 100.
  • the semiconductor substrate 100 has a front surface 100A and a back surface 100B. After the semiconductor substrate 100 is subjected to the above steps from the front surface 100A of the semiconductor substrate 100, defects are easily caused in the semiconductor substrate 100. Therefore, the defects are closer to the semiconductor substrate 100 100A of the front. After determining the target position 110 where the defect exists, the semiconductor substrate 100 is thinned from the back surface 100B of the semiconductor substrate 100 to prepare a planar TEM sample. In some embodiments, the size of the semiconductor substrate 100 is gradually reduced during the thinning of the semiconductor substrate 100, but the semiconductor substrate 100 at the target position 110 cannot be removed, that is, the final planar TEM sample needs to contain the Target location 110.
  • planar TEM sample refers to the thickness of the semiconductor substrate 100 in the Z-axis direction after being thinned to meet the TEM observation thickness.
  • the thickness of the planar TEM sample is less than or equal to And the smaller the thickness, the better the quality of the acquired image. In an embodiment, the thickness of the planar TEM sample is less than or equal to
  • step S100 may specifically include:
  • Step S110 mark the target position where the defect exists on the front surface of the semiconductor substrate.
  • the target position 110 can be determined by counting addresses or fixed-point bright points.
  • the approximate position of the defect in the substrate can be observed by SEM and used as the target position 110.
  • the semiconductor substrate 100 can be marked at the target position 110 by laser or FIB, so as to identify the target position 110 in a subsequent process.
  • the mark may be a cross mark.
  • Step S120 The semiconductor substrate is cut to form a substrate to be tested, the front surface of the substrate to be tested is pasted on a glass slide, and the target position is located at the center of the substrate to be tested.
  • the size of the semiconductor substrate 100 directly acquired is relatively large, and the size of the defect in the semiconductor substrate 100 is very small, and it is not necessary to use the entire semiconductor substrate 100 when analyzing the defect.
  • the semiconductor substrate 100 is first cut around the defect to obtain the substrate 120 under test including the defect area, that is, the mark in step S110 is at the center of the substrate 120 under test,
  • the front surface of the substrate to be tested 120 is then pasted on the glass slide 200, wherein the front surface of the substrate to be tested 120 is the front surface 100A of the semiconductor substrate 100.
  • the substrate 120 to be tested is square, and its length ⁇ width dimension is about 1 cm ⁇ 1 cm.
  • the glass slide 200 may also be square, and the size of the glass slide 200 is slightly larger than the size of the substrate 120 to be measured, and the length ⁇ width may be about 1.2 cm ⁇ 1.2 cm.
  • the front surface of the substrate 120 to be tested is pasted on the slide glass 200 by paraffin, and under the premise that the two are firmly pasted, the thinner the paraffin, the better, and the substrate 120 to be tested and the slide glass 200 Avoid air bubbles between them.
  • a process layer such as a dielectric layer, a metal layer, etc. is usually formed on the front surface 100A of the semiconductor substrate 100, so the substrate to be tested Before the front surface of 120 is pasted on the glass slide 200, the process layer on the front surface of the semiconductor substrate 100 needs to be removed.
  • the semiconductor substrate 100 with the process layer grown on the front surface 100A is immersed in hydrofluoric acid, the immersion time can be controlled to about 10 minutes to remove the front surface of the semiconductor substrate 100 Process layer, the front surface 100A of the semiconductor substrate 100 is exposed.
  • the immersion time can be controlled to about 10 minutes to remove the process layer on the front surface of the substrate to be tested 130, The front side of the substrate to be tested 130 is exposed.
  • Step S130 grinding the back surface of the substrate to be tested, and judging whether the substrate to be tested is ground to a target thickness, and if so, stopping the grinding, and grinding the substrate to be tested to the target thickness to form a planar TEM sample.
  • the substrate 120 to be tested is supported and fixed through the glass slide 200, so as to facilitate the thinning of the substrate 120 from the back of the substrate 120 to be tested
  • the back surface of the substrate 120 to be tested is the back surface 100A of the semiconductor substrate 100.
  • the back surface of the substrate to be tested 120 is ground to gradually thin the substrate 120 to the target thickness.
  • a planar TEM sample 130 is formed. The thickness is the thickness of the planar TEM sample 130.
  • the planar TEM sample refers to a sample with the front surface of the semiconductor substrate as the observation surface, and the thickness perpendicular to the front surface conforms to the TEM observation thickness.
  • the grinding strength of the edge of the substrate 120 to be tested is greater than the grinding strength of the middle region.
  • the length and width of the substrate 120 to be measured will be grinded smaller and smaller, but the target needs to be guaranteed Position 110 will not be ground away. As shown in FIG.
  • the size of the substrate to be tested 120 gradually becomes smaller, and because the forces on both sides of the substrate to be tested 120 are not completely uniform, so The grinding speed on one side is slightly higher than the grinding speed on the other side.
  • the method for determining whether the substrate 120 to be tested has been ground to the target thickness may be: Observe whether the edge of the substrate 120 to be tested after the grinding is colored under a microscope If there is a pattern 121, it is further observed whether the target position 110 is on the color pattern 121. If so, it is determined that the substrate 120 to be tested has been ground to a target thickness to form a planar TEM sample 130. In other embodiments, the thickness of the substrate 120 to be measured can also be measured with an instrument.
  • the step of grinding the back surface of the substrate 120 to be tested specifically includes: firstly using 320 mesh, 600 mesh, 800 mesh, and 1200 mesh sandpaper to grind the back surface of the substrate 120 to be tested, and then using a polishing flannel The back surface of the substrate 120 is polished.
  • the polishing speed can be less than the speed of using sandpaper grinding.
  • the relatively fast sandpaper grinding is performed to quickly thin the substrate 120 to be measured, and the mesh number of the sandpaper is adjusted during the grinding process. The higher the mesh number of sandpaper, the grinding The finer, the smoother the surface of the grinding.
  • the substrate 120 to be tested against a fluorescent lamp see if the red light is transmitted near the target position 110 in the substrate 120 to be tested, and observe whether the edges of the substrate 120 to be tested have color lines under the microscope 121. If there is, replace the sandpaper with a polishing flannel, reduce the speed, and continue to polish the substrate 120 to be tested at a low speed to remove debris and scratches near the target location 110 to avoid interference with the observed image. After polishing, observe whether the target position 110 is just on the color pattern 121. If it is, the grinding can be stopped.
  • the substrate 120 to be measured to the target thickness is the planar TEM sample 130.
  • Step S140 Paste the metal ring on the back of the flat TEM sample, and cut the flat TEM sample along the outside of the metal ring to cut off the flat TEM sample outside the metal ring, with the target position at the center of the metal ring.
  • a metal ring 300 needs to be pasted on the back of the planar TEM sample 130, and the planar TEM sample 130 is cut along the outside of the metal ring 300, and The target position 110 is placed at the center of the metal ring 300.
  • the metal ring 300 may be a copper ring.
  • the metal ring 300 is pasted on the back of the planar TEM sample 130 by a two-component epoxy resin adhesive.
  • the two-component epoxy resin adhesive is also called AB glue, which consists of a main agent and a hardener Mixed configuration, where the main agent is A glue and the hardener is B glue.
  • Step S150 separating the planar TEM sample and the slide glass to obtain the planar TEM sample pasted with the metal ring.
  • step S140 the obtained flat TEM sample 130 is pasted with the metal ring 300 and the slide glass 200 on both sides, and the slide glass 200 does not need to be used in the subsequent process.
  • the carrier sheet 200 is separated from the planar TEM sample 130, that is, the slide glass 200 is peeled off to obtain the planar TEM sample 130 that is attached only to the metal ring 300.
  • the planar TEM sample 130 when the planar TEM sample 130 and the slide glass 200 are pasted by paraffin, the planar TEM sample 130 can be immersed in acetone for 20 to 30 minutes to make the planar TEM sample 130 pasted on the metal ring 300 After being separated from the slide glass 200, the metal ring 300 and the planar TEM sample 130 bonded together are taken out from the acetone with tweezers, dried and then subjected to the subsequent process operations.
  • Step S200 The back surface of the planar TEM sample is pasted on the conductive pad with adhesive glue, and the thickness of the adhesive glue is less than or equal to 50 ⁇ m.
  • planar TEM sample 130 is thin and small in size, it is difficult to perform the subsequent cutting process, and the planar TEM sample 130 needs to be fixed on the spacer.
  • the FIB machine will scan the planar TEM sample 130 to obtain a scanned image of the defect before the FIB cutting.
  • the FIB machine scans the planar TEM sample 130 to obtain a scanned image of the defect. Specifically, the FIB machine emits an ion beam to bombard the surface of the planar TEM sample 130.
  • the planar TEM sample 130 generates secondary ions and secondary electrons, and the FIB machine receives the secondary
  • the ions and secondary electrons generate a scanned image based on the secondary ions and secondary electrons, and determine the shape and plane position of the defect from the scanned image, so that precise cutting can be achieved at the defect. Therefore, the spacer in the present application needs to have a certain conductivity to ensure the generation rate of secondary electrons during the scanning process, thereby ensuring the quality of the scanned image.
  • the back surface 130B of the planar TEM sample 130 is pasted on the conductive pad 400 through the adhesive 500, wherein the front surface of the planar TEM sample 130 is the front surface of the original semiconductor substrate 100 100A, the back surface 130B of the planar TEM sample is the side opposite to the front surface 100A.
  • a silicon wafer can be used as the conductive pad 400.
  • the planar TEM sample 130 and the conductive pad 400 are bonded by the adhesive 500.
  • the thickness of the adhesive 500 affects the conductive pad 400
  • the adhesive 500 has little effect on the conductivity of the conductive gasket 400 It can not only fix the planar TEM sample 130 and the conductive pad 400 better, but also ensure the quality of the scanned image.
  • AB glue may be used as the adhesive glue 500. If the adhesive 500 is made of double-sided tape, the surface of the double-sided tape is rough, and it is easy to damage the planar TEM sample 130.
  • the adhesive 500 is made of paraffin
  • the stability of the paraffin is poor, and it will overflow to the front of the planar TEM sample 130 after hot melting. Contaminate the scanning area.
  • AB glue has good viscosity and strong stability, only a little AB glue is needed, and the thickness of the glue is controlled to be 10 ⁇ m to 50 ⁇ m, which can fix the planar TEM sample 130 and the conductive gasket 400 well, and will not damage or pollute the planar TEM sample The front of 130, and will not affect the quality of the FIB scanned image.
  • a small amount of AB glue is coated on the conductive pad 400, the thickness of the glue is controlled to be between 10 ⁇ m and 50 ⁇ m, and the back surface of the planar TEM sample 130 is pasted on the conductive pad 400 and air-dried for 15 minutes to 20 minutes.
  • the metal ring 300 when the metal ring 300 is pasted on the back of the planar TEM sample 130, the metal ring 300 can be pasted on the conductive pad 400 together.
  • step S100 In an embodiment, between step S100 and step S200, the following steps may also be included:
  • step S200 Observe the planar TEM sample to determine whether the defect exists in the planar TEM sample. If so, perform step S200.
  • step S100 when the semiconductor substrate 100 is thinned, if the position of the defect is deep, the defect may be removed during the thinning process. Once the defect is removed, step S200 and subsequent steps are meaningless. Therefore, before step S200, the planar TEM sample 130 may be scanned to determine that the defect is still located in the planar TEM sample 130 before step S200 is performed. If the fabricated planar TEM sample 130 has no defects, that is, the depth of the defect is greater than the TEM The thickness of the sample indicates that this defect is not suitable for analysis by the method of making a TEM sample, and the subsequent steps need to be stopped.
  • Step S300 Determine the shape and plane position of the defect and use a focused ion beam to cut perpendicular to the plane TEM sample at the plane position of the defect to prepare a cross-sectional TEM sample, and the defect is located on the cross-section of the cross-sectional TEM sample.
  • the planar TEM sample 130 can be FIB cut.
  • the FIB machine can scan and cut the flat TEM sample 130. Before cutting, the front of the flat TEM sample 130 is scanned, and the defect morphology and plane position are obtained according to the scanned image, and then the plane TEM is perpendicular to the defect position The sample 130 is subjected to FIB cutting, and a small piece of sample is cut out from the planar TEM sample 130, and the defect is located in the cutting profile, thereby obtaining the profile TEM sample 131. 3a and FIG.
  • the cross-sectional TEM sample 131 has four cut sections, the projections of the four cut sections form a quadrilateral, the defect is located in one of the sections 131C, and the section 131C containing the defect is a vertical section.
  • the cross section 131C may be rectangular or inverted trapezoidal.
  • the section 131C containing defects is defined as a plane formed by the X-axis and the Z-axis.
  • the width direction of the TEM sample 131 in the section is the Y-axis direction
  • the width b of the section TEM sample 131 corresponds to the thickness of the TEM sample, that is, the section TEM sample refers to Taking the section 131C having defects as the observation surface, the thickness (width b) perpendicular to the section direction satisfies the thickness observed by TEM.
  • the width b of the cross-sectional TEM sample 131 is less than or equal to
  • the thickness h of the cross-sectional TEM sample 131 is the thickness of the planar TEM sample 130.
  • the thickness h is less than or equal to
  • the length a of the cross-sectional TEM sample 131 is relatively long, which may be on the order of micrometers, that is, the cross-sectional TEM sample 131 may have a long strip structure. Observing the cross-sectional TEM sample 131 is actually observing the cross-sectional TEM sample 131 having a defective cross-section 131C. The width b of the cross-sectional TEM sample 131 satisfies the TEM observation thickness so that the cross-section can be TEM-scanned to form a clear scan image.
  • FIG. 5 is a front scan image obtained by scanning a planar TEM sample 130, wherein the morphology and plane position of the defect can be obtained from the scan image.
  • the defect dashed line (In frame) is linear.
  • FIG. 6 a cross-sectional view formed by cutting FIG. 5. The defect (in the dotted frame) is located in the cross-section. After acquiring the cross-sectional image, the depth of the defect can be measured.
  • the above TEM sample preparation method can prepare a profile TEM sample, and the defect is located on the profile of the profile TEM sample.
  • information about the defect in the thickness direction of the semiconductor substrate, such as the depth of the defect can be obtained.
  • the manufacturing process of the semiconductor device that causes the defect can be deduced from the acquired defect information, so as to improve the process, avoid more products from having the same problem, and thus improve the product yield.

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Abstract

一种TEM样品制备方法，包括，S100：确定半导体衬底(100)上存在缺陷的目标位置(110)，对半导体衬底(100)的背面(100B)进行减薄，制成平面TEM样品(130)，目标位置(110)位于平面TEM样品(130)内；S200：用粘合胶(500)将平面TEM样品(130)的背面(130B)粘贴于导电垫片(400)上，粘合胶(500)的厚度小于或等于50um；S300：确定缺陷的平面形貌和位置并采用聚焦离子束在缺陷位置处垂直于平面TEM样品(130)进行切割，制成剖面TEM样品(131)，缺陷位于剖面TEM样品(131)的剖面(131C)上。

Description

TEM样品制备方法
相关申请
本申请要求于2019年01月03日提交中国专利局的、申请号为201910003403.4、申请名称为“TEM样品制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种TEM样品制备方法。
背景技术
在半导体器件制备工艺中，通常包含对半导体衬底进行阱注入、离子推进、退火等工序，容易使半导体衬底内部晶格排列发生错乱而产生缺陷。同时，随着半导体器件尺寸的越来越小，半导体器件集成度越来越高，缺陷对器件的良率和可靠性的影响越来越大。因此在半导体器件失效分析中，找到半导体衬底缺陷的位置并获取缺陷的相关信息，可以反推出导致该缺陷的工序，从而可以对相关工序进行改进，避免后续出现类型缺陷，提高产品良率和器件的可靠性。目前，有两种方法可以获知缺陷信息：一种是对半导体衬底进行化学腐蚀并利用SEM(scanning electron microscopy，扫描电子显微镜)进行观察，可以确定半导体衬底上是否存在缺陷以及缺陷的大概位置，但是对于缺陷的具体位置和形貌无法获知；另一种是制备平面TEM(Transmission Electron Microscope，透射电镜)样品并利用TEM进行观察，可以获取缺陷的平面位置及平面形貌，但是无法获知半导体衬底厚度方向的缺陷信息，如 缺陷的深度信息，由此使半导体器件的失效分析受到限制。
发明内容
根据本申请的各种实施例提供一种TEM样品制备方法。
一种TEM样品制备方法，包括：
确定半导体衬底上存在缺陷的目标位置并从所述半导体衬底的背面对所述半导体衬底进行减薄，制成平面TEM样品，所述目标位置位于所述平面TEM样品内；
用粘合胶将所述平面TEM样品的背面粘贴于导电垫片上，所述粘合胶的厚度小于或等于50μm；及
确定所述缺陷的形貌和平面位置并采用聚焦离子束在所述缺陷的所述平面位置处垂直于所述平面TEM样品进行切割，制成剖面TEM样品，所述缺陷位于所述剖面TEM样品的剖面上。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为本申请一实施例中TEM样品制备方法的步骤流程图；
图2a至2e为本申请一实施例中制备平面TEM样品各步骤对应的结构示意图；
图3a为本申请一实施例中平面TEM样品与导电垫片粘贴后的俯视图；
图3b为本申请一实施例中平面TEM样品与导电垫片粘贴后的侧面剖视图；
图4为本申请一实施例中剖面TEM样品的结构示意图；
图5为本申请一实施例中平面TEM样品正面的扫描电镜图；
图6为对图5平面TEM样品切割形成剖面TEM样品的剖面的扫描电镜图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本申请，将在下列的描述中提出详细步骤以及结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
如图1所示，TEM样品制备方法包括：
步骤S100：确定半导体衬底上存在缺陷的目标位置并从半导体衬底的背面对半导体衬底进行减薄，制成平面TEM样品，目标位置位于平面TEM样品内。
半导体衬底内经过如阱注入、退火等一系列工序后，其内部晶格排布会发生改变，从而在半导体衬底内部产生缺陷。如图2a所示，定义半导体衬底100的长度方向为X轴，定义半导体衬底100的宽度方向为Y轴，定义半导体衬底100的厚度方向为Z轴。在本申请中，先确定半导体衬底100上存在缺陷的目标位置110，该目标位置110为在X轴和Y轴所形成的二维平面内的二维坐标，即只能在X轴和Y轴所形成的二维平面内定位该目标位置110，该目标位置110不包含缺陷的Z轴坐标。由于利用扫描仪进行观察时，只能 获取平面图像信息，因此该目标位置110实际为缺陷在半导体衬底100观测面的投影位置。
半导体衬底100具有正面100A和背面100B，其中，从半导体衬底100的正面100A对半导体衬底100进行上述工序后容易在半导体衬底100内引起缺陷，因此，缺陷更加靠近于半导体衬底100的正面100A。确定好存在缺陷的目标位置110后，从半导体衬底100的背面100B对半导体衬底100减薄，制成平面TEM样品。在一些实施例中，对半导体衬底100减薄过程中会逐渐缩小半导体衬底100的尺寸，但是该目标位置110处的半导体衬底100不能被去除，即最终得到的平面TEM样品内需包含该目标位置110。需要说明的是，平面TEM样品指的是半导体衬底100减薄后在Z轴方向的厚度满足TEM观察厚度，在本实施例中，平面TEM样品的厚度小于或等于
Figure PCTCN2019127439-appb-000001
且其厚度越小，获取的图像质量越好，在一实施例中，平面TEM样品的厚度小于或等于
Figure PCTCN2019127439-appb-000002
在一实施例中，步骤S100具体可以包括：
步骤S110：在半导体衬底的正面标记出存在缺陷的目标位置。
在一实施例中，对于定点样品，可通过数地址或定亮点的方式确定目标位置110，对于非定点样品，可通过SEM观察缺陷在衬底中的大概位置并作为目标位置110。确定目标位置110后，可通过激光或FIB在目标位置110处对半导体衬底100进行标记，以便于在后续工序中识别该目标位置110。在一实施例中，该标记可为十字标记。
步骤S120：对半导体衬底进行切割形成待测衬底，将待测衬底的正面粘贴于载玻片上，目标位置位于所述待测衬底的中心位置。
通常，直接获取的半导体衬底100尺寸较大，而半导体衬底100内的缺陷尺寸很小，对缺陷进行分析时不需要使用整块半导体衬底100。在本实施例中，如图2b所示，先围绕缺陷对半导体衬底100进行切割，获取包含缺陷区域的待测衬底120，即步骤S110中的标记处于待测衬底120的中心位置，再将待测衬底120的正面粘贴于载玻片200上，其中，待测衬底120的正面 为半导体衬底100的正面100A。在一实施例中，待测衬底120呈正方形，其长×宽的尺寸约为1cm×1cm。在一实施例中，载玻片200也可呈正方形，载玻片200的尺寸略大于待测衬底120的尺寸，其长×宽的尺寸可约为1.2cm×1.2cm。在一实施例中，待测衬底120的正面通过石蜡粘贴于载玻片200上，且在两者粘贴稳固的前提下，石蜡越薄越好，且待测衬底120与载玻片200之间需避免出现气泡。
由于通常是在做半导体器件失效分析时需要获取半导体衬底100的缺陷信息，半导体衬底100的正面100A上通常还形成有工艺层，如介质层、金属层等，因此在将待测衬底120的正面粘贴于载玻片200上前，需去除半导体衬底100正面上的工艺层。在一实施例中，在切割半导体衬底前，将正面100A生长有工艺层的半导体衬底100置于氢氟酸中浸泡，浸泡的时间可控制为约10分钟，以去除半导体衬底100正面的工艺层，暴露出半导体衬底100的正面100A。在另一实施例中，在切割半导体衬底后，将待测衬底130置于氢氟酸中浸泡，浸泡的时间可控制为约10分钟，以去除待测衬底130正面的工艺层，暴露出待测衬底130的正面。
步骤S130：对待测衬底的背面进行研磨，判断待测衬底是否研磨至目标厚度，若是，则停止研磨，待测衬底研磨至目标厚度后形成平面TEM样品。
将待测衬底120的正面粘贴于载玻片200上后，通过载玻片200对待测衬底120进行支撑与固定，以方便从待测衬底120的背面对待测衬底120进行减薄，其中，待测衬底120的背面为半导体衬底100的背面100A。在一实施例中，通过对待测衬底120的背面进行研磨以逐渐减薄该待测衬底120至目标厚度，待测衬底120减薄至目标厚度后，形成平面TEM样品130，该目标厚度即为平面TEM样品130的厚度，即平面TEM样品指的是以半导体衬底的正面作为观察面，垂直于正面的厚度符合TEM观察厚度的样品。通常，在研磨过程中，待测衬底120边缘的研磨强度大于中间区域的研磨强度，在研磨过程中，待测衬底120的长宽尺寸会被研磨得越来越小，但是需保证目标位置110不会被研磨掉。如图2c所示，在一实施例中，在待测衬底120研 磨过程中，待测衬底120的尺寸逐渐变小时，又由于待测衬底120两侧受力并不完全均一，因此会有一侧的研磨速度略大于另一侧的研磨速度，判断待测衬底120是否已经被研磨至目标厚度的方法可为：在显微镜下观察研磨后的待测衬底120边缘处是否有彩纹121，若有，则进一步观察目标位置110是否处于该彩纹121上，若是，则判断出待测衬底120已经研磨至目标厚度，形成平面TEM样品130。在其他实施例中，也可以用仪器测量待测衬底120的厚度。
在一实施例中，对待测衬底120的背面进行研磨的步骤具体包括：先依次使用320目、600目、800目和1200目的砂纸对待测衬底120的背面进行研磨，再使用抛光绒布对待测衬底120的背面进行抛光。其中，抛光的速度可小于使用砂纸研磨的速度，先进行速度相对较快的砂纸研磨，快速减薄待测衬底120，且研磨过程中调整砂纸的目数，砂纸的目数越高，研磨越精细，研磨处的表面越光滑。高速研磨至一定程度后，将待测衬底120对着日光灯观察，看待测衬底120中的目标位置110附近是否透红光，并在显微镜下观察待测衬底120的边缘是否有彩纹121，若有，则将砂纸换成抛光绒布，降低速度，对待测衬底120继续低速抛光，以去除目标位置110附近的碎屑和划痕，避免其对观测图像造成干扰。抛光后再观察目标位置110是否正好处于彩纹121上，若是，则可以停止研磨，被研磨至目标厚度的待测衬底120即为平面TEM样品130。
步骤S140：将金属环粘贴于平面TEM样品的背面，并沿金属环外侧对平面TEM样品进行切割以切除金属环外侧的平面TEM样品，目标位置位于金属环的中心位置。
在一些实施例中，如图2d所示，为配合后续平面TEM样品130的观测，需在平面TEM样品130的背面粘贴金属环300，并沿金属环300外侧对平面TEM样品130进行切割，并使目标位置110处于金属环300的中心位置。在一实施例中，金属环300可为铜环。在一实施例中，金属环300通过双组份环氧树脂粘合剂粘贴于平面TEM样品130的背面，双组份环氧树脂粘合剂又 称AB胶水，AB胶水由主剂和硬化剂混合配置而成，其中，主剂为A胶，硬化剂为B胶，具体可为将A胶和B胶混合形成AB胶水后，将金属环300蘸少量AB胶水贴于平面TEM样品130的背面，并使目标位置110处于金属环300的中心，将粘贴在一起的金属环300、平面TEM样品130和载玻片200一同放进氮气柜中风干15分钟，使胶水固化，然后用美工刀沿金属环300外侧切断平面TEM样品130。
步骤S150：分离平面TEM样品和载玻片，得到与金属环粘贴的平面TEM样品。
经过步骤S140，得到的平面TEM样品130两侧分别粘贴有金属环300和载玻片200，在后续工序中，不需要使用到载玻片200。如图2e所示，使载波片200与平面TEM样品130分离，即将载玻片200剥离出来，得到仅与金属环300粘贴的平面TEM样品130。在一实施例中，当平面TEM样品130与载玻片200通过石蜡粘贴时，可将平面TEM样品130置于丙酮中浸泡20分钟至30分钟，使粘贴在金属环300上的平面TEM样品130与载玻片200分离，然后将粘合在一起的金属环300和平面TEM样品130用镊子从丙酮中取出，晾干后进行后续工序操作。
步骤S200：用粘合胶将平面TEM样品的背面粘贴于导电垫片上，粘合胶的厚度小于或等于50μm。
由于平面TEM样品130较薄且尺寸较小，难以进行后续的切割工艺，需要将平面TEM样品130固定于垫片上。在本申请中，由于平面TEM样品130后续要进行FIB(Focused Ion beam，聚焦离子束)切割，在FIB切割前FIB机台会对平面TEM样品130进行扫描以获取缺陷的扫描图像。FIB机台对平面TEM样品130扫描以获取缺陷的扫描图像具体是FIB机台发射离子束轰击平面TEM样品130表面，平面TEM样品130产生二次离子和二次电子，FIB机台接收该二次离子和二次电子并根据该二次离子和二次电子生成扫描图像，从扫描图像中确定缺陷的形貌和平面位置，从而可以实现在缺陷处精准切割。因此，在本申请中的垫片需要有一定的导电性，以保证扫描过程中二次电子 的产生率，从而确保扫描图像的质量。结合图3a和图3b所示，在本实施例中，平面TEM样品130的背面130B通过粘合胶500粘贴于导电垫片400上，其中平面TEM样品130的正面为原始半导体衬底100的正面100A，平面TEM样品的背面130B为与正面100A相对的一面。在一实施例中，可使用硅片作为导电垫片400。在本申请中，平面TEM样品130和导电垫片400通过粘合胶500粘合，由于扫描图像的质量受导电垫片400导电性的影响，而粘合胶500的厚度会影响导电垫片400的导电性，在本申请中，通过控制粘合胶500的厚度小于或等于50μm，具体可为10μm至50μm，在该厚度尺寸下，粘合胶500对导电垫片400的导电性基本没有影响，既能使平面TEM样品130与导电垫片400较好固定，也可以保证扫描图像的质量。在一实施例中，粘合胶500可选用AB胶水。若粘合胶500选用双面胶带，双面胶带的表面粗糙，容易损坏平面TEM样品130，若粘合胶500选用石蜡，石蜡稳定性较差，热熔后会溢到平面TEM样品130正面，污染扫描区域。AB胶水粘性较好且稳定性强，只需少许的AB胶水，控制胶水的厚度为10μm至50μm，可以很好地固定平面TEM样品130和导电垫片400，也不会损坏或污染平面TEM样品130的正面，并且不会影响FIB扫描图像的质量。在一具体的实施例中，在导电垫片400上涂覆少量AB胶水，控制胶水厚度在10μm至50μm之间，将平面TEM样品130的背面粘贴于导电垫片400上，晾干15分钟至20分钟即可。在一实施例中，当平面TEM样品130的背面粘贴有金属环300时，可一同将金属环300粘贴于导电垫片400上。
在一实施例中，在步骤S100和步骤S200之间，还可包括如下步骤：
对平面TEM样品进行观察，判断平面TEM样品内是否存在所述缺陷，若存在，则执行步骤S200。
在步骤S100中，对半导体衬底100进行减薄时，若缺陷位置较深，在减薄过程中也可能将缺陷去掉，一旦缺陷被去除，步骤S200及后续的工序均没有意义。因此，可在步骤S200前，对平面TEM样品130进行扫描，确定缺陷还位于平面TEM样品130内后才实施步骤S200，若制成的平面TEM样品 130中不存在缺陷，即缺陷的深度大于TEM样品厚度，说明此缺陷不适合通过制成TEM样品的方法进行分析，需停止后续步骤。
步骤S300：确定缺陷的形貌和平面位置并采用聚焦离子束在缺陷的平面位置处垂直于平面TEM样品进行切割，制成剖面TEM样品，缺陷位于剖面TEM样品的剖面上。
将平面TEM样品130固定于导电垫片400上后，便可对平面TEM样品130进行FIB切割。FIB机台可以对平面TEM样品130进行扫描和切割，在切割前，先对平面TEM样品130的正面进行扫描，并根据扫描图像获取缺陷的形貌和平面位置，然后在缺陷位置处垂直平面TEM样品130进行FIB切割，从平面TEM样品130内切割出一小块样品，且缺陷位于切割剖面内，从而获取剖面TEM样品131。结合图3a和图4所示，剖面TEM样品131具有四个切割剖面，该四个切割剖面的投影形成一四边形，缺陷位于其中的一个剖面131C内，且包含缺陷的剖面131C为垂直剖面。在一实施例中，该剖面131C可为矩形，也可为倒梯形。定义包含缺陷的剖面131C为X轴和Z轴构成的平面，该剖面TEM样品131的宽度方向为Y轴方向，则该剖面TEM样品131的宽度b符合TEM样品厚度，即剖面TEM样品指的是以具有缺陷的剖面131C为观察面，垂直于该剖面方向的厚度(宽度b)满足TEM观察的厚度。在一实施例中，剖面TEM样品131的宽度b小于或等于
Figure PCTCN2019127439-appb-000003
该剖面TEM样品131的厚度h为平面TEM样品130的厚度，在一实施例中，该厚度h小于或等于
Figure PCTCN2019127439-appb-000004
剖面TEM样品131的长度a相对较长，可为微米级别，即剖面TEM样品131可为一长条形结构。对剖面TEM样品131进行观测实际为对剖面TEM样品131具有缺陷的剖面131C进行观察，剖面TEM样品131的宽度b满足TEM观测厚度，以能够对该剖面进行TEM扫描形成清晰的扫描图像。在一实施例中，制成剖面TEM样品131后，可对剖面TEM样品131具有缺陷的剖面131C进行扫描，获取该剖面的扫描图像，找到缺陷在该剖面的位置，从而可以测量出该缺陷的深度。在一具体的实施例中，如图5为对平面TEM样品130进行扫描得到的正面扫描图像，其中，可从该扫描 图像中获取缺陷的形貌和平面位置，在该图中，缺陷(虚线框内)呈线型状。如图6为对图5进行切割形成的剖面图，缺陷(虚线框内)位于该剖面内，获取该剖面图像后，可以测量缺陷的深度。
上述TEM样品制备方法，可以制备出剖面TEM样品，且缺陷位于该剖面TEM样品的剖面上，通过观测剖面TEM样品的剖面，可以获取缺陷在半导体衬底厚度方向的信息，如缺陷的深度，从而可以从获取到的缺陷信息推导出导致该缺陷的半导体器件制备工序，以便对该工序进行改进，避免更多产品出现相同问题，从而提高产品良率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种TEM样品制备方法，包括：
    确定半导体衬底上存在缺陷的目标位置，并从所述半导体衬底的背面对所述半导体衬底进行减薄，制成平面TEM样品，所述目标位置位于所述平面TEM样品内；
    用粘合胶将所述平面TEM样品的背面粘贴于导电垫片上，所述粘合胶的厚度小于或等于50μm；及
    确定所述缺陷的形貌和平面位置，并采用聚焦离子束在所述缺陷的所述平面位置处垂直于所述平面TEM样品进行切割，制成剖面TEM样品，所述缺陷位于所述剖面TEM样品的剖面上。
  2. 如权利要求1所述的制备方法，其中，在所述制成平面TEM样品后的步骤后，以及在所述用粘合胶将所述平面TEM样品的背面粘贴于导电垫片上的步骤之前，还包括：
    对所述平面TEM样品进行观察，判断所述平面TEM样品内是否存在所述缺陷，若存在，则执行所述用粘合胶将所述平面TEM样品的背面粘贴于导电垫片上的步骤。
  3. 如权利要求1所述的制备方法，其中，所述导电垫片为硅片。
  4. 如权利要求1所述的制备方法，其中，所述粘合胶为双组份环氧树脂粘合剂。
  5. 如权利要求1所述的制备方法，其中，所述粘合胶的厚度范围为10μm～50μm。
  6. 如权利要求1所述的制备方法，其中，在制成所述剖面TEM样品之后，还包括：
    对所述剖面TEM样品的所述剖面进行观察并测量所述缺陷的深度。
  7. 如权利要求1所述的制备方法，其中，所述平面TEM样品的厚度小于或等于
    Figure PCTCN2019127439-appb-100001
  8. 如权利要求1所述的制备方法，其中，所述确定半导体衬底上的缺陷区域并从所述半导体衬底的背面对所述半导体衬底进行减薄，制成平面TEM样品的步骤具体包括：
    在所述半导体衬底的正面标记出存在缺陷的目标位置；
    对所述半导体衬底进行切割形成待测衬底，将所述待测衬底的正面粘贴于载玻片上，所述目标位置位于所述待测衬底的中心位置；
    对所述待测衬底的背面进行研磨，判断所述待测衬底是否研磨至目标厚度，若是，则停止研磨，所述待测衬底研磨至所述目标厚度后形成所述平面TEM样品；
    将金属环粘贴于所述平面TEM样品的背面，并沿所述金属环外侧对所述平面TEM样品进行切割以切除所述金属环外侧的所述平面TEM样品，所述目标位置位于所述金属环的中心位置；及
    分离所述平面TEM样品和所述载玻片，得到与所述金属环粘贴的所述平面TEM样品。
  9. 如权利要求8所述的制备方法，其中，在所述将所述待测衬底的正面粘贴于载玻片上的步骤之前，还包括：
    将所述待测衬底置于氢氟酸中浸泡以去除所述待测衬底正面上的工艺层，暴露出所述半导体衬底的正面。
  10. 如权利要求8所述的制备方法，其中，所述对所述待测衬底的背面进行研磨的步骤具体包括：
    先依次使用320目、600目、800目和1200目的砂纸对所述待测衬底的背面进行研磨，再使用抛光绒布对所述待测衬底的背面进行抛光。
  11. 如权利要求8所述的制备方法，其中，所述判断所述待测衬底是否研磨至目标厚度，包括：
    在显微镜下观察所述待测衬底的边缘是否出现彩纹以及所述目标位置是否处于所述彩纹上，若是，则判定所述待测衬底已研磨至目标厚度。
  12. 如权利要求8所述的制备方法，其中，所述将所述待测衬底的正面 粘贴于载玻片上，包括：通过石蜡将所述待测衬底的正面粘贴于载玻片上；
    所述分离所述平面TEM样品和所述载玻片，包括：将所述平面TEM样品置于丙酮中浸泡，使所述平面TEM样品与所述载玻片分离。
  13. 如权利要求1所述的制备方法，其中，确定所述缺陷的形貌和平面位置，包括：利用FIB机台发射离子束轰击所述平面TEM样品的表面，并接收所述平面TEM样品产生的二次离子和二次电子，根据所述二次离子和二次电子生成扫描图像，从扫描图像中确定缺陷的形貌和平面位置。
  14. 如权利要求1所述的制备方法，其中，所述剖面TEM样品呈长条型，所述剖面TEM样品的长度为微米级别，所述剖面TEM样品的宽度小于或等于
    Figure PCTCN2019127439-appb-100002
  15. 如权利要求1所述的制备方法，其中，所述剖面TEM样品的剖面为矩形或倒梯形。
PCT/CN2019/127439 2019-01-03 2019-12-23 Tem样品制备方法 Ceased WO2020140785A1 (zh)

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