WO2020135257A1 - 一种能减少漏电流的可寻址测试芯片及其测试系统 - Google Patents

一种能减少漏电流的可寻址测试芯片及其测试系统 Download PDF

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WO2020135257A1
WO2020135257A1 PCT/CN2019/126994 CN2019126994W WO2020135257A1 WO 2020135257 A1 WO2020135257 A1 WO 2020135257A1 CN 2019126994 W CN2019126994 W CN 2019126994W WO 2020135257 A1 WO2020135257 A1 WO 2020135257A1
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test
leakage current
circuit
transmission gate
switch circuit
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PCT/CN2019/126994
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French (fr)
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蓝帆
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杭州广立微电子有限公司
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Publication of WO2020135257A1 publication Critical patent/WO2020135257A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Definitions

  • the invention relates to the field of semiconductor design and production, in particular to an addressable test chip and test system capable of reducing leakage current.
  • the independent test chip has a large area and needs to occupy the position of one chip, which is equivalent to the semiconductor manufacturer having to pay the manufacturing cost of this part of the area mask.
  • the dicing groove is the space reserved for cutting chips on the wafer.
  • the test chip is placed in the dicing groove so that it does not occupy the position of the chip. This eliminates the need for semiconductor manufacturers to bear the cost of expensive masks and saves a lot the cost of.
  • the short-range test chip needs to connect the test unit to the PAD (pad) separately, and each test structure requires two or more PADs, which results in a low area utilization rate of the short-range test chip.
  • the general addressable test chip introduces an address decoding circuit similar to the static memory chip, which greatly reduces the number of PADs and relatively increases the area utilization of the test chip.
  • the general addressable test chip is a general-purpose test chip with an addressable circuit, which is composed of four basic structures: an addressing circuit, a switching circuit, a device under test (DUT), and a pad.
  • the addressing circuit is connected to the switch circuit, and outputs an address signal to control the on-off state of the switch in the switch circuit; the switch circuit is connected to the device under test to select a specific DUT for measurement through the on-off state of the switch.
  • the entire DUT area can be divided into several small DUT areas, that is, the DUT is divided into several arrays, and then switches are set between different arrays. Circuit and addressing circuit.
  • a better design is to use only one DUT array for testing. All DUTs are in the same DUT area, and there are no redundant circuits or devices in this DUT area, which is more similar to the real chip. scenes to be used.
  • the peripheral circuits it configures will have more switching circuits. According to the principle of addressable testing, each group of test ports Only one DUT is selected for testing, and the remaining unselected switching circuits will increase leakage current. With the current switch circuit structure, the leakage current will reach a leakage current of tens or even hundreds of nanoamperes, resulting in inaccurate measurement of the test chip.
  • the main purpose of the present invention is to overcome the shortcomings in the prior art and provide an addressable test chip and test system, which can effectively reduce the leakage current during the measurement process.
  • the invention discloses an addressable test chip capable of reducing leakage current.
  • the test chip includes a switch circuit, an address circuit, several devices to be tested and several pads; the output terminal of the address circuit is connected to the input terminal of the switch circuit ,
  • the addressing circuit controls the on and off of the switch in the switch circuit; the output of the switch circuit is connected to the input of the device under test, and the device under test is selected by the on and off state of the switch; the feature is that the addressing circuit includes several decoding
  • the switch circuit includes multiple transmission gates, among which several transmission gates are a group, and the input terminals of the same group of transmission gates are connected to the same decoder in the addressing circuit; multiple groups of transmission gates are connected in multiples according to the signal transmission direction
  • the transmission gate structure of the first level in which the output terminal of the higher-level transmission gate is connected to the input terminal of the lower-level transmission gate connected to it, and the output terminal of the lowest-level transmission gate is connected to the test signal line of the device under test.
  • each transmission gate in the same group of transmission gates has the same number of lower-level transmission gates.
  • the type of each decoder in the addressing circuit is determined according to the group of connected transmission gates: the number of digital signal output bits of the decoder is not less than the number of transmission gates in the group of transmission gates connected to it number.
  • all the devices under test are distributed in the same DUT array, and the switching circuit and the addressing circuit are arranged on the periphery of the DUT array.
  • the above addressable test chip that can reduce leakage current uses multi-level transmission gates as the switching circuit, which can realize that all devices under test (DUT) are in the same DUT area, and there are no extra circuits or equipment in this DUT area, only Use a DUT array for testing, which is more similar to the real use scenario of the chip.
  • the addressable test chip that can reduce the leakage current can realize the device under test without array division, and of course can also be applied to the case where the array under test is divided, that is, each divided DUT array needs to be configured with a set of switches Circuit and addressing circuit, and the addressing circuit of the entire test chip also needs to configure an array selection decoder for DUT array selection.
  • the switch circuit includes a row switch circuit and a column switch circuit
  • the address circuit includes a row address decoder and a column address decoder
  • the row address decoder is connected to the row switch circuit and is used to control the row switch circuit selection The row of the device under test is determined
  • the column address decoder is connected to the column switch circuit and is used to control the column switch circuit to select the column of the device under test.
  • the invention also provides an addressable test system capable of reducing leakage current, including a test instrument, a probe card and the above addressable test chip capable of reducing leakage current, a test instrument and an addressable test chip capable of reducing leakage current Connected through the probe card and constitute the test path.
  • the above addressable test system capable of reducing leakage current also includes a multi-purpose address register, which is connected to the test instrument, and is also connected to the input terminal of the addressing circuit in the addressable test chip, and can implement a counter according to changes in external signals Or the function of the shifter.
  • a multi-purpose address register which is connected to the test instrument, and is also connected to the input terminal of the addressing circuit in the addressable test chip, and can implement a counter according to changes in external signals Or the function of the shifter.
  • the addressable test chip capable of reducing leakage current of the present invention 1) uses a multi-level transmission gate circuit as a switching circuit to control the leakage current; 2) uses a complete DUT area for testing on the test chip without dividing the DUT array , More similar to the real use scenario of the chip; 3) compatible with the test process of the general addressable test chip; 4) can be used to measure test objects in real hot products.
  • the addressable test chip system capable of reducing leakage current of the present invention uses the above addressable test chip capable of reducing leakage current to achieve the same advantages as above.
  • FIG. 1 is a schematic diagram of a DUT array layout of an existing test chip.
  • FIG. 2 is a schematic diagram of the DUT array layout of the test chip of the present invention.
  • FIG. 3 is a schematic structural diagram of a test chip of the present invention.
  • FIG. 4 is a schematic diagram of an embodiment of a first-level transmission gate.
  • FIG. 5 is a schematic diagram of an embodiment of a secondary transmission gate.
  • FIG. 6 is a schematic diagram of an embodiment of a three-level transmission gate.
  • Fig. 7 is a schematic diagram of the first-level transmission gate and decoder.
  • Fig. 8 is a schematic diagram of a three-level transmission gate and a decoder.
  • An addressable test chip capable of reducing leakage current as shown in Figures 2, 3, and 4 includes a switching circuit, an addressing circuit, several devices under test and several pads; the addressing circuit is connected to the switching circuit, Used to output address signals to control the on-off state of the switch in the switch circuit; the switch circuit is connected to the device under test to select the specified device under test through the on-off state of the switch.
  • the addressing circuit includes several decoders.
  • the switch circuit uses a multi-level transmission gate circuit. Each stage of the multi-level transmission gate circuit includes several transmission gate structures. The input end of the lower-level transmission gate structure is connected to the output end of the higher-level transmission gate structure. The output terminal of the gate structure is connected to the test signal line of the device under test; the input terminal of each transmission gate structure is also connected to the decoder in the addressing circuit, and the input terminal of the transmission gate structure of the same level is the same Coder connection.
  • the peripheral circuits configured there will have more switching circuits. According to the principle of addressable testing, only one DUT is selected for testing in each group of test ports at a time, and the rest are not selected. The switching circuit will increase the leakage current.
  • the above addressable test chip capable of reducing leakage current uses a multi-level transmission gate circuit as a switching circuit to reduce leakage current, so the leakage current Ioff, etc. can be accurately measured to ensure accurate measurement of the test chip.
  • each transmission gate structure of the same stage has the same number of lower-level transmission gate structures connected. This ensures that the leakage current of each device under test is the same during measurement, and the numerical accuracy of each device under test is the same.
  • the addressing circuit includes several types of decoders, the type of the decoder is selected according to the multi-level transmission gate circuit: the number of digital signal output bits of the decoder is N, and the K-th level transmission in the multi-level transmission gate circuit
  • the input of the door mechanism is connected to the output of the decoder.
  • K is an integer greater than 1, that is, the multi-level transmission gate circuit includes at least two levels; the value of N is not less than the number of the K-th transmission gate structure, that is, the number of digital signal output bits can be equal to the K-th transmission gate structure
  • the number of decoders can also be a decoder with a digital signal output bit number more than the number of the K-th stage transmission gate structure.
  • the device under test is not divided into arrays, that is, all the devices under test are in the same DUT area, and the switching circuit and the decoder are all arranged in the periphery of the DUT area.
  • the above addressable test chip capable of reducing leakage current uses multi-level transmission gates as switching circuits to reduce leakage current, making it possible to not divide the DUT array, that is, there is no extra circuit or equipment in the DUT area, and only one DUT is used The array is tested, which is more similar to the real use scenario of the chip.
  • the addressable test chip that can reduce the leakage current can realize that the device under test is not divided into arrays, and of course can be applied to the case where the array under test is divided, that is, each divided DUT array needs to be configured with a set of switches Circuit and addressing circuit, and the addressing circuit of the entire test chip also needs to configure an array selection decoder for DUT array selection.
  • the switch circuit includes a row switch circuit and a column switch circuit
  • the address circuit includes a row address decoder and a column address decoder
  • the row address decoder is connected to the row switch circuit and is used to control the row
  • the switch circuit selects the row of the device under test
  • the column address decoder is connected to the column switch circuit and is used to control the column switch circuit to select the column of the device under test.
  • the row address decoder outputs an address signal to control the on-off state of the switch in the row switch circuit, select the row where the structure under test is located, and the column address decoder outputs an address signal to control the on-off state of the switch in the column switch circuit Select the column where the structure under test is located, the test structure under test is uniquely turned on, and the test signal can smoothly enter the test structure for inspection.
  • An addressable test system capable of reducing leakage current includes a test instrument, a probe card and the above addressable test chip capable of reducing leakage current, the test instrument and the addressable test chip capable of reducing leakage current pass through the probe The cards are connected and form a test path.
  • the addressable test system uses a multi-level transmission gate circuit as the test chip of the switch circuit, which can reduce the leakage current.
  • the following provides examples to illustrate that the switching circuit uses a multi-level transmission gate circuit, which is compatible with the test process of the original addressable test chip and can control the leakage current, so that it is not possible to divide the DUT array and can be used to measure real hot products. Crystal test object.
  • the output terminals of the 1024 transmission gate structures are respectively connected to the test signal lines of the device under test, and the input terminals of the 1024 transmission gate structures are all connected to the same decoder.
  • the decoder uses a 10-1024 decoder, and the output of the 10-1024 decoder is connected with a structure of 1024 transmission gates.
  • 1024 DUTs are led out through the 32-32 two-stage transmission gate circuit.
  • the leakage current Ioff cannot be accurately measured, it can detect some leakage current Ioff abnormalities and can also measure the threshold voltage Vt relatively accurately.
  • the 8-8-16 three-level transmission gate circuit includes (8+64+1024) transmission gate structures, so a 3-8 decoder, a 6-64 decoder, and a 10-1024 translator are used.
  • the encoder is respectively connected to the input end of the third-stage transmission gate structure, the input end of the second-stage transmission gate structure, and the input end of the first-stage transmission gate structure.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种能减少漏电流的可寻址测试芯片及其测试系统，测试芯片包括开关电路、寻址电路、若干待测器件和若干焊盘；寻址电路的输出端连接到开关电路的输入端；开关电路的输出端与待测器件的输入端相连，通过开关的通断状态选定待测器件；寻址电路包括若干译码器，开关电路包括多个传输门，其中若干个传输门为一组，同一组传输门的输入端连接到寻址电路中的同一个译码器；多组传输门按信号传递方向连接成多级传输门结构，其中高一级的传输门的输出端连接到与之相连的低一级传输门的输入端，最低一级传输门的输出端与待测器件的测试信号线相连，能够在测量过程中有效地减少漏电流。

Description

一种能减少漏电流的可寻址测试芯片及其测试系统 技术领域
本发明是关于半导体设计和生产领域，特别涉及一种能减少漏电流的可寻址测试芯片及其测试系统。
 背景技术
传统统半导体制造通过短程测试芯片来测试获取生产工艺的缺陷率和成品率，根据在晶圆内放置位置的不同，可分为两类：独立测试芯片和放置在划片槽内的测试芯片。独立测试芯片面积较大，需要占据一个芯片的位置，这样就相当于半导体制造厂商需要支付这一部分面积掩模的制造费用。划片槽是晶圆上为切割芯片时预留的空间，将测试芯片放置于划片槽，可以不占据芯片的位置，这使半导体制造厂商就不需要承担昂贵的掩模费用，节省了大量的成本。
但是短程测试芯片需要将测试单元单独的连接到PAD（焊盘）上，每个测试结构需要两个或多个PAD，这造成了短程测试芯片的面积利用率很低。基于这个考虑，普通可寻址测试芯片通过引入类似于静态记忆体芯片的地址译码电路，大大减少了PAD的数量，相对提高了测试芯片的面积利用率。
普通可寻址测试芯片（Test Chip）是通用的带有可寻址电路的测试芯片，由寻址电路、开关电路、待测器件（DUT）、焊盘（pad）四部分基本结构构成，其中寻址电路与开关电路相连，且输出地址信号以控制开关电路中的开关通断状态；开关电路与待测器件相连，以通过开关的通断状态选择特定的DUT进行测量。
如图1所示，对于区域放置较多DUT的测试芯片，可以将其整个DUT区域划分成若干个小DUT区域，即将DUT划分成若干个阵列，然后再在不同的阵列之间，分别设置开关电路和寻址电路。但是，在实际芯片测试中，更好的设计是只使用一个DUT阵列进行测试，所有的DUT都在同一个DUT区域，在该DUT区域没有多余的电路或设备，这样就更类似于芯片的真实使用场景。
无论是否将DUT划分为若干个DUT区域，当DUT阵列中的DUT数量较多，其所配置的外围电路就会有更多的开关电路，根据可寻址测试的原理，每组测试端口每次仅选中一个DUT进行测试，其余未被选中的开关电路会增加漏电流。采用目前的开关电路结构，其漏电流会达到几十甚至上百纳安的漏电流，从而导致测试芯片测量不够精确。
 技术问题
本发明的主要目的在于克服现有技术中的不足，提供一种可寻址测试芯片及测试系统，能够在测量过程中有效地减少漏电流。
 技术解决方案
本发明公开了一种能减少漏电流的可寻址测试芯片，该测试芯片包括开关电路、寻址电路、若干待测器件和若干焊盘；寻址电路的输出端连接到开关电路的输入端，寻址电路控制开关电路中开关的通断；开关电路的输出端与待测器件的输入端相连，通过开关的通断状态选定待测器件；其特征在于，寻址电路包括若干译码器，开关电路包括多个传输门，其中若干个传输门为一组，同一组传输门的输入端连接到寻址电路中的同一个译码器；多组传输门按信号传递方向连接成多级传输门结构，其中高一级的传输门的输出端连接到与之相连的低一级传输门的输入端，最低一级传输门的输出端与待测器件的测试信号线相连。
作为优选，同一组传输门中的每个传输门所连接的低一级传输门的数量相同。
作为优选，所述寻址电路中每个译码器的型号，根据所连接的该组传输门确定：译码器的数字信号输出位数不小于与其连接的该组传输门中的传输门个数。
作为优选，所有待测器件分布在同一个DUT阵列中，开关电路和寻址电路都设置在该DUT阵列的外围。
上述能减少漏电流的可寻址测试芯片，利用多级传输门作为开关电路，能实现所有的待测器件（DUT）都在同一个DUT区域，在该DUT区域没有多余的电路或设备，只使用一个DUT阵列进行测试，这样就更类似于芯片的真实使用场景。当然，该能减少漏电流的可寻址测试芯片，能实现待测器件不进行阵列分割，也当然能适用待测阵列进行分割的情况，即每个分割后的DUT阵列均需要配置一组开关电路和寻址电路，且整个测试芯片的寻址电路还需要配置一个阵列选择译码器用于DUT阵列选择。
作为优选，所述开关电路包括行开关电路和列开关电路，寻址电路包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，用于控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，用于控制列开关电路选定待测器件的所在列。
本发明还提供一种能减少漏电流的可寻址测试系统，包括测试仪器、探针卡及上述能减少漏电流的可寻址测试芯片，测试仪器与能减少漏电流的可寻址测试芯片通过探针卡相连并构成测试通路。
上述能减少漏电流的可寻址测试系统还包括多用地址寄存器，该多用地址寄存器与测试仪器连接，还与可寻址测试芯片中的寻址电路输入端相连，能根据外部信号的变化实现计数器或移位器的功能。根据多用寄存器的特性，当多用地址寄存器具有移位寄存器功能时，可以有选择地测试待测器件；当多用地址寄存器具有计数器功能时，则产生连续地址信号，无需在测量完一个待测器件后测量另外一个待测器件之前进行测试算法读取、设置，即可将需要测试的待测器件按顺序依次测完。
 有益效果
与现有技术相比，本发明的有益效果是：
本发明的能减少漏电流的可寻址测试芯片：1）使用多级传输门电路作为开关电路，以控制漏电流；2）在测试芯片上采用一个完整的DUT区域进行测试，不划分DUT阵列，更类似于芯片的真实使用场景；3）与一般的可寻址测试芯片的测试流程相兼容；4）能用于测量真实热点产品中的测试对象。
本发明的能减少漏电流的可寻址测试芯片系统，使用上述能减少漏电流的可寻址测试芯片，实现同上的优势。
 附图说明
图1为现有测试芯片的DUT阵列布局示意图。
图2为本发明测试芯片的DUT阵列布局示意图。
图3为本发明测试芯片的结构示意图。
图4为一级传输门的实施例示意图。
图5为二级传输门的实施例示意图。
图6为三级传输门的实施例示意图。
图7为一级传输门及译码器示意图。
图8为三级传输门及译码器示意图。
 本发明的实施方式
下面结合附图与具体实施方式对本发明作进一步详细描述：
如图2、图3、图4所示的一种能减少漏电流的可寻址测试芯片，包括开关电路、寻址电路、若干待测器件和若干焊盘；寻址电路与开关电路相连，用于输出地址信号以控制开关电路中的开关通断状态；开关电路与待测器件相连，以通过开关的通断状态选定指定的待测器件。所述寻址电路包括若干译码器。所述开关电路采用多级传输门电路，多级传输门电路的每一级包括若干传输门结构，低一级传输门结构的输入端连接到高一级传输门结构的输出端，最低级传输门结构的输出端分别与待测器件的测试信号线相连接；每个传输门结构的输入端还与寻址电路中的译码器连接，且同级传输门结构的输入端与同一个译码器连接。
当DUT阵列中的DUT数量较多时，其所配置的外围电路就会有更多的开关电路，根据可寻址测试的原理，每组测试端口每次仅选中一个DUT进行测试，其余未被选中的开关电路会增加漏电流。上述能减少漏电流的可寻址测试芯片，使用多级传输门电路作为开关电路，减少了漏电流，因此能准确测量漏电流Ioff等，保证测试芯片进行精确测量。
在多级传输门电路中，同一级的每个传输门结构，所连接的低一级传输门结构数量相同。这样就保证了每个待测器件在测量时的漏电流相同，每个待测器件测量得到的数值精度相同。
所述寻址电路包括若干型号的译码器，译码器的型号根据多级传输门电路进行选择：译码器的数字信号输出位数为N，多级传输门电路中第K级的传输门机构的输入端都与该译码器的输出端连接。其中，K是大于1的整数，即多级传输门电路至少包括两级；N的值不小于第K级传输门结构的个数，即可以采用数字信号输出位数等于第K级传输门结构个数的译码器，也可以采用数字信号输出位数多于第K级传输门结构个数的译码器。
所述能减少漏电流的可寻址测试芯片中，待测器件不进行阵列分割，即所有待测器件在同一个DUT区域中，开关电路和译码器都设置在该DUT区域的外围。
上述能减少漏电流的可寻址测试芯片，利用多级传输门作为开关电路，减少了漏电流，使得不划分DUT阵列成为可能，即在该DUT区域没有多余的电路或设备，只使用一个DUT阵列进行测试，这样就更类似于芯片的真实使用场景。当然，该能减少漏电流的可寻址测试芯片，能实现待测器件不进行阵列分割，也当然能适用待测阵列进行分割的情况，即每个分割后的DUT阵列均需要配置一组开关电路和寻址电路，且整个测试芯片的寻址电路还需要配置一个阵列选择译码器用于DUT阵列选择。
如图3所示，所述开关电路包括行开关电路和列开关电路，寻址电路包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，用于控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，用于控制列开关电路选定待测器件的所在列。测试时，行地址译码器输出地址信号以控制行开关电路中的开关通断状态，选择被测结构所在的行，列地址译码器输出地址信号以控制列开关电路中的开关通断状态，选择被测结构所在的列，被测的测试结构被唯一确定导通，测试信号可以顺利进入测试结构进行检测。
提供一种能减少漏电流的可寻址测试系统，包括测试仪器、探针卡及上述能减少漏电流的可寻址测试芯片，测试仪器与能减少漏电流的可寻址测试芯片通过探针卡相连并构成测试通路。该可寻址测试系统，使用多级传输门电路作为开关电路的测试芯片，能减少漏电流。
下面提供实施例，说明开关电路采用多级传输门电路，能与原始可寻址测试芯片的测试流程相兼容并能控制漏电流，使不划分DUT阵列成为现实，能用于测量真实热点产品中的晶测试对象。
实施例1
如图4所示的一级传输门电路，1024个传输门结构的输出端分别与待测器件的测试信号线相连接，1024个传输门结构的输入端均连接到同一个译码器。如图7所示，该译码器采用10-1024译码器，10-1024译码器的输出端连接有1024个传输门结构。
对于这1024个DUT，当其中一个DUT被选中导通时，其漏电流的大小采用下述公式进行估计：Ibg= 1023× Ioff_TG；Ioff_TG是指每个传输门结构未导通时所产生的漏电流；估算时，取Ioff_TG为0.1nA，计算得到漏电流Ibg，通过该漏电流Ibg的数量级来看漏电流的情况。很明显，采用一级传输门结构会产生很大的漏电流，Ibg的值会达到100 nA，因此不能准确测量漏电流Ioff，不能检测漏电流Ioff异常，也不能准确测量阈值电压Vt。
实施例2
如图5所示的二级传输门电路，1024个DUT通过32-32两级传输门电路引出。对于这1024个DUT，当其中一个DUT被选中导通时，其漏电流的大小采用下述公式进行估计：Ibg= 31× Ioff_TG+ 31× Ioff_TG；Ioff_TG是指每个传输门结构未导通时所产生的漏电流；估算时，取Ioff_TG为0.1nA，Ibg的值降低到50 nA，虽然不能准确测量漏电流Ioff，但能检测部分漏电流Ioff异常，也能相对准确地测量阈值电压Vt。
实施例3
如图6所示的三级传输门电路，1024个DUT通过8-8-16三级传输门电路引出。如图8所示，该8-8-16三级传输门电路包括（8+64+1024）个传输门结构，因此采用3-8译码器、6-64译码器、10-1024译码器，分别与第三级传输门结构的输入端、第二级传输门结构的输入端、第一级传输门结构的输入端连接。
对于这1024个DUT，当其中一个DUT被选中导通时，其漏电流的大小采用下述公式进行估计：Ibg=7× Ioff_TG+7× Ioff_TG+15× Ioff_TG；Ioff_TG是指每个传输门结构未导通时所产生的漏电流；估算时，取Ioff_TG为0.1nA，Ibg的值降低到10 nA，虽然不能准确测量漏电流Ioff，但能检测漏电流Ioff异常，也能准确地测量阈值电压Vt。
最后，需要注意的是，以上列举的仅是本发明的具体实施例。显然，本发明不限于以上实施例，还可以有很多变形。本领域的普通技术人员能从本发明公开的内容中直接导出或联想到的所有变形，均应认为是本发明的保护范围。

Claims (6)

  1. 一种能减少漏电流的可寻址测试芯片，包括开关电路、寻址电路、若干待测器件和若干焊盘；寻址电路的输出端连接到开关电路的输入端，寻址电路控制开关电路中开关的通断；开关电路的输出端与待测器件的输入端相连，通过开关的通断状态选定待测器件；其特征在于，寻址电路包括若干译码器，开关电路包括多个传输门，其中若干个传输门为一组，同一组传输门的输入端连接到寻址电路中的同一个译码器；多组传输门按信号传递方向连接成多级传输门结构，其中高一级的传输门的输出端连接到与之相连的低一级传输门的输入端，最低一级传输门的输出端与待测器件的测试信号线相连。
  2. 根据权利要求1所述的一种能减少漏电流的可寻址测试芯片，其特征在于，同一组传输门中的每个传输门所连接的低一级传输门的数量相同。
  3. 根据据权利要求1所述的一种能减少漏电流的可寻址测试芯片，其特征在于，所述寻址电路中每个译码器的型号，根据所连接的该组传输门个数确定：译码器的数字信号输出位数不小于与其连接的该组传输门中的传输门个数。
  4. 根据权利要求1所述的一种能减少漏电流的可寻址测试芯片，其特征在于，所有待测器件分布在同一个DUT阵列中，开关电路和寻址电路都设置在该DUT阵列的外围。
  5. 根据权利要求1所述的一种能减少漏电流的可寻址测试芯片，其特征在于，所述开关电路包括行开关电路和列开关电路，寻址电路包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，用于控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，用于控制列开关电路选定待测器件的所在列。
  6. 一种能减少漏电流的可寻址测试系统，其特征在于，包括测试仪器、探针卡及权利要求1至5中任意一项所述的能减少漏电流的可寻址测试芯片，测试仪器与能减少漏电流的可寻址测试芯片通过探针卡相连并构成测试通路。
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