WO2020135258A1 - 一种能提高电阻测量精度的可寻址测试芯片及其测试系统 - Google Patents

一种能提高电阻测量精度的可寻址测试芯片及其测试系统 Download PDF

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Publication number
WO2020135258A1
WO2020135258A1 PCT/CN2019/126995 CN2019126995W WO2020135258A1 WO 2020135258 A1 WO2020135258 A1 WO 2020135258A1 CN 2019126995 W CN2019126995 W CN 2019126995W WO 2020135258 A1 WO2020135258 A1 WO 2020135258A1
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Prior art keywords
circuit
test
under test
addressing
switch
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PCT/CN2019/126995
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English (en)
French (fr)
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蓝帆
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杭州广立微电子有限公司
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Publication of WO2020135258A1 publication Critical patent/WO2020135258A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the invention relates to the field of semiconductor design and production, and particularly relates to an addressable test chip and a test system which can improve the resistance measurement accuracy.
  • the independent test chip has a large area and needs to occupy the position of one chip, which is equivalent to the semiconductor manufacturer having to pay the manufacturing cost of this part of the area mask.
  • the dicing groove is the space reserved for cutting chips on the wafer.
  • the test chip is placed in the dicing groove so that it does not occupy the position of the chip. This eliminates the need for semiconductor manufacturers to bear the cost of expensive masks and saves a lot the cost of.
  • the short-range test chip needs to connect the test unit to the PAD (pad) separately, and each test structure requires two or more PADs, which results in a low area utilization rate of the short-range test chip.
  • the general addressable test chip introduces an address decoding circuit similar to the static memory chip, which greatly reduces the number of PADs and relatively increases the area utilization of the test chip.
  • the general addressable test chip is a general-purpose test chip with an addressable circuit. It consists of four basic structures: an addressing circuit, a switching circuit, a device under test (DUT), and a pin.
  • the addressing circuit is connected to the switch circuit, and outputs an address signal to control the on-off state of the switch in the switch circuit; the switch circuit is connected to the device under test to select a specific DUT for measurement through the on-off state of the switch.
  • the entire DUT area can be divided into several small DUT areas, that is, the DUT is divided into several arrays, and then switches are set between different arrays. Circuit and addressing circuit.
  • a better design is to use only one DUT array for testing. All DUTs are in the same DUT area, and there are no redundant circuits or devices in this DUT area, which is more similar to the real chip. scenes to be used.
  • the resistance of the DUT is mainly affected by the switching circuit, not the metal resistance in the DUT array.
  • the resistance of the DUT will reach 1.5k ohm ⁇ 3k ohm, resulting in a voltage drop when measuring ldsat, which will cause measurement
  • the value is not accurate, and the problem that the small resistance cannot be measured. Therefore, how to eliminate the influence of pressure drop and improve accuracy is a problem to be solved in the art.
  • the main purpose of the present invention is to overcome the shortcomings in the prior art, and to provide an addressable test chip and test system that can eliminate the influence of voltage drop and accurately measure the resistance value.
  • the object of the present invention is also to provide an addressable test chip capable of improving resistance measurement accuracy, including an excitation circuit, a sensing circuit, several devices under test and several pads; the devices under test form a DUT array, each DUT array The periphery of the is provided with an excitation circuit and an induction circuit;
  • the excitation circuit includes a switching circuit A and an addressing circuit A.
  • the addressing circuit A is connected to the switching circuit A.
  • the addressing circuit A outputs an address signal to control the on-off state of the switch in the switching circuit A.
  • the switching circuit A is connected to the device under test.
  • the switching circuit A selects the specified device under test through the on-off state of the switch; the excitation circuit is used to apply a test voltage to the selected device under test;
  • the sensing circuit includes a switching circuit B and an addressing circuit B.
  • the addressing circuit B is connected to the switching circuit B.
  • the addressing circuit B outputs an address signal to control the on-off state of the switch in the switching circuit B.
  • the switching circuit B is connected to the device under test.
  • the switching circuit B selects the designated device under test through the on-off state of the switch; the sensing circuit is used to pass a low current to the selected device under test to measure the voltage across the device under test;
  • the addressing circuit A and the addressing circuit B can be shared in the excitation circuit and the sensing circuit around the same DUT array
  • One addressing circuit is realized, or one addressing circuit is configured for addressing circuit A and addressing circuit B respectively; that is, addressing circuit A and addressing circuit B can be implemented by sharing the same circuit structure, or two independent circuits are configured Structure to implement addressing circuit A and addressing circuit B respectively.
  • all devices under test are not divided into arrays, that is, all devices under test form a DUT array, and the excitation circuit and the sensing circuit are respectively arranged in the DUT array The periphery.
  • the above addressable test chip that can improve the accuracy of resistance measurement uses the sensing circuit to measure the voltage across the device under test to calculate the resistance of the device under test to eliminate the effect of the voltage drop caused by the increase in the switching circuit, so that the DUT array is not divided It is possible to realize that all DUTs are in the same DUT area, and there are no redundant circuits or devices in this DUT area, and only one DUT array is used for testing, which is more similar to the real use scenario of the chip.
  • the addressable test chip that can improve the accuracy of resistance measurement can realize that the device under test is not divided into arrays, and of course it can be applied to the case where the array under test is divided, but the addressing circuit of the entire test chip also needs to be equipped with an array
  • the selection decoder is used for DUT array selection.
  • the switch circuit A and/or the switch circuit B respectively include a row switch circuit and a column switch circuit
  • the address circuit A and/or the address circuit B include a row address decoder and a column address decoder, respectively;
  • the address decoder is connected to the row switch circuit, the row address decoder controls the row switch circuit to select the row of the device under test;
  • the column address decoder is connected to the column switch circuit, and the column address decoder controls the column switch circuit to select The column of the device under test.
  • the addressing circuit A includes several decoders
  • the switching circuit A includes multiple transmission gates, of which several transmission gates are a group, and the input terminals of the same group of transmission gates are connected to the same one in the addressing circuit A Decoder; multiple groups of transmission gates are connected into a multi-level transmission gate structure according to the signal transmission direction, in which the output of the higher-level transmission gate is connected to the input of the lower-level transmission gate connected to it, and the lowest-level transmission gate Is connected to the test port of the device under test.
  • the switch circuit A in the excitation circuit uses a multi-level transmission gate circuit, which can effectively reduce the leakage interference of the DUT that is not selected during the circuit measurement to the DUT to be measured.
  • the type of each decoder in the addressing circuit A is determined according to the group of transmission gates connected to it: the number of digital signal output bits of the decoder is not less than the number of transmission gates in the group of transmission gates connected to it .
  • the switch circuit A in the excitation circuit is implemented using a multi-stage transmission gate structure, and the decoding in the address circuit A is determined according to the multi-stage transmission gate structure of the switch circuit A The configuration of the device.
  • the switch circuit B in the sensing circuit can use conventional switches
  • the circuit implementation can also be implemented with the same multi-level transmission gate structure as the switch circuit A; if the addressing circuit A and the addressing circuit B share the same addressing circuit, then due to the limitation of the addressing circuit, the The switch circuit B is also implemented using the same multi-level transmission gate structure as the switch circuit A.
  • the number of lower-level transmission gates connected to each transmission gate in the same group of transmission gates is the same to ensure that the leakage current of each device under test during measurement is the same.
  • the numerical precision is the same.
  • the invention also provides an addressable test system which can improve the resistance measurement accuracy, including a test instrument, a probe card and the above addressable test chip which can improve the resistance measurement accuracy, the test instrument and the searchable which can improve the resistance measurement accuracy
  • the address test chip is connected through a probe card and forms a test path.
  • the above-mentioned addressable test system that can improve the resistance measurement accuracy also includes a multi-purpose address register, which is connected to the test instrument, and is also connected to the addressing circuit input terminal in the addressable test chip, which can be realized according to the change of the external signal Counter or shifter function.
  • a multi-purpose address register which is connected to the test instrument, and is also connected to the addressing circuit input terminal in the addressable test chip, which can be realized according to the change of the external signal Counter or shifter function.
  • the multi-purpose address register when the multi-purpose address register has a shift register function, the device under test can be selectively tested; when the multi-purpose address register has a counter function, a continuous address signal is generated, and there is no need to measure a device under test By reading and setting the test algorithm before measuring another device under test, the devices under test to be tested can be tested in order.
  • the multi-purpose address register is in the prior art.
  • the multi-purpose address register can realize the function of a counter or a shifter according to
  • the addressable test chip which can improve the resistance measurement accuracy of the present invention: 1) Add a sensing circuit to the test chip, and use the sensing circuit as a low current path to measure the voltage across the selected DUT in the low current sensing circuit , To avoid the voltage drop caused by the large current in the excitation circuit, and then accurately measure the resistance of the DUT; 2) use a complete DUT area for testing on the test chip, without dividing the DUT array, to achieve the test of accommodating complete products; 3)
  • the switch circuit in the test chip uses a multi-level transmission gate, which can effectively reduce the impact of the leakage current generated by the branch where the unselected DUT is located on the DUT under test; 4) Compatible with the general test process of the addressable test chip; 5) Can be used to measure test objects in real hot products.
  • the addressable test system capable of improving resistance measurement accuracy of the present invention uses the above addressable test chip which can improve resistance measurement accuracy to achieve the advantages described above.
  • FIG. 1 is a schematic diagram of the layout of an existing high-density test chip.
  • FIG. 2 is a schematic diagram of the layout of the test chip of the present invention.
  • Figure 3 is a schematic diagram of the structure of the excitation circuit.
  • FIG. 4 is a schematic diagram of the structure of the sensing circuit.
  • FIG. 5 is a schematic diagram of an embodiment of a peripheral circuit in a test chip of the present invention.
  • FIG. 6 is a schematic diagram of an embodiment of a peripheral circuit in a test chip of the present invention.
  • an addressable test chip capable of improving resistance measurement accuracy includes an excitation circuit, a sensing circuit, several devices under test and several pads; the devices under test form a DUT array, and each DUT array An excitation circuit and an induction circuit are respectively arranged on the periphery.
  • the excitation circuit includes a switching circuit and an addressing circuit.
  • the addressing circuit is connected to the switching circuit for outputting an address signal to control the on-off state of the switch in the switching circuit, and the switching circuit is connected to the device under test for passing through the switch The off state selects the designated device under test; the excitation circuit is used to apply a test voltage to the selected device under test.
  • the sensing circuit includes a switching circuit and an addressing circuit.
  • the addressing circuit is connected to the switching circuit for outputting an address signal to control the on-off state of the switch in the switching circuit, and the switching circuit is connected to the device under test for passing through the switch The off state selects the designated device under test; the sensing circuit is used to pass a low current to the selected device under test to calculate the voltage across the device under test.
  • the switch circuit is connected to the voltage source through the pad.
  • the voltage source provides the required voltage, and then There will also be voltage on the line (excitation circuit), but due to the voltage drop, the voltage on the force line and the voltage provided by the voltage source are different.
  • the switch circuit is connected to the current source through the pad.
  • the current source provides the smallest possible current, such as a current of less than 1pA, so that the source measurement unit (SMU) can sense the voltage, because at this time
  • the current on the sense line (induction circuit) is very small, so the voltage of the current source is very close to the voltage of the sense line, and the DUT resistance can be calculated accurately.
  • the above addressable test chip that can improve the resistance measurement accuracy adds an induction circuit as a low current path, which is used to measure the voltage across the selected DUT in the low current induction circuit, thereby accurately measuring the resistance of the DUT.
  • the addressable test chip that can improve the resistance measurement accuracy is compatible with the general addressable test chip test process.
  • all devices under test are not divided into arrays, that is, all devices under test form a DUT array, and the excitation circuit and the sensing circuit are respectively arranged on the periphery of the DUT array.
  • the DUT array is not divided on the test chip, that is, there are no redundant circuits or devices in the DUT area, and only one DUT array is used for testing, which is more similar to the real use scenario of the chip.
  • the switch circuit includes a row switch circuit and a column switch circuit.
  • the addressing circuit includes a row address decoder and a column address decoder; the row address decoder is connected to the row switch circuit and is used to control the row switch circuit to select a test The row of the device; the column address decoder is connected to the column switch circuit and is used to control the column switch circuit to select the column of the device under test.
  • the row address decoder outputs an address signal to control the on-off state of the switch in the row switch circuit, select the row where the structure under test is located, and the column address decoder outputs an address signal to control the on-off state of the switch in the column switch circuit Select the column where the structure under test is located, the test structure under test is uniquely turned on, and the test signal can smoothly enter the test structure for inspection.
  • the switch circuit in the excitation circuit uses a multi-level transmission gate circuit.
  • Each stage of the multi-level transmission gate circuit includes several transmission gate structures.
  • the input end of the lower-level transmission gate structure is connected to the output end of the higher-level transmission gate structure.
  • the output terminal of the lowest-level transmission gate structure is connected to the test signal line of the device under test; the input terminal of each transmission gate structure is also connected to the decoder of the addressing circuit in the excitation circuit, and the transmission gate structure of the same level The input is connected to the same decoder.
  • the peripheral circuits configured there will have more switching circuits. According to the principle of addressable testing, only one DUT is selected for testing in each group of test ports at a time, and the rest are not selected. Will cause leakage current.
  • the use of a multi-level transmission gate circuit as a switching circuit can effectively reduce the influence of the leakage current generated by the branch where the unselected DUT is located on the DUT to be tested, and ensure accurate measurement of the test chip.
  • each transmission gate structure of the same stage has the same number of lower-level transmission gate structures connected through a decoder. This ensures that the leakage current of each device under test is the same during measurement, and the numerical accuracy of each device under test is the same.
  • the addressing circuit in the excitation circuit includes several types of decoders, and the type of each decoder is selected according to the multi-level transmission gate circuit: the number of digital signal output bits of the decoder is N, and the multi-level transmission gate The input ends of the transmission gate mechanism of the Kth stage in the circuit are connected to the output end of the decoder, and the value of N is not less than the number of the transmission gate structure of the Kth stage.
  • the addressing circuit in the excitation circuit and the addressing circuit in the sensing circuit can use the same search
  • the address circuit realizes that the same group of decoders are used to output address signals to the switch circuits in the excitation circuit and the induction circuit respectively.
  • the sharing of the addressing circuit requires that the switch circuit in the excitation circuit and the switch circuit in the induction circuit have the same structure. For example, when the switch circuit in the excitation circuit is implemented by a multi-level transmission gate circuit, the The switch circuit is also implemented using the same multi-level transmission gate circuit.
  • an addressable test system capable of improving resistance measurement accuracy, including a test instrument, a probe card and the above addressable test chip capable of improving resistance measurement accuracy, a test instrument and an addressable test chip capable of improving resistance measurement accuracy Connected through the probe card and constitute the test path.
  • This addressable test system which can improve the accuracy of resistance measurement, adds a sensing circuit to the test chip, which can measure the resistance of the DUT and solve the inaccuracy caused by the voltage drop in the original test system.
  • the above-mentioned addressable test system that can improve the resistance measurement accuracy also includes a multi-purpose address register, which is connected to the test instrument, and is also connected to the addressing circuit input terminal in the addressable test chip, which can be realized according to the change of the external signal Counter or shifter function.
  • a multi-purpose address register which is connected to the test instrument, and is also connected to the addressing circuit input terminal in the addressable test chip, which can be realized according to the change of the external signal Counter or shifter function.
  • the test experiment proves that the voltage drop during the test is mainly affected by the switching circuit.
  • a sensing circuit is added to deal with the problem of non-negligible voltage drop under high voltage test. Apply a high voltage in the excitation circuit and measure the current value flowing through the DUT under test; apply a small current in the induction circuit and sense the voltage value across the DUT under test; further calculate the high accuracy from the above voltage and current values The resistance value of the measured DUT.
  • the switch circuit of the excitation circuit in the addressable test circuit uses a multi-level transmission gate circuit (except for the multi-level transmission gate, the structure of other peripheral circuits of the addressable test circuit is similar to FIG. 5, so it is omitted),
  • the circuit structure of the multi-level transmission gate can effectively reduce the impact of leakage current on the measurement accuracy during the measurement, but when the DUT is tested, compared to the test path in the first-level switch circuit, there is only one switch. Contains multiple switches in series. The more stages of the multi-level transmission gate structure, the more the voltage drop will be affected by the switch during measurement. Therefore, the addressable test circuit needs to be equipped with a sensing circuit to eliminate multiple levels. Voltage drop caused by the switching circuit. In FIG.
  • the switch circuits on the left and bottom of the DUT array belong to the excitation circuit, and the switch circuits on the right and top of the DUT array belong to the induction circuit.
  • the switching circuit in the sensing circuit is also implemented using a multi-level transmission gate circuit, but in fact the switching circuit in the sensing circuit can use a multi-level transmission gate circuit or a one-level switching circuit according to requirements , Different choices have almost no effect on the induction accuracy, and there will be no obvious performance and accuracy improvement.
  • a high voltage VH is applied to the bottom switch circuit terminal, and a low voltage VL is applied to the left switch circuit terminal, then a current flows from bottom to left; at the top 1.
  • the switch circuit on the right applies a low current, and the voltage applied to the side of the DUT under test with a high voltage is (VH-IR) through the sensing circuit, where IR is the voltage drop at the high voltage applied side.
  • VH-IR the voltage applied to the side of the DUT under test with a high voltage
  • the voltage on the low voltage side of the DUT under test is induced as (VL+IR).
  • the current value flowing through the DUT under test is measured through the test end of the test chip, that is, the current value flowing through the DUT under test on the excitation circuit, the resistance value of the DUT under test can be calculated.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种能提高电阻测量精度的可寻址测试芯片及其测试系统，可寻址测试芯片包括激励电路、感应电路、若干待测器件和若干焊盘；待测器件形成DUT阵列，每个DUT阵列的外围分别设置有一个激励电路和一个感应电路。可寻址测试芯片及其测试系统能消除压降的影响，精确测量电阻值。

Description

一种能提高电阻测量精度的可寻址测试芯片及其测试系统 技术领域
本发明是关于半导体设计和生产领域，特别涉及一种能提高电阻测量精度的可寻址测试芯片及其测试系统。
 背景技术
传统半导体制造通过短程测试芯片来测试获取生产工艺的缺陷率和成品率，根据在晶圆内放置位置的不同，可分为两类：独立测试芯片和放置在划片槽内的测试芯片。独立测试芯片面积较大，需要占据一个芯片的位置，这样就相当于半导体制造厂商需要支付这一部分面积掩模的制造费用。划片槽是晶圆上为切割芯片时预留的空间，将测试芯片放置于划片槽，可以不占据芯片的位置，这使半导体制造厂商就不需要承担昂贵的掩模费用，节省了大量的成本。
但是短程测试芯片需要将测试单元单独的连接到PAD（焊盘）上，每个测试结构需要两个或多个PAD，这造成了短程测试芯片的面积利用率很低。基于这个考虑，普通可寻址测试芯片通过引入类似于静态记忆体芯片的地址译码电路，大大减少了PAD的数量，相对提高了测试芯片的面积利用率。
普通可寻址测试芯片（Test Chip）是通用的带有可寻址电路的测试芯片，由寻址电路、开关电路、待测器件（DUT）、引脚（pad）四部分基本结构构成，其中寻址电路与开关电路相连，且输出地址信号以控制开关电路中的开关通断状态；开关电路与待测器件相连，以通过开关的通断状态选择特定的DUT进行测量。
如图1所示，对于区域放置较多DUT的测试芯片，可以将其整个DUT区域划分成若干个小DUT区域，即将DUT划分成若干个阵列，然后再在不同的阵列之间，分别设置开关电路和寻址电路。但是，在实际芯片测试中，更好的设计是只使用一个DUT阵列进行测试，所有的DUT都在同一个DUT区域，在该DUT区域没有多余的电路或设备，这样就更类似于芯片的真实使用场景。
但是，随着制造企业对集成度的要求，越来越多的DUT数量会有更多的开关电路，开关电路的增加势必导致测试电路中的电阻增大。根据实验数据可知，DUT的电阻主要受到开关电路的影响，而非DUT阵列中的金属电阻。对于目前的一些密度较高的测试芯片，若采用更多的开关电路来实现更多的DUT选择，其DUT的电阻会达到1.5k欧姆~ 3k欧姆，导致测量ldsat时存在压降，会造成测量值不准确，以及小电阻无法测量的问题。因此，如何消除压降的影响提高准确度是本领域一个需要解决的问题。
 技术问题
本发明的主要目的在于克服现有技术中的不足，提供一种能消除压降的影响，精确测量电阻值的可寻址测试芯片及其测试系统。
 技术解决方案
本发明的目的还在于提供一种能提高电阻测量精度的可寻址测试芯片，包括激励电路、感应电路、若干待测器件和若干焊盘；所述待测器件形成DUT阵列，每个DUT阵列的外围分别设置有一个激励电路和一个感应电路；
激励电路包括开关电路A和寻址电路A，寻址电路A与开关电路A相连，寻址电路A输出地址信号以控制开关电路A中的开关通断状态，开关电路A与待测器件相连，开关电路A通过开关的通断状态选定指定的待测器件；激励电路用于对选定的待测器件施加测试电压；
感应电路包括开关电路B和寻址电路B，寻址电路B与开关电路B相连，寻址电路B输出地址信号以控制开关电路B中的开关通断状态，开关电路B与待测器件相连，开关电路B通过开关的通断状态选定指定的待测器件；感应电路用于对选定的待测器件通入低电流，以测量该待测器件两端的电压；
对于同一个DUT阵列，因为其外围的激励电路和感应电路选定的是同一个待测器件，所以同一个DUT阵列外围的激励电路和感应电路中，寻址电路A和寻址电路B能共用一个寻址电路实现，或者对于寻址电路A和寻址电路B分别配置一个寻址电路实现；也即寻址电路A和寻址电路B可以共用同一电路结构实现，或者配置两个独立的电路结构来分别实现寻址电路A和寻址电路B。
作为进一步的改进，所述能提高电阻测量精度的可寻址测试芯片中，所有待测器件不进行阵列分割，即所有待测器件形成一个DUT阵列，激励电路和感应电路分别设置在该DUT阵列的外围。
上述能提高电阻测量精度的可寻址测试芯片，利用感应电路测量待测器件两端的电压，以计算待测器件的电阻，来消除开关电路增多带来的压降的影响，使不划分DUT阵列成为可能，即实现所有的DUT都在同一个DUT区域，在该DUT区域没有多余的电路或设备，只使用一个DUT阵列进行测试，这样就更类似于芯片的真实使用场景。当然，该能提高电阻测量精度的可寻址测试芯片，能实现待测器件不进行阵列分割，也当然能适用待测阵列进行分割的情况，只是整个测试芯片的寻址电路还需要配置一个阵列选择译码器用于DUT阵列选择。
作为进一步的改进，开关电路A和/或开关电路B分别包括行开关电路和列开关电路，寻址电路A和/或寻址电路B分别包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，行地址译码器控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，列地址译码器控制列开关电路选定待测器件的所在列。
作为进一步的改进，寻址电路A包括若干译码器，开关电路A包括多个传输门，其中若干个传输门为一组，同一组传输门的输入端连接到寻址电路A中的同一个译码器；多组传输门按信号传递方向连接成多级传输门结构，其中高一级的传输门的输出端连接到与之相连的低一级传输门的输入端，最低一级传输门的输出端与待测器件的测试端口相连。激励电路中的开关电路A采用多级传输门电路，能够有效地减少电路测量时未被选中的DUT对被测DUT的漏电干扰。其中，寻址电路A中每个译码器的型号，根据其所连接的该组传输门确定：译码器的数字信号输出位数不小于与其连接的该组传输门中的传输门个数。
上述能提高电阻测量精度的可寻址测试芯片中，激励电路中的开关电路A采用多级传输门结构来实现，并根据开关电路A的多级传输门结构确定寻址电路A中各译码器的配置。对于同一个DUT阵列外围的激励电路和感应电路，若其中的寻址电路A和寻址电路B是分别配置了一个寻址电路来实现的，那么感应电路中的开关电路B可采用常规的开关电路实现，也可以采用和开关电路A相同的多级传输门结构实现；若其中的寻址电路A和寻址电路B共用同一个寻址电路，那么因寻址电路的限制，感应电路中的开关电路B也采用和开关电路A相同的多级传输门结构实现。
作为进一步的改进，同一组传输门中的每个传输门所连接的低一级传输门的数量相同，以保证每个待测器件在测量时的漏电流相同，每个待测器件测量得到的数值精度相同。
本发明还提供一种能提高电阻测量精度的可寻址测试系统，包括测试仪器、探针卡及上述能提高电阻测量精度的可寻址测试芯片，测试仪器与能提高电阻测量精度的可寻址测试芯片通过探针卡相连并构成测试通路。
上述能提高电阻测量精度的可寻址测试系统还包括多用地址寄存器，该多用地址寄存器与测试仪器连接，还与可寻址测试芯片中的寻址电路输入端相连，能根据外部信号的变化实现计数器或移位器的功能。根据多用寄存器的特性，当多用地址寄存器具有移位寄存器功能时，可以有选择地测试待测器件；当多用地址寄存器具有计数器功能时，则产生连续地址信号，无需在测量完一个待测器件后测量另外一个待测器件之前进行测试算法读取、设置，即可将需要测试的待测器件按顺序依次测完。所述多用地址寄存器为现有技术，多用地址寄存器可根据外部信号的变化实现计数器或移位器的功能，其具体结构以及功能实现可参考公开号为CN207742296U的专利文件公开的内容。
 有益效果
与现有技术相比，本发明的有益效果是：
1、本发明能提高电阻测量精度的可寻址测试芯片：1）在测试芯片中增加感应电路，通过将感应电路作为低电流路径，用于在低电流的感应电路中测量选中DUT两端的电压，避免激励电路中大电流所造成的电压降，进而准确测量DUT的电阻；2）在测试芯片上采用一个完整的DUT区域进行测试，不划分DUT阵列，实现容纳完整的产品进行测试；3）测试芯片中的开关电路采用多级传输门，能够有效降低未被选中的DUT所在支路产生的漏电流对被测DUT的影响；4）与一般的可寻址测试芯片的测试流程相兼容；5）能用于测量真实热点产品中的测试对象。
2、本发明能提高电阻测量精度的可寻址测试系统，使用上述能提高电阻测量精度的可寻址测试芯片，实现同上的优势。
 附图说明
图1为现有高密度测试芯片的布局示意图。
图2为本发明测试芯片的布局示意图。
图3为激励电路的结构示意图。
图4为感应电路的结构示意图。
图5为本发明测试芯片中外围电路的实施例示意图。
图6为本发明测试芯片中外围电路的的实施例示意图。
 本发明的实施方式
下面结合附图与具体实施方式对本发明作进一步详细描述：
如图2所示的一种能提高电阻测量精度的可寻址测试芯片，包括激励电路、感应电路、若干待测器件和若干焊盘；所述待测器件形成DUT阵列，每个DUT阵列的外围分别设置有一个激励电路和一个感应电路。
所述激励电路包括开关电路和寻址电路，寻址电路与开关电路相连，用于输出地址信号以控制开关电路中的开关通断状态，开关电路与待测器件相连，用于通过开关的通断状态选定指定的待测器件；激励电路用于对选定的待测器件施加测试电压。
所述感应电路包括开关电路和寻址电路，寻址电路与开关电路相连，用于输出地址信号以控制开关电路中的开关通断状态，开关电路与待测器件相连，用于通过开关的通断状态选定指定的待测器件；感应电路用于对选定的待测器件通入低电流，以计算该待测器件两端的电压。
如图3所示的激励电路，开关电路通过焊盘连接到电压源，电压源提供所需的电压，然后在force line（激励电路）上也会有电压，但是因为压降，导致force line上的电压和电压源提供的电压是不同的。
如图4所示的感应电路，开关电路通过焊盘连接到电流源，电流源提供尽可能小的电流，比如小于1pA的电流，使源测量单元（SMU）能感知到电压，正因为此时在sense line（感应电路）上的电流是非常小的，所以电流源的电压非常接近于sense line的电压，进行可以精确计算出DUT电阻。
上述能提高电阻测量精度的可寻址测试芯片，增加了作为低电流路径的感应电路，用于在低电流的感应电路中测量选中DUT两端的电压，进而准确测量DUT的电阻。另外，该种能提高电阻测量精度的可寻址测试芯片与一般的可寻址测试芯片测试流程相兼容。
所述能提高电阻测量精度的可寻址测试芯片上，所有待测器件不进行阵列分割，即所有待测器件形成一个DUT阵列，激励电路和感应电路分别设置在该DUT阵列的外围。在测试芯片上不划分DUT阵列，即在该DUT区域没有多余的电路或设备，只使用一个DUT阵列进行测试，这样就更类似于芯片的真实使用场景。
所述开关电路包括行开关电路和列开关电路，寻址电路包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，用于控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，用于控制列开关电路选定待测器件的所在列。测试时，行地址译码器输出地址信号以控制行开关电路中的开关通断状态，选择被测结构所在的行，列地址译码器输出地址信号以控制列开关电路中的开关通断状态，选择被测结构所在的列，被测的测试结构被唯一确定导通，测试信号可以顺利进入测试结构进行检测。
所述激励电路中的开关电路采用多级传输门电路，多级传输门电路的每一级包括若干传输门结构，低一级传输门结构的输入端连接到高一级传输门结构的输出端，最低级传输门结构的输出端分别与待测器件的测试信号线相连接；每个传输门结构的输入端还与激励电路中寻址电路的译码器连接，且同级传输门结构的输入端与同一个译码器连接。
当DUT阵列中的DUT数量较多时，其所配置的外围电路就会有更多的开关电路，根据可寻址测试的原理，每组测试端口每次仅选中一个DUT进行测试，其余未被选中的开关电路会产生漏电流。上述激励电路中，使用多级传输门电路作为开关电路，能够有效降低未被选中的DUT所在支路产生的漏电流对被测DUT的影响，保证测试芯片进行精确测量。
在多级传输门电路中，同一级的每个传输门结构，通过译码器连接的低一级传输门结构数量相同。这样就保证了每个待测器件在测量时的漏电流相同，每个待测器件测量得到的数值精度相同。
所述激励电路中的寻址电路包括若干型号的译码器，且每个译码器的型号根据多级传输门电路进行选择：译码器的数字信号输出位数为N，多级传输门电路中第K级的传输门机构的输入端都与该译码器的输出端连接，N的值不小于第K级传输门结构的个数。
在具体的应用中，对于同一个DUT阵列，因为激励电路和感应电路所要选定的是同一个待测器件，所以激励电路中的寻址电路和感应电路中的寻址电路能够采用同一个寻址电路实现，即利用同一组译码器来向激励电路、感应电路中的开关电路分别输出地址信号。同时，寻址电路的共用，要求激励电路中的开关电路和感应电路中的开关电路的结构是相同的，比如，当激励电路中的开关电路采用多级传输门电路实现时，感应电路中的开关电路也采用相同的多级传输门电路实现。
提供一种能提高电阻测量精度的可寻址测试系统，包括测试仪器、探针卡及上述能提高电阻测量精度的可寻址测试芯片，测试仪器与能提高电阻测量精度的可寻址测试芯片通过探针卡相连并构成测试通路。该种能提高电阻测量精度的可寻址测试系统，在测试芯片中增加了感应电路，能测量出DUT电阻，解决原测试系统中因压降导致的不准确问题。
上述能提高电阻测量精度的可寻址测试系统还包括多用地址寄存器，该多用地址寄存器与测试仪器连接，还与可寻址测试芯片中的寻址电路输入端相连，能根据外部信号的变化实现计数器或移位器的功能。根据多用寄存器的特性，当多用地址寄存器具有移位寄存器功能时，可以有选择地测试待测器件；当多用地址寄存器具有计数器功能时，则产生连续地址信号，无需在测量完一个待测器件后测量另外一个待测器件之前进行测试算法读取、设置，即可将需要测试的待测器件按顺序依次测完。
下面的实施例可以使本专业的专业技术人员更全面地理解本发明，但不以任何方式限制本发明。
实施例1
对于目前连接几百个待测器件（DUT）的开关电路，为不划分DUT阵列，当DUT阵列中的DUT数量增加至非常多时，例如1024x1024，即1个阵列包含百万级数的DUT，其行开关电路连接的DUT数量增加到1024个，列开关电路连接的DUT数量增加到1024个，可参考图5。
当采用1个完整的DUT阵列进行测试，测试实验证明：测试时的电压降主要受到开关电路的影响，本实施例通过增加感应电路来处理高电压测试下会产生不可忽略的压降问题。在激励电路中施加高电压，并测得流经被测DUT的电流值；在感应电路中施加小电流，并感应被测DUT两端的电压值；通过上述电压值和电流值进一步计算出高精度的被测DUT的电阻值。
实施例2
如图6所示，可寻址测试电路中激励电路的开关电路采用多级传输门电路（除多级传输门以外，可寻址测试电路的其他外围电路结构与图5类似，所以省略），多级传输门的电路结构可以有效地减少测量时漏电流对测量精度的影响，但是被测DUT在测试时，对比一级开关电路中的测试通路仅有一个开关来说，其所在的通路中含有多个串联的开关，多级传输门结构的级数越多则其在测量时电压降收到开关的影响越大，因此，该可寻址测试电路中更需要配置感应电路以消除多级开关电路造成的电压降。在图6中，DUT阵列左边和底部的开关电路属于激励电路，DUT阵列右边和顶部的开关电路属于感应电路。需要说明的是，在本实施例中，感应电路中的开关电路也是采用多级传输门电路来实现的，但其实感应电路中的开关电路可以根据需求采用多级传输门电路或者一级开关电路，不同的选择对感应精度几乎没有影响，不会有明显的性能和精度提升。
下面，以测试第一行第二列（L1H2）的DUT为例，在底部的开关电路端施加高电压VH、左边的开关电路端施加低电压VL，则产生从下到左的电流；在顶部、右边的开关电路施加低电流，则通过感应电路可以感应出被测DUT施加高电压一侧的电压为（VH-IR），其中IR为施加高电压端的电压降，同理，通过感应电路可以感应出被测DUT施加低电压一侧的电压为（VL+IR）。另外，通过测试芯片的测试端测量出流经被测DUT的电流值，即激励电路上流经被测DUT的电流值，就可以计算出被测DUT的电阻值。
最后，需要注意的是，以上列举的仅是本发明的具体实施例。显然，本发明不限于以上实施例，还可以有很多变形。本领域的普通技术人员能从本发明公开的内容中直接导出或联想到的所有变形，均应认为是本发明的保护范围。

Claims (7)

  1. 一种能提高电阻测量精度的可寻址测试芯片，其特征在于，包括激励电路、感应电路、若干待测器件和若干焊盘；所述待测器件形成DUT阵列，每个DUT阵列的外围分别设置有一个激励电路和一个感应电路；
    激励电路包括开关电路A和寻址电路A，寻址电路A与开关电路A相连，寻址电路A输出地址信号以控制开关电路A中的开关通断状态，开关电路A与待测器件相连，开关电路A通过开关的通断状态选定指定的待测器件；激励电路用于对选定的待测器件施加测试电压；
    感应电路包括开关电路B和寻址电路B，寻址电路B与开关电路B相连，寻址电路B输出地址信号以控制开关电路B中的开关通断状态，开关电路B与待测器件相连，开关电路B通过开关的通断状态选定指定的待测器件；感应电路用于对选定的待测器件通入低电流，以测量该待测器件两端的电压；
    同一个DUT阵列外围的激励电路和感应电路中，寻址电路A和寻址电路B共用一个寻址电路实现，或者对于寻址电路A和寻址电路B分别配置一个寻址电路实现。
  2. 根据权利要求1所述的一种能提高电阻测量精度的可寻址测试芯片，其特征在于，所有待测器件分布在同一个DUT阵列中，开关电路和寻址电路设置在该DUT阵列的外围。
  3. 根据权利要求1所述的一种能提高电阻测量精度的可寻址测试芯片，其特征在于，开关电路A和/或开关电路B分别包括行开关电路和列开关电路，寻址电路A和/或寻址电路B包括行地址译码器和列地址译码器；行地址译码器与行开关电路相连，行地址译码器控制行开关电路选定待测器件的所在行；列地址译码器与列开关电路相连，列地址译码器控制列开关电路选定待测器件的所在列。
  4. 根据权利要求1所述的一种能提高电阻测量精度的可寻址测试芯片，其特征在于，寻址电路A包括若干译码器，开关电路A包括多个传输门，其中若干个传输门为一组，同一组传输门的输入端连接到寻址电路A中的同一个译码器；多组传输门按信号传递方向连接成多级传输门结构，其中高一级的传输门的输出端连接到与之相连的低一级传输门的输入端，最低一级传输门的输出端与待测器件的测试端口相连。
  5. 根据权利要求4所述的一种能提高电阻测量精度的可寻址测试芯片，其特征在于，同一组传输门中的每个传输门所连接的低一级传输门的数量相同。
  6. 根据权利要求4所述的一种能提高电阻测量精度的可寻址测试芯片，其特征在于，所述寻址电路A中每个译码器的型号，根据所连接的该组传输门确定：译码器的数字信号输出位数不小于与其连接的该组传输门中的传输门个数。
  7. 一种能提高电阻测量精度的可寻址测试系统，其特征在于，包括测试仪器、探针卡及权利要求1至6中任意一项所述的能提高电阻测量精度的可寻址测试芯片，测试仪器与能提高电阻测量精度的可寻址测试芯片通过探针卡相连并构成测试通路。
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