WO2020133844A1 - 芯片结构及显示装置 - Google Patents

芯片结构及显示装置 Download PDF

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Publication number
WO2020133844A1
WO2020133844A1 PCT/CN2019/084180 CN2019084180W WO2020133844A1 WO 2020133844 A1 WO2020133844 A1 WO 2020133844A1 CN 2019084180 W CN2019084180 W CN 2019084180W WO 2020133844 A1 WO2020133844 A1 WO 2020133844A1
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WIPO (PCT)
Prior art keywords
bumps
chip
chip substrate
chip structure
lateral direction
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Ceased
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PCT/CN2019/084180
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English (en)
French (fr)
Inventor
刘娟
刘宇
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/485,429 priority Critical patent/US20210408198A1/en
Publication of WO2020133844A1 publication Critical patent/WO2020133844A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Definitions

  • the invention relates to the field of display technology, in particular to a chip structure and a display device.
  • organic light-emitting diode Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the bonding pad of the chip uses fine pitch (Fine pitch) ), getting smaller and smaller to the micron level, the requirements for binding are getting higher and higher.
  • the chip binding is usually to bind the chip to the panel through a conductive adhesive film, and to achieve the upper and lower conduction function through the conductive particles in the conductive adhesive film. With a certain offset, the number of conductive particles in the overlapping part of the chip and the conductive adhesive and the panel must be greater than a certain number to ensure the conduction effect. And between the left and right electrodes, it is necessary to prevent the conductive particles from gathering to cause a short circuit.
  • the electrodes (also called contact bumps) on the surface of the traditional chip are mostly I-shaped, but the spacing between the I-type electrodes is small, the conductive particles have poor fluidity, and it is easy for the conductive particles to gather and cause a circuit short circuit.
  • the overlapping area of the I-type electrode and the panel becomes smaller, so the number of effective conductive particles is small, which is likely to cause poor bonding.
  • the distribution of the contact bump electrodes of the conventional chip has a larger length in the Y axis, which limits the design size of the electrodes, is not conducive to the design of small electrodes and cannot improve the contact conduction effect.
  • the shortcomings caused by the structure of the aforementioned conventional chip electrode seriously affect the bonding effect of the chip, and will also cause a short circuit in the circuit and prevent the display device from displaying normally.
  • the object of the present invention is to provide a chip structure and a display device, which can make the conductive particles used to adhere the conductive adhesive film of the chip structure flow smoothly between each chip electrode when the chip structure is bound, increasing the capture rate of the conductive particles To improve the reliability of binding and avoid short circuit.
  • the present invention provides a chip structure, including: a chip substrate; and a plurality of bumps, which are provided on one surface of the chip substrate, and serve as an interface for electrically connecting the chip substrate and the outer end butt joint,
  • the plurality of bumps are arranged at intervals from each other, and each of the bumps has a rhombic configuration and four sides of equal length, and at least one side of the four sides and a horizontal line passing through an end point of the at least one side form a 45-degree angle
  • the angle between the plurality of bumps is arranged in multiple rows in the horizontal direction and in multiple columns in the longitudinal direction, and the multiple rows of lateral bumps are staggered, and the multiple columns of longitudinal bumps are also staggered.
  • the present invention further provides a chip structure, including: a chip substrate, and a plurality of bumps provided on a surface of the chip substrate, as an interface for electrically connecting the chip substrate and an outer end docking portion.
  • the several bumps are arranged at intervals, and each of the bumps has a diamond-shaped configuration.
  • each of the bumps has four sides of equal length, and at least one of the four sides and a horizontal line passing through the end of the at least one side form an included angle of 45 degrees.
  • the plurality of bumps are arranged in multiple rows in the lateral direction and in multiple columns in the longitudinal direction, and the multiple rows of lateral bumps are staggered, and the multiple columns of longitudinal bumps are also Staggered
  • the plurality of protrusions in the horizontal direction of each row are arranged at an equal interval, and the plurality of protrusions in the longitudinal direction of each column are arranged at an equal interval.
  • the chip substrate is adhered to the outer end butt joint via an adhesive film, and an offset distance is generated, wherein the plurality of bumps are aligned in the lateral direction and are located in the lateral phase There is a spacing between adjacent bumps, which is greater than or equal to the offset distance.
  • the surface of the chip substrate has a rectangular configuration with a first side and a second side perpendicular to the first side, each of the bumps with a diamond configuration has The first vertex connection line is perpendicular to the first side, and the second vertex connection line is perpendicular to the first vertex connection line and the second side.
  • the present invention further provides a display device including an organic light emitting diode panel, a bonding area, and a chip structure provided in the bonding area.
  • the chip structure includes: a chip substrate; and a plurality of bumps, It is provided on one surface of the chip substrate and serves as an interface for electrically connecting the chip substrate and the outer end butt joint, the several bumps are arranged at intervals, and each of the bumps is parallel to the cross section of the surface With diamond configuration.
  • each of the bumps has four sides of equal length, and at least one of the four sides and a horizontal line passing through the end of the at least one side form an included angle of 45 degrees.
  • the plurality of bumps are arranged in multiple rows in the lateral direction and in multiple columns in the longitudinal direction, and the multiple rows of lateral bumps are staggered, and the multiple columns of longitudinal bumps are also It is staggered.
  • the chip substrate is adhered to the bonding area through a conductive adhesive film, and an offset distance is generated, wherein the plurality of bumps are aligned in the lateral direction and are in the lateral phase There is a spacing between adjacent bumps, which is greater than or equal to the offset distance.
  • the chip structure and the display device of the present invention utilize the structure of diamond-shaped bumps to effectively enhance the flow of conductive particles of the conductive adhesive film when the chip is bound, and at the same time increase the capture rate of conductive particles, reduce the phenomenon of conductive particle aggregation, avoid circuit short circuits, and thus ensure the display device working normally.
  • the chip structure of the present invention effectively solves the disadvantages that the flow of conductive particles between the bump electrodes of the conventional chip is blocked, which is easy to cause a short circuit, and is not conducive to the development of small-sized chips.
  • FIG. 1 is a schematic side view of a chip structure binding according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a chip structure according to a preferred embodiment of the present invention.
  • FIG. 3 is a partial schematic diagram of a chip structure according to a preferred embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a chip structure according to a preferred embodiment of the present invention, which is used to show the difference in the attachment area of the chip structure after the binding offset.
  • FIG. 5 is a schematic diagram of a display device according to a preferred embodiment of the present invention.
  • the present invention is a chip structure, which may be a driver chip (IC) that controls each pixel, and is suitable for a display device, where the display device may be a liquid crystal display panel or an organic light-emitting display panel.
  • FIG. 1 is a schematic side view of a chip structure bonding according to a preferred embodiment of the present invention.
  • the chip structure 1 of the present invention is applied to a display device 2 that includes a glass substrate 21, an organic film layer 22 provided on the glass substrate 21, and an organic film layer provided on the organic film layer 22, the paste area 20 and the organic light emitting diode (organic light emitting diode, OLED) panel 23.
  • the chip structure 1 is adhered to the bonding area 20 via the conductive adhesive film 3.
  • the conductive adhesive film 3 is an anisotropic conductive adhesive film (anisotropic conductive film, ACF).
  • the chip structure 1 of the present invention includes a chip substrate 11 and a plurality of bumps 12 provided on one surface of the chip substrate 11, the plurality of bumps 12 are the chip substrate 11 and the OLED panel 23 electrically connected
  • the interface is regarded as the electrode.
  • the plurality of bumps 12 are arranged at intervals, and each of the bumps 12 has a diamond-shaped configuration in cross section parallel to the surface of the chip substrate 11.
  • each of the bumps 12 has four sides of equal length, and the four sides form a 45-degree included angle based on the horizontal line.
  • the plurality of bumps 12 are arranged in multiple rows in the lateral direction and in multiple columns in the longitudinal direction, and the multiple rows of lateral bumps 12 and the multiple rows of longitudinal bumps 12 are alternately arranged with each other.
  • the plurality of bumps 12 in the horizontal direction of each row are arranged at an equal interval, and the plurality of bumps 12 in the vertical direction of each column are arranged at an equal interval, but they are not Limited to the equidistance.
  • FIG. 3 is a partial schematic diagram of a chip structure according to a preferred embodiment of the present invention.
  • the chip structure 1 is adhered and bound via the ACF conductive adhesive film 3.
  • the bumps 12 of the present invention have a diamond configuration and are staggered with each other, the four-sided structure through the diamond shape makes the adjacent
  • the area between the two rhombic electrodes is a parallelogram, and the channel formed by the conductive particles is not conducive to the flow of the conductive particles of the ACF, which can avoid the short circuit of the conductive particles of the ACF and improve the reliability of binding.
  • the surface of the chip substrate 11 has a rectangular configuration, and has a first side 111 and a second side 112 perpendicular to the first side 111.
  • Each of the projections 12 with a diamond configuration has a first vertex connection line L1 perpendicular to the first side 111, and a second vertex connection line L2 perpendicular to the first vertex connection line L1 and the The second side 112.
  • the arrangement relationship between the diamond-shaped bumps 12 and the chip substrate 11 also helps the conductive particles of the ACF not to be hindered when flowing.
  • the chip when the chip is adhesively bonded, it will more or less shift the distance D (as shown in FIG. 4) from the bonding area of the docking part, and the IC bonding is offset to the X axis and Y
  • the axial direction is generally less than or equal to 5 microns.
  • the plurality of bumps 12 of the present invention are aligned in the lateral direction and are located between adjacent bumps 12 in the lateral direction There is a pitch P which is greater than or equal to the offset distance D.
  • the spacing P between the adjacent bumps 12 in the lateral direction is greater than or equal to 5 ⁇ m.
  • the plurality of diamond-shaped bumps 12 cooperate with the setting of the pitch P, so that the conductive particles of the ACF can flow smoothly, which not only strengthens the stability of the binding, but also ensures the electrical connection between the chip substrate 11 and the butt bonding area 20 sexual connection.
  • FIG. 4 is a schematic diagram of a chip structure according to a preferred embodiment of the present invention, which is used to show the difference in the attachment area of the chip structure after the binding offset.
  • the bump 12 of the present invention is diamond-shaped, under the condition that the offset distance D is equal, the diamond-shaped bump 12 is bound to the The overlapping area of the butting portion of the bonding area 20 is large, which is beneficial to capture more conductive particles, thereby increasing the conductive effect.
  • each bump 12 has a contact area with a size between 500 and 1500 microns.
  • the diamond-shaped bumps 12 are more conducive to shortening the length of the electrode in the Y-axis direction, so that the distribution range of the bumps is smaller, so as to meet the development of current small-sized chips.
  • the chip structure 1 of the present invention utilizes the structure of the diamond-shaped bump 12 to effectively enhance the flow of conductive particles of the ACF when the chip is bound, and at the same time increase the capture rate of the conductive particles, reduce the phenomenon of conductive particle aggregation, and avoid circuit short circuits. Make sure the display device is functioning properly.
  • the chip structure 1 of the present invention effectively solves the disadvantages that the flow of conductive particles between the bump electrodes of the conventional chip is blocked, which is easy to cause a short circuit, and is not conducive to the development of small-sized chips.
  • FIG. 5 is a schematic diagram of a display device according to a preferred embodiment of the present invention. Please refer to Figure 5 to see with Figure 1.
  • the present invention further provides a display device 2 including a bonding area 20, a chip structure 1 disposed on the bonding area 20, and an organic light emitting diode panel 23.
  • the organic light emitting diode panel 23 includes a display area 24 and a non-display area 25 located on the periphery of the display area.
  • the bonding area 20 is located in the non-display area 25.
  • the chip structure 1 includes a chip substrate 11; and a plurality of bumps 12, provided on a surface of the chip substrate 11, as the chip substrate 11 and the bonding area 20 (ie, the outer end butt joint) electricity
  • the plurality of bumps 12 are arranged at intervals from each other, and each of the bumps 12 has a diamond-shaped configuration in cross section parallel to the surface.
  • the display device 2 of the present invention further includes a flexible circuit board (not shown), and one end of the flexible circuit board is electrically connected to the chip substrate of the chip structure.
  • the other end of the flexible circuit board is electrically connected to an electronic device main board (not shown) with a display device, such as a mobile phone.
  • the flexible circuit board transmits a control command and a power supply voltage from the main board of the electronic device to the chip structure, so that the chip structure provides voltage and data signals to the organic light-emitting diode panel 23, and then the organic light-emitting diode panel 23
  • the effective display area 24 displays the required screen (as shown in FIG. 5).

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Abstract

一种芯片结构，包含芯片基板及数个凸块。所述数个凸块设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口。所述数个凸块相互间隔排列，且每一所述凸块具有菱形构型。

Description

芯片结构及显示装置 技术领域
本发明涉及显示技术领域，特别是涉及一种芯片结构及显示装置。
 背景技术
随着显示技术的进步，平板显示早已成为当下主流显示器件所用。尤其有机发光二极管（Organic Light-Emitting Diode, OLED）以其自发光、全固态、高对比度等优点，成为近年来最具潜力的显示器件。在有机发光二极管显示装置中，为了对各像素进行控制，通常设有驱动芯片。
此外，随着解析度的增加到宽四倍高清(Wide Quad High Definition,WQHD)，甚至超高清(Ultra High Definition，UHD)，芯片(IP)的焊垫(bonding pad)采用微间距(Fine pitch)，越来越小达到微米级，对绑定的要求越来越高。芯片绑定通常是通过导电胶膜将芯片绑定于面板上，通过导电胶膜中的导电粒子实现上下导通功能。在有一定偏移下，芯片和导电胶及面板重叠部分的导电粒子个数需大于一定数量，才能保证导通效果。且左右电极之间需防止导电粒子聚集造成短路。传统芯片表面的电极(亦称接触凸起)多为I字构型，惟I型电极之间间距小，导电粒子流动性差,容易因导电粒子聚集，造成电路短路。此外，在芯片绑定偏位时，I型电极和面板重叠面积变小，因此有效导电粒子数量少，容易造成绑定不良。再者，传统芯片的接触凸起电极的分布，于Y轴向长度较大，使电极的设计尺寸在受限，不利于小电极的设计而无法提升接触导通效果。诸如前述传统芯片电极的结构所造成的缺点，严重影响芯片的绑定效果，更会导致电路短路而使显示器件无法正常显示。
 技术问题
本发明的目的在于提供一种芯片结构及显示装置，其可使芯片结构于绑定时，用于黏着芯片结构的导电胶膜的导电粒子顺畅流动于各芯片电极之间，增加导电粒子捕捉率，提高绑定可靠性，且避免造成短路。
 技术解决方案
为实现上述目的，本发明提供一种芯片结构，包含：芯片基板；及数个凸块，设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口，所述数个凸块相互间隔排列，且每一所述凸块具有菱形构型及等长的四边，且所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角，其中所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列。
本发明另外提供一种芯片结构，包含：芯片基板，及数个凸块设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口。所述数个凸块相互间隔排列，且每一所述凸块具有菱形构型。
依据本发明的一优选实施例，每一所述凸块具有等长的四边，且所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角。
依据本发明的另一优选实施例，所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列
依据本发明的另一优选实施例，所述每一行横向的数个凸块是以一等距间隔排列，而所述每一列纵向的数个凸块是以一等距间隔排列。
依据本发明的另一优选实施例，所述芯片基板经由胶膜黏着于所述外端对接部，并产生一偏移距离，其中所述数个凸块于横向对齐排列，且位于横向的相邻凸块之间具有一间距，其大于或等于所述偏移距离。
依据本发明的另一优选实施例，所述芯片基板的表面为一矩形构型, 具有第一边和垂直于所述第一边的第二边，每一具菱形构型的凸块, 具有第一顶角连接线垂直于所述第一边，和第二顶角连接线垂直于所述第一顶角连接线和所述第二边。
本发明另外提供一种显示装置，所述显示装置包含有机发光二极管面板、贴合区，及设于所述贴合区的芯片结构，所述芯片结构包括：芯片基板；及数个凸块，设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口，所述数个凸块相互间隔排列，且每一所述凸块平行于所述表面的截面具有菱形构型。
依据本发明的一优选实施例，每一所述凸块具有等长的四边，且所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角。
依据本发明的另一优选实施例，所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列。
依据本发明的另一优选实施例，所述芯片基板经由导电胶膜黏着于所述贴和区，并产生一偏移距离，其中所述数个凸块于横向对齐排列，且位于横向的相邻凸块之间具有一间距，其大于或等于所述偏移距离。
 有益效果
本发明芯片结构及显示装置利用菱形凸块的结构，有效增强芯片绑定时导电胶膜的导电粒子的流动，同时增加导电粒子捕捉率，减少导电粒子聚集现象，避免电路短路，进而确保显示装置正常运作。本发明的芯片结构有效解决传统芯片凸块电极之间的导电粒子流动受阻，容易造成短路，且不利于小尺寸芯片发展的缺点。
 附图说明
图1为根据本发明的一较佳实施例的芯片结构绑定的侧向示意图。
图2为根据本发明的一较佳实施例的芯片结构的示意图。
图3为根据本发明的一较佳实施例的芯片结构的局部示意图。
图4为根据本发明的一较佳实施例的芯片结构的示意图，用以显示芯片结构于绑定偏移后的附着面积的差异关系。
图5为根据本发明的一较佳实施例的显示装置的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明为一种芯片结构，其可为对各像素进行控制的驱动器芯片(IC)，适用于显示装置，其中所述显示装置可为液晶显示面板或有机发光显示面板。图1为根据本发明的一较佳实施例的芯片结构绑定(bonding)的侧向示意图。如图1所示，本发明的芯片结构1应用于显示装置2，所述显示装置2包括玻璃基板21、设于所述玻璃基板21上的有机膜层22，及设于所述有机膜层22上的贴和区20及有机发光二极管(organic light emitting diode, OLED)面板23。具体而言，所述芯片结构1是经由导电胶膜3黏着于所述贴合区20。于此较佳实施例中，所述导电胶膜3为异方性导电胶膜(anisotropic conductive film, ACF)。
图2为根据本发明的一较佳实施例的芯片结构的示意图。本发明的芯片结构1包括芯片基板11及设于所述芯片基板11的一表面的数个凸块12，所述数个凸块12是所述芯片基板11与所述OLED面板23电性连接的接口，亦即视为电极所用。所述数个凸块12相互间隔排列，且每一所述凸块12平行于所述芯片基板11的表面的截面具有菱形构型。特别说明的是，于此较佳实施例中，每一所述凸块12具有等长的四边，且所述四边以水平线为基准，分别构成45度的夹角。具体而言，所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角。此外，所述数个凸块12于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块12与所述多行纵向凸块12相互交错排列。于另一具体实施例中，所述每一行横向的数个凸块12是以一等距间隔排列，而所述每一列纵向的数个凸块12是以等距的间隔排列，但并不以所述等距为限。
图3为根据本发明的一较佳实施例的芯片结构的局部示意图。如前所述，所述芯片结构1经由ACF导电胶膜3黏着绑定，由于本发明的数个凸块12为菱形构型，并相互交错排列，在透过菱形的四边结构，使相邻两菱形电极之间的区域为平行四边形，其所形成的通道有利于ACF的导电粒子于流动时不会受阻，进而可避免ACF的导电粒子聚集造成短路，同时提高绑定的可靠性。此外，所述芯片基板11的表面为一矩形构型, 具有第一边111和垂直于所述第一边111的第二边112。每一具菱形构型的凸块12, 具有第一顶角连接线L1垂直于所述第一边111，和第二顶角连接线L2垂直于所述第一顶角连接线L1和所述第二边112。藉由所述菱形凸块12与所述芯片基板11的配置关系，同样有利于ACF的导电粒子于流动时不会受阻。
续请参阅图2及图3。一般而言，芯片于黏着绑定时，或多或少会和对接部的贴合区产生偏移(shifting)距离D(如图4所示)，而IC绑定偏移于X轴及Y轴向一般为小于或等于5微米。特别说明的是，考量前述偏移范围会造成芯片接触凸块和对接部重叠面积的差异，本发明的所述数个凸块12于横向对齐排列，且位于横向的相邻凸块12之间具有一间距P，其大于或等于所述偏移距离D。亦即，于此具体实施例中，所述横向的相邻凸块12之间的间距P为大于或等于5微米。所述数个菱形凸块12配合所述间距P的设置，可使ACF的导电粒子流动顺畅，不仅强化绑定的稳固性，亦确保所述芯片基板11与所述对接贴合区20的电性连接。
图4为根据本发明的一较佳实施例的芯片结构的示意图，用以显示芯片结构于绑定偏移后的附着面积的差异关系。相较于传统I柱型电极4的矩形构型，由于本发明的凸块12为菱形，在偏移距离D同等的条件下，所述菱形凸块12于绑定偏移后，与所述贴合区20的对接部重叠的面积较大，有利于捕捉到更多的导电粒子，进而增加导电效果。具体而言，所述每一凸块12具有一接触面积，其大小为500至1500微米之间。此外，所述菱形凸块12更有利于缩短电极于Y轴向的长度，使凸块的分布范围更小，以符合当下小尺寸芯片的发展。
综上所述，本发明的芯片结构1利用菱形凸块12的结构，有效增强芯片绑定时ACF的导电粒子的流动，同时增加导电粒子捕捉率，减少导电粒子聚集现象，避免电路短路，进而确保显示装置正常运作。本发明的芯片结构1有效解决传统芯片凸块电极之间的导电粒子流动受阻，容易造成短路，且不利于小尺寸芯片发展的缺点。
图5为根据本发明的一较佳实施例的显示装置的示意图。请参阅图5必配合图1观之。本发明另外提供一种显示装置2，包含贴合区20，设于所述贴合区20的芯片结构1及有机发光二极管面板23。如图5所示，所述有机发光二极管面板23包括显示区24及位于显示区周缘的非显示区25，所述贴合区20位于所述非显示区25内。
所述芯片结构1包括包括芯片基板11；及数个凸块12，设于所述芯片基板11的一表面，作为所述芯片基板11与所述贴和区20(即外端对接部)电性连接的接口，所述数个凸块12相互间隔排列，且每一所述凸块12平行于所述表面的截面具有菱形构型。其他有关本发明芯片结构1的细部构造已详述于前述图1至图4的实施例说明中，于此不再复述。
于另一具体实施中，本发明的显示装置2还包括柔性电路板(未图示)，所述柔性电路板的一端与所述芯片结构的芯片基板电性连接。所述柔性电路板的另一端电性连接具有显示装置的电子装置主板(未图示)，如手机。所述柔性电路板从所述电子装置主板传送控制命令以及电源电压给所述芯片结构，使所述芯片结构提供电压和数据信号给所述有机发光二极管面板23，进而使有机发光二极管面板23的有效显示区24显示需要的画面(如图5所示)。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种芯片结构，包含：
    芯片基板；及
    数个凸块，设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口，所述数个凸块相互间隔排列，且每一所述凸块具有菱形构型及等长的四边，且所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角，
    其中所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列。
  2. 如权利要求1的芯片结构，所述芯片基板经由导电胶膜黏着于所述外端对接部，并产生一偏移距离，其中所述数个凸块于横向对齐排列，且位于横向的相邻凸块之间具有一间距，其大于或等于所述偏移距离。
  3. 如权利要求1的芯片结构，其中所述芯片基板的表面为一矩形构型, 具有第一边和垂直于所述第一边的第二边，每一具菱形构型的凸块, 具有第一顶角连接线垂直于所述第一边，和第二顶角连接线垂直于所述第一顶角连接线和所述第二边。
  4. 一种芯片结构，包含：
    芯片基板；及
    数个凸块，设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口，所述数个凸块相互间隔排列，且每一所述凸块具有菱形构型。
  5. 如权利要求4的芯片结构，其中每一所述凸块具有等长的四边，且所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角。
  6. 如权利要求4的芯片结构，其中所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列。
  7. 如权利要求6的芯片结构，其中所述每一行横向的数个凸块是以一等距间隔排列，而所述每一列纵向的数个凸块是以一等距间隔排列。
  8. 如权利要求4的芯片结构，其中所述芯片基板经由导电胶膜黏着于所述外端对接部，并产生一偏移距离，其中所述数个凸块于横向对齐排列，且位于横向的相邻凸块之间具有一间距，其大于或等于所述偏移距离。
  9. 如权利要求4的芯片结构，其中所述芯片基板的表面为一矩形构型, 具有第一边和垂直于所述第一边的第二边，每一具菱形构型的凸块, 具有第一顶角连接线垂直于所述第一边，和第二顶角连接线垂直于所述第一顶角连接线和所述第二边。
  10. 一种显示装置，包含有机发光显示面板、贴合区，及设于所述贴合区的芯片结构，所述芯片结构包括：
    芯片基板；及
    数个凸块，设于所述芯片基板的一表面，作为所述芯片基板与外端对接部电性连接的接口，所述数个凸块相互间隔排列，且每一所述凸块平行于所述表面的截面具有菱形构型。
  11. 如权利要求10的显示装置，其中每一所述凸块具有等长的四边，所述四边中之至少一边和一通过所述至少一边之端点的水平线构成45度角的夹角。
  12. 如权利要求10的显示装置，其中所述数个凸块于横向呈多行排列，于纵向呈多列排列，且所述多行横向凸块为交错排列，所述多列纵向凸块亦为交错排列。
  13. 如权利要求10的显示装置，其中所述芯片基板经由导电胶膜黏着于所述贴和区，并产生一偏移距离，其中所述数个凸块于横向对齐排列，且位于横向的相邻凸块之间具有一间距，其大于或等于所述偏移距离。
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