WO2020133804A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2020133804A1
WO2020133804A1 PCT/CN2019/082654 CN2019082654W WO2020133804A1 WO 2020133804 A1 WO2020133804 A1 WO 2020133804A1 CN 2019082654 W CN2019082654 W CN 2019082654W WO 2020133804 A1 WO2020133804 A1 WO 2020133804A1
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Prior art keywords
layer
flat
film transistor
thin film
preparing
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French (fr)
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卢改平
唐维
黄建龙
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Definitions

  • the invention relates to the field of displays, in particular to an array substrate and a preparation method thereof.
  • PI coating is applied by APR plate transfer.
  • the coating principle is: using the APR plate transfer method to apply the alignment material Polyimide.
  • the specific steps are as follows :
  • the PI on the plate is uniformly transferred to the substrate 100 to form a liquid crystal alignment layer 200.
  • the quality of PI coating mainly refers to PI coating accuracy, PI film thickness and flatness of PI film layer, among which PI accuracy is the most important.
  • PI accuracy generally refers to the distance from the PI boundary to the AA zone and the fluctuation of the distance. If the PI accuracy is not well controlled, it will cause various defects, such as too small PI accuracy will cause PI The edge (or hale area) enters the AA area, causing light leakage or uneven brightness of the surrounding display (Mura); too large PI accuracy may easily lead to PI coating on the IC side to Ag dots or ICs output pin, causing the circuit to fail to conduct.
  • the existing array substrate includes a display area 500 and a fan-out area 600.
  • the display area 500 includes a flat layer trench 510.
  • the terminal side fan-out area 600 has dense metal traces 610. In order to protect the metal traces 610 is not crushed, to prevent water vapor from entering the array substrate high temperature and high humidity phenomenon, the flat layer can not be grooved.
  • the panel design PLN groove can be used as a PI buffer to improve PI
  • the accuracy is too large to reflow to the useful pattern area on the IC side, but it is limited by the large number of metal traces in the fan-out area on the terminal side, which requires the protection of the flat layer to prevent moisture and pressure injuries from causing the flat layer to not be grooved.
  • the purpose of the present invention is to solve the technical problems in the prior art, such as poor PI coating accuracy, easily damaged metal traces, and inability to groove the flat layer.
  • the present invention provides an array substrate, including: a base layer including a display area and a fan-out area; a first thin film transistor structure layer attached to one side surface of the base layer; a flat layer, attached A side surface of the first thin film transistor structure layer that is far away from the base layer; a flat layer groove, recessed in the fan-out area of the flat layer; and a second thin film transistor structure layer, attached to the A side surface of the flat layer away from the first thin film transistor structure layer.
  • the first thin-film transistor structure layer includes: a light-shielding layer attached to a side surface of the display region of a part of the base layer; a buffer layer attached to a side surface of the light-shielding layer and the remaining base layer; a semiconductor Layer, attached to a portion of the buffer layer's display area away from the surface of the base layer; a first insulating layer attached to the semiconductor layer and the remaining buffer layer away from the surface of the base layer; a gate layer , A display surface attached to a portion of the first insulating layer away from the buffer layer; and a second insulating layer attached to the gate layer and the remaining first insulating layer away from the buffer layer Side surface.
  • the first thin film transistor structure layer further includes: two first vias penetrating the second insulating layer and the upper half of the first insulating layer, the first via and the semiconductor The layers are arranged oppositely; the source and the drain are arranged in the first via and on the side wall extension of the first via; and the metal trace is arranged in the fan-out area of the second insulating layer away from One side surface of the first insulating layer.
  • the flat layer further includes a second via, penetrating the display area of the flat layer and connected to the drain.
  • the second thin film transistor structure layer includes: an electrode layer attached to a side surface of the flat layer away from the second insulating layer and the groove of the flat layer; a passivation layer, attached Attached to the second via and the groove of the flat layer, the electrode layer is away from the side surface of the flat layer; and a pixel electrode layer is attached to the passivation layer away from the electrode layer On one side of the surface, part of the pixel electrode layer is connected to the drain through the second via.
  • the present invention also provides a method for preparing an array substrate, comprising: an S1 base layer setting step, setting a base layer, the base layer including a display area and a fan-out area; S2 The first thin film transistor structure layer preparation step prepares a first thin film transistor structure layer on the upper surface of the base layer; the S3 flat layer preparation step prepares a flat layer on the first thin film transistor structure layer upper surface; S4 flat A step of layer slotting, processing the flat layer with a photomask to form a flat layer groove and a second via; and S5 In the second thin film transistor structure layer preparation step, a second thin film transistor structure layer is prepared on the upper surface of the flat layer.
  • the first thin film transistor structure layer preparation step includes: S21 In the step of preparing the shading layer, a layer of shading material is coated on the upper surface of the display area of the base layer to form a shading layer; In the buffer layer preparation step, a buffer layer is prepared on the upper surface of the shading layer and the remaining base layer; S23 In the semiconductor layer preparation step, a semiconductor layer is prepared on the upper surface of the display area of the buffer layer; S24 In the first insulating layer preparation step, a first insulating layer is prepared on the upper surface of the semiconductor layer and the remaining buffer layer; S25 In the step of preparing a gate layer, a gate layer is prepared on the upper surface of the display area of the first insulating layer; S26 In the second insulating layer preparation step, a second insulating layer is prepared on the upper surface of the gate layer and the remaining first insulating layer; S27 In the first via opening step, a hole is formed in the second insulating layer to form a first via, penetrating through the second insulating layer and
  • the step of preparing the second thin film transistor structure layer includes: S51 An electrode layer preparation step, an electrode layer is prepared on the upper surface of the flat layer and the groove of the flat layer; S52 In the passivation layer preparation step, a passivation layer is prepared in the upper surface of the electrode layer, the second via, and the groove of the flat layer; and S53 In the pixel electrode layer preparation step, a pixel electrode layer is prepared on the upper surface of the passivation layer.
  • the semiconductor layer preparation step includes: S231 An amorphous silicon layer preparation step, an amorphous silicon layer is prepared on the upper surface of the display area of the buffer layer; S232 A polysilicon layer preparation step, performing laser laser annealing on the amorphous silicon layer to form a polysilicon layer; and S233 In the semiconductor layer forming step, the polysilicon layer is ion-doped to form a semiconductor layer.
  • the photomask includes a first opening and a semi-transparent second opening; the first opening is disposed opposite to the drain to form a second via; And the second opening is disposed opposite to the metal trace to form a flat layer groove.
  • the technical effect of the present invention is to use a Halftone mask to semi-slot the fan-out area of the flat layer to protect the dense metal traces in the fan-out area, avoid damage to the array substrate caused by high temperature and high humidity, and prevent PI coating from appearing. There is a phenomenon that the useful side is covered on the terminal side when laying.
  • Figure 1 is a schematic diagram of the APR plate transfer method in the prior art
  • FIG. 3 is a cross-sectional view of an array substrate in the prior art
  • FIG. 4 is a top view of an array substrate according to an embodiment of the invention.
  • FIG. 5 is a cross-sectional view of an array substrate according to an embodiment of the invention.
  • FIG. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
  • FIG. 7 is a flowchart of steps for preparing a first thin film transistor structure layer according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of steps for preparing a second thin film transistor structure layer according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of steps for preparing a semiconductor layer according to an embodiment of the invention.
  • Base layer 2. First thin film transistor structure layer; 3. Flat layer; 4. Second thin film transistor structure layer;
  • Light shielding layer 22, buffer layer; 23, semiconductor layer; 24, first insulating layer; 25, gate layer; 26, second insulating layer;
  • the component When certain components are described as “on” another component, the component may be directly placed on the other component; there may also be an intermediate component, which is placed on the intermediate component , And the intermediate component is placed on another component.
  • the two When a component is described as “installed to” or “connected to” another component, the two can be understood to be “installed” or “connected” directly, or a component “installed to” or “connected to” through an intermediate component Another component.
  • the present invention provides an array substrate, which includes a base layer 1, a first thin film transistor structure layer 2, a flat layer 3, and a second thin film transistor structure layer 4 in order from bottom to top.
  • the base layer 1 includes a display Area and fan-out area.
  • the first thin film transistor structure layer 2 includes a light shielding layer 21, a buffer layer 22, a semiconductor layer 23, a first insulating layer 24, a gate layer 25, and a second insulating layer 26.
  • the light shielding layer 21 is attached to the upper surface of the display area of some base layers, and the material of the light shielding layer 21 is Mo.
  • the buffer layer 22 is attached to the upper surface of the remaining base layer and the light shielding layer 21.
  • the semiconductor layer 23 is attached to the upper surface of the display area of part of the buffer layer, and the material of the semiconductor layer 23 is silicon.
  • the first insulating layer 24 is attached to the upper surface of the remaining buffer layer and the semiconductor layer 23, and the first insulating layer 24 is a gate insulating layer (Gate Insulator, GI), the material is usually SiNx or SiOx.
  • the gate layer 25 is attached to a part of the upper surface of the display area of the first insulating layer.
  • the second insulating layer 26 is attached to the upper surfaces of the remaining first insulating layer and the gate layer 25.
  • the two first vias 261 penetrate the second insulating layer 26 and are connected to the semiconductor layer 23.
  • the drain 262 and the source 263 are respectively located on the sidewall extensions on both sides of the first via 261.
  • the metal traces 264 are densely distributed on the upper surface of the fan-out area of the second insulating layer 26.
  • the flat layer 3 has a second via hole 31 and a flat layer groove 32.
  • the second via hole 31 penetrates the display area of the flat layer 3 and is connected to the drain 262 to facilitate the subsequent second thin film transistor structure layer 4 and the drain 262 connected.
  • the flat layer groove 32 is half-recessed in the fan-out area of the flat layer 3 and is located above the metal trace 264 to protect the metal trace.
  • the second thin film transistor structure layer 4 includes an electrode layer 41, a passivation layer 42 and a pixel electrode layer 43.
  • the electrode layer 41 is attached to the upper surface of the flat layer 3 and the flat layer groove 32.
  • the passivation layer 42 is attached to the upper surface of the electrode layer 41 and the inner sidewall of the second via 31.
  • the material of the passivation layer 42 is PI film solution (polyimide film solution).
  • the pixel electrode layer 43 is attached to the upper surface of the passivation layer 42 and is connected to the drain electrode 262 through the second via 31.
  • the technical effect of the present invention is that, in the fan-out area of the flat layer, the semi-slot is provided to protect the dense metal traces, prevent the metal traces from being damaged by high temperature and high humidity, and at the same time, prevent covering during the passivation layer coating preparation process A useful pattern on the terminal side causes an abnormal phenomenon on the array substrate.
  • This embodiment also provides a method for preparing an array substrate, including steps S1 to S5.
  • a base layer is provided, and the base layer includes a display area and a fan-out area;
  • S2 In the first thin film transistor structure layer preparation step, a first thin film transistor structure layer is prepared on the upper surface of the base layer.
  • the first thin film transistor structure layer preparation step includes: S21 In the light-shielding layer preparation step, a layer of light-shielding material is coated on the upper surface of the display area of the base layer to form a light-shielding layer, and the material of the light-shielding material is Mo. S22 In the buffer layer preparation step, a buffer layer is prepared on the upper surfaces of the light-shielding layer and the remaining base layer. S23 In the semiconductor layer preparation step, a semiconductor layer is prepared on the upper surface of the display area of the buffer layer.
  • the semiconductor layer preparation step includes: S231 An amorphous silicon layer preparation step, an amorphous silicon layer is prepared on the upper surface of the display area of the buffer layer; S232 A polysilicon layer preparation step, performing laser laser annealing on the amorphous silicon layer to form a polysilicon layer; and S233 In the semiconductor layer forming step, the polysilicon layer is ion-doped to form a semiconductor layer (see FIG. 9).
  • S24 In the first insulating layer preparation step a first insulating layer is prepared on the upper surfaces of the semiconductor layer and the remaining buffer layer.
  • S25 In the gate layer preparation step a gate layer is prepared on the upper surface of the display area of the first insulating layer.
  • a second insulating layer is prepared on the upper surfaces of the gate layer and the remaining first insulating layer.
  • S27 In the first via opening step a hole is formed in the second insulating layer to form a first via, the first via penetrates through the second insulating layer and the upper half of the first insulating layer The position of the first via is opposite to the semiconductor layer.
  • S28 In the source-drain preparation step a drain is prepared in the first via and on the upper surface of the side wall extension, and a source is prepared at a position opposite to the first via and the semiconductor layer.
  • S29 In the metal wiring preparation step a metal wiring is prepared on the upper surface of the fan-out area of the second insulating layer.
  • a flat layer is prepared on the upper surface of the second insulating layer and the metal trace, and in the first via hole, the flat layer is based on its thickness, process, etc.
  • the smoothness of the structure facilitates the subsequent preparation of the second thin film transistor structure layer.
  • the photomask includes a first opening and a semi-transparent second opening; the first opening is disposed opposite to the drain to form a second via; and the second opening is opposite to the metal trace Set to form a flat layer groove.
  • the flat layer groove protects the dense metal traces underneath, and is convenient for coating in the design range in the subsequent preparation process of the second thin film transistor structure layer, without covering the useful pattern, and ensuring the normal use of the array substrate.
  • S5 a second thin film transistor structure layer preparation step, a second thin film transistor structure layer is prepared on the upper surface of the flat layer.
  • the step of preparing the second thin film transistor structure layer includes: S51 In the electrode layer preparation step, an electrode layer is prepared on the upper surface of the flat layer and the groove of the flat layer. S52 In the preparation step of the passivation layer, a layer of PI film liquid is coated on the upper surface of the electrode layer, the second via hole and the groove of the flat layer by means of APR transfer to form a passivation layer. S53 In the pixel electrode layer preparation step, a pixel electrode layer is prepared on the upper surface of the passivation layer.
  • the technical effect of this embodiment is that the halftone mask is used to process the flat layer to form a flat layer groove, which not only protects the dense metal traces in the fan-out area from damage due to high temperature and high humidity, but also prevents dullness.
  • the coating layer exceeds the original design position when coating, so that the useful pattern on the terminal side is covered and abnormal.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制备方法，所述阵列基板包括：基层（1）、第一薄膜晶体管结构层（2）、平坦层（3）、平坦层凹槽（32）以及第二薄膜晶体管结构层（4）。所述阵列基板的制备方法包括：基层设置步骤（S1）、第一薄膜晶体管结构层制备步骤（S2）、平坦层制备步骤（S3）、平坦层开槽步骤（S4）以及第二薄膜晶体管结构层制备步骤（S5）。本发明的技术效果在于，保护密集的金属走线，防止PI涂布精度差等情况。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示器领域，特别涉及一种阵列基板及其制备方法。
 背景技术
如图1所示，在小尺寸的LCD面板行业中，PI涂布采用APR版转印的方式进行涂布，涂布原理为：利用APR板转印的方式涂布配向材料Polyimide，具体步骤如下：
1.利用压力将PI液通过堵孔（Nozzle）滴在网纹辊300（Anilox Roll）上；
2.用刮刀400（Doctor Blade）将网纹辊上的PI液整平；
3.APR板上的圆型凸出物将网纹辊凹槽内PI挤压出来并带走；
4.将APR 板上PI均匀转印到基板100上，形成液晶配向层200。
PI涂布的质量主要指PI涂布精度，PI膜厚以及PI膜层的平坦度等，其中PI精度最为重要。PI精度一般指PI边界到AA区距离以及距离的波动性，PI精度如果控制不好会引起各种不良，如PI精度过小会导致PI edge（或hale区）进入AA区，引起漏光或者周边显示器亮度不均匀（Mura）；PI精度过大容易导致IC侧PI涂布到Ag点或者IC output pin，从而导致电路无法导通。
如图2、3所示，现有的阵列基板包括显示区500及扇出区600，显示区500包括平坦层沟槽510，端子侧扇出区600金属走线610密集，为了保护金属走线610不被压伤，防止水汽进入导致阵列基板高温高湿现象，平坦层无法做开槽处理。
随着面板窄边框化，端子侧PI 涂布距离IC Pin等有用图形越来越近，这样对于PI涂布精度要求越来越高；针对PI涂布精度过差的问题：面板设计PLN沟槽可做为PI缓冲，改善PI 精度过大回流至IC侧有用图形区域，但受限于端子侧扇出区金属走线较多，需平坦层保护，防止水汽及压伤而导致平坦层无法开槽等问题。
 技术问题
本发明的目的在于，解决现有技术中PI涂布精度差、金属走线易受损、平坦层无法开槽等技术问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，包括：一基层，包括显示区及扇出区；一第一薄膜晶体管结构层，贴附于所述基层的一侧表面；一平坦层，贴附于所述第一薄膜晶体管结构层远离所述基层的一侧表面；一平坦层凹槽，下凹于所述平坦层的扇出区；以及一第二薄膜晶体管结构层，贴附于所述平坦层远离所述第一薄膜晶体管结构层的一侧表面。
进一步地，所述第一薄膜晶体管结构层包括：一遮光层，贴附于部分基层的显示区一侧表面；一缓冲层，贴附于所述遮光层及剩余基层的一侧表面；一半导体层，贴附于部分缓冲层的显示区远离所述基层的一侧表面；一第一绝缘层，贴附于所述半导体层及剩余缓冲层远离所述基层的一侧表面；一栅极层，贴附于部分第一绝缘层的显示区远离所述缓冲层的一侧表面；以及一第二绝缘层，贴附于所述栅极层及剩余第一绝缘层远离所述缓冲层的一侧表面。
进一步地，所述第一薄膜晶体管结构层还包括：二个第一过孔，贯穿所述第二绝缘层及所述第一绝缘层的上半部，所述第一过孔与所述半导体层相对设置；源极及漏极，设于所述第一过孔内及所述第一过孔侧壁延伸部上；以及金属走线，设于所述第二绝缘层的扇出区远离所述第一绝缘层的一侧表面。
进一步地，所述平坦层还包括一第二过孔，贯穿所述平坦层的显示区，且连接至所述漏极。
进一步地，所述第二薄膜晶体管结构层包括：一电极层，贴附于所述平坦层远离所述第二绝缘层的一侧表面及所述平坦层凹槽内；一钝化层，贴附于所述第二过孔及所述平坦层凹槽内、所述电极层远离所述平坦层的一侧表面；以及一像素电极层，贴附于所述钝化层远离所述电极层的一侧表面，部分像素电极层通过所述第二过孔连接至所述漏极。
为实现上述目的，本发明还提供一种阵列基板的制备方法，包括：S1基层设置步骤，设置一基层，所述基层包括显示区及扇出区；S2 第一薄膜晶体管结构层制备步骤，在所述基层上表面制备出一第一薄膜晶体管结构层；S3平坦层制备步骤，在所述第一薄膜晶体管结构层上表面制备出一平坦层；S4 平坦层开槽步骤，利用光罩处理所述平坦层，形成一平坦层凹槽及一第二过孔；以及S5 第二薄膜晶体管结构层制备步骤，在所述平坦层上表面制备出一第二薄膜晶体管结构层。
进一步地，所述第一薄膜晶体管结构层制备步骤包括：S21 遮光层制备步骤，在所述基层的显示区上表面涂布一层遮光材料，形成一遮光层；S22 缓冲层制备步骤，在所述遮光层及剩余基层的上表面制备出一缓冲层；S23 半导体层制备步骤，在所述缓冲层的显示区上表面制备出一半导体层；S24 第一绝缘层制备步骤，在所述半导体层及剩余缓冲层上表面制备出一第一绝缘层；S25 栅极层制备步骤，在所述第一绝缘层的显示区上表面制备出一栅极层；S26 第二绝缘层制备步骤，在所述栅极层及剩余第一绝缘层的上表面制备出一第二绝缘层；S27 第一过孔开孔步骤，在所述第二绝缘层上开孔，形成第一过孔，贯穿于所述第二绝缘层及所述第一绝缘层的上半部，所述第一过孔位置与所述半导体层相对设置；S28 源漏极制备步骤，在所述第一绝缘层及所述第二绝缘层内制备源极及漏极；以及S29 金属走线制备步骤，在所述第二绝缘层的扇出区的上表面制备出金属走线。
进一步地，所述第二薄膜晶体管结构层制备步骤包括：S51 电极层制备步骤，在所述平坦层上表面及所述平坦层凹槽内制备出一电极层；S52 钝化层制备步骤，在所述电极层上表面、所述第二过孔及所述平坦层凹槽内制备出一钝化层；以及S53 像素电极层制备步骤，在所述钝化层上表面制备出一像素电极层。
进一步地，所述半导体层制备步骤包括：S231 非晶硅层制备步骤，在所述缓冲层的显示区的上表面制备出一非晶硅层；S232 多晶硅层制备步骤，对所述非晶硅层进行镭射激光退火处理，形成以多晶硅层；以及S233 半导体层形成步骤，对所述多晶硅层进行离子掺杂，形成以半导体层。
进一步地，在所述平坦层开槽步骤中，所述光罩包括第一开口和半透光的第二开口；所述第一开口与所述漏极相对设置，形成一第二过孔；以及所述第二开口与所述金属走线相对设置，形成一平坦层凹槽。
 有益效果
本发明的技术效果在于，利用Halftone光罩，在平坦层的扇出区上方半开槽，既保护扇出区密集金属走线，避免高温高湿导致阵列基板受损，又可以防止出现PI涂布时端子侧有用图形被覆盖的现象。
 附图说明
图1为现有技术中APR版转印方式示意图；
图2为现有技术中阵列基板的俯视图；
图3为现有技术中阵列基板的剖面图；
图4为本发明实施例所述阵列基板的俯视图；
图5为本发明实施例所述阵列基板的剖面图；
图6为本发明实施例所述阵列基板的制备方法的流程图；
图7为本发明实施例所述第一薄膜晶体管结构层制备步骤的流程图；
图8为本发明实施例所述第二薄膜晶体管结构层制备步骤的流程图；
图9为本发明实施例所述半导体层制备步骤的流程图。
部分部件标识如下：
100、基板；200、液晶配向层；300、网纹辊；400、刮刀；
500、显示区；510、平坦层沟槽；600、扇出区；610、金属走线；
1、基层；2、第一薄膜晶体管结构层；3、平坦层；4、第二薄膜晶体管结构层；
21、遮光层；22、缓冲层；23、半导体层；24、第一绝缘层；25、栅极层；26、第二绝缘层；
261、第一过孔；262、漏极；263、源极；264、金属走线；
31、第二过孔；32、平坦层凹槽；
41、电极层；42、钝化层；43、像素电极层。
 本发明的最佳实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
如图4、5所示，本发明提供一种阵列基板，从下往上依次为包括基层1、第一薄膜晶体管结构层2、平坦层3及第二薄膜晶体管结构层4，基层1包括显示区及扇出区。
第一薄膜晶体管结构层2包括：遮光层21、缓冲层22、半导体层23、第一绝缘层24、栅极层25及第二绝缘层26。
遮光层21贴附于部分基层的显示区的上表面，遮光层21的材质为Mo。缓冲层22贴附于剩余基层及遮光层21的上表面。半导体层23贴附于部分缓冲层的显示区的上表面，半导体层23的材质为硅。第一绝缘层24贴附于剩余缓冲层及半导体层23的上表面，第一绝缘层24为栅极绝缘层（Gate Insulator，GI），材质通常为SiNx或SiOx。栅极层25贴附于部分第一绝缘层的显示区的上表面。第二绝缘层26贴附于剩余第一绝缘层及栅极层25的上表面。
二个第一过孔261贯穿第二绝缘层26，连接至半导体层23，漏极262和源极263分别位于第一过孔261两侧侧壁延伸部上。金属走线264密集分布于第二绝缘层26的扇出区的上表面。
平坦层3上有第二过孔31和平坦层凹槽32，第二过孔31贯穿平坦层3的显示区，且连接至漏极262，便于后续的第二薄膜晶体管结构层4与漏极262相连。平坦层凹槽32半下凹于平坦层3的扇出区，位于金属走线264的上方，保护金属走线。
第二薄膜晶体管结构层4包括：电极层41、钝化层42及像素电极层43。
电极层41贴附于平坦层3的上表面及平坦层凹槽32内。钝化层42贴附于电极层41的上表面及第二过孔31内侧壁，钝化层42的材质为PI膜液（聚酰亚胺膜液）。像素电极层43贴附于钝化层42的上表面，且通过第二过孔31连接至漏极262。
本发明的技术效果在于，在平坦层的扇出区半开槽，保护密集金属走线，防止金属走线受到高温高湿的损伤，同时，防止在钝化层涂布制备的过程中，覆盖端子侧有用图形导致阵列基板出现异常现象。
本实施例还提供一种阵列基板的制备方法，包括步骤S1~S5。
如图6所示，S1 基层设置步骤，设置一基层，所述基层包括显示区及扇出区；S2 第一薄膜晶体管结构层制备步骤，在所述基层上表面制备出一第一薄膜晶体管结构层。
如图7所示，所述第一薄膜晶体管结构层制备步骤包括：S21 遮光层制备步骤，在在所述基层的显示区上表面涂布一层遮光材料，形成一遮光层，所述遮光材料的材质为Mo。S22 缓冲层制备步骤，在所述遮光层及剩余基层的上表面制备出一缓冲层。S23 半导体层制备步骤，在所述缓冲层的显示区上表面制备出一半导体层。所述半导体层制备步骤包括：S231 非晶硅层制备步骤，在所述缓冲层的显示区的上表面制备出一非晶硅层；S232 多晶硅层制备步骤，对所述非晶硅层进行镭射激光退火处理，形成以多晶硅层；以及S233 半导体层形成步骤，对所述多晶硅层进行离子掺杂，形成以半导体层（参见图9）。S24 第一绝缘层制备步骤，在所述半导体层及剩余缓冲层上表面制备出一第一绝缘层。S25 栅极层制备步骤，在所述第一绝缘层的显示区上表面制备出一栅极层。S26 第二绝缘层制备步骤，在所述栅极层及剩余第一绝缘层的上表面制备出一第二绝缘层。S27 第一过孔开孔步骤，在所述第二绝缘层上开孔，形成第一过孔，所述第一过孔贯穿于所述第二绝缘层及所述第一绝缘层的上半部，所述第一过孔位置与所述半导体层相对设置。S28 源漏极制备步骤，在所述第一过孔内以及侧壁延伸部的上表面制备出漏极，在所述第一过孔与所述半导体层相对位置制备出一源极。S29 金属走线制备步骤，在所述第二绝缘层的扇出区的上表面制备出金属走线。
S2 平坦层制备步骤，在所述第二绝缘层及所述金属走线的上表面、所述第一过孔内制备出一平坦层，所述平坦层基于其厚度、工艺等，本身具有良好的平整性，便于后续第二薄膜晶体管结构层的制备。
S3 平坦层开槽步骤，利用Halftone光罩处理所述平坦层，形成一平坦层凹槽及一第二过孔。所述光罩包括第一开口和半透光的第二开口；所述第一开口与所述漏极相对设置，形成一第二过孔；以及所述第二开口与所述金属走线相对设置，形成一平坦层凹槽。所述平坦层凹槽在保护下方密集金属走线的同时，便于在后续第二薄膜晶体管结构层的制备过程中，涂布在设计范围内，不覆盖有用图形，保证阵列基板的正常使用。
S5 第二薄膜晶体管结构层制备步骤，在所述平坦层上表面制备出一第二薄膜晶体管结构层。
如图8所示，所述第二薄膜晶体管结构层制备步骤包括：S51 电极层制备步骤，在所述平坦层上表面及所述平坦层凹槽内制备出一电极层。S52 钝化层制备步骤，利用APR转印的方式在所述电极层上表面、所述第二过孔及所述平坦层凹槽内涂布一层PI膜液，形成一钝化层。S53 像素电极层制备步骤，在所述钝化层上表面制备出一像素电极层。
本实施例的技术效果在于，利用Halftone光罩处理平坦层，形成一平坦层凹槽，既保护了扇出区的密集金属走线，使其避免因高温高湿而受损，又可以防止钝化层在涂布的时候超出原有设计位置，使得端子侧有用图形被覆盖而异常。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括：
    一基层，包括显示区及扇出区；
    一第一薄膜晶体管结构层，贴附于所述基层的一侧表面；
    一平坦层，贴附于所述第一薄膜晶体管结构层远离所述基层的一侧表面；
    一平坦层凹槽，下凹于所述平坦层的扇出区；以及
    一第二薄膜晶体管结构层，贴附于所述平坦层远离所述第一薄膜晶体管结构层的一侧表面。
  2. 如权利要求1所述的阵列基板，其中，
    所述第一薄膜晶体管结构层包括：
    一遮光层，贴附于部分基层的显示区一侧表面；
    一缓冲层，贴附于所述遮光层及剩余基层的一侧表面；
    一半导体层，贴附于部分缓冲层的显示区远离所述基层的一侧表面；
    一第一绝缘层，贴附于所述半导体层及剩余缓冲层远离所述基层的一侧表面；
    一栅极层，贴附于部分第一绝缘层的显示区远离所述缓冲层的一侧表面；以及
    一第二绝缘层，贴附于所述栅极层及剩余第一绝缘层远离所述缓冲层的一侧表面。
  3. 如权利要求2所述的阵列基板，其中，
    所述第一薄膜晶体管结构层还包括：
    二个第一过孔，贯穿所述第二绝缘层及所述第一绝缘层的上半部，所述第一过孔与所述半导体层相对设置；
    源极及漏极，设于所述第一过孔内及所述第一过孔侧壁延伸部上；以及
    金属走线，设于所述第二绝缘层的扇出区远离所述第一绝缘层的一侧表面。
  4. 如权利要求1所述的阵列基板，其中，
    所述平坦层还包括一第二过孔，贯穿所述平坦层的显示区，且连接至所述漏极。
  5. 如权利要求1所述的阵列基板，其中，
    所述第二薄膜晶体管结构层包括：
    一电极层，贴附于所述平坦层远离所述第二绝缘层的一侧表面及所述平坦层凹槽内；
    一钝化层，贴附于所述第二过孔及所述平坦层凹槽内、所述电极层远离所述平坦层的一侧表面；以及
    一像素电极层，贴附于所述钝化层远离所述电极层的一侧表面，部分像素电极层通过所述第二过孔连接至所述漏极。
  6. 一种阵列基板的制备方法，其包括：
    S1 基层设置步骤，设置一基层，所述基层包括显示区及扇出区；
    S2 第一薄膜晶体管结构层制备步骤，在所述基层上表面制备出一第一薄膜晶体管结构层；
    S3 平坦层制备步骤，在所述第一薄膜晶体管结构层上表面制备出一平坦层；
    S4 平坦层开槽步骤，利用光罩处理所述平坦层，形成一平坦层凹槽及一第二过孔；以及
    S5 第二薄膜晶体管结构层制备步骤，在所述平坦层上表面制备出一第二薄膜晶体管结构层。
  7. 如权利要求6所述的阵列基板的制备步骤，其中，
    所述第一薄膜晶体管结构层制备步骤包括：
    S21 遮光层制备步骤，在所述基层的显示区上表面涂布一层遮光材料，形成一遮光层；
    S22 缓冲层制备步骤，在所述遮光层及剩余基层的上表面制备出一缓冲层；
    S23 半导体层制备步骤，在所述缓冲层的显示区上表面制备出一半导体层；
    S24 第一绝缘层制备步骤，在所述半导体层及剩余缓冲层上表面制备出一第一绝缘层；
    S25 栅极层制备步骤，在所述第一绝缘层的显示区上表面制备出一栅极层；
    S26 第二绝缘层制备步骤，在所述栅极层及剩余第一绝缘层的上表面制备出一第二绝缘层；
    S27 第一过孔开孔步骤，在所述第二绝缘层上表面开孔，形成第一过孔，贯穿于所述第二绝缘层及所述第一绝缘层的上半部，所述第一过孔位置与所述半导体层相对设置；
    S28 源漏极制备步骤，在所述第一绝缘层及所述第二绝缘层内制备源极及漏极；以及
    S29 金属走线制备步骤，在所述第二绝缘层的扇出区的上表面制备出金属走线。
  8. 如权利要求6所述的阵列基板的制备步骤，其中，
    所述第二薄膜晶体管结构层制备步骤包括：
    S51 电极层制备步骤，在所述平坦层上表面及所述平坦层凹槽内制备出一电极层；
    S52 钝化层制备步骤，在所述电极层上表面、所述第二过孔及所述平坦层凹槽内制备出一钝化层；以及
    S53 像素电极层制备步骤，在所述钝化层上表面制备出一像素电极层。
  9. 如权利要求7所述的阵列基板的制备步骤，其中，
    所述半导体层制备步骤包括，
    S231 非晶硅层制备步骤，在所述缓冲层的显示区的上表面制备出一非晶硅层；
    S232 多晶硅层制备步骤，对所述非晶硅层进行镭射激光退火处理，形成以多晶硅层；以及
    S233 半导体层形成步骤，对所述多晶硅层进行离子掺杂，形成以半导体层。
  10. 如权利要求6所述的阵列基板的制备方法，其中，
    在所述平坦层开槽步骤中，
    所述光罩包括第一开口和半透光的第二开口；
    所述第一开口与所述漏极相对设置，形成一第二过孔；以及
    所述第二开口与所述金属走线相对设置，形成一平坦层凹槽。
PCT/CN2019/082654 2018-12-27 2019-04-15 阵列基板及其制备方法 Ceased WO2020133804A1 (zh)

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