WO2020124858A1 - 薄膜晶体管的制作方法以及薄膜晶体管 - Google Patents

薄膜晶体管的制作方法以及薄膜晶体管 Download PDF

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WO2020124858A1
WO2020124858A1 PCT/CN2019/080720 CN2019080720W WO2020124858A1 WO 2020124858 A1 WO2020124858 A1 WO 2020124858A1 CN 2019080720 W CN2019080720 W CN 2019080720W WO 2020124858 A1 WO2020124858 A1 WO 2020124858A1
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active layer
thin film
film transistor
manufacturing
forming
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PCT/CN2019/080720
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French (fr)
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黄田玉
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武汉华星光电半导体显示技术有限公司
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Priority to US16/604,262 priority Critical patent/US11309401B2/en
Publication of WO2020124858A1 publication Critical patent/WO2020124858A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Definitions

  • the present application relates to a thin film transistor technology, in particular to a method for manufacturing a thin film transistor and a thin film transistor.
  • the manufacturing process of the thin film transistor of the display panel includes forming an active layer.
  • LTPS Low Temperature Poly-Silicon
  • the process steps are relatively complicated.
  • the embodiments of the present application provide a method for manufacturing a thin film transistor and a thin film transistor, to solve the technical problem that the existing thin film transistor has complicated process steps in the manufacturing process.
  • An embodiment of the present application provides a method for manufacturing a thin film transistor, which includes:
  • the material of the active layer is cubic phase boron nitride
  • the active layer is formed by a chemical vapor deposition process, and gases forming the active layer include boron chloride, boron hydride, and ammonia gas;
  • the step of forming an active layer on the substrate and patterning the active layer includes:
  • the patterned active layer includes a channel region and doped regions on both sides of the channel region, and the manufacturing method of the thin film transistor includes the active Layer is doped, and the step of doping the active layer includes:
  • the second doping process is performed on the doped region exposed by the via, and the element doping amount of the second doping process is less than one third of the element doping amount of the first doping process.
  • the doping region is an N-type doping region
  • the doping element of the doping region is one or a mixture of phosphorus, arsenic, and antimony.
  • the doped region is a P-type doped region
  • the doping element of the doped region is one or a mixture of boron and indium.
  • the doping process is an ion implantation process.
  • the source-drain metal layer is electrically connected to the doped region through a via.
  • An embodiment of the present application also provides a method for manufacturing a thin film transistor, which includes:
  • the material of the active layer is cubic phase boron nitride
  • a source-drain metal layer is formed on the substrate.
  • the active layer is formed by a chemical vapor deposition process, and the gas forming the active layer includes chlorination Boron (BCl 3 ), boron hydride (B 2 H 4 ) and ammonia gas (NH 3 ).
  • the gas forming the active layer includes chlorination Boron (BCl 3 ), boron hydride (B 2 H 4 ) and ammonia gas (NH 3 ).
  • the steps of forming an active layer on the substrate and patterning the active layer include:
  • the patterned active layer includes a channel region and doped regions on both sides of the channel region, and the manufacturing method of the thin film transistor includes the active Layer is doped, and the step of doping the active layer includes:
  • the second doping process is performed on the doped region exposed by the via, and the element doping amount of the second doping process is less than one third of the element doping amount of the first doping process.
  • the doping region is an N-type doping region
  • the doping element of the doping region is one or a mixture of phosphorus, arsenic, and antimony.
  • the doped region is a P-type doped region
  • the doping element of the doped region is one or a mixture of boron and indium.
  • the doping process is an ion implantation process.
  • the manufacturing method of the thin film transistor includes:
  • a second insulating layer and a source-drain metal layer are sequentially formed on the gate metal layer, and the source-drain metal layer is electrically connected to the doped region through a via.
  • the present application also relates to a thin film transistor, which includes:
  • An active layer provided on the substrate
  • a first insulating layer provided on the active layer
  • a gate metal layer provided on the first insulating layer
  • a second insulating layer provided on the gate metal layer
  • a source-drain metal layer provided on the second insulating layer
  • the active layer is made of cubic boron nitride.
  • the thin film transistor is an N-type thin film transistor or a P-type thin film transistor.
  • the manufacturing method and thin film transistor of the present application use cubic phase boron nitride instead of polysilicon as the material of the active layer, and directly use the chemical vapor deposition process (Chemical Vapor Deposition (CVD) forms a cubic phase boron nitride active layer, saving the existing process of thin film transistors using polysilicon as the active layer material, performing three processes of dehydrogenation, annealing and hydrogenation, simplifying the thin film transistor
  • CVD Chemical Vapor Deposition
  • the manufacturing process improves the manufacturing efficiency of the thin film transistor; it solves the technical problem that the existing thin film transistor has more complicated process steps in the manufacturing process.
  • FIG. 1 is a flowchart of a method for manufacturing a thin film transistor in the prior art
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present application
  • step S2 of the method for manufacturing a thin film transistor according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application.
  • the manufacturing method of the thin film transistor of the present application includes:
  • the material of the active layer is cubic phase boron nitride
  • a source-drain metal layer is formed on the substrate.
  • the present application takes a thin film transistor with a top gate structure as an example for description, but it is not limited thereto.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present application.
  • the manufacturing method of the thin film transistor of the present application includes:
  • the material of the active layer is cubic phase boron nitride
  • the source-drain metal layer is formed on the second insulating layer, and patterning the source-drain metal layer, the source-drain metal layer is connected to the doped region of the active layer through a via;
  • a flat layer is formed on the source-drain metal layer.
  • a cubic phase boron nitride (C-boron nitride) active layer is used to replace the prior art polysilicon active layer, because the cubic phase boron nitride has a higher hole migration Rate (500cm 2 V -1 s -1 ), while the hole mobility of polysilicon is 480cm 2 V -1 s -1 .
  • the cubic phase boron nitride has the property of being dopable, and the carrier concentration can be adjusted by ion implantation, so the chemical vapor deposition process (Chemical Vapor Deposition, CVD) can be directly used to directly form the cubic phase boron nitride active layer, saving The process of dehydrogenating the amorphous silicon film, the process of laser annealing the amorphous silicon film to form the polysilicon active layer, and the process of hydrogenating the entire thin film transistor.
  • CVD Chemical Vapor Deposition
  • cubic phase boron nitride has a wider forbidden band width (6.4eV) than polysilicon, so that when cubic phase boron nitride is used as the channel, the thin film transistor has a smaller leakage current; and it has double doping characteristics , So that the source, drain and channel of the MOS tube can be doped with P-type or N-type to form a wider space charge region, further reducing leakage current.
  • the manufacturing method of the thin film transistor of the present embodiment the manufacturing method of the thin film transistor is described in detail below.
  • step S1 prepare a substrate.
  • the substrate includes a base, and a barrier layer and a buffer layer sequentially disposed on the base.
  • step S2 forming an active layer on a substrate and patterning the active layer, the material of the active layer is cubic phase boron nitride.
  • the active layer is directly formed on the substrate by a chemical vapor deposition process (CVD).
  • the gas forming the cubic phase boron nitride active layer includes boron chloride (BCl 3 ), boron hydride (B 2 H 4 ), and ammonia gas (NH 3 ).
  • step S2 includes:
  • Step 201 Coating photoresist on the active layer
  • Step 202 Expose and develop the photoresist by using a mask process to form an exposed area exposing the active layer;
  • Step 203 Etching the active layer in the exposed area to form a patterned active layer
  • Step 204 Remove the remaining photoresist.
  • the patterned active layer includes a channel region and doped regions on both sides of the channel region, and the manufacturing method of the thin film transistor includes doping the active layer, step S3 : Perform the first doping treatment on the doped area.
  • the doping element in the doped region is one or a mixture of phosphorus, arsenic, and antimony.
  • the doping area is a P-type doping area
  • the doping element in the doping area is one or a mixture of boron and indium.
  • the doping process is an ion implantation process.
  • step S4 forming the first insulating layer on the active layer.
  • the first insulating layer can be prepared by spin coating, chemical vapor deposition and other methods.
  • step S5 forming a gate metal layer on the first insulating layer, and patterning the gate metal layer.
  • the gate metal layer is formed on the first insulating layer by chemical vapor deposition or sputtering.
  • step S6 forming a second insulating layer on the gate metal layer.
  • step S7 forming via holes in regions of the second insulating layer and the first insulating layer corresponding to the doped regions of the active layer, so as to expose at least part of the doped regions.
  • the via penetrates the first insulating layer and the second insulating layer.
  • step S8 performing a second doping process on the doped region exposed by the via.
  • the element doping amount in the second doping process is less than one third of the element doping amount in the first doping process.
  • the manufacturing method of this embodiment adopts a secondary doping process, in which the doping area is doped with a larger amount of doping element for the first time, and the doping area is doped with a smaller amount of doping element for the second time, which is convenient for precision
  • the content of doping elements in the doped region is regulated by, so as to control the carrier concentration.
  • step S9 forming a source-drain metal layer on the second insulating layer and patterning the source-drain metal layer, the source-drain metal layer is electrically connected to the doped region of the active layer through the via hole.
  • step S10 forming a flat layer on the source-drain metal layer.
  • FIG. 4 is a schematic structural diagram of a thin film transistor of the present application.
  • the thin film transistor 100 of the embodiment of the present application includes a substrate 11, an active layer 12, a first insulating layer 13, a gate metal layer 14, a second insulating layer 15, a source-drain metal layer 16, and a flat layer 17.
  • the active layer 12 is provided on the substrate 11.
  • the first insulating layer 13 is provided on the active layer 12.
  • the gate metal layer 14 is provided on the first insulating layer 13.
  • the second insulating layer 15 is provided on the gate metal layer 14.
  • the source-drain metal layer 16 is provided on the second insulating layer 15.
  • the flat layer 17 is provided on the source-drain metal layer 16.
  • the active layer 12 is made of cubic boron nitride.
  • the thin film transistor is an N-type thin film transistor or a P-type thin film transistor.
  • the manufacturing method and the thin film transistor of the present application use cubic phase boron nitride instead of polysilicon as the material of the active layer, and directly use the CVD process to form the cubic phase boron nitride
  • the active layer saves the existing thin film transistor manufacturing process using polysilicon as the active layer material, and performs three processes of dehydrogenation, annealing and hydrogenation, which simplifies the thin film transistor manufacturing process and improves the manufacturing efficiency of the thin film transistor; It solves the technical problem that the process steps of the existing thin film transistor are relatively complicated in the manufacturing process.

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Abstract

本申请提供一种薄膜晶体管的制作方法以及薄膜晶体管，其包括准备衬底；在衬底上形成有源层，并图案化有源层，有源层的材料为立方相氮化硼；以及依次在有源层上形成第一绝缘层、栅极金属层、第二绝缘层、源漏金属层和平坦层。本申请采用立方相氮化硼替代多晶硅作为有源层的材料，直接采用CVD工艺形成立方相氮化硼有源层。

Description

薄膜晶体管的制作方法以及薄膜晶体管 技术领域
本申请涉及一种薄膜晶体管技术，特别涉及一种薄膜晶体管的制作方法以及薄膜晶体管。
 背景技术
在显示面板的薄膜晶体管的制程中，包括形成有源层。目前采用低温多晶硅（Low Temperature Poly-Silicon，LTPS）作为薄膜晶体管的沟道。在制程中，需要先以等离子体增强化学的气相沉积法沉积非晶硅，然后对非晶硅作去氢处理，接着进行激光退火处理以将非晶硅形成多晶硅，而后在进行离子植入和氢化处理。但是在形成有源层的制程中，工艺步骤相对复杂。
故，需要提供一种简化工艺步骤的薄膜晶体管及其制作方法，以解决上述技术问题。
 技术问题
本申请实施例提供一种薄膜晶体管的制作方法以及薄膜晶体管，以解决现有的薄膜晶体管在制程上工艺步骤较为复杂的技术问题。
 技术解决方案
本申请实施例提供一种薄膜晶体管的制作方法，其包括：
准备衬底；
在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
在所述衬底上形成第一绝缘层；
在所述衬底上形成栅极金属层；
在所述衬底上形成第二绝缘层；
在所述衬底上形成源漏金属层；
所述在所述衬底上形成有源层的步骤中，所述有源层通过化学气相沉积工艺形成，形成所述有源层的气体包括氯化硼、氢化硼和氨气；
所述在所述衬底上形成有源层，并图案化所述有源层的步骤包括：
在所述有源层上涂覆光刻胶；
采用掩模工艺对所述光刻胶进行曝光和显影处理，以形成露出所述有源层的暴露区域；
对所述暴露区域的所述有源层进行刻蚀，形成图案化的有源层；
去除剩余的光刻胶。
在本申请的薄膜晶体管的制作方法中，图案化的所述有源层包括沟道区和位于所述沟道区两侧的掺杂区，所述薄膜晶体管的制作方法包括对所述有源层进行掺杂处理，所述对所述有源层进行掺杂处理的步骤包括：
对所述掺杂区进行第一次掺杂处理；
在图案化的所述有源层上形成所述第一绝缘层；
在所述第一绝缘层上对应于所述掺杂区的区域形成过孔，以暴露出至少部分所述掺杂区；
对所述过孔暴露出的所述掺杂区进行第二次掺杂处理，第二次掺杂工艺的元素掺杂量小于第一掺杂工艺的元素掺杂量的三分之一。
在本申请的薄膜晶体管的制作方法中，所述掺杂区为N型掺杂区，所述掺杂区的掺杂元素为磷、砷和锑中的一种或几种的混合。
在本申请的薄膜晶体管的制作方法中，所述掺杂区为P型掺杂区，所述掺杂区的掺杂元素为硼、铟中的一种或两种的混合。
在本申请的薄膜晶体管的制作方法中，所述掺杂工艺为离子注入工艺。
在本申请的薄膜晶体管的制作方法中，所述源漏金属层通过过孔电性连接于所述掺杂区。
本申请实施例还提供一种薄膜晶体管的制作方法，其包括：
准备衬底；
在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
在所述衬底上形成第一绝缘层；
在所述衬底上形成栅极金属层；
在所述衬底上形成第二绝缘层；
在所述衬底上形成源漏金属层。
在本申请的薄膜晶体管的制作方法中，所述在所述衬底上形成有源层的步骤中，所述有源层通过化学气相沉积工艺形成，形成所述有源层的气体包括氯化硼（BCl 3）、氢化硼（B 2H 4）和氨气（NH 3）。
在本申请的薄膜晶体管的制作方法中，所述在所述衬底上形成有源层，并图案化所述有源层的步骤包括：
在所述有源层上涂覆光刻胶；
采用掩模工艺对所述光刻胶进行曝光和显影处理，以形成露出所述有源层的暴露区域；
对所述暴露区域的所述有源层进行刻蚀，形成图案化的有源层；
去除剩余的光刻胶。
在本申请的薄膜晶体管的制作方法中，图案化的所述有源层包括沟道区和位于所述沟道区两侧的掺杂区，所述薄膜晶体管的制作方法包括对所述有源层进行掺杂处理，所述对所述有源层进行掺杂处理的步骤包括：
对所述掺杂区进行第一次掺杂处理；
在图案化的所述有源层上形成第一绝缘层；
在所述第一绝缘层上对应于所述掺杂区的区域形成过孔，以暴露出至少部分所述掺杂区；
对所述过孔暴露出的所述掺杂区进行第二次掺杂处理，第二次掺杂工艺的元素掺杂量小于第一掺杂工艺的元素掺杂量的三分之一。
在本申请的薄膜晶体管的制作方法中，所述掺杂区为N型掺杂区，所述掺杂区的掺杂元素为磷、砷和锑中的一种或几种的混合。
在本申请的薄膜晶体管的制作方法中，所述掺杂区为P型掺杂区，所述掺杂区的掺杂元素为硼、铟中的一种或两种的混合。
在本申请的薄膜晶体管的制作方法中，所述掺杂工艺为离子注入工艺。
在本申请的薄膜晶体管的制作方法中，所述薄膜晶体管的制作方法包括：
在所述第一绝缘层上形成栅极金属层，并图案化所述栅极金属层；
在所述栅极金属层上依次形成第二绝缘层和源漏金属层，所述源漏金属层通过过孔电性连接于所述掺杂区。
本申请还涉及一种薄膜晶体管，其包括：
衬底；
有源层，设置在所述衬底上；
第一绝缘层，设置在所述有源层上；
栅极金属层，设置在所述第一绝缘层上；
第二绝缘层，设置在所述栅极金属层上；以及
源漏金属层，设置在所述第二绝缘层上；
其中，所述有源层由立方氮化硼制成。
在本申请的薄膜晶体管中，所述薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
 有益效果
相较于现有技术的薄膜晶体管及其制作方法，本申请的薄膜晶体管的制作方法以及薄膜晶体管采用立方相氮化硼替代多晶硅作为有源层的材料，直接采用化学气相沉积工艺（Chemical Vapor Deposition，CVD）形成立方相氮化硼有源层，节省了现有的以多晶硅为有源层材料的薄膜晶体管的制程中，进行去氢、退火和氢化三道工序，简化了薄膜晶体管的制程，提高了薄膜晶体管的制作效率；解决了现有的薄膜晶体管在制程上工艺步骤较为复杂的技术问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为现有技术的薄膜晶体管的制作方法的流程图；
图2为本申请实施例的薄膜晶体管的制作方法的流程图；
图3为本申请实施例的薄膜晶体管的制作方法的步骤S2的流程图；
图4为本申请实施例的薄膜晶体管的结构示意图。
 本发明的实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
本申请的薄膜晶体管的制作方法，其包括：
准备衬底；
在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
在所述衬底上形成第一绝缘层；
在所述衬底上形成栅极金属层；
在所述衬底上形成第二绝缘层；
在所述衬底上形成源漏金属层。
具体的，本申请以顶栅结构的薄膜晶体管为例进行说明，但并不限于此。请参照图2，图2为本申请实施例的薄膜晶体管的制作方法的流程图。本申请的薄膜晶体管的制作方法，其包括：
准备衬底；
在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
在所述有源层上形成第一绝缘层；
在所述第一绝缘层上形成栅极金属层，并图案化所述栅极金属层；
在所述栅极金属层上形成第二绝缘层；
在所述第二绝缘层和第一绝缘层对应于所述有源层掺杂区的区域形成过孔；
在所述第二绝缘层形成源漏金属层，并图案化所述源漏金属层，所述源漏金属层通过过孔连接于所述有源层的掺杂区；
在所述源漏金属层上形成平坦层。
本申请相较于现有技术的以多晶硅作为有源层材料的薄膜晶体管的制程，请参照图1。本申请在形成薄膜晶体管的制程中，采用立方相氮化硼（C-boron nitride）有源层替代现有技术的多晶硅有源层，这是由于立方相氮化硼具有较高的空穴迁移率（500cm 2V -1s -1），而多晶硅的空穴迁移率为480cm 2V -1s -1。且立方相氮化硼具有可掺杂特性，可以通过离子注入调控载流子浓度，因此可以直接采用化学气相沉积工艺（Chemical Vapor Deposition，CVD）直接形成立方相氮化硼有源层，节省了对非晶硅薄膜进行去氢处理的制程、对非晶硅薄膜进行激光退火形成多晶硅有源层的制程以及对整个薄膜晶体管进行氢化处理的制程。
另外，立方相氮化硼具有比多晶硅更宽的禁带宽度（6.4eV），使得以立方相氮化硼为沟道时，薄膜晶体管具有更小的漏电流；且其具有可双掺杂特性，使得MOS管源、漏极和沟道之间可以通过P型或N型掺杂形成更宽的空间电荷区，进一步降低漏电流。
在本实施例的薄膜晶体管的制作方法中，以下对本薄膜晶体管的制作方法进行详细的阐述。
在本实施例的薄膜晶体管的制作方法中，步骤S1：准备衬底。衬底包括基底和依次设置在基底上的阻挡层和缓冲层。
在本实施例的薄膜晶体管的制作方法中，步骤S2：在衬底上形成有源层，并图案化有源层，有源层的材料为立方相氮化硼。其中，有源层通过化学气相沉积工艺（CVD）在衬底上直接形成。形成立方相氮化硼有源层的气体包括氯化硼（BCl 3）、氢化硼（B 2H 4）和氨气（NH 3）。
请参照图3，步骤S2包括：
步骤201：在有源层上涂覆光刻胶；
步骤202：采用掩模工艺对光刻胶进行曝光和显影处理，以形成露出有源层的暴露区域；
步骤203：对暴露区域的有源层进行刻蚀，形成图案化的有源层；
步骤204：去除剩余的光刻胶。
至此形成图案化的立方相氮化硼有源层。
另外，在本薄膜晶体管的制作方法中，图案化的有源层包括沟道区和位于沟道区两侧的掺杂区，薄膜晶体管的制作方法包括对有源层进行掺杂处理，步骤S3：对掺杂区进行第一次掺杂处理。
其中，当掺杂区为N型掺杂区，掺杂区的掺杂元素为磷、砷和锑中的一种或几种的混合。当掺杂区为P型掺杂区，掺杂区的掺杂元素为硼、铟中的一种或两种的混合。掺杂工艺为离子注入工艺。
在本薄膜晶体管的制作方法中，步骤S4：在有源层上形成所述第一绝缘层。其中第一绝缘层可以采用旋涂、化学气相沉积等方法制备。
在本薄膜晶体管的制作方法中，步骤S5：在第一绝缘层上形成栅极金属层，并图案化栅极金属层。采用化学气相沉积或溅射法在第一绝缘层上形成栅极金属层。
在本薄膜晶体管的制作方法中，步骤S6：在栅极金属层上形成第二绝缘层。
在本薄膜晶体管的制作方法中，步骤S7：在第二绝缘层和第一绝缘层对应于有源层掺杂区的区域形成过孔，以暴露出至少部分掺杂区。其中，该过孔贯穿第一绝缘层和第二绝缘层。
在本薄膜晶体管的制作方法中，步骤S8：对过孔暴露出的掺杂区进行第二次掺杂处理。第二次掺杂工艺的元素掺杂量小于第一掺杂工艺的元素掺杂量的三分之一。
本实施例的制作方法采用二次掺杂工艺的方式，第一次向掺杂区掺杂较大量的掺杂元素，第二次向掺杂区掺杂较小量的掺杂元素，便于精准的调控掺杂区掺杂元素的含量，从而调控载流子的浓度。
在本薄膜晶体管的制作方法中，步骤S9：在第二绝缘层形成源漏金属层，并图案化源漏金属层，源漏金属层通过过孔电性连接于有源层的掺杂区。
在本薄膜晶体管的制作方法中，步骤S10：在源漏金属层上形成平坦层。
至此，完成了本申请的薄膜晶体管的制作方法的制程。
请参照图4，图4为本申请的薄膜晶体管的结构示意图。本申请实施例的薄膜晶体管100，其包括衬底11、有源层12、第一绝缘层13、栅极金属层14、第二绝缘层15、源漏金属层16和平坦层17。
其中，有源层12设置在衬底11上。第一绝缘层13设置在有源层12上。栅极金属层14设置在第一绝缘层13上。第二绝缘层15设置在栅极金属层14上。源漏金属层16设置在第二绝缘层15上。平坦层17设置在源漏金属层16上。其中，有源层12由立方氮化硼制成。
在本实施例的薄膜晶体管中，薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
相较于现有技术的薄膜晶体管及其制作方法，本申请的薄膜晶体管的制作方法以及薄膜晶体管采用立方相氮化硼替代多晶硅作为有源层的材料，直接采用CVD工艺形成立方相氮化硼有源层，节省了现有的以多晶硅为有源层材料的薄膜晶体管的制程中，进行去氢、退火和氢化三道工序，简化了薄膜晶体管的制程，提高了薄膜晶体管的制作效率；解决了现有的薄膜晶体管在制程上工艺步骤较为复杂的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (16)

  1. 一种薄膜晶体管的制作方法，其包括：
    准备衬底；
    在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
    在所述衬底上形成第一绝缘层；
    在所述衬底上形成栅极金属层；
    在所述衬底上形成第二绝缘层；
    在所述衬底上形成源漏金属层；
    所述在所述衬底上形成有源层的步骤中，所述有源层通过化学气相沉积工艺形成，形成所述有源层的气体包括氯化硼、氢化硼和氨气；
    所述在所述衬底上形成有源层，并图案化所述有源层的步骤包括：
    在所述有源层上涂覆光刻胶；
    采用掩模工艺对所述光刻胶进行曝光和显影处理，以形成露出所述有源层的暴露区域；
    对所述暴露区域的所述有源层进行刻蚀，形成图案化的有源层；
    去除剩余的光刻胶。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中，图案化的所述有源层包括沟道区和位于所述沟道区两侧的掺杂区，所述薄膜晶体管的制作方法包括对所述有源层进行掺杂处理，所述对所述有源层进行掺杂处理的步骤包括：
    对所述掺杂区进行第一次掺杂处理；
    在图案化的所述有源层上形成所述第一绝缘层；
    在所述第一绝缘层上对应于所述掺杂区的区域形成过孔，以暴露出至少部分所述掺杂区；
    对所述过孔暴露出的所述掺杂区进行第二次掺杂处理，第二次掺杂工艺的元素掺杂量小于第一掺杂工艺的元素掺杂量的三分之一。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其中，所述掺杂区为N型掺杂区，所述掺杂区的掺杂元素为磷、砷和锑中的一种或几种的混合。
  4. 根据权利要求2所述的薄膜晶体管的制作方法，其中，所述掺杂区为P型掺杂区，所述掺杂区的掺杂元素为硼、铟中的一种或两种的混合。
  5. 根据权利要求2所述的薄膜晶体管的制作方法，其中，所述掺杂工艺为离子注入工艺。
  6. 根据权利要求2所述的薄膜晶体管的制作方法，其中，所述源漏金属层通过过孔电性连接于所述掺杂区。
  7. 一种薄膜晶体管的制作方法，其包括：
    准备衬底；
    在所述衬底上形成有源层，并图案化所述有源层，所述有源层的材料为立方相氮化硼；
    在所述衬底上形成第一绝缘层；
    在所述衬底上形成栅极金属层；
    在所述衬底上形成第二绝缘层；
    在所述衬底上形成源漏金属层。
  8. 根据权利要求7所述的薄膜晶体管的制作方法，其中，所述在所述衬底上形成有源层的步骤中，所述有源层通过化学气相沉积工艺形成，形成所述有源层的气体包括氯化硼、氢化硼和氨气。
  9. 根据权利要求7所述的薄膜晶体管的制作方法，其中，所述在所述衬底上形成有源层，并图案化所述有源层的步骤包括：
    在所述有源层上涂覆光刻胶；
    采用掩模工艺对所述光刻胶进行曝光和显影处理，以形成露出所述有源层的暴露区域；
    对所述暴露区域的所述有源层进行刻蚀，形成图案化的有源层；
    去除剩余的光刻胶。
  10. 根据权利要求7所述的薄膜晶体管的制作方法，其中，图案化的所述有源层包括沟道区和位于所述沟道区两侧的掺杂区，所述薄膜晶体管的制作方法包括对所述有源层进行掺杂处理，所述对所述有源层进行掺杂处理的步骤包括：
    对所述掺杂区进行第一次掺杂处理；
    在图案化的所述有源层上形成所述第一绝缘层；
    在所述第一绝缘层上对应于所述掺杂区的区域形成过孔，以暴露出至少部分所述掺杂区；
    对所述过孔暴露出的所述掺杂区进行第二次掺杂处理，第二次掺杂工艺的元素掺杂量小于第一掺杂工艺的元素掺杂量的三分之一。
  11. 根据权利要求10所述的薄膜晶体管的制作方法，其中，所述掺杂区为N型掺杂区，所述掺杂区的掺杂元素为磷、砷和锑中的一种或几种的混合。
  12. 根据权利要求10所述的薄膜晶体管的制作方法，其中，所述掺杂区为P型掺杂区，所述掺杂区的掺杂元素为硼、铟中的一种或两种的混合。
  13. 根据权利要求10所述的薄膜晶体管的制作方法，其中，所述掺杂工艺为离子注入工艺。
  14. 根据权利要求10所述的薄膜晶体管的制作方法，其中，所述源漏金属层通过过孔电性连接于所述掺杂区。
  15. 一种薄膜晶体管，其包括：
    衬底；
    有源层，设置在所述衬底上；
    第一绝缘层，设置在所述有源层上；
    栅极金属层，设置在所述第一绝缘层上；
    第二绝缘层，设置在所述栅极金属层上；以及
    源漏金属层，设置在所述第二绝缘层上；
    其中，所述有源层由立方氮化硼制成。
  16. 根据权利要求15所述的薄膜晶体管，其中，所述薄膜晶体管为P型薄膜晶体管。
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