WO2020124376A1 - 移位寄存器及其驱动方法、栅极驱动电路以及显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路以及显示装置 Download PDF

Info

Publication number
WO2020124376A1
WO2020124376A1 PCT/CN2018/121813 CN2018121813W WO2020124376A1 WO 2020124376 A1 WO2020124376 A1 WO 2020124376A1 CN 2018121813 W CN2018121813 W CN 2018121813W WO 2020124376 A1 WO2020124376 A1 WO 2020124376A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
coupled
pull
electrode
terminal
Prior art date
Application number
PCT/CN2018/121813
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020560483A priority Critical patent/JP7258044B2/ja
Priority to EP18932318.1A priority patent/EP3940684A4/en
Priority to CN201880002510.9A priority patent/CN111788624B/zh
Priority to US16/643,966 priority patent/US11328651B2/en
Priority to PCT/CN2018/121813 priority patent/WO2020124376A1/zh
Publication of WO2020124376A1 publication Critical patent/WO2020124376A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register and its driving method, a gate driving circuit, an array substrate, and a display device.
  • the gate driving circuit may include a plurality of cascaded shift registers.
  • the scan signal is output from the output terminal of the shift register to drive the pixel circuit and the cascade signal is simultaneously output to drive the shift register of the next stage.
  • the gate drive circuit is currently integrated in GATE IC.
  • the area of the chip is the main factor affecting the cost of the chip.
  • the embodiments described herein provide a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • a shift register includes a blanking input circuit, N shift register circuits and a compensation selection circuit.
  • the blanking input circuit is configured to store a blanking input signal, and provide a blanking pull-down signal to the N shift register circuits via N pull-down nodes based on the blanking input signal and the blanking control signal.
  • the N shift register circuits are coupled to the blanking input circuit, and are configured to output respective blanking output signals based on the blanking pull-down signal and the corresponding clock signal during blanking.
  • the compensation selection circuit is configured to provide the blanking input signal to the blanking input circuit under the control of a compensation selection control signal.
  • N is a natural number greater than 1.
  • the N shift register circuits are further configured to output respective display output signals based on the display input signal and the corresponding clock signal during display.
  • One of the display output signals is supplied to the compensation selection circuit as the blanking input signal.
  • the blanking input circuit includes a storage sub-circuit and an isolation sub-circuit.
  • the storage subcircuit is configured to store the blanking input signal.
  • the isolation sub-circuit is configured to provide the blanking pull-down signal to the N pull-down nodes based on the blanking input signal and the blanking control signal.
  • the isolation sub-circuit includes a first transistor and N second transistors.
  • the control electrode of the first transistor is coupled to the storage subcircuit.
  • the first electrode of the first transistor is coupled to the blanking pull-down signal terminal.
  • the second electrode of the first transistor is coupled to the first electrodes of the N second transistors.
  • the control electrodes of the N second transistors are coupled to the blanking control terminal.
  • the second electrodes of the N second transistors are coupled to the corresponding pull-down nodes.
  • the isolation sub-circuit includes a third transistor, a fourth transistor, and N fifth transistors.
  • the control electrode of the third transistor is coupled to the storage subcircuit.
  • the first electrode of the third transistor is coupled to the blanking control terminal.
  • the second electrode of the third transistor is coupled to the second electrode of the fourth transistor and the control electrodes of the N fifth transistors.
  • the control electrode of the fourth transistor is coupled to the second blanking control terminal.
  • the first electrode of the fourth transistor is coupled to the first voltage terminal.
  • the first electrodes of the N fifth transistors are coupled to the blanking pull-down signal terminal.
  • the second poles of the N fifth transistors are coupled to the corresponding pull-down nodes.
  • the isolation sub-circuit includes a sixth transistor, two seventh transistors, and N eighth transistors.
  • the control electrode of the sixth transistor is coupled to the storage subcircuit.
  • the first electrode of the sixth transistor is coupled to the blanking control terminal.
  • the second electrode of the sixth transistor is coupled to the second electrodes of the two seventh transistors and the control electrodes of the N eighth transistors.
  • the control electrodes of the two seventh transistors are respectively coupled to the third blanking control terminal and the fourth blanking control terminal.
  • the first electrodes of the two seventh transistors are coupled to the first voltage terminal.
  • the first electrodes of the N eighth transistors are coupled to the blanking pull-down signal terminal.
  • the second poles of the N eighth transistors are coupled to the corresponding pull-down nodes.
  • the storage sub-circuit includes a first capacitor.
  • the first end of the first capacitor is coupled to the compensation selection circuit and the isolation sub-circuit.
  • the second terminal of the first capacitor is coupled to the first voltage terminal.
  • the compensation selection circuit includes a ninth transistor.
  • the control electrode of the ninth transistor is coupled to the compensation selection control terminal.
  • the first electrode of the ninth transistor is coupled to the blanking input signal terminal.
  • the second electrode of the ninth transistor is coupled to the isolator sub-circuit.
  • the shift register circuit includes: a display input circuit, a display reset circuit, a blanking reset circuit, a pull-up circuit, an output pull-up circuit, and an output circuit.
  • the display input circuit is configured to provide a display pull-down signal to the pull-down node based on a display input signal.
  • the display reset circuit is configured to reset the pull-down node based on a display reset signal.
  • the blanking reset circuit is configured to reset the pull-down node based on a blanking reset signal.
  • the pull-up circuit is configured to maintain the level of the pull-down node after resetting the pull-down node, and alternately pull down the first pull-up node and the second pull-up node.
  • the output pull-up circuit is configured to pull up the blanking output signal and the display output signal of the shift register based on the levels of the first pull-up node and the second pull-up node.
  • the output circuit is configured to output the blanking output signal based on the blanking pull-down signal and the corresponding clock signal during blanking, and output the display based on the display pull-down signal and the corresponding clock signal during display output signal.
  • the display reset circuit includes an eleventh transistor.
  • the control electrode of the eleventh transistor is coupled to the display reset terminal.
  • the first electrode of the eleventh transistor is coupled to the first voltage terminal.
  • the second electrode of the eleventh transistor is coupled to the pull-down node.
  • the blanking reset circuit includes a twelfth transistor.
  • the control electrode of the twelfth transistor is coupled to the blanking reset terminal.
  • the first electrode of the twelfth transistor is coupled to the first voltage terminal.
  • the second electrode of the twelfth transistor is coupled to the pull-down node.
  • the pull-up circuit includes thirteenth to twenty-fourth transistors.
  • the control electrode and the first electrode of the thirteenth transistor are coupled to the first control terminal.
  • the second electrode of the thirteenth transistor is coupled to the first pull-up node.
  • the gate electrode of the fourteenth transistor is coupled to the pull-down node.
  • the first electrode of the fourteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fourteenth transistor is coupled to the first pull-up node.
  • the control electrode of the fifteenth transistor is coupled to the first pull-up node.
  • the first electrode of the fifteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fifteenth transistor is coupled to the pull-down node.
  • the control electrode of the sixteenth transistor is coupled to the blanking control terminal.
  • the first pole of the sixteenth transistor is coupled to the second pole of the seventeenth transistor.
  • the second electrode of the sixteenth transistor is coupled to the first pull-up node.
  • the control electrode of the seventeenth transistor is coupled to the pull-down control node.
  • the first electrode of the seventeenth transistor is coupled to the first voltage terminal.
  • the control electrode of the eighteenth transistor is coupled to the display input terminal.
  • the first electrode of the eighteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the eighteenth transistor is coupled to the first pull-up node.
  • the control electrode and the first electrode of the nineteenth transistor are coupled to the second control terminal.
  • the second pole of the nineteenth transistor is coupled to the second pull-up node.
  • the control electrode of the twentieth transistor is coupled to the pull-down node.
  • the first electrode of the twentieth transistor is coupled to the first voltage terminal.
  • the second pole of the twentieth transistor is coupled to the second pull-up node.
  • the control electrode of the twenty-first transistor is coupled to the second pull-up node.
  • the first electrode of the twenty-first transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-first transistor is coupled to the pull-down node.
  • the control electrode of the twenty-second transistor is coupled to the blanking control terminal.
  • the first electrode of the twenty-second transistor is coupled to the second electrode of the twenty-third transistor.
  • the second electrode of the twenty-second transistor is coupled to the second pull-up node.
  • the control electrode of the twenty-third transistor is coupled to the pull-down control node.
  • the first electrode of the twenty-third transistor is coupled to the first voltage terminal.
  • the control electrode of the twenty-fourth transistor is coupled to the display input terminal.
  • the first electrode of the twenty-fourth transistor is coupled to the first voltage terminal.
  • the pull-up circuit includes thirteenth to sixteenth transistors, eighteenth to twenty-second transistors, and twenty-fourth transistors.
  • the control electrode and the first electrode of the thirteenth transistor are coupled to the first control terminal.
  • the second electrode of the thirteenth transistor is coupled to the first pull-up node.
  • the gate electrode of the fourteenth transistor is coupled to the pull-down node.
  • the first electrode of the fourteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fourteenth transistor is coupled to the first pull-up node.
  • the control electrode of the fifteenth transistor is coupled to the first pull-up node.
  • the first electrode of the fifteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fifteenth transistor is coupled to the pull-down node.
  • the control electrode of the sixteenth transistor is coupled to the blanking control terminal.
  • the first electrode of the sixteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the sixteenth transistor is coupled to the first pull-up node.
  • the control electrode of the eighteenth transistor is coupled to the display input terminal.
  • the first electrode of the eighteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the eighteenth transistor is coupled to the first pull-up node.
  • the control electrode and the first electrode of the nineteenth transistor are coupled to the second control terminal.
  • the second pole of the nineteenth transistor is coupled to the second pull-up node.
  • the control electrode of the twentieth transistor is coupled to the pull-down node.
  • the first electrode of the twentieth transistor is coupled to the first voltage terminal.
  • the second pole of the twentieth transistor is coupled to the second pull-up node.
  • the control electrode of the twenty-first transistor is coupled to the second pull-up node.
  • the first electrode of the twenty-first transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-first transistor is coupled to the pull-down node.
  • the control electrode of the twenty-second transistor is coupled to the blanking control terminal.
  • the first electrode of the twenty-second transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-second transistor is coupled to the second pull-up node.
  • the control electrode of the twenty-fourth transistor is coupled to the display input terminal.
  • the first electrode of the twenty-fourth transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-fourth transistor is coupled to the second pull-up node.
  • the pull-up circuit includes thirteenth to fifteenth transistors, eighteenth to twenty-first transistors, and twenty-fourth transistors.
  • the control electrode and the first electrode of the thirteenth transistor are coupled to the first control terminal.
  • the second electrode of the thirteenth transistor is coupled to the first pull-up node.
  • the gate electrode of the fourteenth transistor is coupled to the pull-down node.
  • the first electrode of the fourteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fourteenth transistor is coupled to the first pull-up node.
  • the control electrode of the fifteenth transistor is coupled to the first pull-up node.
  • the first electrode of the fifteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the fifteenth transistor is coupled to the pull-down node.
  • the control electrode of the eighteenth transistor is coupled to the display input terminal.
  • the first electrode of the eighteenth transistor is coupled to the first voltage terminal.
  • the second electrode of the eighteenth transistor is coupled to the first pull-up node.
  • the control electrode and the first electrode of the nineteenth transistor are coupled to the second control terminal.
  • the second pole of the nineteenth transistor is coupled to the second pull-up node.
  • the control electrode of the twentieth transistor is coupled to the pull-down node.
  • the first electrode of the twentieth transistor is coupled to the first voltage terminal.
  • the second pole of the twentieth transistor is coupled to the second pull-up node.
  • the control electrode of the twenty-first transistor is coupled to the second pull-up node.
  • the first electrode of the twenty-first transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-first transistor is coupled to the pull-down node.
  • the control electrode of the twenty-fourth transistor is coupled to the display input terminal.
  • the first electrode of the twenty-fourth transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-fourth transistor is coupled to the second pull-up node.
  • the output pull-up circuit includes twenty-fifth to twenty-eight transistors.
  • the control electrode of the twenty-fifth transistor is coupled to the first pull-up node.
  • the first electrode of the twenty-fifth transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-fifth transistor is coupled to the shift signal output terminal.
  • the control electrode of the twenty-sixth transistor is coupled to the first pull-up node.
  • the first electrode of the twenty-sixth transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-sixth transistor is coupled to the first pixel signal output terminal.
  • the control electrode of the twenty-seventh transistor is coupled to the second pull-up node.
  • the first electrode of the twenty-seventh transistor is coupled to the first voltage terminal.
  • the second electrode of the twenty-seventh transistor is coupled to the shift signal output terminal.
  • the control electrode of the 28th transistor is coupled to the second pull-up node.
  • the first electrode of the twenty-eighth transistor is coupled to the first voltage terminal.
  • the second electrode of the 28th transistor is coupled to the first pixel signal output terminal.
  • the output circuit includes a twenty-ninth transistor, a thirtieth transistor, and a second capacitor.
  • the gate of the twenty-ninth transistor is coupled to the pull-down node.
  • the first electrode of the twenty-ninth transistor is coupled to the first clock signal terminal.
  • the second electrode of the twenty-ninth transistor is coupled to the shift signal output terminal.
  • the gate electrode of the thirtieth transistor is coupled to the pull-down node.
  • the first electrode of the thirtieth transistor is coupled to the first clock signal terminal.
  • the second electrode of the thirtieth transistor
  • the output pull-up circuit further includes a thirty-first transistor and a thirty-second transistor.
  • the control electrode of the thirty-first transistor is coupled to the first pull-up node.
  • the first electrode of the thirty-first transistor is coupled to the first voltage terminal.
  • the second electrode of the thirty-first transistor is coupled to the second pixel signal output terminal.
  • the control electrode of the thirty-second transistor is coupled to the second pull-up node.
  • the first electrode of the thirty-second transistor is coupled to the first voltage terminal.
  • the second electrode of the thirty-second transistor is coupled to the second pixel signal output terminal.
  • the output circuit further includes a thirty-third transistor and a third capacitor. The control electrode of the thirty-third transistor is coupled to the pull-down node.
  • the first electrode of the 33rd transistor is coupled to the second clock signal terminal.
  • the second electrode of the 33rd transistor is coupled to the second pixel signal output terminal.
  • the first end of the third capacitor is coupled to the pull-down node.
  • the second terminal of the third capacitor is coupled to the second pixel signal output terminal.
  • the display input circuit includes a tenth transistor.
  • the control electrode of the tenth transistor is coupled to the display input terminal.
  • the first electrode of the tenth transistor is coupled to the display pull-down signal terminal.
  • the second electrode of the tenth transistor is coupled to the pull-down node.
  • the display input circuit includes a thirty-fourth transistor and a thirty-fifth transistor.
  • the control electrode and the first electrode of the thirty-fourth transistor are coupled to the display input terminal.
  • the second pole of the thirty-fourth transistor is coupled to the first pole of the thirty-fifth transistor.
  • the control electrode of the thirty-fifth transistor is coupled to the display input terminal.
  • the second electrode of the thirty-fifth transistor is coupled to the pull-down node.
  • the display input circuit includes a thirty-sixth transistor and a thirty-seventh transistor.
  • the control electrode of the thirty-sixth transistor is coupled to the display input terminal.
  • the first electrode of the thirty-sixth transistor is coupled to the display pull-down signal terminal.
  • the second pole of the thirty-sixth transistor is coupled to the control pole and the first pole of the thirty-seventh transistor.
  • the second electrode of the thirty-seventh transistor is coupled to the pull-down node.
  • the display input circuit includes a thirty-eighth transistor.
  • the control electrode and the first electrode of the thirty-eighth transistor are coupled to the display input terminal.
  • the second electrode of the thirty-eighth transistor is coupled to the pull-down node.
  • a gate drive circuit includes a plurality of cascaded shift registers as described in the first aspect of the present disclosure.
  • the compensation selection control terminal of the shift register of each stage is provided with a corresponding compensation selection control signal.
  • the blanking control terminal of the shift register of each stage is provided with a corresponding blanking control signal.
  • the display input terminal of the first shift register circuit among the K ⁇ N shift register circuits is supplied with a start signal.
  • the display reset terminal of the first shift register circuit is coupled to the shift signal output terminal of the (i/2+2)th shift register circuit.
  • a first clock signal is provided to the first clock signal terminal of the first shift register circuit.
  • the display input terminal of the second shift register circuit is supplied with the start signal.
  • the display reset terminal of the second shift register circuit is coupled to the shift signal output terminal of the (i/2+3)th shift register circuit.
  • the second clock signal is provided to the first clock signal terminal of the second shift register circuit.
  • the display input terminal of the nth shift register circuit is coupled to the shift signal output terminal of the (n-i/2)th shift register circuit.
  • the display reset terminal of the nth shift register circuit is coupled to the shift signal output terminal of the (n+i/2+1)th shift register circuit.
  • the first clock signal terminal of the nth shift register circuit is supplied with the Mth clock signal. During the display period, the clock periods of the first to i-th clock signals are the same.
  • the clock cycle includes i phases of equal duration.
  • the first to i-th clock signals are sequentially phase-shifted by 1/i clock cycles.
  • K is a natural number greater than 1.
  • i is even.
  • n is a natural number greater than 2 and less than or equal to K ⁇ N.
  • M is i; otherwise, M is n modulo i.
  • N is 4.
  • i 4.
  • the (i+M)th clock signal is provided to the second clock signal terminal of the nth shift register circuit.
  • the (i+1)th to 2ith clock signals have the same waveform as the first to ith clock signals, respectively.
  • a driving method for driving the shift register includes: providing the blanking input signal to the blanking input circuit according to the compensation selection signal during display, and storing the blanking input signal in the blanking input circuit; and during blanking During the blanking period, the blanking pull-down signal is provided to the N pull-down nodes according to the stored blanking input signal and blanking control signal, so that the N shift register circuits are based on the blanking pull-down signal and the corresponding The clock signal outputs the respective blanking output signal.
  • the driving method further includes: during display, inputting a display pull-down signal to a corresponding pull-down node according to the display input signal; and outputting a corresponding according to the level of the pull-down node and a corresponding clock signal The output signal is displayed.
  • an array substrate includes the gate driving circuit according to the second aspect of the present disclosure.
  • a display device includes the array substrate according to the fourth aspect of the present disclosure.
  • FIG. 1 is a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit diagram of a compensation selection circuit and a blanking input circuit in a shift register according to an embodiment of the present disclosure
  • FIG. 4 is a schematic circuit diagram of a compensation selection circuit and a blanking input circuit in a shift register according to another embodiment of the present disclosure
  • FIG. 5 is a schematic circuit diagram of a compensation selection circuit and a blanking input circuit in a shift register according to yet another embodiment of the present disclosure
  • FIG. 6 is a schematic circuit diagram of a compensation selection circuit and a blanking input circuit in a shift register according to still another embodiment of the present disclosure
  • FIG. 7 is a schematic circuit diagram of a shift register circuit in a shift register according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit diagram of a shift register circuit in a shift register according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic circuit diagram of a shift register circuit in a shift register according to yet another embodiment of the present disclosure.
  • FIG. 10 is a schematic circuit diagram of a shift register circuit in a shift register according to still another embodiment of the present disclosure.
  • FIG. 11 is a schematic circuit diagram of a display input circuit in a shift register according to an embodiment of the present disclosure
  • FIG. 12 is a timing diagram of some signals used for the shift register shown in FIG. 1 or FIG. 2;
  • FIG. 13 is a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are The direction of the on-state current is reversed. Therefore, in some embodiments of the present disclosure, the controlled intermediate terminal of the transistor is called a control electrode, the signal input terminal is called a first electrode, and the signal output terminal is called a second electrode.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. In addition, terms such as "first" and "second” are only used to distinguish one component (or part of a component) from another component (or another part of a component).
  • FIG. 1 shows a schematic block diagram of a shift register 100 according to an embodiment of the present disclosure.
  • the shift register 100 includes a blanking input circuit 120, N shift register circuits (130_1...130_n, hereinafter may be collectively referred to as 130), and a compensation selection circuit 110.
  • the blanking input circuit 120 is configured to store the blanking input signal OUT_1, and the blanking pull-down signal V2 via N pull-down nodes (Q(1)-Q(N)) based on the blanking input signal OUT_1 and the blanking control signal CLA Provide to N shift register circuits 130.
  • the N shift register circuits 130 are coupled to the blanking input circuit 120, and are configured to output respective blanking output signals (OUT_1 ⁇ , based on the blanking pull-down signal V2 and the corresponding clock signal (not shown) during blanking. OUT_N).
  • the compensation selection circuit 110 is configured to provide a blanking input signal to the blanking input circuit 120 under the control of the compensation selection control signal OE.
  • N is a natural number greater than 1.
  • the shift register circuit 130 may be further configured to output respective display output signals based on display input signals (not shown) and corresponding clock signals during display.
  • One of the display output signals may be provided to the compensation selection circuit 110 as a blanking input signal.
  • a compensation selection circuit 110 and a blanking input circuit 120 can provide the blanking pull-down signal V2 to N pull-down nodes (Q(1) to Q(N)).
  • the embodiments of the present disclosure can save the compensation selection circuit 110 and blanking input in the gate driving circuit The number of circuits 120.
  • FIG. 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure.
  • the blanking input circuit 120 includes a storage sub-circuit 121 and an isolation sub-circuit 122.
  • the storage sub-circuit 121 is configured to store the blanking input signal OUT.
  • the isolation sub-circuit 122 is configured to provide the blanking pull-down signal V2 to the corresponding pull-down node Q(n) based on the blanking input signal OUT and the blanking control signal CLA.
  • 3-6 show schematic circuit diagrams of the compensation selection circuit 110 and the blanking input circuit 120 in the shift register (100 and 200) according to an embodiment of the present disclosure.
  • a P-type transistor is used to implement the compensation selection circuit 110 and the blanking input circuit 120.
  • the first voltage V1 is at a high level.
  • the second voltage V2 is low.
  • N is 4, for example.
  • an N-type transistor may also be used to implement the compensation selection circuit 110 and the blanking input circuit 120.
  • the compensation selection circuit 110 may include a ninth transistor M9.
  • the storage sub-circuit 121 may include a first capacitor C1.
  • the isolation sub-circuit 122 may include a first transistor M1 and four second transistors (M2_1, M2_2, M2_3, and M2_4).
  • the gate of the ninth transistor M9 is coupled to the compensation selection control terminal OE.
  • the first electrode of the ninth transistor M9 is coupled to the blanking input signal terminal.
  • the blanking input signal terminal may be, for example, the shift signal output terminal CR(n) of the shift register.
  • the second electrode of the ninth transistor M9 is coupled to the pull-down control node H.
  • the first terminal of the first capacitor C1 is coupled to the pull-down control node H.
  • the second terminal of the first capacitor C1 is coupled to the first voltage terminal V1.
  • the control electrode of the first transistor M1 is coupled to the pull-down control node H.
  • the first electrode of the first transistor M1 is coupled to the blanking pull-down signal terminal.
  • the blanking pull-down signal terminal may be provided with, for example, the second voltage V2.
  • the second pole of the first transistor M1 is coupled to the first pole (point P) of four second transistors (M2_1, M2_2, M2_3, and M2_4).
  • the control electrodes of the four second transistors (M2_1, M2_2, M2_3, and M2_4) are coupled to the blanking control terminal CLA.
  • the second electrodes of the four second transistors (M2_1, M2_2, M2_3, and M2_4) are coupled to the corresponding pull-down nodes (Q(n)-Q(n+3)).
  • the four second transistors (M2_1, M2_2, M2_3, and M2_4) are turned on, thereby providing the blanking pull-down signal V2 from the blanking pull-down signal terminal to the four pull-downs Node (Q(n) ⁇ Q(n+3)).
  • the difference between the isolation sub-circuit 122 shown in FIG. 4 and the isolation sub-circuit 122 shown in FIG. 3 is that the signal CLC provided by the blanking pull-down signal terminal does not have to be kept low all the time, it only needs to be
  • the blanking control signal CLA of the blanking control terminal CLA may be low during the low level.
  • the four second transistors (M2_1, M2_2, M2_3, and M2_4) are turned on, thereby providing the low level from the blanking pull-down signal terminal to the four pull-down nodes ( Q(n) ⁇ Q(n+3)).
  • FIG. 5 shows another exemplary structure of the isolation sub-circuit 122.
  • the isolation sub-circuit 122 may include a third transistor M3, a fourth transistor M4, and four fifth transistors (M5_1, M5_2, M5_3, and M5_4).
  • the control electrode of the third transistor M3 is coupled to the pull-down control node H.
  • the first electrode of the third transistor M3 is coupled to the blanking control terminal CLA.
  • the second electrode of the third transistor M3 is coupled to the second electrode of the fourth transistor M4 and the control electrodes (point P) of the four fifth transistors (M5_1, M5_2, M5_3, and M5_4).
  • the control electrode of the fourth transistor M4 is coupled to the second blanking control terminal CLC.
  • the first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1.
  • the first electrodes of four fifth transistors (M5_1, M5_2, M5_3, and M5_4) are coupled to the blanking pull-down signal terminal V2.
  • Four fifth transistors (M5_1) , M5_2, M5_3 and M5_4) the second pole is coupled to the corresponding pull-down node (Q (n) ⁇ Q (n + 3)).
  • the signal from the second blanking control terminal CLC has an inverted voltage with respect to the signal from the blanking control terminal CLA.
  • the second blanking control terminal CLC provides a low level. Therefore, the fourth transistor M4 is turned on, thereby making the point P high. In this way, the four fifth transistors (M5_1, M5_2, M5_3, and M5_4) are turned off.
  • the four fifth transistors (M5_1, M5_2, M5_3, and M5_4) are turned on, thereby providing the low level from the blanking pull-down signal terminal to the four pull-down nodes ( Q(n) ⁇ Q(n+3)).
  • the second blanking control terminal CLC provides a high level. Therefore, the fourth transistor M4 is turned off, and the first voltage from the first voltage terminal is not applied to the point P.
  • FIG. 6 shows another exemplary structure of the isolation sub-circuit 122.
  • the isolation sub-circuit 122 may include a sixth transistor M6, two seventh transistors (M7_a and M7_b), and four eighth transistors (M8_1, M8_2, M8_3, and M8_4).
  • the control electrode of the sixth transistor M6 is coupled to the pull-down control node H.
  • the first electrode of the sixth transistor M6 is coupled to the blanking control terminal CLA.
  • the second pole of the sixth transistor M6 is coupled to the second poles of two seventh transistors (M7_a and M7_b) and the control poles of four eighth transistors (M8_1, M8_2, M8_3, and M8_4).
  • the control electrodes of the two seventh transistors are respectively coupled to the third blanking control terminal QB_A and the fourth blanking control terminal QB_B.
  • the signals of the third blanking control terminal QB_A and the fourth blanking control terminal QB_B alternately turn on the seventh transistors M7_a and M7_b.
  • the first poles of the two seventh transistors are coupled to the first voltage terminal V1.
  • the first poles of the four eighth transistors (M8_1, M8_2, M8_3, and M8_4) are coupled to the blanking pull-down signal terminal V2. 4
  • the second electrodes of the eighth transistors (M8_1, M8_2, M8_3, and M8_4) are coupled to the corresponding pull-down nodes (Q(n)-Q(n+3)).
  • the signals of the third blanking control terminal QB_A and the fourth blanking control terminal QB_B alternately turn on the seventh transistors M7_a and M7_b. Therefore, point P is high. In this way, the four eighth transistors (M8_1, M8_2, M8_3, and M8_4) are turned off.
  • the four eighth transistors (M8_1, M8_2, M8_3, and M8_4) are turned on, thereby providing the low level from the blanking pull-down signal terminal to the four pull-down nodes ( Q(n) ⁇ Q(n+3)).
  • the shift register circuit 130 may include: a display input circuit 210, a display reset circuit 220, a blanking reset circuit 230, a pull-up circuit 240, an output pull-up circuit 260, and an output Circuit 250.
  • the display input circuit 210 is configured to provide the display pull-down signal V2 to the pull-down node Q(n) based on the display input signal STU.
  • the display reset circuit 220 is configured to reset the pull-down node Q(n) based on the display reset signal STD.
  • the blanking reset circuit 230 is configured to reset the pull-down node Q(n) based on the blanking reset signal TRST.
  • the pull-up circuit 240 is configured to maintain the level of the pull-down node Q(n) after resetting the pull-down node Q(n), and alternately pull down the first pull-up node and the second pull-up node (not shown).
  • the output pull-up circuit 260 is configured to pull up the blanking output signal and the display output signal OUT of the shift register based on the levels of the first pull-up node and the second pull-up node.
  • the output circuit 250 is configured to output the blanking output signal OUT based on the blanking pull-down signal V2 and the corresponding clock signal during the blanking period, and output the display output signal OUT based on the display pull-down signal V2 and the corresponding clock signal during the display period.
  • the display input circuit 210 includes a tenth transistor M10.
  • the control electrode of the tenth transistor M10 is coupled to the display input signal STU.
  • the display input signal STU is, for example, the display output signal CR(n-2) of the shift register circuit of the first two lines.
  • the first electrode of the tenth transistor M10 is coupled to the pull-down signal V2.
  • the second electrode of the tenth transistor M10 is coupled to the pull-down node Q(n).
  • the display reset circuit 220 includes an eleventh transistor M11.
  • the control electrode of the eleventh transistor M11 is coupled to the display reset signal STD.
  • the display reset signal STD is, for example, the display output signal CR(n+3) of the shift register circuit in the last three rows.
  • the first electrode of the eleventh transistor M11 is coupled to the first voltage terminal V1.
  • the second electrode of the eleventh transistor M11 is coupled to the pull-down node Q(n).
  • the blanking reset circuit 230 includes a twelfth transistor M12.
  • the control electrode of the twelfth transistor M12 is coupled to the blanking reset signal TRST.
  • the first electrode of the twelfth transistor M12 is coupled to the first voltage terminal V1.
  • the second electrode of the twelfth transistor M12 is coupled to the pull-down node Q(n).
  • the pull-up circuit 240 includes a thirteenth transistor M13 to a twenty-fourth transistor M24.
  • the control electrode and the first electrode of the thirteenth transistor M13 are coupled to the first control terminal VA.
  • the second electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A.
  • the control electrode of the fourteenth transistor M14 is coupled to the pull-down node Q(n).
  • the first electrode of the fourteenth transistor M14 is coupled to the first voltage terminal V1.
  • the second electrode of the fourteenth transistor M14 is coupled to the first pull-up node QB_A.
  • the control electrode of the fifteenth transistor M15 is coupled to the first pull-up node QB_A.
  • the first electrode of the fifteenth transistor M15 is coupled to the first voltage terminal V1.
  • the second electrode of the fifteenth transistor M15 is coupled to the pull-down node Q(n).
  • the control electrode of the sixteenth transistor M16 is coupled to the blanking control terminal CLA.
  • the first pole of the sixteenth transistor M16 is coupled to the second pole of the seventeenth transistor M17.
  • the second electrode of the sixteenth transistor M16 is coupled to the first pull-up node QB_A.
  • the control electrode of the seventeenth transistor M17 is coupled to the pull-down control node H.
  • the first electrode of the seventeenth transistor M17 is coupled to the first voltage terminal V1.
  • the control electrode of the eighteenth transistor M18 is coupled to the display input terminal STU.
  • the first electrode of the eighteenth transistor M18 is coupled to the first voltage terminal V1.
  • the second electrode of the eighteenth transistor M18 is coupled to the first pull-up node QB_A.
  • the control electrode and the first electrode of the nineteenth transistor M19 are coupled to the second control terminal VB.
  • the second electrode of the nineteenth transistor M19 is coupled to the second pull-up node QB_B.
  • the control electrode of the twentieth transistor M20 is coupled to the pull-down node Q(n).
  • the first electrode of the twentieth transistor M20 is coupled to the first voltage terminal V1.
  • the second electrode of the twentieth transistor M20 is coupled to the second pull-up node QB_B.
  • the control electrode of the twenty-first transistor M21 is coupled to the second pull-up node QB_B.
  • the first electrode of the twenty-first transistor M21 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-first transistor M21 is coupled to the pull-down node Q(n).
  • the control electrode of the twenty-second transistor M22 is coupled to the blanking control terminal CLA.
  • the first electrode of the twenty-second transistor M22 is coupled to the second electrode of the twenty-third transistor M23.
  • the second electrode of the twenty-second transistor M22 is coupled to the second pull-up node QB_B.
  • the control electrode of the twenty-third transistor M23 is coupled to the pull-down control node H.
  • the first electrode of the twenty-third transistor M23 is coupled to the first voltage terminal V1.
  • the control electrode of the twenty-fourth transistor M24 is coupled to the display input terminal STU.
  • the first electrode of the twenty-fourth transistor M24 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-fourth transistor M24 is coupled to the second pull-up node QB_B.
  • the output pull-up circuit 260 includes a twenty-fifth transistor M25 to a twenty-eighth transistor M28.
  • the control electrode of the twenty-fifth transistor M25 is coupled to the first pull-up node QB_A.
  • the first electrode of the twenty-fifth transistor M25 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-fifth transistor M25 is coupled to the shift signal output terminal CR(n).
  • the control electrode of the twenty-sixth transistor M26 is coupled to the first pull-up node QB_A.
  • the first electrode of the twenty-sixth transistor M26 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-sixth transistor M26 is coupled to the first pixel signal output terminal OUT1(n).
  • the control electrode of the twenty-seventh transistor M27 is coupled to the second pull-up node QB_B.
  • the first electrode of the twenty-seventh transistor M27 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-seventh transistor M27 is coupled to the shift signal output terminal CR(n).
  • the control electrode of the 28th transistor M28 is coupled to the second pull-up node QB_B.
  • the first electrode of the 28th transistor M28 is coupled to the first voltage terminal V1.
  • the second electrode of the twenty-eighth transistor M28 is coupled to the first pixel signal output terminal OUT1(n).
  • the output circuit 250 includes a twenty-ninth transistor M29, a thirtieth transistor M30, and a second capacitor C2.
  • the control electrode of the twenty-ninth transistor M29 is coupled to the pull-down node Q(n).
  • the first electrode of the twenty-ninth transistor M29 is coupled to the first clock signal terminal CLKD.
  • the second electrode of the twenty-ninth transistor M29 is coupled to the shift signal output terminal CR(n).
  • the gate electrode of the thirtieth transistor M30 is coupled to the pull-down node Q(n).
  • the first electrode of the thirtieth transistor M30 is coupled to the first clock signal terminal CLKD.
  • the second electrode of the thirtieth transistor M30 is coupled to the first pixel signal output terminal OUT1(n).
  • FIG. 8 shows a schematic circuit diagram of the shift register circuit 130 in the shift register according to another embodiment of the present disclosure.
  • the shift register circuit 130 shown in FIG. 8 is different from the shift register circuit 130 shown in FIG. 7 in that: the seventeenth transistor M17 and the twenty-third transistor M23 are omitted; the sixteenth transistor M16 The first electrode and the first electrode of the twenty-second transistor M22 are directly connected to the first voltage terminal V1.
  • FIG. 9 shows a schematic circuit diagram of the shift register circuit 130 in the shift register according to still another embodiment of the present disclosure.
  • the shift register circuit 130 shown in FIG. 9 differs from the shift register circuit 130 shown in FIG. 7 in that the sixteenth transistor M16, the seventeenth transistor M17, the twenty-second transistor M22, and the second The thirteen transistor M23 is omitted.
  • FIG. 10 shows a schematic circuit diagram of the shift register circuit 130 in the shift register according to still another embodiment of the present disclosure.
  • the output pull-up circuit 260 further includes a thirty-first transistor M31 and a thirty-second transistor M32.
  • the control electrode of the thirty-first transistor M31 is coupled to the first pull-up node QB_A.
  • the first electrode of the thirty-first transistor M31 is coupled to the first voltage terminal V1.
  • the second electrode of the thirty-first transistor M31 is coupled to the second pixel signal output terminal OUT2(n).
  • the control electrode of the thirty-second transistor M32 is coupled to the second pull-up node QB_B.
  • the first electrode of the thirty-second transistor M32 is coupled to the first voltage terminal V1.
  • the second electrode of the thirty-second transistor M32 is coupled to the second pixel signal output terminal OUT2(n).
  • the output circuit 250 further includes a thirty-third transistor M33 and a third capacitor C3.
  • the control electrode of the 33rd transistor M33 is coupled to the pull-down node Q(n).
  • the first electrode of the 33rd transistor M33 is coupled to the second clock signal terminal CLKE.
  • the second electrode of the 33rd transistor M33 is coupled to the second pixel signal output terminal OUT2(n).
  • the first terminal of the third capacitor C3 is coupled to the pull-down node Q(n).
  • the second terminal of the third capacitor C3 is coupled to the second pixel signal output terminal OUT2(n).
  • the second pixel signal output terminal OUT2(n) can output a second display output signal during display and a second blanking output signal during the blanking period under the control of the second clock signal terminal CLKE and the pull-down node Q(n).
  • the thirteenth transistor M13 to the eighteenth transistor M18 and the twenty-fifth transistor can be omitted when the second control terminal VB always outputs a low level M25, a twenty-sixth transistor M26 and a thirty-first transistor M31. It is also possible to omit the nineteenth transistor M19 to the twenty-fourth transistor M24, the twenty-seventh transistor M27, the twenty-eighth transistor M28, and the thirty-second transistor when the first control terminal VA always outputs a low level M32.
  • FIG. 11 shows a schematic circuit diagram of the display input circuit 210 in the shift register according to an embodiment of the present disclosure.
  • the display input circuit 210 includes a thirty-fourth transistor M34 and a thirty-fifth transistor M35.
  • the control electrode and the first electrode of the thirty-fourth transistor M34 are coupled to the display input signal CR(n-2).
  • the second pole of the thirty-fourth transistor M34 is coupled to the first pole of the thirty-fifth transistor M35.
  • the control electrode of the thirty-fifth transistor M35 is coupled to the display input signal CR(n-2).
  • the second electrode of the thirty-fifth transistor M35 is coupled to the pull-down node Q(n).
  • the display input circuit 210 includes a thirty-sixth transistor M36 and a thirty-seventh transistor M37.
  • the control electrode of the thirty-sixth transistor M36 is coupled to the display input signal CR(n-2).
  • the first electrode of the thirty-sixth transistor M36 is coupled to the pull-down signal V2.
  • the second pole of the thirty-sixth transistor M36 is coupled to the control pole and the first pole of the thirty-seventh transistor M37.
  • the second electrode of the thirty-seventh transistor M37 is coupled to the pull-down node Q(n).
  • the display input circuit 210 includes a thirty-eighth transistor M38.
  • the control electrode and the first electrode of the thirty-eighth transistor M38 are coupled to the display input signal CR(n-2).
  • the second electrode of the thirty-eighth transistor M38 is coupled to the pull-down node Q(n).
  • FIG. 12 shows a timing diagram of some signals used for the shift registers (100 and 200) shown in FIG. 1 or FIG. 2.
  • the shift registers (100 and 200) shown in FIG. 1 or FIG. 2 can be composed of the compensation selection circuit 110 and the blanking input circuit 120 shown in FIG. 3 and four shift register circuits 130 shown in FIG. 10, for example. composition.
  • the working process of the compensation selection circuit 110 and the blanking input circuit 120 shown in FIG. 3 and the shift register circuit 130 shown in FIG. 10 will be described in detail in conjunction with the timing chart shown in FIG. 12. In the following description, it is assumed that all transistors are P-type transistors, and the first voltage V1 is at a high level. The second voltage V2 is low.
  • the first control terminal VA and the second control terminal VB alternately output low levels.
  • the first clock signal terminal CLKD of the first shift register circuit provides the first clock signal CLKD_1.
  • the first clock signal terminal CLKD of the second shift register circuit provides a second clock signal CLKD_2.
  • the first clock signal terminal CLKD of the third shift register circuit provides a third clock signal CLKD_3.
  • the first clock signal terminal CLKD of the fourth shift register circuit provides a fourth clock signal CLKD_4.
  • the second clock signal terminal CLKE of the first shift register circuit provides a fifth clock signal CLKE_1.
  • the second clock signal terminal CLKE of the second shift register circuit provides a sixth clock signal CLKE_2.
  • the second clock signal terminal CLKE of the third shift register circuit provides the seventh clock signal CLKE_3.
  • the second clock signal terminal CLKE of the fourth shift register circuit provides an eighth clock signal CLKE_4.
  • the display input signal STU provided by the shift register circuit 130_1 in the first row and the shift register circuit 130_2 in the second row is at a low level in the first stage, and then at a high level.
  • the display input signal STU provided by the shift register circuit 130_n of the other row is CR(n-2).
  • the display reset signal STD supplied to each row of shift register circuits 130_n is CR(n+3).
  • n is the row number of the shift register circuit.
  • the stages 1 to 5 belong to the display period, and the stage 6 belong to the blanking period.
  • the pull-down node Q(n) and the pull-down control node H are reset to a high level by setting the blanking reset signal TRST and the compensation selection control signal OE to a low level.
  • the display pull-down signal V2 is supplied to the pull-down node Q(1), so that the pull-down node Q(1) is set to a low level. Since the pull-down node Q(1) is at a low level, the fourteenth transistor M14 and the twentieth transistor M20 are turned on. Therefore, the first pull-up node QB_A(1) and the second pull-up node QB_B(1) are set to a high level, thereby turning off the twenty-fifth transistor M25 to the twenty-eighth transistor M28.
  • the pull-down node Q(1) is at a low level
  • the twenty-ninth transistor M29, the thirtieth transistor M30, and the thirty-third transistor M33 are turned on. Therefore, the shift signal output terminal CR(1) and the first pixel signal output terminal OUT1(1) output the high level from the first clock signal CLKD_1, and the second pixel signal output terminal OUT2(1) outputs the fifth clock signal High level of CLKE_1.
  • the shift signal output terminal CR(1) and the first pixel signal output terminal OUT1(1) output the high level from the first clock signal CLKD_1, and the second pixel signal output terminal OUT2(1) outputs the fifth clock signal High level of CLKE_1.
  • the display output signal OUT1(1) output from the first pixel signal output terminal OUT1(1) lags the display input signal STU by half a clock cycle.
  • the input signal is shown as CR(1).
  • CR(1) has the same waveform as OUT1(1). Therefore, in the second phase, the tenth transistor M10 is turned on, so that the pull-down node Q(3) is set to a low level. Since the pull-down node Q(3) is at a low level, the fourteenth transistor M14 and the twentieth transistor M20 are turned on. Therefore, the first pull-up node QB_A(3) and the second pull-up node QB_B(3) are set to a high level, thereby turning off the twenty-fifth transistor M25 to the twenty-eighth transistor M28.
  • the pull-down node Q(3) is at a low level, the twenty-ninth transistor M29, the thirtieth transistor M30, and the thirty-third transistor M33 are turned on. Therefore, the shift signal output terminal CR(3) and the first pixel signal output terminal OUT1(3) output the high level from the third clock signal CLKD_3, and the second pixel signal output terminal OUT2(3) outputs the seventh clock signal High level of CLKE_3.
  • CR(1) is at a high level, so the tenth transistor M10 is turned off.
  • the pull-down node Q(3) is held at a low level under the holding action of the second capacitor C2. Since the pull-down node Q(3) is at a low level, the twenty-ninth transistor M29, the thirtieth transistor M30, and the thirty-third transistor M33 continue to be turned on. Therefore, the shift signal output terminal CR(3) and the first pixel signal output terminal OUT1(3) output the low level from the third clock signal CLKD_3, and the second pixel signal output terminal OUT2(3) outputs the seventh clock signal Low level of CLKE_3. The potential of the pull-down node Q(3) is further lowered due to the bootstrap effect.
  • OE is at a low level at this stage, so the ninth transistor M9 is turned on.
  • the pull-down control node H is supplied with a low level (ie, blanking input signal) from the shift signal output terminal CR(3).
  • the first capacitor C1 stores the blanking input signal. Since the pull-down control node H is at a low level, the seventeenth transistor M17 and the twenty-third transistor M23 are turned on.
  • the twenty-ninth transistor M29, the thirty-th transistor M30, and the thirty-third transistor M33 continue to be turned on. Therefore, the shift signal output terminal CR(3) and the first pixel signal output terminal OUT1(3) output the high level from the third clock signal CLKD_3, and the second pixel signal output terminal OUT2(3) outputs the seventh clock signal High level of CLKE_3. Due to the equational jump of the voltage across the second capacitor C2, the potential of the pull-down node Q(3) will increase by a magnitude.
  • the display reset signal STD of the shift register circuit in the third row comes from the shift output terminal CR(6) of one shift register circuit in the other shift register.
  • the shift output terminal CR(6) outputs a low level at this stage.
  • the pull-down node Q(3) is reset to a high level. Therefore, the twenty-ninth transistor M29, the thirtieth transistor M30, the thirty-third transistor M33, the fourteenth transistor M14, and the twentieth transistor M20 are turned off. Since the first control terminal VA and the second control terminal VB alternately output a low level, the first pull-up node QB_A(3) and the second pull-up node QB_B(3) are alternately set to a low level.
  • the twenty-fifth transistor M25, the twenty-sixth transistor M26, the thirty-first transistor M31 and the twenty-seventh transistor M27, the twenty-eighth transistor M28, and the thirty-second transistor M32 are turned on alternately , So that the shift signal output terminal CR(3), the first pixel signal output terminal OUT1(3) and the second pixel signal output terminal OUT2(3) output high levels.
  • the pull-down control node H remains low. Therefore, the first transistor M1 is turned on, thereby providing the low level from the blanking pull-down signal terminal to the point P. Since the blanking control terminal CLA outputs a low level, the second transistor M2, the sixteenth transistor M16, and the twenty-second transistor M22 are turned on. In the case where the second transistor M2 is turned on, the pull-down node Q(3) is set to a low level. Therefore, the fourteenth transistor M14 and the twentieth transistor M20 are turned on, thereby setting the first pull-up node QB_A(3) and the second pull-up node QB_B(3) to a high level.
  • the first pull-up node QB_A(3) and the second pull-up node QB_B(3) are also set to a high level, thereby reducing the first Noise on the pull-up node QB_A(3) and the second pull-up node QB_B(3).
  • the twenty-fifth transistor M25 to the twenty-eighth transistor M28, the thirty-first transistor M31, and the third The twelve transistors M32 are turned off, so they do not affect the outputs of the shift signal output terminal CR(3), the first pixel signal output terminal OUT1(3), and the second pixel signal output terminal OUT2(3).
  • the shift signal output terminal CR(3) and the first pixel signal output terminal OUT1(3) output the same signal as the third clock signal CLKD_3 as a blanking output signal.
  • the second pixel signal output terminal OUT2 (3) outputs the same signal as the seventh clock signal CLKE_3, which can be used as another blanking output signal.
  • the embodiments of the present disclosure also provide a driving method for driving any one of the shift registers (100 and 200) shown in FIGS. 1 and 2.
  • the blanking input circuit 120 is provided with a blanking input signal according to the compensation selection signal OE, and the blanking input signal is stored in the blanking input circuit 120; and during the blanking period, according to the stored
  • the blanking input signal and blanking control signal CLA provide the blanking pull-down signal V2 to N pull-down nodes (Q(1) ⁇ Q(N)), so that the N shift register circuits (130_1 ⁇ 130_N) are based on The blanking pull-down signal V2 and the corresponding clock signal output respective blanking output signals.
  • the driving method further includes: during display, inputting the display pull-down signal V2 to the corresponding pull-down node (Q(1)-Q(N)) according to the display input signal STU; and according to the pull-down The levels of the nodes (Q(1) to Q(N)) and the corresponding clock signals output the corresponding display output signals.
  • FIG. 13 shows a schematic block diagram of a gate driving circuit 1300 according to an embodiment of the present disclosure.
  • the gate driving circuit 1300 includes K (K is a natural number greater than 1) cascaded shift registers (100 and 200) as in the first aspect of the present disclosure. Therefore, it can be considered that the gate driving circuit 1300 includes K ⁇ N shift register circuits.
  • the display input terminal of the first shift register circuit among the K ⁇ N shift register circuits is supplied with a start signal.
  • the display reset terminal of the first shift register circuit is coupled to the shift signal output terminal of the (i/2+2)th shift register circuit.
  • a first clock signal is provided to the first clock signal terminal of the first shift register circuit.
  • the display input terminal of the second shift register circuit is supplied with the start signal.
  • the display reset terminal of the second shift register circuit is coupled to the shift signal output terminal of the (i/2+3)th shift register circuit.
  • the second clock signal is provided to the first clock signal terminal of the second shift register circuit.
  • the display input terminal of the nth shift register circuit is coupled to the shift signal output terminal of the (n-i/2)th shift register circuit.
  • the display reset terminal of the nth shift register circuit is coupled to the shift signal output terminal of the (n+i/2+1)th shift register circuit.
  • the first clock signal terminal of the nth shift register circuit is supplied with the Mth clock signal.
  • the gate driving circuit is supplied with the first to ith clock signals.
  • the clock cycles of the first to i-th clock signals are the same.
  • the clock cycle of each clock signal includes i stages of equal duration.
  • the first to i-th clock signals are sequentially phase-shifted by 1/i clock cycles.
  • i is an even number
  • n is a natural number greater than 2 and less than or equal to K ⁇ N.
  • N and i are 4, for example.
  • Each stage of the shift register includes: a compensation selection circuit 110, a blanking input circuit 120, and four shift register circuits (A1-A4).
  • the compensation selection control terminal OE of the shift register of each stage is provided with a corresponding compensation selection control signal OE, and the blanking control terminal CLA of the shift register of each stage is provided with a corresponding blanking control signal CLA.
  • the display input terminal STU of the first shift register circuit A1 among the K ⁇ 4 shift register circuits is coupled to the start signal STU.
  • the display reset terminal STD of the first shift register circuit A1 is coupled to the shift signal output terminal CR(4) of the fourth shift register circuit A4.
  • the first clock signal terminal CLKD of the first shift register circuit A1 is supplied with the first clock signal CLKD_1.
  • the display input terminal STU of the second shift register circuit A2 is coupled to the start signal STU.
  • the display reset terminal STD of the second shift register circuit A2 is coupled to the shift signal output terminal CR(5) of the fifth shift register circuit (not shown).
  • the first clock signal terminal CLKD of the second shift register circuit A2 is supplied with the second clock signal CLKD_2.
  • the display input terminal STU of the nth shift register circuit is coupled to the shift signal output terminal CR(n-2) of the (n-2)th shift register circuit.
  • the display reset terminal STD of the nth shift register circuit is coupled to the shift signal output terminal CR(n+3) of the (n+3)th shift register circuit.
  • the first clock signal terminal CLKD of the nth shift register circuit is supplied with the Mth clock signal CLKD_M.
  • n is a natural number greater than 2 and less than or equal to 2K.
  • M is i, otherwise, M is n modulo i.
  • M is n modulo i.
  • M is n modulo i.
  • M is a natural number greater than 2 and less than or equal to 2K.
  • the second clock signal terminal CLKE of the nth shift register circuit is provided with the (i+M)th clock signal CLKE_M.
  • the (i+1)th to 2ith clock signals have the same waveform as the first to ith clock signals, respectively.
  • the second clock signal terminal CLKE of the first shift register circuit A1 is supplied with the fifth clock signal CLKE_1.
  • the second clock signal terminal CLKE of the second shift register circuit A2 is supplied with the sixth clock signal CLKE_2.
  • the second clock signal terminal CLKE of the third shift register circuit A3 is supplied with the seventh clock signal CLKE_3.
  • the second clock signal terminal CLKE of the fourth shift register circuit A4 is supplied with the eighth clock signal CLKE_4.
  • FIG. 14 shows a schematic block diagram of a display device 1300 according to an embodiment of the present disclosure.
  • the display device 1300 includes an array substrate 1310.
  • the array substrate 1310 includes the gate drive circuit 1200 described above.
  • the display device 1300 provided by the embodiments of the present disclosure may be applied to any product with a display function, for example, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, wearable device, or navigator.
  • a display function for example, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, wearable device, or navigator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

一种移位寄存器，包括：消隐输入电路（120）、N个移位寄存电路（130_1……130_N）和补偿选择电路（110）。所述消隐输入电路（120）被配置为存储消隐输入信号（OUT_1），以及基于所述消隐输入信号（OUT_1）和消隐控制信号（CLA）将消隐下拉信号（V2）提供给N个下拉节点（Q(1)……Q(N)）。所述N个移位寄存电路（130_1……130_N）分别经由所述N个下拉节点（Q(1)……Q(N)）连接到所述消隐输入电路（120），并被配置为在消隐期间基于所述消隐下拉信号（V2）和相应的时钟信号输出各自的消隐输出信号（OUT_1……OUT_N）。所述补偿选择电路（110）被配置为在补偿选择控制信号（OE）的控制下向所述消隐输入电路（120）提供所述消隐输入信号（OUT_1）。其中，N为大于1的自然数。

Description

移位寄存器及其驱动方法、栅极驱动电路以及显示装置 技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器及其驱动方法、栅极驱动电路、阵列基板以及显示装置。
背景技术
阵列基板行驱动(Gate Driver on Array，简称GOA)技术将栅极驱动电路制作在阵列基板上，实现对像素电路逐行扫描的功能。栅极驱动电路可包括多个级联的移位寄存器。从移位寄存器的输出端输出扫描信号以驱动像素电路并同时输出级联信号以驱动下一级移位寄存器。
在显示领域特别是有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置中，栅极驱动电路目前都集成在GATE IC中。在IC设计中，芯片的面积是影响芯片成本的主要因素。
发明内容
本文中描述的实施例提供了一种移位寄存器及其驱动方法、栅极驱动电路以及显示装置。
根据本公开的第一方面，提供了一种移位寄存器。该移位寄存器包括：消隐输入电路、N个移位寄存电路和补偿选择电路。所述消隐输入电路被配置为存储消隐输入信号，以及基于所述消隐输入信号和消隐控制信号将消隐下拉信号经由N个下拉节点提供给所述N个移位寄存电路。所述N个移位寄存电路耦接到所述消隐输入电路，并被配置为在消隐期间基于所述消隐下拉信号和相应的时钟信号输出各自的消隐输出信号。所述补偿选择电路被配置为在补偿选择控制信号的控制下向所述消隐输入电路提供所述消隐输入信号。在这里，N为大于1的自然数。
在本公开的一些实施例中，所述N个移位寄存电路进一步被配置为在显示期间基于显示输入信号和相应的时钟信号输出各自的显示输出信号。 所述显示输出信号中的一个显示输出信号被提供给所述补偿选择电路作为所述消隐输入信号。
在本公开的一些实施例中，所述消隐输入电路包括存储子电路和隔离子电路。所述存储子电路被配置为存储所述消隐输入信号。所述隔离子电路被配置为基于所述消隐输入信号和所述消隐控制信号将所述消隐下拉信号提供给所述N个下拉节点。
在本公开的一些实施例中，所述隔离子电路包括第一晶体管和N个第二晶体管。所述第一晶体管的控制极耦接所述存储子电路。所述第一晶体管的第一极耦接消隐下拉信号端。所述第一晶体管的第二极耦接所述N个第二晶体管的第一极。所述N个第二晶体管的控制极耦接消隐控制端。所述N个第二晶体管的第二极耦接相应的下拉节点。
在本公开的一些实施例中，所述隔离子电路包括第三晶体管、第四晶体管和N个第五晶体管。所述第三晶体管的控制极耦接所述存储子电路。所述第三晶体管的第一极耦接所述消隐控制端。所述第三晶体管的第二极耦接所述第四晶体管的第二极和所述N个第五晶体管的控制极。所述第四晶体管的控制极耦接第二消隐控制端。所述第四晶体管的第一极耦接第一电压端。所述N个第五晶体管的第一极耦接消隐下拉信号端。所述N个第五晶体管的第二极耦接相应的下拉节点。
在本公开的一些实施例中，所述隔离子电路包括第六晶体管、两个第七晶体管和N个第八晶体管。所述第六晶体管的控制极耦接所述存储子电路。所述第六晶体管的第一极耦接消隐控制端。所述第六晶体管的第二极耦接所述两个第七晶体管的第二极和所述N个第八晶体管的控制极。所述两个第七晶体管的控制极分别耦接第三消隐控制端和第四消隐控制端。所述两个第七晶体管的第一极耦接第一电压端。所述N个第八晶体管的第一极耦接消隐下拉信号端。所述N个第八晶体管的第二极耦接相应的下拉节点。
在本公开的一些实施例中，所述存储子电路包括第一电容器。所述第一电容器的第一端耦接所述补偿选择电路和所述隔离子电路。所述第一电 容器的第二端耦接第一电压端。
在本公开的一些实施例中，所述补偿选择电路包括第九晶体管。所述第九晶体管的控制极耦接补偿选择控制端。所述第九晶体管的第一极耦接消隐输入信号端。所述第九晶体管的第二极耦接所述隔离子电路。
在本公开的一些实施例中，所述移位寄存电路包括：显示输入电路、显示复位电路、消隐复位电路、上拉电路、输出上拉电路和输出电路。所述显示输入电路被配置为基于显示输入信号将显示下拉信号提供给所述下拉节点。所述显示复位电路被配置为基于显示复位信号对所述下拉节点进行复位。所述消隐复位电路被配置为基于消隐复位信号对所述下拉节点进行复位。所述上拉电路被配置为在对所述下拉节点进行复位之后维持所述下拉节点的电平，并交替下拉第一上拉节点和第二上拉节点。所述输出上拉电路被配置为基于所述第一上拉节点和所述第二上拉节点的电平来上拉所述移位寄存器的消隐输出信号和显示输出信号。所述输出电路被配置为在消隐期间基于所述消隐下拉信号和相应的时钟信号输出所述消隐输出信号，以及在显示期间基于所述显示下拉信号和相应的时钟信号输出所述显示输出信号。
在本公开的一些实施例中，所述显示复位电路包括第十一晶体管。所述第十一晶体管的控制极耦接显示复位端。所述第十一晶体管的第一极耦接第一电压端。所述第十一晶体管的第二极耦接所述下拉节点。
在本公开的一些实施例中，所述消隐复位电路包括第十二晶体管。所述第十二晶体管的控制极耦接消隐复位端。所述第十二晶体管的第一极耦接第一电压端。所述第十二晶体管的第二极耦接所述下拉节点。
在本公开的一些实施例中，所述上拉电路包括第十三至二十四晶体管。第十三晶体管的控制极和第一极耦接第一控制端。所述第十三晶体管的第二极耦接第一上拉节点。第十四晶体管的控制极耦接所述下拉节点。所述第十四晶体管的第一极耦接第一电压端。所述第十四晶体管的第二极耦接所述第一上拉节点。第十五晶体管的控制极耦接所述第一上拉节点。所述第十五晶体管的第一极耦接所述第一电压端。所述第十五晶体管的第二极 耦接所述下拉节点。第十六晶体管的控制极耦接消隐控制端。所述第十六晶体管的第一极耦接所述第十七晶体管的第二极。所述第十六晶体管的第二极耦接所述第一上拉节点。第十七晶体管的控制极耦接下拉控制节点。所述第十七晶体管的第一极耦接所述第一电压端。第十八晶体管的控制极耦接显示输入端。所述第十八晶体管的第一极耦接所述第一电压端。所述第十八晶体管的第二极耦接所述第一上拉节点。第十九晶体管的控制极和第一极耦接第二控制端。所述第十九晶体管的第二极耦接第二上拉节点。第二十晶体管的控制极耦接所述下拉节点。所述第二十晶体管的第一极耦接所述第一电压端。所述第二十晶体管的第二极耦接所述第二上拉节点。第二十一晶体管的控制极耦接所述第二上拉节点。所述第二十一晶体管的第一极耦接所述第一电压端。所述第二十一晶体管的第二极耦接所述下拉节点。第二十二晶体管的控制极耦接所述消隐控制端。所述第二十二晶体管的第一极耦接所述第二十三晶体管的第二极。所述第二十二晶体管的第二极耦接所述第二上拉节点。第二十三晶体管的控制极耦接所述下拉控制节点。所述第二十三晶体管的第一极耦接所述第一电压端。第二十四晶体管的控制极耦接所述显示输入端。所述第二十四晶体管的第一极耦接所述第一电压端。所述第二十四晶体管的第二极耦接所述第二上拉节点。
在本公开的一些实施例中，所述上拉电路包括第十三至十六晶体管、第十八至第二十二晶体管和第二十四晶体管。第十三晶体管的控制极和第一极耦接第一控制端。所述第十三晶体管的第二极耦接第一上拉节点。第十四晶体管的控制极耦接所述下拉节点。所述第十四晶体管的第一极耦接所述第一电压端。所述第十四晶体管的第二极耦接所述第一上拉节点。第十五晶体管的控制极耦接所述第一上拉节点。所述第十五晶体管的第一极耦接所述第一电压端。所述第十五晶体管的第二极耦接所述下拉节点。第十六晶体管的控制极耦接所述消隐控制端。所述第十六晶体管的第一极耦接所述第一电压端。所述第十六晶体管的第二极耦接所述第一上拉节点。第十八晶体管的控制极耦接所述显示输入端。所述第十八晶体管的第一极耦接所述第一电压端。所述第十八晶体管的第二极耦接所述第一上拉节点。 第十九晶体管的控制极和第一极耦接第二控制端。所述第十九晶体管的第二极耦接第二上拉节点。第二十晶体管的控制极耦接所述下拉节点。所述第二十晶体管的第一极耦接所述第一电压端。所述第二十晶体管的第二极耦接所述第二上拉节点。第二十一晶体管的控制极耦接所述第二上拉节点。所述第二十一晶体管的第一极耦接所述第一电压端。所述第二十一晶体管的第二极耦接所述下拉节点。第二十二晶体管的控制极耦接所述消隐控制端。所述第二十二晶体管的第一极耦接所述第一电压端。所述第二十二晶体管的第二极耦接所述第二上拉节点。第二十四晶体管的控制极耦接所述显示输入端。所述第二十四晶体管的第一极耦接所述第一电压端。所述第二十四晶体管的第二极耦接所述第二上拉节点。
在本公开的一些实施例中，所述上拉电路包括第十三至十五晶体管、第十八至第二十一晶体管和第二十四晶体管。第十三晶体管的控制极和第一极耦接第一控制端。所述第十三晶体管的第二极耦接第一上拉节点。第十四晶体管的控制极耦接所述下拉节点。所述第十四晶体管的第一极耦接所述第一电压端。所述第十四晶体管的第二极耦接所述第一上拉节点。第十五晶体管的控制极耦接所述第一上拉节点。所述第十五晶体管的第一极耦接所述第一电压端。所述第十五晶体管的第二极耦接所述下拉节点。第十八晶体管的控制极耦接所述显示输入端。所述第十八晶体管的第一极耦接所述第一电压端。所述第十八晶体管的第二极耦接所述第一上拉节点。第十九晶体管的控制极和第一极耦接第二控制端。所述第十九晶体管的第二极耦接第二上拉节点。第二十晶体管的控制极耦接所述下拉节点。所述第二十晶体管的第一极耦接所述第一电压端。所述第二十晶体管的第二极耦接所述第二上拉节点。第二十一晶体管的控制极耦接所述第二上拉节点。所述第二十一晶体管的第一极耦接所述第一电压端。所述第二十一晶体管的第二极耦接所述下拉节点。第二十四晶体管的控制极耦接所述显示输入端。所述第二十四晶体管的第一极耦接所述第一电压端。所述第二十四晶体管的第二极耦接所述第二上拉节点。
在本公开的一些实施例中，所述输出上拉电路包括第二十五至二十八 晶体管。第二十五晶体管的控制极耦接所述第一上拉节点。所述第二十五晶体管的第一极耦接第一电压端。所述第二十五晶体管的第二极耦接移位信号输出端。第二十六晶体管的控制极耦接所述第一上拉节点。所述第二十六晶体管的第一极耦接所述第一电压端。所述第二十六晶体管的第二极耦接第一像素信号输出端。第二十七晶体管的控制极耦接所述第二上拉节点。所述第二十七晶体管的第一极耦接所述第一电压端。所述第二十七晶体管的第二极耦接所述移位信号输出端。第二十八晶体管的控制极耦接所述第二上拉节点。所述第二十八晶体管的第一极耦接所述第一电压端。所述第二十八晶体管的第二极耦接所述第一像素信号输出端。所述输出电路包括第二十九晶体管、第三十晶体管和第二电容器。第二十九晶体管的控制极耦接所述下拉节点。所述第二十九晶体管的第一极耦接第一时钟信号端。所述第二十九晶体管的第二极耦接所述移位信号输出端。第三十晶体管的控制极耦接所述下拉节点。所述第三十晶体管的第一极耦接所述第一时钟信号端。所述第三十晶体管的第二极耦接所述第一像素信号输出端。
在本公开的一些实施例中，所述输出上拉电路还包括第三十一晶体管和第三十二晶体管。第三十一晶体管的控制极耦接所述第一上拉节点。所述第三十一晶体管的第一极耦接所述第一电压端。所述第三十一晶体管的第二极耦接第二像素信号输出端。第三十二晶体管的控制极耦接所述第二上拉节点。所述第三十二晶体管的第一极耦接所述第一电压端。所述第三十二晶体管的第二极耦接所述第二像素信号输出端。所述输出电路还包括第三十三晶体管和第三电容器。第三十三晶体管的控制极耦接所述下拉节点。所述第三十三晶体管的第一极耦接第二时钟信号端。所述第三十三晶体管的第二极耦接所述第二像素信号输出端。所述第三电容器的第一端耦接所述下拉节点。所述第三电容器的第二端耦接所述第二像素信号输出端。
在本公开的一些实施例中，所述显示输入电路包括第十晶体管。所述第十晶体管的控制极耦接显示输入端。所述第十晶体管的第一极耦接显示下拉信号端。所述第十晶体管的第二极耦接所述下拉节点。
在本公开的一些实施例中，所述显示输入电路包括第三十四晶体管和 第三十五晶体管。所述第三十四晶体管的控制极和第一极耦接所述显示输入端。所述第三十四晶体管的第二极耦接所述第三十五晶体管的第一极。所述第三十五晶体管的控制极耦接所述显示输入端。所述第三十五晶体管的第二极耦接所述下拉节点。
在本公开的一些实施例中，所述显示输入电路包括第三十六晶体管和第三十七晶体管。所述第三十六晶体管的控制极耦接所述显示输入端。所述第三十六晶体管的第一极耦接所述显示下拉信号端。所述第三十六晶体管的第二极耦接所述第三十七晶体管的控制极和第一极。所述第三十七晶体管的第二极耦接所述下拉节点。
在本公开的一些实施例中，所述显示输入电路包括第三十八晶体管。所述第三十八晶体管的控制极和第一极耦接所述显示输入端。所述第三十八晶体管的第二极耦接所述下拉节点。
根据本公开的第二方面，提供了一种栅极驱动电路。该栅极驱动电路包括多个级联的如本公开的第一方面所述的移位寄存器。每级移位寄存器的补偿选择控制端被提供相应的补偿选择控制信号。每级移位寄存器的消隐控制端被提供相应的消隐控制信号。K×N个移位寄存电路中的第一移位寄存电路的显示输入端被提供起始信号。所述第一移位寄存电路的显示复位端耦接第(i/2+2)移位寄存电路的移位信号输出端。所述第一移位寄存电路的第一时钟信号端被提供第一时钟信号。第二移位寄存电路的显示输入端被提供所述起始信号。所述第二移位寄存电路的显示复位端耦接第(i/2+3)移位寄存电路的移位信号输出端。所述第二移位寄存电路的第一时钟信号端被提供第二时钟信号。第n移位寄存电路的显示输入端耦接第(n-i/2)移位寄存电路的移位信号输出端。第n移位寄存电路的显示复位端耦接第(n+i/2+1)移位寄存电路的移位信号输出端。第n移位寄存电路的第一时钟信号端被提供第M时钟信号。在显示期间，第一至第i时钟信号的时钟周期相同。所述时钟周期包括i个时长相等的阶段。第一至第i时钟信号依次相移1/i个时钟周期。K为大于1的自然数。i为偶数。n为大于2且小于或等于K×N的自然数。当n为i的整数倍时，M为i；否则， M为n模i。
在本公开的一些实施例中，N为4。
在本公开的一些实施例中，i为4。
在本公开的一些实施例中，第n移位寄存电路的第二时钟信号端被提供第(i+M)时钟信号。在显示期间，第(i+1)至第2i时钟信号分别与第一至第i时钟信号的波形相同。
根据本公开的第三方面，提供了一种用于驱动根据本公开第一方面所述的移位寄存器的驱动方法。该驱动方法包括：在显示期间，根据所述补偿选择信号向所述消隐输入电路提供所述消隐输入信号，并在所述消隐输入电路中存储所述消隐输入信号；以及在消隐期间，根据所存储的消隐输入信号和消隐控制信号将消隐下拉信号提供给所述N个下拉节点，从而使得所述N个移位寄存电路分别基于所述消隐下拉信号和相应的时钟信号输出各自的消隐输出信号。
在本公开的一些实施例中，该驱动方法还包括：在显示期间，根据显示输入信号将显示下拉信号输入到相应的下拉节点；以及根据所述下拉节点的电平和相应的时钟信号输出相应的显示输出信号。
根据本公开的第四方面，提供了一种阵列基板。该阵列基板包括根据本公开第二方面所述的栅极驱动电路。
根据本公开的第五方面，提供了一种显示装置。该显示装置包括根据本公开的第四方面所述的阵列基板。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的移位寄存器的示意性框图；
图2是根据本公开的另一实施例的移位寄存器的示意性框图；
图3是根据本公开的实施例的移位寄存器中的补偿选择电路和消隐输 入电路的示意性电路图；
图4是根据本公开的另一实施例的移位寄存器中的补偿选择电路和消隐输入电路的示意性电路图；
图5是根据本公开的又一实施例的移位寄存器中的补偿选择电路和消隐输入电路的示意性电路图；
图6是根据本公开的再一实施例的移位寄存器中的补偿选择电路和消隐输入电路的示意性电路图；
图7是根据本公开的实施例的移位寄存器中的移位寄存电路的示意性电路图；
图8是根据本公开的另一实施例的移位寄存器中的移位寄存电路的示意性电路图；
图9是根据本公开的又一实施例的移位寄存器中的移位寄存电路的示意性电路图；
图10是根据本公开的再一实施例的移位寄存器中的移位寄存电路的示意性电路图；
图11是根据本公开的实施例的移位寄存器中的显示输入电路的示意性电路图；
图12是用于如图1或图2所示的移位寄存器的一些信号的时序图；
图13是根据本公开的实施例的栅极驱动电路的示意性框图；以及
图14是根据本公开的实施例的显示装置的示意性框图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具 有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的一些实施例中，将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
图1示出根据本公开的实施例的移位寄存器100的示意性框图。该移位寄存器100包括：消隐输入电路120、N个移位寄存电路(130_1……130_n，以下可统一称为130)和补偿选择电路110。消隐输入电路120被配置为存储消隐输入信号OUT_1，以及基于消隐输入信号OUT_1和消隐控制信号CLA将消隐下拉信号V2经由N个下拉节点(Q(1)～Q(N))提供给N个移位寄存电路130。N个移位寄存电路130耦接到消隐输入电路120，并被配置为在消隐期间基于消隐下拉信号V2和相应的时钟信号(未示出)输出各自的消隐输出信号(OUT_1～OUT_N)。补偿选择电路110被配置为在补偿选择控制信号OE的控制下向消隐输入电路120提供消隐输入信号。在这里，N为大于1的自然数。
移位寄存电路130还可以被进一步配置为在显示期间基于显示输入信号(未示出)和相应的时钟信号输出各自的显示输出信号。显示输出信号中的一个显示输出信号可以被提供给补偿选择电路110作为消隐输入信号。
这样，一个补偿选择电路110和一个消隐输入电路120能够将消隐下 拉信号V2提供给N个下拉节点(Q(1)～Q(N))。相对于一个补偿选择电路110和一个消隐输入电路120只能够向一个下拉节点提供消隐下拉信号V2的情况，本公开的实施例能够节省栅极驱动电路中的补偿选择电路110和消隐输入电路120的数量。
图2示出根据本公开的另一实施例的移位寄存器的示意性框图。如图2所示，消隐输入电路120包括存储子电路121和隔离子电路122。存储子电路121被配置为存储消隐输入信号OUT。隔离子电路122被配置为基于消隐输入信号OUT和消隐控制信号CLA将消隐下拉信号V2提供给相应的下拉节点Q(n)。
图3-6示出根据本公开的实施例的移位寄存器(100和200)中的补偿选择电路110和消隐输入电路120的示意性电路图。在本公开的实施例中采用P型晶体管来实现补偿选择电路110和消隐输入电路120。在下文中，第一电压V1为高电平。第二电压V2为低电平。N例如为4。本领域技术人员应理解，在本公开的替代实施例中也可以采用N型晶体管来实现补偿选择电路110和消隐输入电路120。
如图3所示，补偿选择电路110可包括第九晶体管M9。存储子电路121可包括第一电容器C1。隔离子电路122可包括第一晶体管M1和4个第二晶体管(M2_1、M2_2、M2_3和M2_4)。
第九晶体管M9的控制极耦接补偿选择控制端OE。第九晶体管M9的第一极耦接消隐输入信号端。消隐输入信号端可以例如是移位寄存器的移位信号输出端CR(n)。第九晶体管M9的第二极耦接下拉控制节点H。第一电容器C1的第一端耦接下拉控制节点H。第一电容器C1的第二端耦接第一电压端V1。第一晶体管M1的控制极耦接下拉控制节点H。第一晶体管M1的第一极耦接消隐下拉信号端。消隐下拉信号端可以被提供例如第二电压V2。第一晶体管M1的第二极耦接4个第二晶体管(M2_1、M2_2、M2_3和M2_4)的第一极(P点)。4个第二晶体管(M2_1、M2_2、M2_3和M2_4)的控制极耦接消隐控制端CLA。4个第二晶体管(M2_1、M2_2、M2_3和M2_4)的第二极耦接相应的下拉节点(Q(n)～Q(n+3))。在消隐控 制端CLA被提供低电平的情况下，4个第二晶体管(M2_1、M2_2、M2_3和M2_4)导通，从而将来自消隐下拉信号端的消隐下拉信号V2提供给4个下拉节点(Q(n)～Q(n+3))。
图4所示出的隔离子电路122与图3所示出的隔离子电路122的不同之处在于，消隐下拉信号端被提供的信号CLC可以不必一直保持低电平，其只需要在来自消隐控制端CLA的消隐控制信号CLA为低电平期间也为低电平即可。在消隐控制端CLA被提供低电平的情况下，4个第二晶体管(M2_1、M2_2、M2_3和M2_4)导通，从而将来自消隐下拉信号端的低电平提供给4个下拉节点(Q(n)～Q(n+3))。
图5示出隔离子电路122的另一种示例性结构。如图5所示，隔离子电路122可包括第三晶体管M3、第四晶体管M4和4个第五晶体管(M5_1、M5_2、M5_3和M5_4)。第三晶体管M3的控制极耦接下拉控制节点H。第三晶体管M3的第一极耦接消隐控制端CLA。第三晶体管M3的第二极耦接第四晶体管M4的第二极和4个第五晶体管(M5_1、M5_2、M5_3和M5_4)的控制极(P点)。第四晶体管M4的控制极耦接第二消隐控制端CLC。第四晶体管M4的第一极耦接第一电压端V1。4个第五晶体管(M5_1、M5_2、M5_3和M5_4)的第一极耦接消隐下拉信号端V2。4个第五晶体管(M5_1、M5_2、M5_3和M5_4)的第二极耦接相应的下拉节点(Q(n)～Q(n+3))。在本实施例中，来自第二消隐控制端CLC的信号具有相对于来自消隐控制端CLA的信号的反相电压。
在消隐控制端CLA被提供高电平的情况下，第二消隐控制端CLC提供低电平。因此，第四晶体管M4导通，从而使得P点为高电平。这样，4个第五晶体管(M5_1、M5_2、M5_3和M5_4)截止。在消隐控制端CLA被提供低电平的情况下，4个第五晶体管(M5_1、M5_2、M5_3和M5_4)导通，从而将来自消隐下拉信号端的低电平提供给4个下拉节点(Q(n)～Q(n+3))。另一方面，此时，第二消隐控制端CLC提供高电平。因此，第四晶体管M4截止，来自第一电压端的第一电压不被施加到P点。
图6示出隔离子电路122的另一种示例性结构。如图6所示，隔离子 电路122可包括第六晶体管M6、两个第七晶体管(M7_a和M7_b)和4个第八晶体管(M8_1、M8_2、M8_3和M8_4)。第六晶体管M6的控制极耦接下拉控制节点H。第六晶体管M6的第一极耦接消隐控制端CLA。第六晶体管M6的第二极耦接两个第七晶体管(M7_a和M7_b)的第二极和4个第八晶体管(M8_1、M8_2、M8_3和M8_4)的控制极。两个第七晶体管(M7_a和M7_b)的控制极分别耦接第三消隐控制端QB_A和第四消隐控制端QB_B。第三消隐控制端QB_A和第四消隐控制端QB_B的信号交替导通第七晶体管M7_a和M7_b。两个第七晶体管(M7_a和M7_b)的第一极耦接第一电压端V1。4个第八晶体管(M8_1、M8_2、M8_3和M8_4)的第一极耦接消隐下拉信号端V2。4个第八晶体管(M8_1、M8_2、M8_3和M8_4)的第二极耦接相应的下拉节点(Q(n)～Q(n+3))。
在消隐控制端CLA被提供高电平的情况下，第三消隐控制端QB_A和第四消隐控制端QB_B的信号交替导通第七晶体管M7_a和M7_b。因此，P点为高电平。这样，4个第八晶体管(M8_1、M8_2、M8_3和M8_4)截止。在消隐控制端CLA被提供低电平的情况下，4个第八晶体管(M8_1、M8_2、M8_3和M8_4)导通，从而将来自消隐下拉信号端的低电平提供给4个下拉节点(Q(n)～Q(n+3))。
回到图2，在本公开的一些实施例中，移位寄存电路130可包括：显示输入电路210、显示复位电路220、消隐复位电路230、上拉电路240、输出上拉电路260和输出电路250。显示输入电路210被配置为基于显示输入信号STU将显示下拉信号V2提供给下拉节点Q(n)。显示复位电路220被配置为基于显示复位信号STD对下拉节点Q(n)进行复位。消隐复位电路230被配置为基于消隐复位信号TRST对下拉节点Q(n)进行复位。上拉电路240被配置为在对下拉节点Q(n)进行复位之后维持下拉节点Q(n)的电平，并交替下拉第一上拉节点和第二上拉节点(未示出)。输出上拉电路260被配置为基于所述第一上拉节点和所述第二上拉节点的电平来上拉移位寄存器的消隐输出信号和显示输出信号OUT。输出电路250被配置为在消隐期间基于消隐下拉信号V2和相应的时钟信号输出消隐输出信号 OUT，以及在显示期间基于显示下拉信号V2和相应的时钟信号输出显示输出信号OUT。
图7示出根据本公开的实施例的移位寄存器(100和200)中的移位寄存电路130的示意性电路图。显示输入电路210包括第十晶体管M10。第十晶体管M10的控制极耦接显示输入信号STU。显示输入信号STU例如为前两行的移位寄存电路的显示输出信号CR(n-2)。第十晶体管M10的第一极耦接显示下拉信号V2。第十晶体管M10的第二极耦接下拉节点Q(n)。显示复位电路220包括第十一晶体管M11。第十一晶体管M11的控制极耦接显示复位信号STD。显示复位信号STD例如为后三行的移位寄存电路的显示输出信号CR(n+3)。第十一晶体管M11的第一极耦接第一电压端V1。第十一晶体管M11的第二极耦接下拉节点Q(n)。消隐复位电路230包括第十二晶体管M12。第十二晶体管M12的控制极耦接消隐复位信号TRST。第十二晶体管M12的第一极耦接第一电压端V1。第十二晶体管M12的第二极耦接下拉节点Q(n)。上拉电路240包括第十三晶体管M13至第二十四晶体管M24。第十三晶体管M13的控制极和第一极耦接第一控制端VA。第十三晶体管M13的第二极耦接第一上拉节点QB_A。第十四晶体管M14的控制极耦接下拉节点Q(n)。第十四晶体管M14的第一极耦接第一电压端V1。第十四晶体管M14的第二极耦接第一上拉节点QB_A。第十五晶体管M15的控制极耦接第一上拉节点QB_A。第十五晶体管M15的第一极耦接第一电压端V1。第十五晶体管M15的第二极耦接下拉节点Q(n)。第十六晶体管M16的控制极耦接消隐控制端CLA。第十六晶体管M16的第一极耦接第十七晶体管M17的第二极。第十六晶体管M16的第二极耦接第一上拉节点QB_A。第十七晶体管M17的控制极耦接下拉控制节点H。第十七晶体管M17的第一极耦接第一电压端V1。第十八晶体管M18的控制极耦接显示输入端STU。第十八晶体管M18的第一极耦接第一电压端V1。第十八晶体管M18的第二极耦接第一上拉节点QB_A。第十九晶体管M19的控制极和第一极耦接第二控制端VB。第十九晶体管M19的第二极耦接第二上拉节点QB_B。第二十晶体管M20的控制极耦接下拉节点Q(n)。第 二十晶体管M20的第一极耦接第一电压端V1。第二十晶体管M20的第二极耦接第二上拉节点QB_B。第二十一晶体管M21的控制极耦接第二上拉节点QB_B。第二十一晶体管M21的第一极耦接第一电压端V1。第二十一晶体管M21的第二极耦接下拉节点Q(n)。第二十二晶体管M22的控制极耦接消隐控制端CLA。第二十二晶体管M22的第一极耦接第二十三晶体管M23的第二极。第二十二晶体管M22的第二极耦接第二上拉节点QB_B。第二十三晶体管M23的控制极耦接下拉控制节点H。第二十三晶体管M23的第一极耦接第一电压端V1。第二十四晶体管M24的控制极耦接显示输入端STU。第二十四晶体管M24的第一极耦接第一电压端V1。第二十四晶体管M24的第二极耦接第二上拉节点QB_B。输出上拉电路260包括第二十五晶体管M25至第二十八晶体管M28。第二十五晶体管M25的控制极耦接第一上拉节点QB_A。第二十五晶体管M25的第一极耦接第一电压端V1。第二十五晶体管M25的第二极耦接移位信号输出端CR(n)。第二十六晶体管M26的控制极耦接第一上拉节点QB_A。第二十六晶体管M26的第一极耦接第一电压端V1。第二十六晶体管M26的第二极耦接第一像素信号输出端OUT1(n)。第二十七晶体管M27的控制极耦接第二上拉节点QB_B。第二十七晶体管M27的第一极耦接第一电压端V1。第二十七晶体管M27的第二极耦接移位信号输出端CR(n)。第二十八晶体管M28的控制极耦接第二上拉节点QB_B。第二十八晶体管M28的第一极耦接第一电压端V1。第二十八晶体管M28的第二极耦接第一像素信号输出端OUT1(n)。输出电路250包括第二十九晶体管M29、第三十晶体管M30和第二电容器C2。第二十九晶体管M29的控制极耦接下拉节点Q(n)。第二十九晶体管M29的第一极耦接第一时钟信号端CLKD。第二十九晶体管M29的第二极耦接移位信号输出端CR(n)。第三十晶体管M30的控制极耦接下拉节点Q(n)。第三十晶体管M30的第一极耦接第一时钟信号端CLKD。第三十晶体管M30的第二极耦接第一像素信号输出端OUT1(n)。
图8示出根据本公开的另一实施例的移位寄存器中的移位寄存电路130的示意性电路图。图8所示出的移位寄存电路130与图7所示出的移 位寄存电路130的不同之处在于：第十七晶体管M17和第二十三晶体管M23被省略；第十六晶体管M16的第一极和第二十二晶体管M22的第一极直接连接到第一电压端V1。
图9示出根据本公开的又一实施例的移位寄存器中的移位寄存电路130的示意性电路图。图9所示出的移位寄存电路130与图7所示出的移位寄存电路130的不同之处在于：第十六晶体管M16、第十七晶体管M17、第二十二晶体管M22和第二十三晶体管M23被省略。
图10示出根据本公开的再一实施例的移位寄存器中的移位寄存电路130的示意性电路图。在本实施例中，输出上拉电路260还包括第三十一晶体管M31和第三十二晶体管M32。第三十一晶体管M31的控制极耦接第一上拉节点QB_A。第三十一晶体管M31的第一极耦接第一电压端V1。第三十一晶体管M31的第二极耦接第二像素信号输出端OUT2(n)。第三十二晶体管M32的控制极耦接第二上拉节点QB_B。第三十二晶体管M32的第一极耦接第一电压端V1。第三十二晶体管M32的第二极耦接第二像素信号输出端OUT2(n)。输出电路250还包括第三十三晶体管M33和第三电容器C3。第三十三晶体管M33的控制极耦接下拉节点Q(n)。第三十三晶体管M33的第一极耦接第二时钟信号端CLKE。第三十三晶体管M33的第二极耦接第二像素信号输出端OUT2(n)。第三电容器C3的第一端耦接下拉节点Q(n)。第三电容器C3的第二端耦接第二像素信号输出端OUT2(n)。第二像素信号输出端OUT2(n)可在第二时钟信号端CLKE和下拉节点Q(n)的控制下在显示期间输出第二显示输出信号以及在消隐期间输出第二消隐输出信号。
对于图7-图10所示出的移位寄存电路130，可以在第二控制端VB一直输出低电平的情况下，省略第十三晶体管M13至第十八晶体管M18、第二十五晶体管M25、第二十六晶体管M26和第三十一晶体管M31。也可以在第一控制端VA一直输出低电平的情况下，省略第十九晶体管M19至第二十四晶体管M24、第二十七晶体管M27、第二十八晶体管M28和第三十二晶体管M32。
图11示出根据本公开的实施例的移位寄存器中的显示输入电路210的示意性电路图。在如图11(A)所示的实施例中，显示输入电路210包括第三十四晶体管M34和第三十五晶体管M35。第三十四晶体管M34的控制极和第一极耦接显示输入信号CR(n-2)。第三十四晶体管M34的第二极耦接第三十五晶体管M35的第一极。第三十五晶体管M35的控制极耦接显示输入信号CR(n-2)。第三十五晶体管M35的第二极耦接下拉节点Q(n)。
在如图11(B)所示的实施例中，显示输入电路210包括第三十六晶体管M36和第三十七晶体管M37。第三十六晶体管M36的控制极耦接显示输入信号CR(n-2)。第三十六晶体管M36的第一极耦接显示下拉信号V2。第三十六晶体管M36的第二极耦接第三十七晶体管M37的控制极和第一极。第三十七晶体管M37的第二极耦接下拉节点Q(n)。
在如图11(C)所示的实施例中，显示输入电路210包括第三十八晶体管M38。第三十八晶体管M38的控制极和第一极耦接显示输入信号CR(n-2)。第三十八晶体管M38的第二极耦接下拉节点Q(n)。
图12示出用于如图1或图2所示的移位寄存器(100和200)的一些信号的时序图。如图1或图2所示的移位寄存器(100和200)可以例如由如图3所示的补偿选择电路110和消隐输入电路120以及4个如图10所示的移位寄存电路130组成。下面结合图12所示的时序图，对如图3所示的补偿选择电路110和消隐输入电路120以及如图10所示的移位寄存电路130的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是P型晶体管，第一电压V1为高电平。第二电压V2为低电平。第一控制端VA和第二控制端VB交替输出低电平。第一移位寄存电路的第一时钟信号端CLKD提供第一时钟信号CLKD_1。第二移位寄存电路的第一时钟信号端CLKD提供第二时钟信号CLKD_2。第三移位寄存电路的第一时钟信号端CLKD提供第三时钟信号CLKD_3。第四移位寄存电路的第一时钟信号端CLKD提供第四时钟信号CLKD_4。第一移位寄存电路的第二时钟信号端CLKE提供第五时钟信号CLKE_1。第二移位寄存电路的第二时钟信号端CLKE提供第六时钟信号CLKE_2。第三移位寄存电路的第二时钟信号 端CLKE提供第七时钟信号CLKE_3。第四移位寄存电路的第二时钟信号端CLKE提供第八时钟信号CLKE_4。第一行移位寄存电路130_1和第二行的移位寄存电路130_2被提供的显示输入信号STU在第①阶段为低电平，其后为高电平。其它行的移位寄存电路130_n被提供的显示输入信号STU为CR(n-2)。各行移位寄存电路130_n被提供的显示复位信号STD为CR(n+3)。在这里，n为移位寄存电路的行号。
如图12所示，第①至⑤阶段属于显示期间，第⑥阶段属于消隐期间。在显示期间之前，通过设置消隐复位信号TRST和补偿选择控制信号OE为低电平来将下拉节点Q(n)和下拉控制节点H复位为高电平。
对于第一行的移位寄存电路130_1，在第①阶段，STU为低电平，从而使得第十晶体管M10导通。因此，显示下拉信号V2被提供给下拉节点Q(1)，从而使得下拉节点Q(1)被设置为低电平。由于下拉节点Q(1)为低电平，第十四晶体管M14和第二十晶体管M20导通。因此，第一上拉节点QB_A(1)和第二上拉节点QB_B(1)被设置为高电平，从而使得第二十五晶体管M25到第二十八晶体管M28截止。此外，由于下拉节点Q(1)为低电平，第二十九晶体管M29、第三十晶体管M30和第三十三晶体管M33导通。因此，移位信号输出端CR(1)和第一像素信号输出端OUT1(1)输出来自第一时钟信号CLKD_1的高电平，第二像素信号输出端OUT2(1)输出来自第五时钟信号CLKE_1的高电平。
在第②阶段，STU为高电平，因此第十晶体管M10截止。下拉节点Q(1)在第二电容器C2的保持作用下被保持为低电平。由于下拉节点Q(1)为低电平，第二十九晶体管M29、第三十晶体管M30和第三十三晶体管M33继续导通。因此，移位信号输出端CR(1)和第一像素信号输出端OUT1(1)输出来自第一时钟信号CLKD_1的低电平，第二像素信号输出端OUT2(1)输出来自第五时钟信号CLKE_1的低电平。下拉节点Q(1)的电位由于自举效应而进一步被拉低。
在第③阶段，由于下拉节点Q(1)继续为低电平，第二十九晶体管M29、第三十晶体管M30和第三十三晶体管M33继续导通。因此，移位信号输 出端CR(1)和第一像素信号输出端OUT1(1)输出来自第一时钟信号CLKD_1的高电平，第二像素信号输出端OUT2(1)输出来自第五时钟信号CLKE_1的高电平。
从图12可以看出，第一像素信号输出端OUT1(1)输出的显示输出信号OUT1(1)比显示输入信号STU滞后了半个时钟周期。
下面参考图12来具体描述第三行的移位寄存电路130_3的工作过程。对于第三行的移位寄存电路130_3，显示输入信号为CR(1)。CR(1)与OUT1(1)的波形相同。因此，在第②阶段，第十晶体管M10导通，从而使得下拉节点Q(3)被设置为低电平。由于下拉节点Q(3)为低电平，第十四晶体管M14和第二十晶体管M20导通。因此，第一上拉节点QB_A(3)和第二上拉节点QB_B(3)被设置为高电平，从而使得第二十五晶体管M25到第二十八晶体管M28截止。此外，由于下拉节点Q(3)为低电平，第二十九晶体管M29、第三十晶体管M30和第三十三晶体管M33导通。因此，移位信号输出端CR(3)和第一像素信号输出端OUT1(3)输出来自第三时钟信号CLKD_3的高电平，第二像素信号输出端OUT2(3)输出来自第七时钟信号CLKE_3的高电平。
在第③阶段，CR(1)为高电平，因此第十晶体管M10截止。下拉节点Q(3)在第二电容器C2的保持作用下被保持为低电平。由于下拉节点Q(3)为低电平，第二十九晶体管M29、第三十晶体管M30和第三十三晶体管M33继续导通。因此，移位信号输出端CR(3)和第一像素信号输出端OUT1(3)输出来自第三时钟信号CLKD_3的低电平，第二像素信号输出端OUT2(3)输出来自第七时钟信号CLKE_3的低电平。下拉节点Q(3)的电位由于自举效应而进一步被拉低。
此外，OE在本阶段为低电平，因此第九晶体管M9导通。下拉控制节点H被提供来自移位信号输出端CR(3)的低电平(即，消隐输入信号)。第一电容器C1存储该消隐输入信号。由于下拉控制节点H为低电平，第十七晶体管M17和第二十三晶体管M23导通。
在第④阶段，由于下拉节点Q(3)继续为低电平，第二十九晶体管M29、 第三十晶体管M30和第三十三晶体管M33继续导通。因此，移位信号输出端CR(3)和第一像素信号输出端OUT1(3)输出来自第三时钟信号CLKD_3的高电平，第二像素信号输出端OUT2(3)输出来自第七时钟信号CLKE_3的高电平。由于第二电容器C2两端电压的等式跳变，下拉节点Q(3)的电位会上升一个幅度。
在第⑤阶段，第三行的移位寄存电路的显示复位信号STD来自另一移位寄存器中的一个移位寄存电路的移位输出端CR(6)。该移位输出端CR(6)在本阶段输出低电平。下拉节点Q(3)被复位为高电平。因此，第二十九晶体管M29、第三十晶体管M30、第三十三晶体管M33、第十四晶体管M14和第二十晶体管M20截止。由于第一控制端VA和第二控制端VB交替输出低电平，因此第一上拉节点QB_A(3)和第二上拉节点QB_B(3)被交替设置为低电平。在这种情况下，第二十五晶体管M25、第二十六晶体管M26、第三十一晶体管M31与第二十七晶体管M27、第二十八晶体管M28、第三十二晶体管M32交替导通，从而使得移位信号输出端CR(3)、第一像素信号输出端OUT1(3)和第二像素信号输出端OUT2(3)输出高电平。
在消隐期间，在第⑥阶段，下拉控制节点H仍然保持低电平。因此，第一晶体管M1导通，从而将来自消隐下拉信号端的低电平提供给P点。由于消隐控制端CLA输出低电平，因此第二晶体管M2、第十六晶体管M16和第二十二晶体管M22导通。在第二晶体管M2导通的情况下，下拉节点Q(3)被设置为低电平。因此第十四晶体管M14和第二十晶体管M20导通，从而将第一上拉节点QB_A(3)和第二上拉节点QB_B(3)设置为高电平。在第十六晶体管M16和第二十二晶体管M22导通的情况下，第一上拉节点QB_A(3)和第二上拉节点QB_B(3)也被设置为高电平，从而降低第一上拉节点QB_A(3)和第二上拉节点QB_B(3)上的噪声。由于第一上拉节点QB_A(3)和第二上拉节点QB_B(3)被设置为高电平，第二十五晶体管M25至第二十八晶体管M28、第三十一晶体管M31和第三十二晶体管M32截止，因此它们不影响移位信号输出端CR(3)、第一像素信号输出端OUT1(3)和第二像素信号输出端OUT2(3)的输出。
在之后的阶段，移位信号输出端CR(3)和第一像素信号输出端OUT1(3)输出与第三时钟信号CLKD_3相同的信号作为消隐输出信号。第二像素信号输出端OUT2(3)输出与第七时钟信号CLKE_3相同的信号，该信号可以作为另一消隐输出信号。
本公开的实施例还提供了一种用于驱动如图1和2所示的移位寄存器(100和200)中任一个的驱动方法。在该驱动方法中，在显示期间，根据补偿选择信号OE向消隐输入电路120提供消隐输入信号，并在消隐输入电路120中存储消隐输入信号；以及在消隐期间，根据所存储的消隐输入信号和消隐控制信号CLA将消隐下拉信号V2提供给N个下拉节点(Q(1)～Q(N))，从而使得N个移位寄存电路(130_1～130_N)分别基于消隐下拉信号V2和相应的时钟信号输出各自的消隐输出信号。
在本公开的一些实施例中，该驱动方法还包括：在显示期间，根据显示输入信号STU将显示下拉信号V2输入到相应的下拉节点(Q(1)～Q(N))；以及根据下拉节点(Q(1)～Q(N))的电平和相应的时钟信号输出相应的显示输出信号。
图13示出根据本公开的实施例的栅极驱动电路1300的示意性框图。该栅极驱动电路1300包括K(K为大于1的自然数)个级联的如本公开的第一方面的移位寄存器(100和200)。因此，可以认为该栅极驱动电路1300包括K×N个移位寄存电路。K×N个移位寄存电路中的第一移位寄存电路的显示输入端被提供起始信号。所述第一移位寄存电路的显示复位端耦接第(i/2+2)移位寄存电路的移位信号输出端。所述第一移位寄存电路的第一时钟信号端被提供第一时钟信号。第二移位寄存电路的显示输入端被提供所述起始信号。所述第二移位寄存电路的显示复位端耦接第(i/2+3)移位寄存电路的移位信号输出端。所述第二移位寄存电路的第一时钟信号端被提供第二时钟信号。第n移位寄存电路的显示输入端耦接第(n-i/2)移位寄存电路的移位信号输出端。第n移位寄存电路的显示复位端耦接第(n+i/2+1)移位寄存电路的移位信号输出端。第n移位寄存电路的第一时钟信号端被提供第M时钟信号。
在显示期间，栅极驱动电路被提供第一至第i时钟信号。第一至第i时钟信号的时钟周期相同。各个时钟信号的时钟周期包括i个时长相等的阶段。并且第一至第i时钟信号依次相移1/i个时钟周期。在这里，i为偶数，n为大于2且小于或等于K×N的自然数。当n为i的整数倍时，M为i；否则，M为n模i。
在本实施例中，N和i例如为4。每级移位寄存器包括：补偿选择电路110、消隐输入电路120以及4个移位寄存电路(A1-A4)。每级移位寄存器的补偿选择控制端OE被提供相应的补偿选择控制信号OE，每级移位寄存器的消隐控制端CLA被提供相应的消隐控制信号CLA。K×4个移位寄存电路中的第一移位寄存电路A1的显示输入端STU耦接起始信号STU。第一移位寄存电路A1的显示复位端STD耦接第四移位寄存电路A4的移位信号输出端CR(4)。第一移位寄存电路A1的第一时钟信号端CLKD被提供第一时钟信号CLKD_1。第二移位寄存电路A2的显示输入端STU耦接起始信号STU。第二移位寄存电路A2的显示复位端STD耦接第五移位寄存电路(未示出)的移位信号输出端CR(5)。第二移位寄存电路A2的第一时钟信号端CLKD被提供第二时钟信号CLKD_2。第n移位寄存电路的显示输入端STU耦接第(n-2)移位寄存电路的移位信号输出端CR(n-2)。第n移位寄存电路的显示复位端STD耦接第(n+3)移位寄存电路的移位信号输出端CR(n+3)。第n移位寄存电路的第一时钟信号端CLKD被提供第M时钟信号CLKD_M。在这里，n为大于2且小于或等于2K的自然数。当n为i的整数倍时，M为i，否则，M为n模i。例如，当n＝4时，M＝4。当n＝5时，M＝1。在显示期间，第一至第四时钟信号的时钟周期相同。该时钟周期包括4个时长相等的阶段。并且第一至第四时钟信号依次相移1/4个时钟周期。
在本公开的一些实施例中，第n移位寄存电路的第二时钟信号端CLKE被提供第(i+M)时钟信号CLKE_M。在显示期间，第(i+1)至第2i时钟信号分别与第一至第i时钟信号的波形相同。
具体地，如图13所示，第一移位寄存电路A1的第二时钟信号端CLKE 被提供第五时钟信号CLKE_1。第二移位寄存电路A2的第二时钟信号端CLKE被提供第六时钟信号CLKE_2。第三移位寄存电路A3的第二时钟信号端CLKE被提供第七时钟信号CLKE_3。第四移位寄存电路A4的第二时钟信号端CLKE被提供第八时钟信号CLKE_4。
图14示出根据本公开的实施例的显示装置1300的示意性框图。该显示装置1300包括阵列基板1310。阵列基板1310包括上述栅极驱动电路1200。
本公开实施例提供的显示装置1300可以应用于任何具有显示功能的产品，例如，电子纸、移动电话、平板电脑、电视机、笔记本电脑、数码相框、可穿戴设备或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (23)

  1. 一种移位寄存器，包括：消隐输入电路、N个移位寄存电路和补偿选择电路，
    其中，所述消隐输入电路被配置为存储消隐输入信号，以及基于所述消隐输入信号和消隐控制信号将消隐下拉信号经由N个下拉节点提供给所述N个移位寄存电路；
    所述N个移位寄存电路耦接到所述消隐输入电路，并被配置为在消隐期间基于所述消隐下拉信号和相应的时钟信号输出各自的消隐输出信号；
    所述补偿选择电路被配置为在补偿选择控制信号的控制下向所述消隐输入电路提供所述消隐输入信号；
    其中，N为大于1的自然数。
  2. 根据权利要求1所述的移位寄存器，其中，所述N个移位寄存电路进一步被配置为在显示期间，基于显示输入信号和相应的时钟信号输出各自的显示输出信号，其中，所述显示输出信号中的一个显示输出信号被提供给所述补偿选择电路作为所述消隐输入信号。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述消隐输入电路包括存储子电路和隔离子电路，
    其中，所述存储子电路被配置为存储所述消隐输入信号；
    其中，所述隔离子电路被配置为基于所述消隐输入信号和所述消隐控制信号将所述消隐下拉信号提供给所述N个下拉节点。
  4. 根据权利要求3所述的移位寄存器，其中，所述隔离子电路包括第一晶体管和N个第二晶体管，
    其中，所述第一晶体管的控制极耦接所述存储子电路，所述第一晶体管的第一极耦接消隐下拉信号端，所述第一晶体管的第二极耦接所述N个第二晶体管的第一极；
    其中，所述N个第二晶体管的控制极耦接消隐控制端，所述N个第二晶体管的第二极耦接相应的下拉节点。
  5. 根据权利要求3所述的移位寄存器，其中，所述隔离子电路包括第 三晶体管、第四晶体管和N个第五晶体管，
    其中，所述第三晶体管的控制极耦接所述存储子电路，所述第三晶体管的第一极耦接所述消隐控制端，所述第三晶体管的第二极耦接所述第四晶体管的第二极和所述N个第五晶体管的控制极；
    其中，所述第四晶体管的控制极耦接第二消隐控制端，所述第四晶体管的第一极耦接第一电压端；
    其中，所述N个第五晶体管的第一极耦接消隐下拉信号端，所述N个第五晶体管的第二极耦接相应的下拉节点。
  6. 根据权利要求3所述的移位寄存器，其中，所述隔离子电路包括第六晶体管、两个第七晶体管和N个第八晶体管，
    其中，所述第六晶体管的控制极耦接所述存储子电路，所述第六晶体管的第一极耦接消隐控制端，所述第六晶体管的第二极耦接所述两个第七晶体管的第二极和所述N个第八晶体管的控制极；
    其中，所述两个第七晶体管的控制极分别耦接第三消隐控制端和第四消隐控制端，所述两个第七晶体管的第一极耦接第一电压端；
    其中，所述N个第八晶体管的第一极耦接消隐下拉信号端，所述N个第八晶体管的第二极耦接相应的下拉节点。
  7. 根据权利要求3-6中任一项所述的移位寄存器，其中，所述存储子电路包括第一电容器，其中，所述第一电容器的第一端耦接所述补偿选择电路和所述隔离子电路，所述第一电容器的第二端耦接第一电压端。
  8. 根据权利要求1-7中任一项所述的移位寄存器，其中，所述补偿选择电路包括第九晶体管，
    其中，所述第九晶体管的控制极耦接补偿选择控制端，所述第九晶体管的第一极耦接消隐输入信号端，所述第九晶体管的第二极耦接所述隔离子电路。
  9. 根据权利要求1-8中任一项所述的移位寄存器，其中，所述移位寄存电路包括：显示输入电路、显示复位电路、消隐复位电路、上拉电路、输出上拉电路和输出电路，
    其中，所述显示输入电路被配置为基于显示输入信号将显示下拉信号提供给所述下拉节点；
    所述显示复位电路被配置为基于显示复位信号对所述下拉节点进行复位；
    所述消隐复位电路被配置为基于消隐复位信号对所述下拉节点进行复位；
    所述上拉电路被配置为在对所述下拉节点进行复位之后维持所述下拉节点的电平，并交替下拉第一上拉节点和第二上拉节点；
    所述输出上拉电路被配置为基于所述第一上拉节点和所述第二上拉节点的电平来上拉所述移位寄存器的消隐输出信号和显示输出信号；
    所述输出电路被配置为在消隐期间基于所述消隐下拉信号和相应的时钟信号输出所述消隐输出信号，以及在显示期间基于所述显示下拉信号和相应的时钟信号输出所述显示输出信号。
  10. 根据权利要求9所述的移位寄存器，其中，所述显示复位电路包括第十一晶体管，其中，所述第十一晶体管的控制极耦接显示复位端，所述第十一晶体管的第一极耦接第一电压端，所述第十一晶体管的第二极耦接所述下拉节点。
  11. 根据权利要求9或10所述的移位寄存器，其中，所述消隐复位电路包括第十二晶体管，其中，所述第十二晶体管的控制极耦接消隐复位端，所述第十二晶体管的第一极耦接第一电压端，所述第十二晶体管的第二极耦接所述下拉节点。
  12. 根据权利要求9-11中任一项所述的移位寄存器，其中，所述上拉电路包括第十三至二十四晶体管，其中，第十三晶体管的控制极和第一极耦接第一控制端，所述第十三晶体管的第二极耦接第一上拉节点；其中，第十四晶体管的控制极耦接所述下拉节点，所述第十四晶体管的第一极耦接第一电压端，所述第十四晶体管的第二极耦接所述第一上拉节点；其中，第十五晶体管的控制极耦接所述第一上拉节点，所述第十五晶体管的第一极耦接所述第一电压端，所述第十五晶体管的第二极耦接所述下拉节点； 其中，第十六晶体管的控制极耦接消隐控制端，所述第十六晶体管的第一极耦接所述第十七晶体管的第二极，所述第十六晶体管的第二极耦接所述第一上拉节点；其中，第十七晶体管的控制极耦接下拉控制节点，所述第十七晶体管的第一极耦接所述第一电压端；其中，第十八晶体管的控制极耦接显示输入端，所述第十八晶体管的第一极耦接所述第一电压端，所述第十八晶体管的第二极耦接所述第一上拉节点；其中，第十九晶体管的控制极和第一极耦接第二控制端，所述第十九晶体管的第二极耦接第二上拉节点；其中，第二十晶体管的控制极耦接所述下拉节点，所述第二十晶体管的第一极耦接所述第一电压端，所述第二十晶体管的第二极耦接所述第二上拉节点；其中，第二十一晶体管的控制极耦接所述第二上拉节点，所述第二十一晶体管的第一极耦接所述第一电压端，所述第二十一晶体管的第二极耦接所述下拉节点；其中，第二十二晶体管的控制极耦接所述消隐控制端，所述第二十二晶体管的第一极耦接所述第二十三晶体管的第二极，所述第二十二晶体管的第二极耦接所述第二上拉节点；其中，第二十三晶体管的控制极耦接所述下拉控制节点，所述第二十三晶体管的第一极耦接所述第一电压端；其中，第二十四晶体管的控制极耦接所述显示输入端，所述第二十四晶体管的第一极耦接所述第一电压端，所述第二十四晶体管的第二极耦接所述第二上拉节点；或者
    所述上拉电路包括第十三至十六晶体管、第十八至第二十二晶体管和第二十四晶体管，其中，第十三晶体管的控制极和第一极耦接第一控制端，所述第十三晶体管的第二极耦接第一上拉节点；其中，第十四晶体管的控制极耦接所述下拉节点，所述第十四晶体管的第一极耦接所述第一电压端，所述第十四晶体管的第二极耦接所述第一上拉节点；其中，第十五晶体管的控制极耦接所述第一上拉节点，所述第十五晶体管的第一极耦接所述第一电压端，所述第十五晶体管的第二极耦接所述下拉节点；其中，第十六晶体管的控制极耦接所述消隐控制端，所述第十六晶体管的第一极耦接所述第一电压端，所述第十六晶体管的第二极耦接所述第一上拉节点；其中，第十八晶体管的控制极耦接所述显示输入端，所述第十八晶体管的第一极 耦接所述第一电压端，所述第十八晶体管的第二极耦接所述第一上拉节点；其中，第十九晶体管的控制极和第一极耦接第二控制端，所述第十九晶体管的第二极耦接第二上拉节点；其中，第二十晶体管的控制极耦接所述下拉节点，所述第二十晶体管的第一极耦接所述第一电压端，所述第二十晶体管的第二极耦接所述第二上拉节点；其中，第二十一晶体管的控制极耦接所述第二上拉节点，所述第二十一晶体管的第一极耦接所述第一电压端，所述第二十一晶体管的第二极耦接所述下拉节点；其中，第二十二晶体管的控制极耦接所述消隐控制端，所述第二十二晶体管的第一极耦接所述第一电压端，所述第二十二晶体管的第二极耦接所述第二上拉节点；其中，第二十四晶体管的控制极耦接所述显示输入端，所述第二十四晶体管的第一极耦接所述第一电压端，所述第二十四晶体管的第二极耦接所述第二上拉节点；或者
    所述上拉电路包括第十三至十五晶体管、第十八至第二十一晶体管和第二十四晶体管，其中，第十三晶体管的控制极和第一极耦接第一控制端，所述第十三晶体管的第二极耦接第一上拉节点；其中，第十四晶体管的控制极耦接所述下拉节点，所述第十四晶体管的第一极耦接所述第一电压端，所述第十四晶体管的第二极耦接所述第一上拉节点；其中，第十五晶体管的控制极耦接所述第一上拉节点，所述第十五晶体管的第一极耦接所述第一电压端，所述第十五晶体管的第二极耦接所述下拉节点；其中，第十八晶体管的控制极耦接所述显示输入端，所述第十八晶体管的第一极耦接所述第一电压端，所述第十八晶体管的第二极耦接所述第一上拉节点；其中，第十九晶体管的控制极和第一极耦接第二控制端，所述第十九晶体管的第二极耦接第二上拉节点；其中，第二十晶体管的控制极耦接所述下拉节点，所述第二十晶体管的第一极耦接所述第一电压端，所述第二十晶体管的第二极耦接所述第二上拉节点；其中，第二十一晶体管的控制极耦接所述第二上拉节点，所述第二十一晶体管的第一极耦接所述第一电压端，所述第二十一晶体管的第二极耦接所述下拉节点；其中，第二十四晶体管的控制极耦接所述显示输入端，所述第二十四晶体管的第一极耦接所述第一电压 端，所述第二十四晶体管的第二极耦接所述第二上拉节点。
  13. 根据权利要求9-12中任一项所述的移位寄存器，其中，所述输出上拉电路包括第二十五至二十八晶体管，其中，第二十五晶体管的控制极耦接所述第一上拉节点，所述第二十五晶体管的第一极耦接第一电压端，所述第二十五晶体管的第二极耦接移位信号输出端；其中，第二十六晶体管的控制极耦接所述第一上拉节点，所述第二十六晶体管的第一极耦接所述第一电压端，所述第二十六晶体管的第二极耦接第一像素信号输出端；其中，第二十七晶体管的控制极耦接所述第二上拉节点，所述第二十七晶体管的第一极耦接所述第一电压端，所述第二十七晶体管的第二极耦接所述移位信号输出端；其中，第二十八晶体管的控制极耦接所述第二上拉节点，所述第二十八晶体管的第一极耦接所述第一电压端，所述第二十八晶体管的第二极耦接所述第一像素信号输出端；
    其中，所述输出电路包括第二十九晶体管、第三十晶体管和第二电容器，其中，第二十九晶体管的控制极耦接所述下拉节点，所述第二十九晶体管的第一极耦接第一时钟信号端，所述第二十九晶体管的第二极耦接所述移位信号输出端；其中，第三十晶体管的控制极耦接所述下拉节点，所述第三十晶体管的第一极耦接所述第一时钟信号端，所述第三十晶体管的第二极耦接所述第一像素信号输出端。
  14. 根据权利要求13所述的移位寄存器，其中，所述输出上拉电路还包括第三十一晶体管和第三十二晶体管，其中，第三十一晶体管的控制极耦接所述第一上拉节点，所述第三十一晶体管的第一极耦接所述第一电压端，所述第三十一晶体管的第二极耦接第二像素信号输出端；其中，第三十二晶体管的控制极耦接所述第二上拉节点，所述第三十二晶体管的第一极耦接所述第一电压端，所述第三十二晶体管的第二极耦接所述第二像素信号输出端；
    所述输出电路还包括第三十三晶体管和第三电容器，其中，第三十三晶体管的控制极耦接所述下拉节点，所述第三十三晶体管的第一极耦接第二时钟信号端，所述第三十三晶体管的第二极耦接所述第二像素信号输出 端；其中，所述第三电容器的第一端耦接所述下拉节点，所述第三电容器的第二端耦接所述第二像素信号输出端。
  15. 根据权利要求9-14中任一项所述的移位寄存器，其中，所述显示输入电路包括第十晶体管，其中，所述第十晶体管的控制极耦接显示输入端，所述第十晶体管的第一极耦接显示下拉信号端，所述第十晶体管的第二极耦接所述下拉节点；或者
    所述显示输入电路包括第三十四晶体管和第三十五晶体管；其中，所述第三十四晶体管的控制极和第一极耦接所述显示输入端，所述第三十四晶体管的第二极耦接所述第三十五晶体管的第一极，所述第三十五晶体管的控制极耦接所述显示输入端，所述第三十五晶体管的第二极耦接所述下拉节点；或者
    所述显示输入电路包括第三十六晶体管和第三十七晶体管；其中，所述第三十六晶体管的控制极耦接所述显示输入端，所述第三十六晶体管的第一极耦接所述显示下拉信号端，所述第三十六晶体管的第二极耦接所述第三十七晶体管的控制极和第一极，所述第三十七晶体管的第二极耦接所述下拉节点；或者
    所述显示输入电路包括第三十八晶体管；其中，所述第三十八晶体管的控制极和第一极耦接所述显示输入端，所述第三十八晶体管的第二极耦接所述下拉节点。
  16. 一种栅极驱动电路，包括K个级联的如权利要求1-15中任一项所述的移位寄存器，
    其中，每级移位寄存器的补偿选择控制端被提供相应的补偿选择控制信号，每级移位寄存器的消隐控制端被提供相应的消隐控制信号，
    其中，K×N个移位寄存电路中的第一移位寄存电路的显示输入端被提供起始信号，所述第一移位寄存电路的显示复位端耦接第(i/2+2)移位寄存电路的移位信号输出端，所述第一移位寄存电路的第一时钟信号端被提供第一时钟信号；
    第二移位寄存电路的显示输入端被提供所述起始信号，所述第二移位 寄存电路的显示复位端耦接第(i/2+3)移位寄存电路的移位信号输出端，所述第二移位寄存电路的第一时钟信号端被提供第二时钟信号；
    第n移位寄存电路的显示输入端耦接第(n-i/2)移位寄存电路的移位信号输出端，第n移位寄存电路的显示复位端耦接第(n+i/2+1)移位寄存电路的移位信号输出端，第n移位寄存电路的第一时钟信号端被提供第M时钟信号；
    其中，在显示期间，所述栅极驱动电路被提供第一至第i时钟信号；第一至第i时钟信号的时钟周期相同，所述时钟周期包括i个时长相等的阶段，并且第一至第i时钟信号依次相移1/i个时钟周期，i为偶数；K为大于1的自然数，n为大于2且小于或等于K×N的自然数，当n为i的整数倍时，M为i，否则，M为n模i。
  17. 根据权利要求16所述的栅极驱动电路，其中，N为4。
  18. 根据权利要求16或17所述的栅极驱动电路，其中，i为4。
  19. 根据权利要求16-18中任一项所述的栅极驱动电路，其中，第n移位寄存电路的第二时钟信号端被提供第(i+M)时钟信号；
    其中，在显示期间，第(i+1)至第2i时钟信号分别与第一至第i时钟信号的波形相同。
  20. 一种用于驱动根据权利要求1-15中任一项所述的移位寄存器的驱动方法，包括：
    在显示期间，根据所述补偿选择信号向所述消隐输入电路提供所述消隐输入信号，并在所述消隐输入电路中存储所述消隐输入信号；以及
    在消隐期间，根据所存储的消隐输入信号和消隐控制信号将消隐下拉信号提供给所述N个下拉节点，从而使得所述N个移位寄存电路分别基于所述消隐下拉信号和相应的时钟信号输出各自的消隐输出信号。
  21. 根据权利要求20所述的驱动方法，还包括：在显示期间，
    根据显示输入信号将显示下拉信号输入到相应的下拉节点；以及
    根据所述下拉节点的电平和相应的时钟信号输出相应的显示输出信号。
  22. 一种阵列基板，包括根据权利要求16-19中的任一项所述的栅极驱动电路。
  23. 一种显示装置，包括根据权利要求22所述的阵列基板。
PCT/CN2018/121813 2018-12-18 2018-12-18 移位寄存器及其驱动方法、栅极驱动电路以及显示装置 WO2020124376A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2020560483A JP7258044B2 (ja) 2018-12-18 2018-12-18 シフトレジスタ及びその駆動方法、ゲート駆動回路並びに表示装置
EP18932318.1A EP3940684A4 (en) 2018-12-18 2018-12-18 SHIFT REGISTER AND DRIVE METHOD THEREOF, GATE DRIVER CIRCUIT AND DISPLAY DEVICE
CN201880002510.9A CN111788624B (zh) 2018-12-18 2018-12-18 移位寄存器及其驱动方法、栅极驱动电路以及显示装置
US16/643,966 US11328651B2 (en) 2018-12-18 2018-12-18 Shift register for compensation for sub-pixle row, driving method thereof, gate driving circuit and display device
PCT/CN2018/121813 WO2020124376A1 (zh) 2018-12-18 2018-12-18 移位寄存器及其驱动方法、栅极驱动电路以及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/121813 WO2020124376A1 (zh) 2018-12-18 2018-12-18 移位寄存器及其驱动方法、栅极驱动电路以及显示装置

Publications (1)

Publication Number Publication Date
WO2020124376A1 true WO2020124376A1 (zh) 2020-06-25

Family

ID=71101033

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/121813 WO2020124376A1 (zh) 2018-12-18 2018-12-18 移位寄存器及其驱动方法、栅极驱动电路以及显示装置

Country Status (5)

Country Link
US (1) US11328651B2 (zh)
EP (1) EP3940684A4 (zh)
JP (1) JP7258044B2 (zh)
CN (1) CN111788624B (zh)
WO (1) WO2020124376A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202771776U (zh) * 2012-09-17 2013-03-06 深圳市九洲光电科技有限公司 具有消隐功能的led显示屏控制电路
US20140320386A1 (en) * 2013-04-26 2014-10-30 Chunghwa Picture Tubes, Ltd. Display panel
CN108682397A (zh) * 2018-07-27 2018-10-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
CN108806611A (zh) * 2018-06-28 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5528084B2 (ja) * 2009-12-11 2014-06-25 三菱電機株式会社 シフトレジスタ回路
KR102338948B1 (ko) * 2017-05-22 2021-12-14 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 포함한 유기발광 표시장치
CN109935199B (zh) * 2018-07-18 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109935185B (zh) * 2018-07-18 2022-07-01 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108877716B (zh) * 2018-07-20 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN108711401B (zh) * 2018-08-10 2021-08-03 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202771776U (zh) * 2012-09-17 2013-03-06 深圳市九洲光电科技有限公司 具有消隐功能的led显示屏控制电路
US20140320386A1 (en) * 2013-04-26 2014-10-30 Chunghwa Picture Tubes, Ltd. Display panel
CN108806611A (zh) * 2018-06-28 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108682397A (zh) * 2018-07-27 2018-10-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3940684A4 *

Also Published As

Publication number Publication date
EP3940684A4 (en) 2022-08-03
EP3940684A1 (en) 2022-01-19
US20210225255A1 (en) 2021-07-22
US20220084455A9 (en) 2022-03-17
JP2022522549A (ja) 2022-04-20
CN111788624B (zh) 2022-11-11
JP7258044B2 (ja) 2023-04-14
CN111788624A (zh) 2020-10-16
US11328651B2 (en) 2022-05-10

Similar Documents

Publication Publication Date Title
CN109166527B (zh) 显示面板、显示装置及驱动方法
CN111261116B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2016127589A1 (zh) 栅极驱动电路及其驱动方法、阵列基板、显示装置
WO2017211094A1 (zh) 一种移位寄存器、栅极驱动电路及显示装置
CN107909959B (zh) 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
US20220036790A1 (en) Scanning circuit, display panel and display device
WO2020177029A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
WO2020253837A1 (zh) 移位寄存器单元及其驱动方法以及栅极驱动电路
WO2020253789A1 (zh) 移位寄存器单元及其驱动方法以及栅极驱动电路
CN110858469B (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN113345379B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
WO2018126691A1 (zh) 移位寄存器单元及其驱动方法、移位寄存器以及显示装置
WO2020142923A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN112639947B (zh) 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN113781967B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN113362772A (zh) 显示基板、显示面板和显示装置
WO2019080619A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2020140195A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2019227950A1 (zh) 或逻辑运算电路及驱动方法、移位寄存器单元、栅极驱动电路和显示装置
WO2020259379A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置和控制方法
WO2020124376A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路以及显示装置
WO2021000272A1 (zh) 移位寄存器单元、其驱动方法及装置
CN112133355B (zh) 移位寄存器单元、栅极驱动电路、显示装置和控制方法
CN113314076B (zh) 移位寄存器单元、栅极驱动电路及其控制方法
EP4131228A1 (en) Gate drive circuit, driving method therefor, and display panel

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18932318

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020560483

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018932318

Country of ref document: EP

Effective date: 20210719