WO2020119123A1 - 一种存储装置以及电子设备 - Google Patents

一种存储装置以及电子设备 Download PDF

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Publication number
WO2020119123A1
WO2020119123A1 PCT/CN2019/096430 CN2019096430W WO2020119123A1 WO 2020119123 A1 WO2020119123 A1 WO 2020119123A1 CN 2019096430 W CN2019096430 W CN 2019096430W WO 2020119123 A1 WO2020119123 A1 WO 2020119123A1
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Prior art keywords
voltage
coupled
storage device
control chip
chip
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PCT/CN2019/096430
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English (en)
French (fr)
Inventor
胡宏辉
梁广庆
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to JP2021526601A priority Critical patent/JP7207812B2/ja
Priority to EP19896011.4A priority patent/EP3869298A4/en
Priority to KR1020217017885A priority patent/KR102645504B1/ko
Priority to US17/413,209 priority patent/US11699061B2/en
Publication of WO2020119123A1 publication Critical patent/WO2020119123A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/08—Three-wire systems; Systems having more than three wires
    • H02J1/082—Plural DC voltage, e.g. DC supply voltage with at least two different DC voltage levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of storage technology, in particular to a storage device and electronic equipment.
  • Memory cards generally include SD series, MMC series, and PCIe series. Some of these memory cards require two external power supplies (different voltages) to be driven to work, and a dedicated card slot needs to be configured to cooperate with it. It is difficult to be compatible with other memory card slots.
  • the present application provides a storage device and electronic equipment, which only needs to provide an external power source to work, which improves compatibility.
  • a technical solution adopted by the present application is to provide a storage device including: a control chip; a storage chip; a power interface configured to receive an external first voltage; a first transformer circuit whose input terminal is coupled The power interface, the output of which is coupled to the control chip, is configured to convert the first voltage to a second voltage and provide the second voltage to the control chip; the input terminal of the second transformer circuit is coupled to the power interface, and its output The terminal is coupled to the control chip and the memory chip, and is configured to convert the first voltage to a third voltage and provide the third voltage to the control chip and the memory chip.
  • the control chip includes a first power pin, coupled to the output end of the first transformer circuit, to provide a second voltage to the core of the control chip.
  • the first voltage is 3.3V
  • the third voltage is 1.8V.
  • the storage device is a storage device based on the EMMC protocol;
  • the control chip includes: an EMMC IO pin, which is coupled to the output end of the second transformer circuit; a first Flash IO pin, which is respectively coupled to the second transformer circuit through a selection circuit The output terminal and the power supply interface to select the input of the first voltage or the third voltage according to needs;
  • the memory chip includes: a second Flash IO pin, respectively coupled to the output terminal of the second transformer circuit and the power supply interface through the selection circuit, to Choose to input the first voltage or the third voltage as needed.
  • the first input terminal of the selection circuit is coupled to the output terminal of the second transformer circuit, the second input terminal is coupled to the power interface, and the output terminal is coupled to the first Flash IO pin and the second Flash IO pin.
  • the first voltage is 3.3V; the memory chip further includes a second power pin, coupled to the power interface, to provide the first voltage to the core of the memory chip.
  • the storage device further includes: a substrate, including first and second opposite sides; wherein, the storage chip is disposed on the first side, and the control chip is disposed on the side of the storage chip away from the substrate; Two sides; wherein, the power interface is one of a plurality of contacts.
  • Another technical solution adopted by the present application is to provide an electronic device including: a power supply; a processor coupled to the power supply; a storage device coupled to the processor, and the storage device is the storage device as described above.
  • the storage device includes: a control chip; a storage chip; a power interface configured to receive an external first voltage; a first transformer circuit whose input terminal is coupled to the power interface and its output terminal coupled to the control chip It is configured to convert the first voltage to a second voltage and provide the second voltage to the control chip; the second transformer circuit, whose input terminal is coupled to the power interface, and whose output terminal is coupled to the control chip and the memory chip, is configured as The first voltage is converted into a third voltage, and the third voltage is provided to the control chip and the memory chip.
  • three different voltages are provided to the control chip and the memory chip through the two transformer circuits, so that the storage device can be applied to more scenarios and improve compatibility.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a storage device provided by this application.
  • FIG. 2 is a schematic diagram of a circuit structure of a first embodiment of a storage device provided by this application;
  • FIG. 3 is a schematic diagram of a circuit structure of a second embodiment of a storage device provided by this application.
  • FIG. 5 is a schematic structural diagram of a card tray in an embodiment of an electronic device provided by this application.
  • a passive element 15 may also be provided on the substrate 11, wherein the passive element 15 may include common circuit components such as resistors, capacitors, and inductors.
  • control chip 12, the memory chip 13 and the passive element 15 are covered with an encapsulation layer 16.
  • the control chip 12 and the memory chip 13 are unpackaged die.
  • the memory chip 13 is a Nand Flash chip, the number of which can be set according to actual needs, and stacked on the substrate 11 in layers s surface. For example, if the storage capacity of one Flash is 64GB, if two Flashes are stacked, the storage capacity of the entire storage device 10 is 128G, and if four Flashs are stacked, the storage capacity of the entire storage device 10 is 256GB.
  • control chip 12 and the memory chip 13 may also be already packaged chips.
  • control chip 12, the memory chip 13 and the passive element 15 are disposed on one side of the substrate 11, and the interface contact 14 is disposed on the opposite side of the substrate 11.
  • control chip 12 may also be disposed on the memory chip 13 and stacked.
  • FIG. 2 is a schematic diagram of a circuit structure of a first embodiment of a storage device provided by the present application.
  • the storage device 10 further includes a power interface 17, a first transformer circuit 18, and a second transformer circuit 19.
  • the power interface 17 is configured to receive an external first voltage V1; the input terminal of the first transformer circuit 18 is coupled to the power interface 17, and the output terminal thereof is coupled to the control chip 12, configured to convert the first voltage V1 to The second voltage V2, and the second voltage is provided to the control chip 12; the input terminal of the second transformer circuit 19 is coupled to the power interface 17, the output terminal is coupled to the control chip 12 and the memory chip 13, is configured to the first The voltage V1 is converted into a third voltage V3, and the third voltage V3 is supplied to the control chip 12 and the memory chip 13.
  • the first voltage V1 can be converted into the second voltage V2 and the third voltage V3 by two transformer circuits, respectively, plus the first voltage V1 provided by itself, so that the control chip 12 and the memory chip 13 can be provided.
  • Three different voltages of the first voltage V1, the second voltage V2 and the third voltage V3 are provided to drive the two chips to work.
  • the first transformer circuit 18 and the second transformer circuit 19 may be disposed on the substrate 11 or may be integrated inside the control chip 12.
  • the storage device includes: a control chip; a storage chip; a power interface configured to receive an external first voltage; a first transformer circuit whose input terminal is coupled to the power interface and its output terminal coupled to the control chip It is configured to convert the first voltage to a second voltage and provide the second voltage to the control chip; the second transformer circuit, whose input terminal is coupled to the power interface, and whose output terminal is coupled to the control chip and the memory chip, is configured as The first voltage is converted into a third voltage, and the third voltage is provided to the control chip and the memory chip.
  • three different voltages are provided to the control chip and the memory chip through the two transformer circuits, so that the storage device can be applied to more scenarios and improve compatibility.
  • CM multimedia memory card
  • the NM card includes eight contacts, and the eight sub-contacts are respectively represented by 1-8 numbers.
  • the eight sub-contacts are arranged with the long side and the short side of the NM card in columns and rows in 4 rows and 2 columns.
  • the interface contact piece includes a first sub-contact piece, a second sub-contact piece, a third sub-contact piece, a fourth sub-contact piece that are sequentially arranged in the first column, and a fifth sub-contact piece that is sequentially arranged in the reverse order of the second column ,
  • the sixth sub-contact, the seventh sub-contact, the eighth sub-contact is sequentially arranged in the reverse order of the second column.
  • sub-contacts are insulated from each other.
  • the interface contact 14 is used to establish an electrical connection between the storage device 10 and an external device.
  • the external interface uses the eMMC protocol.
  • the interface contact 14 includes a 3.3V power contact (VCC), Ground contact (GND), clock contact (CLK), command contact (CMD) and 4 data contacts (D0-D3).
  • VCC 3.3V power contact
  • GND Ground contact
  • CLK clock contact
  • CMD command contact
  • D0-D3 4 data contacts
  • Sub contact number definition Sub contact number definition 1 D1 5 D2 2 CMD 6 VCC 3 GND 7 D0 4 D3 8 CLK
  • the VCC pin is used to receive the externally provided first voltage, which is equivalent to the power interface in the above embodiment.
  • the power interface 17 is configured to receive an external first voltage V1; the input terminal of the first transformer circuit 18 is coupled to the power interface 17, and the output terminal thereof is coupled to the control chip 12, configured to convert the first voltage V1 to The second voltage V2, and the second voltage is provided to the control chip 12; the input terminal of the second transformer circuit 19 is coupled to the power interface 17, the output terminal is coupled to the control chip 12 and the memory chip 13, is configured to the first The voltage V1 is converted into a third voltage V3, and the third voltage V3 is supplied to the control chip 12 and the memory chip 13.
  • the first voltage is 3.3V
  • the second voltage is 1.2V
  • the third voltage is 1.8V.
  • the operating voltage of the core of the control chip 12 is 1.2V.
  • the control chip 12 includes a first power pin (not shown), which is coupled to the output terminal of the first transformer circuit 18 to control the control chip The core of 12 provides the second voltage V2.
  • control chip 12 also includes an EMMC IO pin (unlabeled) and a first Flash IO pin (unlabeled), and the memory chip 13 includes a second Flash IO pin (unlabeled).
  • first Flash IO pin and the second Flash IO pin are coupled, and are used for transmitting instructions or data between the control chip 12 and the memory chip 13.
  • the EMMC IO pin is coupled to the output terminal of the second transformer circuit 19; the first Flash IO pin is respectively coupled to the output terminal of the second transformer circuit 19 and the power interface 17 through the selection circuit 20 to select according to needs Input the first voltage V1 or the third voltage V3; the second Flash IO pin is respectively coupled to the output terminal of the second transformer circuit 19 and the power interface 17 through the selection circuit 20 to select the first voltage V1 or the third voltage input as required Voltage V3.
  • the first input terminal of the selection circuit 20 is coupled to the output terminal of the second transformer circuit 19, the second input terminal is coupled to the power interface 17, and the output terminal is coupled to the first Flash IO pin and the second Flash IO lead foot.
  • the working voltage of the core of the memory chip 13 is 3.3V.
  • the memory chip 13 further includes a second power pin (not shown), which is coupled to the power interface 17 to connect the memory chip 13 The core of provides a first voltage V1.
  • the storage device 10 provided in this embodiment only has a 3.3V power supply interface and supports only 3.3V power input, then by adding the first transformer circuit 18 and the second transformer circuit 19, the input 3.3V power supply is used Converted to 1.8V and 1.2V power output, and provides 1.8V and 1.2V power input to the main control chip 12 and/or memory chip 13.
  • FIG. 4 is a schematic structural diagram of an embodiment of an electronic device provided by the present application.
  • the electronic device includes a device body 41 and a card holder 42 that can be embedded in the device body 41. It also includes a processor 43 and a power supply 44.
  • the processor 43 is coupled to the power supply 44 and the card slot, respectively.
  • the memory card in the card tray can be further coupled to the processor 43 through the card slot.
  • FIG. 5 is a schematic structural diagram of a card tray in an embodiment of an electronic device provided by the present application.
  • the card tray 42 includes a SIM card slot 42a and a memory card slot 42b, and a SIM card slot 42a and a memory card slot
  • the shape of 42b is the same, wherein the memory card slot 42b is used to accommodate the storage device provided in the above embodiment.

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种存储装置（10）以及电子设备，该存储装置（10）包括：控制芯片（12）；存储芯片（13）；电源接口（17），被配置为接收外部的第一电压；第一变压电路（18），其输入端耦接电源接口（17），其输出端耦接控制芯片（12），被配置为将第一电压转换为第二电压，并将第二电压提供给控制芯片（12）；第二变压电路（19），其输入端耦接电源接口（17），其输出端耦接控制芯片（12）和存储芯片（13），被配置为将第一电压转换为第三电压，并将第三电压提供给控制芯片（12）和存储芯片（13）。通过上述方式只需要外部提供一路电源就可以进行工作，提高了兼容性。

Description

一种存储装置以及电子设备 【技术领域】
本申请涉及存储技术领域，特别是涉及一种存储装置以及电子设备。
【背景技术】
存储卡，是用于手机、数码相机、便携式电脑、MP3和其他数码产品上的独立存储介质，一般是卡片的形态，故统称为“存储卡”，又称为“数码存储卡”、“数字存储卡”、“储存卡”等。
存储卡一般包括SD系列、MMC系列、PCIe系列。其中的一些存储卡需要外部提供两路电源(不同电压)进行驱动才能工作，需配置专用的卡槽与其配合，在与其他存储卡槽兼容时比较难。
【发明内容】
为了解决上述问题，本申请提供了一种存储装置以及电子设备，只需要外部提供一路电源就可以进行工作，提高了兼容性。
本申请采用的一个技术方案是：提供一种存储装置，该存储装置包括：控制芯片；存储芯片；电源接口，被配置为接收外部的第一电压；第一变压电路，其输入端耦接电源接口，其输出端耦接控制芯片，被配置为将第一电压转换为第二电压，并将第二电压提供给控制芯片；第二变压电路，其输入端耦接电源接口，其输出端耦接控制芯片和存储芯片，被配置为将第一电压转换为第三电压，并将第三电压提供给控制芯片和存储芯片。
其中，第一电压为3.3V，第二电压为1.2V。
其中，控制芯片包括第一电源引脚，耦接第一变压电路的输出端，以对控制芯片的内核提供第二电压。
其中，第一电压为3.3V，第三电压为1.8V。
其中，存储装置为基于EMMC协议的存储装置；控制芯片包括：EMMC IO引脚，耦接第二变压电路的输出端；第一Flash IO引脚，通 过选择电路分别耦接第二变压电路的输出端和电源接口，以根据需要选择输入第一电压或第三电压；存储芯片包括：第二Flash IO引脚，通过选择电路分别耦接第二变压电路的输出端和电源接口，以根据需要选择输入第一电压或第三电压。
其中，选择电路的第一输入端耦接第二变压电路的输出端，其第二输入端耦接电源接口，其输出端耦接第一Flash IO引脚和第二Flash IO引脚。
其中，第一电压为3.3V；存储芯片还包括第二电源引脚，耦接电源接口，以对存储芯片的内核提供第一电压。
其中，第一变压电路和/或第二变压电路集成于控制芯片内。
其中，存储装置还包括：基板，包括相对的第一侧面和第二侧面；其中，存储芯片设置于第一侧面，控制芯片设置于存储芯片远离基板的一侧；多个触片，设置于第二侧面；其中，电源接口为多个触片中的一个。
本申请采用的另一个技术方案是：提供一种电子设备，该电子设备包括：电源；处理器，耦接电源；存储装置，耦接处理器，存储装置是如上述的存储装置。
本申请提供的存储装置包括：控制芯片；存储芯片；电源接口，被配置为接收外部的第一电压；第一变压电路，其输入端耦接电源接口，其输出端耦接控制芯片，被配置为将第一电压转换为第二电压，并将第二电压提供给控制芯片；第二变压电路，其输入端耦接电源接口，其输出端耦接控制芯片和存储芯片，被配置为将第一电压转换为第三电压，并将第三电压提供给控制芯片和存储芯片。通过上述方式，能够在外部只提供一路电压的情况下，通过两个变压电路向控制芯片和存储芯片提供三种不同的电压，进一步能够存储装置应用于更多的场景，提高了兼容性。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描 述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请提供的存储装置第一实施例的结构示意图；
图2是本申请提供的存储装置第一实施例的电路结构示意图；
图3是本申请提供的存储装置第二实施例的电路结构示意图；
图4是本申请提供的电子设备一实施例的结构示意图；
图5是本申请提供的电子设备一实施例中卡托的结构示意图。
【具体实施方式】
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
参阅图1，图1是本申请提供的存储装置第一实施例的结构示意图，该存储装置10包括基板11以及设置于基板11上的控制芯片12、存储芯片13、接口触片14。
可选的，基板11上还可以设置被动元件15，其中，被动元件15可以包括电阻、电容、电感等常用的电路元器件。
在本实施例中，控制芯片12、存储芯片13以及被动元件15上覆盖有封装层16。在本实施例中，控制芯片12、存储芯片13是未经封装的裸芯片(die)，一般，存储芯片13为Nand Flash芯片，数量可以根据实际的需求来设置，分层次叠放在基板11的表面。例如，一个Flash的存储容量为64GB，那么，若叠放两个Flash，整个存储装置10的存储容量为128G，若叠放四个Flash，整个存储装置10的存储容量为256GB。
另外，在其他实施例中，控制芯片12、存储芯片13也可以是已经封装好的芯片。
在一可选的实施例中，控制芯片12、存储芯片13以及被动元件15 设置在基板11的一侧面上，而接口触片14设置于基板11上相对的另一侧面上。
另外，在其他实施例中，考虑到存储芯片13的面积比较大，也可以将控制芯片12设置在存储芯片13上，进行叠置。
结合图2，图2是本申请提供的存储装置第一实施例的电路结构示意图，该存储装置10还包括电源接口17、第一变压电路18和第二变压电路19。
其中，电源接口17被配置为接收外部的第一电压V1；第一变压电路18的输入端耦接电源接口17，其输出端耦接控制芯片12，被配置为将第一电压V1转换为第二电压V2，并将第二电压提供给控制芯片12；第二变压电路19的输入端耦接电源接口17，其输出端耦接控制芯片12和存储芯片13，被配置为将第一电压V1转换为第三电压V3，并将第三电压V3提供给控制芯片12和存储芯片13。
通过上述的方式可以通过两个变压电路分别将第一电压V1转化为第二电压V2和第三电压V3，加上本身提供的第一电压V1，这样就可以给控制芯片12和存储芯片13提供第一电压V1、第二电压V2和第三电压V3三种不同的电压，以驱动两个芯片的工作。
在上述的实施例中，第一变压电路18和第二变压电路19可以设置在基板11上，也可以集成于控制芯片12内部。
本申请提供的存储装置包括：控制芯片；存储芯片；电源接口，被配置为接收外部的第一电压；第一变压电路，其输入端耦接电源接口，其输出端耦接控制芯片，被配置为将第一电压转换为第二电压，并将第二电压提供给控制芯片；第二变压电路，其输入端耦接电源接口，其输出端耦接控制芯片和存储芯片，被配置为将第一电压转换为第三电压，并将第三电压提供给控制芯片和存储芯片。通过上述方式，能够在外部只提供一路电压的情况下，通过两个变压电路向控制芯片和存储芯片提供三种不同的电压，进一步能够存储装置应用于更多的场景，提高了兼容性。
下面通过一采用EMMC((Embedded Multi Media Card))协议的存 储装置进行举例说明，如NM卡(多媒体存储卡)。
NM卡包括八个触片，八个子触片分别用1-8个数字表示，八个子触片以NM卡的长边为行、短边为列，以4行2列的方式进行排布。接口触片包括依次顺序排列在第一列的第一子触片、第二子触片、第三子触片、第四子触片，以及依次倒序排列在第二列的第五子触片、第六子触片、第七子触片、第八子触片。
可以理解的，各个子触片之间是相互绝缘的。
在本实施例中，所述接口触片14用于建立存储装置10与外部设备的电连接，外部接口走eMMC协议，本实施例中，接口触片14包括3.3V电源触片(VCC)、接地触片(GND)、时钟触片(CLK)、命令触片(CMD)和4个数据触片(D0-D3)，在本实施例中，8个接口触片的设置如下：
子触片号 定义 子触片号 定义
1 D1 5 D2
2 CMD 6 VCC
3 GND 7 D0
4 D3 8 CLK
其中的VCC引脚用于接收外部提供的第一电压，相当于上述实施例中的电源接口。
标准的eMMC协议需要提供VCC(3.3V)和VCCQ(3.3V或1.8V)两路电源输入，以及8个数据管脚，本实施例提供的NM卡为了减小存储卡的面积，设置8个接口触片，其中只有VCC引脚，因此只保留了3.3V电源输入，并只设置了4个数据接口触片，本实施例的存储装置支持以下几种速率模式：
Figure PCTCN2019096430-appb-000001
Figure PCTCN2019096430-appb-000002
参阅图3，图3是本申请提供的存储装置第二实施例的电路结构示意图。
在本实施例中，该存储装置10包括控制芯片12、存储芯片13、电源接口17、第一变压电路18、第二变压电路19、选择电路20。
其中，电源接口17被配置为接收外部的第一电压V1；第一变压电路18的输入端耦接电源接口17，其输出端耦接控制芯片12，被配置为将第一电压V1转换为第二电压V2，并将第二电压提供给控制芯片12；第二变压电路19的输入端耦接电源接口17，其输出端耦接控制芯片12和存储芯片13，被配置为将第一电压V1转换为第三电压V3，并将第三电压V3提供给控制芯片12和存储芯片13。
进一步的，在本实施例中，第一电压为3.3V，第二电压为1.2V，第三电压为1.8V。
可以理解的，控制芯片12的内核的工作电压为1.2V，具体地，控制芯片12包括第一电源引脚(图未示)，耦接第一变压电路18的输出端，以对控制芯片12的内核提供第二电压V2。
另外，控制芯片12还包括EMMC IO引脚(未标示)和第一Flash IO引脚(未标示)，存储芯片13包括第二Flash IO引脚(未标示)。其中，第一Flash IO引脚和第二Flash IO引脚耦接，用于使控制芯片12与存储芯片13之间传输指令或者数据。
可以理解的，EMMC IO引脚的工作电压为1.8V，而第一Flash IO引脚和第二Flash IO引脚的工作电压为1.8V或3.3V。
具体地，EMMC IO引脚耦接第二变压电路19的输出端；第一Flash IO引脚通过选择电路20分别耦接第二变压电路19的输出端和电源接口17，以根据需要选择输入第一电压V1或第三电压V3；第二Flash IO引 脚通过选择电路20分别耦接第二变压电路19的输出端和电源接口17，以根据需要选择输入第一电压V1或第三电压V3。其中，选择电路20的第一输入端耦接第二变压电路19的输出端，其第二输入端耦接电源接口17，其输出端耦接第一Flash IO引脚和第二Flash IO引脚。
可以理解的，存储芯片13的内核的工作电压为3.3V，在上述的实施例中，存储芯片13还包括第二电源引脚(图未示)，耦接电源接口17，以对存储芯片13的内核提供第一电压V1。
由于本实施例提供的存储装置10只设置了3.3V电源接口，只支持3.3V电源输入，那么通过增加的第一变压电路18和第二变压电路19，用于将输入的3.3V电源转化为1.8V和1.2V电源输出，并为主控芯片12和/或存储芯片13提供1.8V和1.2V电源输入。
可以理解的，在本实施例，第一变压电路18和第二变压电路19均集成于控制芯片12内部。
参阅图4，图4是本申请提供的电子设备一实施例的结构示意图，该电子设备包括设备主体41和可嵌入设备主体41内部的卡托42。另外还包括处理器43和电源44，处理器43分别耦接电源44和卡槽，卡托中的存储卡可以通过卡槽进一步耦接到处理器43。
其中，如图5所示，图5是本申请提供的电子设备一实施例中卡托的结构示意图，该卡托42包括SIM卡槽42a和存储卡槽42b，SIM卡槽42a和存储卡槽42b的形状相同，其中，存储卡槽42b用于容置上述实施例中提供的存储装置。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种存储装置，其特征在于，包括：
    控制芯片；
    存储芯片；
    电源接口，被配置为接收外部的第一电压；
    第一变压电路，其输入端耦接所述电源接口，其输出端耦接所述控制芯片，被配置为将第一电压转换为第二电压，并将第二电压提供给所述控制芯片；
    第二变压电路，其输入端耦接所述电源接口，其输出端耦接所述控制芯片和所述存储芯片，被配置为将第一电压转换为第三电压，并将第三电压提供给所述控制芯片和所述存储芯片。
  2. 根据权利要求1所述的存储装置，其特征在于，
    所述第一电压为3.3V，所述第二电压为1.2V。
  3. 根据权利要求2所述的存储装置，其特征在于，
    所述控制芯片包括第一电源引脚，耦接所述第一变压电路的输出端，以对所述控制芯片的内核提供所述第二电压。
  4. 根据权利要求1所述的存储装置，其特征在于，
    所述第一电压为3.3V，所述第三电压为1.8V。
  5. 根据权利要求4所述的存储装置，其特征在于，
    所述存储装置为基于EMMC协议的存储装置；
    所述控制芯片包括：
    EMMC IO引脚，耦接所述第二变压电路的输出端；
    第一Flash IO引脚，通过选择电路分别耦接所述第二变压电路的输出端和所述电源接口，以根据需要选择输入所述第一电压或所述第三电压；
    所述存储芯片包括：
    第二Flash IO引脚，通过所述选择电路分别耦接所述第二变压电路的输出端和所述电源接口，以根据需要选择输入所述第一电压或所述第 三电压。
  6. 根据权利要求5所述的存储装置，其特征在于，
    所述选择电路的第一输入端耦接所述第二变压电路的输出端，其第二输入端耦接所述电源接口，其输出端耦接所述第一Flash IO引脚和所述第二Flash IO引脚。
  7. 根据权利要求1所述的存储装置，其特征在于，
    所述第一电压为3.3V；
    所述存储芯片还包括第二电源引脚，耦接所述电源接口，以对所述存储芯片的内核提供所述第一电压。
  8. 根据权利要求1所述的存储装置，其特征在于，
    所述第一变压电路和/或所述第二变压电路集成于所述控制芯片内。
  9. 根据权利要求1所述的存储装置，其特征在于，
    所述存储装置还包括：
    基板，包括相对的第一侧面和第二侧面；其中，所述存储芯片设置于所述第一侧面，所述控制芯片设置于所述存储芯片远离所述基板的一侧；
    多个触片，设置于所述第二侧面；其中，所述电源接口为所述多个触片中的一个。
  10. 一种电子设备，其特征在于，包括：
    电源；
    处理器，耦接所述电源；
    存储装置，耦接所述处理器，所述存储装置是如权利要求1-9任一项所述的存储装置。
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