WO2020118950A1 - 用于串行通信的从设备及方法 - Google Patents

用于串行通信的从设备及方法 Download PDF

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Publication number
WO2020118950A1
WO2020118950A1 PCT/CN2019/078699 CN2019078699W WO2020118950A1 WO 2020118950 A1 WO2020118950 A1 WO 2020118950A1 CN 2019078699 W CN2019078699 W CN 2019078699W WO 2020118950 A1 WO2020118950 A1 WO 2020118950A1
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Prior art keywords
data
clock signal
serial
module
bit data
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PCT/CN2019/078699
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English (en)
French (fr)
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黄平
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北京集创北方科技股份有限公司
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Priority to KR1020197038605A priority Critical patent/KR102289930B1/ko
Priority to JP2019572645A priority patent/JP7212637B2/ja
Publication of WO2020118950A1 publication Critical patent/WO2020118950A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Definitions

  • the invention relates to the technical field of data communication, in particular to a slave device and method for serial communication.
  • FIG. 1 a block diagram of a common design method for SPI (Serial Peripheral Interface) to send data from a device is shown in FIG. 1.
  • the SPI slave device 100 receives the serial clock signal SCLK via the clock signal terminal SCLK, receives data via the data input terminal MOSI, and transmits data via the data output terminal MISO.
  • the SPI slave device uses a system clock (SYSCLK) that is several times higher than the SPI serial clock (SCLK) frequency to synchronize and detect the SPI serial clock signal SCLK edge at the edge detection module 110, also known as the sending edge, that is, serial The transition of the rising edge or falling edge of the clock signal SCLK, the resulting transmission edge signal.
  • SYSCLK system clock
  • SCLK serial clock
  • the transmission edge signal maintains only one system clock SYSCLK cycle high level.
  • the logic module 120 reads the data from the storage module 130 according to the enable signal, and shifts and outputs one bit to send the data to the data output terminal MISO, and after the shift output of a group of data (usually 8 bits) is completed, it is taken out from the memory The next set of data is shifted and sent out again.
  • Fig. 2 is a schematic diagram of the waveform of SPI mode 0 transmission data of the method.
  • the SPI serial clock usually only works when the SPI transmits data (CS valid period), and keeps the fixed level unchanged at other times (even if there is a change, it can be gated with CS).
  • SPI mode 0 needs to prepare the first bit of data before the first SPI serial clock transmission edge arrives and output it to the data output terminal MISO. Before the SPI serial clock arrives, the SPI serial clock cannot be used to read data from the memory to send the first bit of data, so the system clock signal SYSCLK is usually used to send data.
  • the half cycle of the SPI serial clock (T SCLK /2) minus the data preparation delay Ta and the data transmission delay Tb (MISO PAD/board delay) in the PAD/board is the setup time Tc (MISO setup time) of the output data at the receiving end .
  • Tc MISO setup time
  • a higher frequency system clock signal SYSCLK is required to reduce data preparation delay Ta; or in the case of a certain frequency of the system clock signal SYSCLK, the highest frequency of the SPI serial clock that can be supported is lower; this is manifested by the higher frequency ratio of the system clock SYSCLK/serial clock SCLK.
  • an object of the present invention is to provide a slave device and method for serial communication, so as to reduce the frequency ratio of the system clock SYSCLK/serial clock signal SCLK and obtain a better output data setup time.
  • a serial communication method for a slave device including: receiving a serial clock signal via a clock signal terminal; receiving data via a data input terminal, the data including a plurality of consecutive bit data; Synchronizing with the system clock signal, shifting the data to obtain bit data; and synchronizing with the serial clock signal, latching the bit data, and sending at least a portion of the latched bit data via the data output, wherein ,
  • the serial clock signal and the system clock signal have a first clock period and a second clock period, respectively, the first clock period is greater than the second clock period.
  • the selection bit data of the data is shifted, latched, and transmitted, respectively.
  • it further includes: generating a driving clock signal according to the serial clock signal, wherein the bit data is sent at an edge of the driving clock signal.
  • the driving clock signal is obtained from the serial clock signal through gating and/or phase conversion.
  • the step of shifting the data includes: delaying at least one second clock cycle in the first clock cycle of the serial clock signal, thereby obtaining an enable signal synchronized with the system clock signal ; And according to the enable signal, the data is shifted to obtain bit data.
  • the method further includes: shifting the bit data according to the enable signal to obtain the first bit data, latching the first bit data, and transmitting the latched first bit data.
  • it further includes: obtaining a selection signal according to the serial clock signal, for selectively providing the first bit data and the remaining bit data of the data to the data output terminal for transmission.
  • the bit data is sent on the rising or falling edge of the serial clock signal.
  • the first bit of data is sent before or after the first edge of the serial clock signal.
  • a slave device for serial communication that receives a serial clock signal via a clock signal terminal, receives data via a data input terminal, and transmits the data via a data output terminal
  • the slave device includes: a storage module for storing the data; a logic module coupled to the storage module for synchronizing with a system clock signal to shift the data to obtain bit data;
  • the first latch module, coupled to the logic module is used to latch the first bit of the data;
  • the second latch module coupled to the logic module, is used to latch the remaining bits of the data;
  • selection A signal generation module is used to obtain a selection signal synchronized with the serial clock signal;
  • a selection module is coupled to the first latch module, the second latch module and the selection signal generation module, and is used to connect the selection signal according to the selection signal
  • One of the first bit data and the remaining bit data is provided to the data output terminal, wherein the serial clock signal and the system clock signal have a first clock cycle and a second clock cycle, respectively, the first The clock
  • an edge detection module configured to delay at least one second clock cycle in the first clock cycle of the serial clock signal, so as to obtain an enable signal synchronized with the system clock signal.
  • it further includes: a clock module, configured to obtain a driving clock signal after gating and/or phase conversion of the serial clock signal, wherein the selection signal generating module generates the driving clock signal according to the edge detection of the driving clock signal The selection signal.
  • a clock module configured to obtain a driving clock signal after gating and/or phase conversion of the serial clock signal, wherein the selection signal generating module generates the driving clock signal according to the edge detection of the driving clock signal The selection signal.
  • the logic module selects to shift the first bit data to the first latch module or the second latch module according to the operating mode of the slave device.
  • the first latch module includes a flip-flop and control logic for latching and outputting the first bit of data.
  • the second latch module includes a flip-flop, and the driving clock signal acts on the clock end of the flip-flop, and is used to latch and output the remaining bit data.
  • the selection signal generation module includes a flip-flop and a control logic module for controlling the selection signal.
  • a slave device and method for serial communication it has the following advantages or benefits: using the system clock SYSCLK, according to the detected edge of the serial clock signal SCLK, also known as the sending edge, that is, the serial clock
  • SCLK also known as the sending edge
  • the rising edge or falling edge of the signal SCLK is shifted in advance to prepare the data to be sent.
  • the clock edge is used to transmit the trigger, latch and send out the data to be sent, and
  • the selector selects the output.
  • the preparation delay of the transmission data is transferred to the arrival of the transmission edge, and the transmission data arrives at the receiving end only with a transmission delay (PAD/board delay), thereby obtaining the best transmission data setup time and reducing the system clock SYSCLK/serial clock The frequency ratio of the signal SCLK.
  • the pre-shift preparation of the data to be sent is based on the sending edge of the serial clock signal SCLK detected by the system clock SYSCLK, and the maximum delay time is 3 system clock SYSCLK cycles, as long as two serial clock signals SCLK are sent
  • the edge interval (that is, the cycle) is greater than 3 SYSCLK cycles of the system clock.
  • the transmission edge of the serial clock signal SCLK (transformed into the drive clock signal GSCLK according to the mode) is used to directly latch and transmit the system clock SYSCLK. , Enough to meet the setup time and hold time requirements of the sending trigger, ensuring the correct sending of data.
  • the operation of the memory module with the system clock SYSCLK solves the problems of the first bit of data reading, preparation, and transmission without the serial clock signal SCLK before the SPI transmission starts, and the memory module during the absence of the serial clock signal SCLK Manipulation issues (such as clearing, synchronization, etc.)
  • the first data latch module is added to solve the problem that the first data is sent before the first serial clock signal SCLK transmission edge in different SPI modes, and the first data latch module uses only one trigger With minimal overhead.
  • a shift data latch and transmission module is added to ensure that each transmission data is transmitted after each serial clock signal SCLK transmission edge, which ensures that the transmission data is held at the receiving end (hold time) ), to ensure that the data transmission will not be misaligned, and the shift data latch and transmission module uses only one flip-flop, with minimal overhead.
  • a selection signal generation module and a selection module are added to ensure that the selection module selects the correct shift bit data output in different modes.
  • FIG. 1 shows a structural block diagram of a slave device for serial communication in the prior art
  • FIG. 3 shows a flowchart of a serial communication method of a slave device according to a first embodiment of the present invention
  • FIG. 4 shows a flowchart of a serial communication method of a slave device according to a second embodiment of the present invention
  • FIG. 6 shows a structural block diagram of a slave device for serial communication according to a third embodiment of the present invention.
  • FIG. 7 shows a timing diagram of the method for transmitting data from the slave device SPI mode 0 according to the fourth embodiment of the present invention.
  • FIG. 8 shows a timing diagram of the method for transmitting data from the slave device SPI mode 1 in the fifth embodiment of the present invention.
  • SPI bus is a full-duplex, synchronous peripheral interface bus.
  • This interface contains 4 signal lines: low-level slave selection line CS, serial clock line (SCLK), master input/slave output data line MISO, master output/slave input data line MOSI. Because there are few signal lines, the protocol is simple, and the relative data rate is high, a large part of the chip integrates the SPI interface.
  • SPI works in a master-slave mode. This mode usually has a master device and one or more slave devices. Data is received between the master and slave devices according to the sampling edge of the SPI serial clock, and the transmission edge sends a bit of data. Data transmission and reception, to achieve full-duplex transmission (transmission).
  • CS is a chip select signal, which is generated by the master device.
  • Each slave device corresponds to a unique CS, which indicates whether the slave device is selected by the master device, and is usually active low. Only during the CS effective period is an effective SPI transmission between the master and slave devices, which can transmit multiple sets of multi-bit data.
  • the SPI serial clock SCLK is also generated by the master device.
  • the master and slave devices receive/transmit data according to the sampling edge/transmission edge of the SPI serial clock SCLK; the master device samples the MISO data sent by the slave device at the sampling edge and sends the data at the transmission edge To the MOSI to the slave device; the slave device receives the MOSI data sent by the master device at the sampling edge, and sends the data to the MISO to the master device at the sending edge.
  • the sending edge is the level transition edge of the clock signal, which is a rising edge or a falling edge.
  • the sending edge is the starting point of timing analysis.
  • FIG. 3 shows a flowchart of a slave device serial communication method according to a first embodiment of the present invention. The method is implemented by a slave device serial communication device, and specific steps include:
  • Step S301 Receive a serial clock signal and receive data.
  • the chip select signal CS of the SPI slave device Before the chip select signal CS of the SPI slave device is valid, it receives the serial clock signal SCLK from the master device, receives the data (DATA) to be sent via the data access terminal (MOSI), and stores it in the data storage module.
  • DATA data
  • MOSI data access terminal
  • the serial clock signal SCLK is the system clock signal of the SPI master device and is generated by the master device.
  • Step S302 Synchronize with the system clock signal, shift the data to obtain bit data.
  • the system clock signal SYSCLK is the system clock inside the SPI slave device.
  • the system clock signal SYSCLK is used to synchronize and detect the edge of the serial clock signal SCLK to obtain the enable signal ENBIT.
  • the enable signal ENBIT maintains a corresponding effective time period, the effective time period starts from the edge of the serial clock signal delayed by the first time period, and the effective time period continues for the second time period, the first time period and the second time period
  • the period of the system clock signal SYSCLK is the second clock period
  • the effective period of the enable signal ENBIT has a delay of 2 to 3 system clock signal periods compared to the edge of the serial clock signal SCLK, and the effective period is only Maintain the validity of one system clock cycle.
  • the edge of the enable signal ENBIT is synchronized with the edge of the system clock signal SYSCLK, and the data in the memory is shifted at this edge to obtain bit data.
  • the edge is a level transition edge of the clock signal, which is a rising edge or a falling edge, and is also called a sending edge.
  • Step S303 Synchronize with the serial clock signal, latch and transmit the pre-shifted bit data.
  • the pre-shifted bit data is latched and sent, latched in the second latch module, and sent to the selection module.
  • the pre-shifted bit data refers to the data sent by this sending edge is the data synchronized by the system clock signal SYSCLK and detects the shift of the enable signal ENBIT obtained at the last sending edge, and the system clock signal SYSCLK is synchronized and detects this
  • the data shifted by the enable signal ENBIT obtained at the transmission edge is transmitted at the time of the next transmission edge.
  • the enable signal ENBIT has a delay compared to the edge of the serial clock signal SCLK, so the bit data shifted according to the enable signal ENBIT also has a delay compared to the edge of the serial clock signal SCLK, that is, the serial clock
  • the signal is synchronized, and the shift bit data latched and transmitted is the bit data shifted according to the enable signal obtained by detecting the edge of the last cycle of the serial clock signal SCLK.
  • Step S304 generate a selection signal, and the selection module selects and outputs bit data according to the selection signal.
  • the selection signal SEL is obtained based on the serial clock signal SCLK. Before the first transmission edge of the serial clock signal SCLK arrives, the selection signal SEL is 1, and after the first transmission edge, the selection signal SEL is 0. When the selection signal SEL is 1, the selection module is connected to the first latch output terminal, and when the selection signal SEL is 0, the selection module is connected to the second latch output terminal.
  • the above steps only show the data transmission process of the slave device serial communication method after the data transmission starts, that is, from the first sending edge.
  • the method further includes: before the first transmission edge, prepare a shift bit data to be transmitted at the time of the first transmission edge.
  • the method further includes: before preparing a shift bit data in advance, shifting and latching the bit data, shifting and latching it to the first latch module, And send it to the data output terminal MISO before the first sending edge.
  • FIG. 4 shows a flowchart of a slave device serial communication method according to a second embodiment of the present invention. Compared with the method shown in FIG. 3, FIG. 4 is a preferred embodiment, except that a driving clock signal is added GSCLK, which latches and transmits shifted bit data at the edge of the driving clock.
  • the steps of this method include:
  • Step S401 Receive a serial clock signal and receive data.
  • the chip select signal CS of the SPI slave device Before the chip select signal CS of the SPI slave device is valid, it receives the serial clock signal SCLK from the master device, receives the data (DATA) to be sent via the data access terminal (MOSI), and stores it in the data storage module.
  • DATA data
  • MOSI data access terminal
  • the serial clock signal SCLK is the system clock signal of the SPI master device and is generated by the master device.
  • Step S402 Obtain a driving clock signal according to the serial clock signal.
  • the input is the serial clock signal SCLK
  • the output is the driving clock signal GSCLK.
  • the driving clock signal GSCLK can be generated by changing the phase and/or gated serial clock signal SCLK. Gating is only enabled during the CS active period, allowing the clock signal GSCLK to work.
  • Step S403 Synchronize with the system clock signal, shift the data to obtain bit data.
  • the system clock signal SYSCLK is the system clock inside the SPI slave device.
  • the system clock signal SYSCLK is used to synchronize and detect the edge of the serial clock signal SCLK to obtain the enable signal ENBIT.
  • the enable signal ENBIT maintains a corresponding effective time period, the effective time period starts from the edge of the serial clock signal delayed by the first time period, and the effective time period continues for the second time period, the first time period and the second time period
  • the period of the system clock signal SYSCLK is the second clock period
  • the effective period of the enable signal ENBIT has a delay of 2 to 3 system clock signal periods compared to the edge of the serial clock signal SCLK, and the effective period is only Maintain the validity of one system clock cycle.
  • the edge of the enable signal ENBIT is synchronized with the edge of the system clock signal SYSCLK, and the data in the memory is shifted at this edge to obtain bit data.
  • the edge is a level transition edge of the clock signal, which is a rising edge or a falling edge, and is also called a sending edge.
  • Step S404 Synchronize with the driving clock signal, latch and transmit the pre-shifted bit data.
  • the pre-shifted bit data is latched and sent, latched in the second latch module, and sent to the selection module.
  • the pre-shifted bit data refers to the data sent by this sending edge is the data synchronized by the system clock signal SYSCLK and detects the shift of the enable signal ENBIT obtained at the last sending edge, and the system clock signal SYSCLK is synchronized and detects this
  • the data shifted by the enable signal ENBIT obtained at the transmission edge is transmitted at the time of the next transmission edge.
  • the edge of the driving clock is synchronized with the edge of the serial clock.
  • the enable signal ENBIT has a delay compared to the edge of the serial clock signal SCLK, so the bit data shifted according to the enable signal ENBIT also has a delay compared to the edge of the serial clock signal SCLK.
  • Synchronized with the driving clock signal GSCLK, that is, with the serial clock signal SCLK, the shift bit data latched and transmitted is the bit data shifted according to the enable signal obtained by detecting the edge of the last cycle of the serial clock signal SCLK.
  • Step S405 Generate a selection signal, and the selection module selects and outputs bit data according to the selection signal.
  • the selection signal SEL is obtained based on the serial clock signal SCLK and the driving clock signal GSCLK. Before the first transmission edge of the serial clock signal SCLK arrives, the selection signal SEL is 1, and after the first transmission edge, the selection signal SEL is 0. When the selection signal SEL is 1, the selection module is connected to the first latch output terminal, and when the selection signal SEL is 0, the selection module is connected to the second latch output terminal.
  • the method further includes: before the first transmission edge, prepare a shift bit data to be transmitted at the time of the first transmission edge. According to different choices of the SPI slave device mode, the method further includes: before preparing a shift bit data in advance, shifting and latching the bit data, shifting and latching it to the first latch module, And send it to the data output terminal MISO before the first sending edge.
  • FIG. 5 shows four working modes of serial communication of a slave device according to an embodiment of the present invention. As shown in the figure, according to the phase CPHA and polarity CPOL of the system clock, it is divided into four working modes.
  • Polarity CPOL indicates whether the serial clock signal SCLK is high or low when the SPI is idle. If CPOL is set to 1, then the clock signal under the serial clock signal SCLK pin of this device is high when it is idle. When CPOL is set to 0, the opposite is true.
  • the phase CPHA indicates whether the SPI device triggers data sampling when the clock signal on the serial clock signal SCLK pin becomes a rising edge or when the serial clock signal SCLK becomes a falling edge. If CPHA is set to 1, the SPI device triggers data sampling when the serial clock signal SCLK becomes a falling edge and sends data on a rising edge. The opposite is also true when CPHA is set to 0.
  • Mode 2 its drive clock signal GSCLK and serial clock signal SCLK are in phase.
  • the SPI Mode 1 and Mode 3 transmit data have the same beat, but Mode 1 drives the clock signal GSCLK in phase with the serial clock signal SCLK, and Mode 3 drives the clock signal GSCLK in phase with the serial clock signal SCLK.
  • SPI mode 1 has sent the first bit of data before the first send edge comes, while mode 1 sends the first bit of data after the first send edge.
  • Mode 1 and Mode 3 all transmission data is transmitted from the second latch module, and the selection signal SEL remains at 0 all the time.
  • the first transmission data comes from the first latch module, and the rest of the transmission data comes from the second latch module.
  • the level of the selection signal SEL is 1 before the first transmission edge. It stays at 0 after the sending edge.
  • FIG. 6 shows a structural block diagram of a slave device for serial communication according to a third embodiment of the present invention.
  • the figure is a structural block diagram corresponding to the flowchart shown in FIG. 4.
  • the SPI slave device 200 according to the embodiment of the present invention may be divided into a system clock domain D1 and a driving clock signal GSCLK domain D2, and further includes a clock module 310 and a selection module 214.
  • the system clock domain D1 includes an edge detection module 110, a storage module 130, a logic module 120, and a first latch module 211.
  • the driving clock signal domain D2 includes a second latch module 212 and a selection signal generation module 213.
  • the edge detection module 110 uses the internal system clock SYSCLK to detect the transmission edge of the serial clock signal SCLK, and obtains the transmission edge enable signal ENBIT that maintains an internal system clock cycle.
  • the storage module 130 stores all data to be sent.
  • the logic module 120 takes a set of transmission data from the storage module 130 and shifts one bit of data BITDATA in the transmission data group to the second latch module 212 when an enable signal ENBIT is detected.
  • the first latch module 211 including a flip-flop and control logic, is used in SPI mode 0 and mode 2, and latches the first set of first transmission data of the transmission before the start of each transmission, and is valid in CS After that, the first bit of data is sent and it is kept in this transmission.
  • the clock module 310 enables gating only when CS is valid, and takes the inverted serial clock signal SCLK in SPI Mode 0 and Mode 3, and takes the in-phase serial clock signal SCLK in Mode 1 and Mode 2, thereby obtaining the driving clock signal GSCLK .
  • the driving clock signal GSCLK only works during the CS active period, and the sending edge of the driving clock signal GSCLK corresponds to the sending edge of the serial system clock SCLK in various modes of SPI, and the sending edge of the driving clock signal GSCLK rises in various modes Edge, thereby driving the clock signal domain D2 to work uniformly with a rising edge trigger.
  • the second latch module 212 includes a flip-flop, the transmission edge of the driving clock signal GSCLK acts on the flip-flop clock terminal, latches and transmits the prepared transmission bit data BITDATA shifted in advance in the system clock domain D1, and passes the second The output of the latch module 212 is sent to the selection module 214.
  • the selection signal generation module 213 includes a flip-flop and control logic for generating the selection signal SEL and selecting the transmission bit data output.
  • the requirement is that the selection signals of SPI Mode 0 and Mode 2 are 1 before the first transmission edge. It is 0 after the first transmit edge and remains 0 until the end of one SPI transfer; SPI Mode 1 and Mode 3 remain 0.
  • the selection module 214 selects the output data of the first latch module 211 in the system clock domain D1 or the output data of the second latch module 212 in the drive clock domain D2 with the selection signal SEL. Specifically, when the selection signal SEL is 1, the output data of the first latch module 211 is selected, and when the selection signal SEL is 0, the output data of the second latch module 212 is selected.
  • FIG. 7 shows a timing diagram of the SPI slave device SPI mode 0 method of transmitting data according to the fourth embodiment of the present invention.
  • the timing diagram is divided into two parts.
  • the signal above the dotted line works in the system clock domain D1
  • the signal below the dotted line works in the driving clock signal GSCLK domain D2.
  • the drive clock signal GSCLK of SPI mode 0 takes the reverse phase of the serial clock signal SCLK.
  • the slave device takes the first set of data from the storage module 130, and stores the first bit data in the BIT0 first latch module 211, and shifts the first The transmission edge moves the data BITDATA to be transmitted to the BIT1-N second latch module 212.
  • the system clock domain D1 generates an asynchronous reset signal, which resets the select signal SEL in the drive clock signal GSCLK domain D2 to 1.
  • the selection signal SEL is 1, and the selection module 214 selects bit 0 of the first latch module 211 of BIT0 to output to MISO as bit 0.
  • the driving clock signal GSCLK is latched via the second latch module 212 and sends BITDATA to the selection module 214, the selection signal SEL is changed to 0, and the selection module 214 selects the data of the second latch module 212 to output to MISO on.
  • the system clock SYSCLK detects the sending edge of the serial clock signal SCLK to obtain the enable signal ENBIT, and the logic module 120 shifts a bit data BITDATA according to the enable signal ENBIT, and the bit data BITDATA shifts To the second latch module 212.
  • bit data bit0 in the first latch module 211 of BIT0 has been output to the MISO, and at time t0, the driving clock signal GSCLK is latched and sent out
  • the bit1 that has been prepared before the start of transmission is also bit1 in the BIT1-N second storage module 212, and then is selected and output by the selection module 214 to MISO as bit1.
  • the sending edge of the serial clock signal SCLK is detected by the system clock SYSCLK, generating an enable signal ENBIT (maintaining a system clock SYSCLK cycle valid period), the enable signal ENBIT shifts data at time t1 to get bit2 To prepare the data for the second sending edge.
  • the driving clock signal GSCLK latches and sends out bit2 that has been prepared before the start of transmission, that is, bit2 in the second storage module, and then the selection module 214 selects and outputs it to MISO as bit2.
  • the sending edge of the serial clock signal SCLK is detected by the system clock SYSCLK, and an enable signal ENBIT is generated.
  • the enable signal shifts the data at time t3 to obtain bit 3, and prepares the data for the third sending edge.
  • Time t4 is the time of the third sending edge. According to the above-mentioned tempo, the pipeline continues to send data. After the first set of data is sent, the next set of data is taken from the memory and sent until the end of the SPI transmission (CS changes from low to high to invalid).
  • the data DATA1 to be transmitted is stable enough to meet the preparation of BITDATA when the transmission edge of the serial system clock signal SCLK arrives Time T1.
  • FIG. 8 shows a timing diagram of the SPI slave device SPI mode 1 method of transmitting data according to the fifth embodiment of the present invention. As shown in the figure, the timing diagram is divided into two parts. The signal works in the driving clock signal domain D2. The drive clock signal GSCLK of SPI mode 1 is the same phase of the serial clock signal SCLK.
  • the slave device Before CS becomes low, in the system clock domain D1, the slave device takes the first set of data from the storage module 130 and shifts the first bit of data bit 0 to the second latch module 212.
  • the selection signal SEL remains at 0 all the time.
  • the selection signal SEL After CS goes low, in the driving clock domain D2, the selection signal SEL remains at 0 before and after the first transmission edge, and the selection module 214 selects the data output of the second latch module 212 according to the selection signal SEL To MISO.
  • the system clock SYSCLK detects the sending edge of the serial clock signal SCLK to obtain the enable signal ENBIT, and the logic module 120 shifts one bit data in the storage module 130 according to the enable signal ENBIT to obtain BITDATA, The bit data BITDATA is shifted to the second latch module 212.
  • bit0 which is also bit0 in the second storage module 212 of BIT1-N, is then selected and output by the selection module 214 to MISO as bit0.
  • the sending edge of the serial clock signal SCLK is detected by the system clock SYSCLK to generate an enable signal ENBIT (maintaining a system clock SYSCLK period effective period), the enable signal ENBIT shifts data at time t1 to get bit1 To prepare the data for the second sending edge.
  • the drive clock signal GSCLK latches and sends out bit1 that has been prepared before the start of transmission, that is, bit1 in the second storage module, and then the selection module 214 selects and outputs it to MISO as bit1.
  • the sending edge of the serial clock signal SCLK is detected by the system clock SYSCLK, and an enable signal ENBIT is generated.
  • the enable signal shifts the data at time t3 to obtain bit 2 and prepares the data for the third sending edge.
  • Time t4 is the time of the third sending edge. According to the above-mentioned tempo, the pipeline continues to send data. After the first set of data is sent, the next set of data is taken from the memory and sent until the end of the SPI transmission (CS changes from low to high to invalid).
  • the slave device and method for serial communication provided by the invention can greatly reduce the frequency ratio of the system clock SYSCLK/serial clock signal SCLK, increase the data transmission rate of the slave device, or reduce the frequency of the slave device system clock SYSCLK.
  • SCLK serial clock signal
  • the following two examples illustrate the beneficial effects of the present invention compared to the prior art.
  • the receiving end receives
  • the minimum setup time (T4 in Figure 7) of the transmitted data from the device is 5 ns.
  • Table 2 The highest frequency of the SPI serial clock signal SCLK that can be supported when the system clock signal SYSCLK is 50MHz
  • the same SPI serial clock signal SCLK is 10MHz
  • the original program requires the minimum frequency of the system clock signal SYSCLK is 100MHz
  • this program requires the minimum frequency of the system clock signal SYSCLK is 33MHz.

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Abstract

公开了一种用于串行通信的从设备及方法，该方法包括：经由时钟信号端接收串行时钟信号；经由数据输入端接收数据，所述数据包括多个连续的位数据；与系统时钟信号同步，对所述数据进行移位以获得位数据；以及与所述串行时钟信号同步，锁存所述位数据，以及经由数据输出端发送至少一部分锁存的位数据，其中，所述串行时钟信号和所述系统时钟信号分别具有第一时钟周期和第二时钟周期，所述第一时钟周期大于所述第二时钟周期。该方法与系统时钟信号同步移位位数据，与串行时钟信号同步锁存及发送预移位的位数据，从而将发送数据准备时间转移到发送沿之前，使得系统时钟/串行时钟信号频率比更低，从而可以提高传输速率。

Description

用于串行通信的从设备及方法
本申请要求了2018年12月10日提交的、申请号为201811501631.6、发明名称为“用于串行通信的从设备及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及数据通信技术领域，具体涉及一种用于串行通信的从设备及方法。
背景技术
现有技术中，SPI(Serial Peripheral Interface，串行外设接口)从设备发送数据的一种常用设计方法的结构框图如图1所示。SPI从设备100经由时钟信号端SCLK接收串行时钟信号SCLK，经由数据输入端MOSI接收数据，以及经由数据输出端MISO发送数据。SPI从设备内部用一个比SPI串行时钟(SCLK)频率高数倍的系统时钟(SYSCLK)，在边沿检测模块110同步并检测SPI串行时钟信号SCLK边沿，也称为发送沿，即串行时钟信号SCLK的上升沿或下降沿的跳变，得到的发送沿信号。该发送沿信号作为使能信号ENTX，只维持一个系统时钟SYSCLK周期的高电平有效。逻辑模块120根据使能信号从存储模块130中读取数据，并且移位输出一位发送数据到数据输出端MISO上，并且在一组数据(通常为8bit)移位输出完毕后，从存储器取出下一组数据并再次移位发送出去。
图2是该方法SPI模式0发送数据的波形示意图。如图所示，SPI串行时钟通常只在SPI传输数据时(CS有效期间)工作，其他时间保持固定电平不变化(即使有变化也可以用CS门控住)。SPI模式0需要在第一个SPI串行时钟发送沿到来前准备好第一位数据，并输出到数据输出端MISO上。在SPI串行时钟到来前，无法使用SPI串行时钟从存储器读取数据进行第一位数据的发送，因此通常使用系统时钟信号SYSCLK来发送数据。
这种数据发送方法存在着一些不足。图2中，从SPI串行时钟的发送沿到系统时钟SYSCLK跨时钟域同步并检测到SPI串行时钟的发送沿跳变信号，用该跳变信号作为使能信号ENTX移位输出数据，这段数据准备延迟Ta(MISO data prepare delay)通常为2～3个系统时钟SYSCLK周期(T SYSCLK)。另外一个延迟是数据在PAD/board上传输延迟Tb(MISO PAD/board delay)。SPI串行时钟的半周期(T SCLK/2)减去数据准备延迟Ta和数据在PAD/board传输延迟Tb(MISO PAD/board delay)，就是输出数据在接收端的建立时间Tc(MISO setup time)。一个项目中，数据 在PAD/board传输延迟Tb是固定的，越大的数据准备延迟Ta将使得输出数据建立时间Tc越小，限制了传输速率的提高。
为了满足输出数据在接收端的建立时间要求，在SPI串行时钟频率(即传输速率)一定的情况下(即T SCLK/2一定)，需要频率较高的系统时钟信号SYSCLK，以减少数据准备延迟Ta；或者说在系统时钟信号SYSCLK频率一定的情况下，能支持的SPI串行时钟的最高频率较低；这都表现为系统时钟SYSCLK/串行时钟SCLK的频率比例较高。
发明内容
鉴于上述问题，本发明的目的在于提供一种用于串行通信的从设备及方法，从而降低系统时钟SYSCLK/串行时钟信号SCLK的频率比例，得到更好的输出数据建立时间。
根据本发明的一方面，提供一种用于从设备的串行通信方法，包括：经由时钟信号端接收串行时钟信号；经由数据输入端接收数据，所述数据包括多个连续的位数据；与系统时钟信号同步，对所述数据进行移位以获得位数据；以及与所述串行时钟信号同步，锁存所述位数据，以及经由数据输出端发送至少一部分锁存的位数据，其中，所述串行时钟信号和所述系统时钟信号分别具有第一时钟周期和第二时钟周期，所述第一时钟周期大于所述第二时钟周期。
可选地，在所述串行时钟信号的连续周期中，分别对所述数据的选择位数据进行移位和锁存以及发送。
可选地，还包括：根据所述串行时钟信号产生驱动时钟信号，其中，在所述驱动时钟信号的边沿发送所述位数据。
可选地，所述驱动时钟信号由所述串行时钟信号经过门控和/或相位变换得到。
可选地，对所述数据进行移位的步骤包括：在所述串行时钟信号的第一时钟周期中，延迟至少一个第二时钟周期，从而获得与所述系统时钟信号同步的使能信号；以及根据所述使能信号，对所述数据进行移位以获得位数据。
可选地，还包括：根据所述使能信号，对所述位数据进行移位以获得第一位数据，以及锁存所述第一位数据，以及发送锁存的第一位数据。
可选地，还包括：根据所述串行时钟信号得到选择信号，用于选择性地将所述数据的第一位数据和其余位数据提供到数据输出端进行发送。
可选地，根据所述从设备的工作模式，在所述串行时钟信号的上升沿或下降沿发送所述位数据。
可选地，根据所述从设备的工作模式，在所述串行时钟信号的第一个边沿之前或之后发送所 述第一位数据。
根据本发明的另一方面，提供一种用于串行通信的从设备，所述从设备经由时钟信号端接收串行时钟信号，经由数据输入端接收数据，以及经由数据输出端发送所述数据，其特征在于，所述从设备包括：存储模块，用于存储所述数据；逻辑模块，与存储模块耦接，用于与系统时钟信号同步，对所述数据进行移位以获得位数据；第一锁存模块，与逻辑模块耦接，用于锁存所述数据的第一位数据；第二锁存模块，与逻辑模块耦接，用于锁存所述数据的其余位数据；选择信号生成模块，用于获得与所述串行时钟信号同步的选择信号；选择模块，与第一锁存模块、第二锁存模块和选择信号生成模块耦接，用于根据选择信号将所述第一位数据和所述其余位数据之一提供至所述数据输出端，其中，所述串行时钟信号和所述系统时钟信号分别具有第一时钟周期和第二时钟周期，所述第一时钟周期大于所述第二时钟周期。
可选地，还包括：边沿检测模块，用于在所述串行时钟信号的第一时钟周期中，延迟至少一个第二时钟周期，从而获得与所述系统时钟信号同步的使能信号。
可选地，还包括：时钟模块，用于对所述串行时钟信号经过门控和/或相位变换得到驱动时钟信号，其中，所述选择信号生成模块根据所述驱动时钟信号的边沿检测生成所述选择信号。
可选地，所述逻辑模块根据从设备的工作模式选择将第一位位数据移位到所述第一锁存模块或所述第二锁存模块。
可选地，所述第一锁存模块包括触发器和控制逻辑，用于锁存和输出第一位数据。
可选地，所述第二锁存模块，包括触发器，所述驱动时钟信号作用于触发器的时钟端，用于锁存和输出其余位数据。
可选地，所述选择信号生成模块包括触发器和控制逻辑模块，用于控制选择信号。
根据本发明提供的一种用于串行通信的从设备及方法，具有以下优点或益处：用系统时钟SYSCLK，根据检测到的串行时钟信号SCLK边沿，也称为发送沿，即串行时钟信号SCLK上升沿或下降沿，预先移位准备好待发位数据，串行时钟信号SCLK发送沿到来时即用该时钟沿作用于发送触发器，锁存及发送出该待发数据，并经选择器选择输出。这样，将发送数据的准备延迟转移到了发送沿到来之前，发送数据到达接收端只有传输延迟(PAD/board delay)，从而得到了最好的发送数据建立时间，降低了系统时钟SYSCLK/串行时钟信号SCLK的频率比例。
进一步的，预先移位准备待发数据是根据系统时钟SYSCLK检测到的串行时钟信号SCLK发送沿进行的，其最大延迟时间为3个系统时钟SYSCLK周期，只要串行时钟信号SCLK的两个发送沿间隔(即周期)大于3个系统时钟SYSCLK周期，用串行时钟信号SCLK的发送沿(按模式变换为驱动时钟信号GSCLK)直接锁存及发送系统时钟SYSCLK预先移位准备好的待发数据， 足以满足发送触发器的建立时间和保持时间要求，确保了数据的正确发送。
进一步的，用系统时钟SYSCLK操作存储模块，解决了SPI传输开始前无串行时钟信号SCLK情况下第一位数据读取、准备、发送的问题，以及存储器模块在无串行时钟信号SCLK期间的操控问题(如清空、同步等)。
进一步的，增加第一位数据锁存模块，解决了SPI不同模式中第一位数据在第一个串行时钟信号SCLK发送沿之前发送的问题，且第一位数据锁存模块只用一个触发器，开销极小。
进一步的，增加移位数据锁存及发送模块，确保了每位发送数据在每个串行时钟信号SCLK发送沿之后才发送出该发送位数据，保证了发送数据在接收端的保持时间(hold time)，确保了数据发送不至于错位，且移位数据锁存及发送模块只用一个触发器，开销极小。
进一步的，增加了选择信号生成模块和选择模块，确保了不同模式中，选择模块选择正确的移位位数据输出。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了现有技术中用于串行通信的从设备的结构框图；
图2示出了现有技术中从设备串行通信的时序图；
图3示出了本发明第一实施例从设备串行通信方法的流程图；
图4示出了本发明第二实施例从设备串行通信方法的流程图；
图5示出了本发明实施例从设备串行通信的四种工作模式；
图6示出了本发明第三实施例用于串行通信的从设备的结构框图；
图7示出了本发明第四实施例从设备SPI模式0发送数据方法的时序图。
图8示出了本发明第五实施例从设备SPI模式1发送数据方法的时序图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。
SPI总线是一种全双工，同步的外围接口总线，该接口包含4根信号线：低电平有效的从机选择线CS，串行时钟线(SCLK)、主机输入/从机输出数据线MISO、主机输出/从机输入数据线 MOSI。由于信号线少，协议简单，相对数据速率高，很大一部分的芯片集成了SPI接口。SPI以主从方式工作，这种模式通常有一个主设备和一个或多个从设备，数据在主从设备之间按照SPI串行时钟的采样沿接收一位数据，发送沿发送一位数据进行数据收发，做到全双工传输(收发)。
CS是片选信号，由主设备产生，每个从设备对应唯一的CS，表征从设备是否被主设备选中，通常低电平有效。CS有效期间才是主从设备间一次有效的SPI传输，可以传输多组多位数据。SPI串行时钟SCLK也由主设备产生，主从设备按SPI串行时钟SCLK的采样沿/发送沿收/发数据；主设备在采样沿采样接收从设备发送的MISO数据，在发送沿发送数据到MOSI给从设备；从设备在采样沿采样接收主设备发送的MOSI数据，在发送沿发送数据到MISO给主设备。
发送沿是时钟信号的电平跳变边沿，为上升沿或下降沿，在一个时序图中，发送沿是时序分析的起点。
图3示出了本发明第一实施例从设备串行通信方法的流程图，该方法由从设备串行通信装置实现，具体步骤包括：
步骤S301：接收串行时钟信号和接收数据。
在SPI从设备的片选信号CS有效之前，接收来自主设备的串行时钟信号SCLK，经由数据接入端(MOSI)接收要发送的数据(DATA)，并存储在数据存储模块中。
串行时钟信号SCLK为SPI主设备系统时钟信号，由主设备产生。
步骤S302：与系统时钟信号同步，对数据进行移位获得位数据。
系统时钟信号SYSCLK为SPI从设备内部的系统时钟，用系统时钟信号SYSCLK同步并检测串行时钟信号SCLK的边沿，获得使能信号ENBIT。使能信号ENBIT维持相应的一个有效时间段，有效时间段从串行时钟信号的边沿延迟第一时间段开始，并且有效时间段持续第二时间段，第一时间段和所述第二时间段分别包括至少一个第二时钟周期。例如：系统时钟信号SYSCLK的周期是第二时钟周期，使能信号ENBIT的有效时间段相较于串行时钟信号SCLK的边沿会有2～3个系统时钟信号周期的延迟，且有效时间段仅维持一个系统时钟周期的有效。
使能信号ENBIT的边沿与系统时钟信号SYSCLK的边沿同步，在这个边沿对存储器中的数据进行移位，以获得位数据。
所述边沿是时钟信号的电平跳变沿，为上升沿或下降沿，也称为发送沿。
步骤S303：与串行时钟信号同步，锁存并发送预移位的位数据。
在串行时钟信号SCLK的边沿即发送沿，对预移位的位数据进行锁存和发送，锁存在第二锁存模块，发送到选择模块。
所述预移位的位数据是指本个发送沿发送的数据是系统时钟信号SYSCLK同步并检测上个 发送沿获得的使能信号ENBIT移位的数据，而系统时钟信号SYSCLK同步并检测本个发送沿获得的使能信号ENBIT移位的数据则在下个发送沿时刻进行发送。
使能信号ENBIT相较于串行时钟信号SCLK的边沿有一个延迟，因此根据使能信号ENBIT进行移位的位数据相较于串行时钟信号SCLK的边沿也存在一个延迟，即与串行时钟信号同步，锁存并发送的移位位数据是根据检测串行时钟信号SCLK上个周期的边沿获得的使能信号移位的位数据。
步骤S304：生成选择信号，选择模块根据选择信号选择输出位数据。
选择信号SEL是根据串行时钟信号SCLK得到的。在串行时钟信号SCLK的第一个发送沿到来之前，选择信号SEL为1，在第一个发送沿之后，选择信号SEL为0。当选择信号SEL为1时，选择模块连接至第一锁存输出端，当选择信号SEL为0时，选择模块连接至第二锁存输出端。
上述步骤仅示出了从设备串行通信方法在数据传输开始后，即从第一个发送沿开始的数据传输流程。在从设备正式开始传输数据前，即第一个发送沿之前，该方法还包括：在第一个发送沿之前，准备好一个移位位数据，以便在第一个发送沿时刻发送。根据SPI从设备模式的不同选择，该方法还包括：在提前准备好一个移位位数据之前，进行一个位数据的移位并锁存，将其移位并锁存至第一锁存模块，并在第一个发送沿之前将其发送到数据输出端MISO。
图4示出了本发明第二实施例从设备串行通信方法的流程图，与图3示出的方法相比较，图4是一个优选地实施例，不同之处在于增加了一个驱动时钟信号GSCLK，在驱动时钟的边沿对移位位数据进行锁存和发送，该方法的步骤包括：
步骤S401：接收串行时钟信号和接收数据。
在SPI从设备的片选信号CS有效之前，接收来自主设备的串行时钟信号SCLK，经由数据接入端(MOSI)接收要发送的数据(DATA)，并存储在数据存储模块中。
串行时钟信号SCLK为SPI主设备系统时钟信号，由主设备产生。
步骤S402：根据串行时钟信号获得驱动时钟信号。
增加一个模块，输入为串行时钟信号SCLK，输出为驱动时钟信号GSCLK，具体的，驱动时钟信号GSCLK可以由变换相位和/或门控串行时钟信号SCLK生成。仅在CS有效期间使能门控，允许驱动时钟信号GSCLK工作。
步骤S403：与系统时钟信号同步，对数据进行移位获得位数据。
系统时钟信号SYSCLK为SPI从设备内部的系统时钟，用系统时钟信号SYSCLK同步并检测串行时钟信号SCLK的边沿，获得使能信号ENBIT。使能信号ENBIT维持相应的一个有效时间段，有效时间段从串行时钟信号的边沿延迟第一时间段开始，并且有效时间段持续第二时间段， 第一时间段和所述第二时间段分别包括至少一个第二时钟周期。例如：系统时钟信号SYSCLK的周期是第二时钟周期，使能信号ENBIT的有效时间段相较于串行时钟信号SCLK的边沿会有2～3个系统时钟信号周期的延迟，且有效时间段仅维持一个系统时钟周期的有效。
使能信号ENBIT的边沿与系统时钟信号SYSCLK的边沿同步，在这个边沿对存储器中的数据进行移位，以获得位数据。
所述边沿是时钟信号的电平跳变沿，为上升沿或下降沿，也称为发送沿。
步骤S404：与驱动时钟信号同步，锁存并发送预移位的位数据。
在驱动时钟信号SCLK的边沿即发送沿，对预移位的位数据进行锁存和发送，锁存在第二锁存模块，发送到选择模块。
所述预移位的位数据是指本个发送沿发送的数据是系统时钟信号SYSCLK同步并检测上个发送沿获得的使能信号ENBIT移位的数据，而系统时钟信号SYSCLK同步并检测本个发送沿获得的使能信号ENBIT移位的数据则在下个发送沿时刻进行发送。
在第二实施例中，由于驱动时钟由变换相位和/或门控串行时钟信号SCLK获得，因此驱动时钟的边沿与串行时钟的边沿同步。
使能信号ENBIT相较于串行时钟信号SCLK的边沿有一个延迟，因此根据使能信号ENBIT进行移位的位数据相较于串行时钟信号SCLK的边沿也存在一个延迟。与驱动时钟信号GSCLK同步，即与串行时钟信号SCLK同步，锁存并发送的移位位数据是根据检测串行时钟信号SCLK上个周期的边沿获得的使能信号移位的位数据。
步骤S405：生成选择信号，选择模块根据选择信号选择输出位数据。
选择信号SEL是根据串行时钟信号SCLK和驱动时钟信号GSCLK得到的。在串行时钟信号SCLK的第一个发送沿到来之前，选择信号SEL为1，在第一个发送沿之后，选择信号SEL为0。当选择信号SEL为1时，选择模块连接至第一锁存输出端，当选择信号SEL为0时，选择模块连接至第二锁存输出端。
上述步骤仅示出了从设备串行通信方法在数据传输开始后，即从第一个发送沿开始数据传输流程。在从设备正式开始传输数据前，即第一个发送沿之前，该方法还包括：在第一个发送沿之前，准备好一个移位位数据，以便在第一个发送沿时刻发送。根据SPI从设备模式的不同选择，该方法还包括：在提前准备好一个移位位数据之前，进行一个位数据的移位并锁存，将其移位并锁存至第一锁存模块，并在第一个发送沿之前将其发送到数据输出端MISO。
图5示出了本发明实施例从设备串行通信的四种工作模式。如图所示，根据系统时钟的相位CPHA和极性CPOL，将其分为四种工作方式。
方式一(SPI0)：极性CPOL为0，相位CPHA为0，
方式二(SPI1)：极性CPOL为0，相位CPHA为1，
方式三(SPI2)：极性CPOL为1，相位CPHA为0，
方式四(SPI3)：极性CPOL为1，相位CPHA为1，
极性CPOL，表示SPI在空闲时，串行时钟信号SCLK是高电平还是低电平。若CPOL被设为1，那么该设备在空闲时串行时钟信号SCLK管脚下的时钟信号为高电平。当CPOL被设为0时则正好相反。
相位CPHA，表示SPI设备是在串行时钟信号SCLK管脚上的时钟信号变为上升沿时触发数据采样，还是在串行时钟信号SCLK变为下降沿时触发数据采样。若CPHA被设置为1，则SPI设备在串行时钟信号SCLK变为下降沿时触发数据采样，在上升沿时发送数据。当CPHA被设为0时也正好相反。
在本发明中，四种模式的区别还表现为：
表一：SPI四种模式的区别
Figure PCTCN2019078699-appb-000001
从图5和表格一中可以看出，SPI模式2与模式0的发送数据节拍是一样的，唯一不同在于模式2其驱动时钟信号GSCLK与串行时钟信号SCLK同相。
SPI模式1与模式3的发送数据节拍一样，但是模式1驱动时钟信号GSCLK与串行时钟信号SCLK同相，模式3驱动时钟信号GSCLK与串行时钟信号SCLK反相。
SPI模式1与模式0发送数据节拍的区别在于：SPI模式0在第一个发送沿到来之前已经将第一位数据发送，而模式1则在第一个发送沿之后发送第一位数据。
在模式1和模式3中，所有发送数据都从第二锁存模块发送出去，选择信号SEL一直保持为0。在模式0和模式2中，第一个发送数据来自第一锁存模块，其余发送数据来自第二锁存模块，选择信号SEL的电平在第一个发送沿之前为1，在第一个发送沿之后保持为0.
图6示出了本发明第三实施例用于串行通信的从设备的结构框图，该图具体为实现图4所示流程图所对应的结构框图。如图所示，本发明实施例SPI从设备200可以分成系统时钟域D1和 驱动时钟信号GSCLK域D2，还包括时钟模块310，选择模块214。
所述系统时钟域D1，包括边沿检测模块110，存储模块130，逻辑模块120和第一锁存模块211。
所述驱动时钟信号域D2包括第二锁存模块212和选择信号生成模块213。
边沿检测模块110，使用内部系统时钟SYSCLK检测串行时钟信号SCLK的发送沿，得到维持一个内部系统时钟周期的发送沿使能信号ENBIT。
存储模块130，存储所有待发送数据。
逻辑模块120，从存储模块130取一组一组的发送数据，以及在检测得到一个使能信号ENBIT时移位发送数据组中的一个位数据BITDATA到第二锁存模块212。
第一锁存模块211，包括一个触发器和控制逻辑，在SPI模式0和模式2中使用，在每次传输开始前锁存好该次传输第一组第一位发送数据，并在CS有效之后发送第一位位数据，且在本次传输中一直保持。
时钟模块310，仅在CS有效时使能门控，在SPI模式0和模式3中取反相串行时钟信号SCLK，模式1和模式2取同相串行时钟信号SCLK，从而得到驱动时钟信号GSCLK。驱动时钟信号GSCLK只在CS有效期间工作，并且驱动时钟信号GSCLK的发送沿对应于SPI各种模式中串行系统时钟SCLK的发送沿，驱动时钟信号GSCLK的发送沿在各种模式中都是上升沿，从而驱动时钟信号域D2统一用上升沿触发器工作。
第二锁存模块212，包括一个触发器，驱动时钟信号GSCLK的发送沿作用于触发器时钟端，锁存及发送系统时钟域D1中预先移位准备好的发送位数据BITDATA，并经由第二锁存模块212的输出端发送到选择模块214。
选择信号生成模块213，包括一个触发器和控制逻辑，用于生成选择信号SEL并选择发送位数据输出，其要求是，SPI模式0和模式2的选择信号在第一个发送沿之前为1，第一个发送沿之后为0，并且一直保持0到一次SPI传输结束；SPI模式1和模式3一直保持为0。
选择模块214，用选择信号SEL选择系统时钟域D1中的第一锁存模块211的输出端数据或者驱动时钟信号域D2中的第二锁存模块212的输出端数据。具体而言，当选择信号SEL为1时选择第一锁存模块211的输出端数据，当选择信号SEL为0时选择第二锁存模块212的输出端数据。
图7示出了本发明第四实施例SPI从设备SPI模式0发送数据方法的时序图。结合图5，该时序图分为两个部分，虚线上方信号工作于系统时钟域D1，虚线下方信号工作于驱动时钟信号GSCLK域D2。
SPI模式0的驱动时钟信号GSCLK是取串行时钟信号SCLK的反相位。
CS变为低电平前，系统时钟域D1中，从设备从存储模块130中取出第一组数据，并把第一位数据存于BIT0第一锁存模块211，并且移位把第一个发送沿将要发送的数据BITDATA移到BIT1-N第二锁存模块212。同时，系统时钟域D1生成一个异步复位信号，复位驱动时钟信号GSCLK域D2中的选择信号SEL为1。
CS变为低电平后，在驱动时钟域D2中，第一个发送沿前，选择信号SEL为1，选择模块214选择BIT0第一锁存模块211的bit 0输出到MISO上为bit 0。第一个发送沿后，驱动时钟信号GSCLK经由第二锁存模块212锁存并发送BITDATA到选择模块214，选择信号SEL变换为0，选择模块214选择第二锁存模块212的数据输出到MISO上。
同时，在系统时钟域D1中，系统时钟SYSCLK检测串行时钟信号SCLK的发送沿得到使能信号ENBIT，逻辑模块120根据使能信号ENBIT进行一个位数据BITDATA的移位，该位数据BITDATA移位至第二锁存模块212。
具体的如图7所示，在第一个发送沿t0时刻之前，BIT0第一锁存模块211中的位数据bit0已经被输出到MISO上，在t0时刻，驱动时钟信号GSCLK锁存并发送出传输开始前已经准备好的bit1，同时也是BIT1-N第二存储模块212中的bit 1，然后被选择模块214选择输出到MISO上为bit1。
同时，在t0时刻，串行时钟信号SCLK发送沿被系统时钟SYSCLK检测到，生成使能信号ENBIT(维持一个系统时钟SYSCLK周期有效时间段)，该使能信号ENBIT在t1时刻移位数据得到bit2，为第二个发送沿准备好数据。
在第二个发送沿t2时刻，驱动时钟信号GSCLK锁存并发送出传输开始前已经准备好的bit2，即在第二存储模块中的bit2，然后被选择模块214选择输出到MISO上为bit2。
同时，在t2时刻，串行时钟信号SCLK发送沿被系统时钟SYSCLK检测到，生成使能信号ENBIT，该使能信号在t3时刻移位数据得到bit3，为第三个发送沿准备好数据。
t4时刻即为第三个发送沿时刻，按照上述节拍，流水线地进行下去发送数据。第一组数据发送完毕后，从存储器取出下一组数据发送，直至本次SPI传输结束(CS从低变高成无效)。
在传输过程中，只要系统时钟SYSCLK的时钟周期为串行系统时钟SCLK周期的至少三倍，就可以在串行系统时钟信号SCLK的发送沿到来时，待发送数据DATA1足够稳定，满足BITDATA的预备时间T1。
图8示出了本发明第五实施例SPI从设备SPI模式1发送数据方法的时序图，如图所示，该时序图分为两个部分，虚线上方信号工作于系统时钟域D1，虚线下方信号工作于驱动时钟信号域 D2。SPI模式1的驱动时钟信号GSCLK是取串行时钟信号SCLK的同相位。
CS变为低电平前，系统时钟域D1中，从设备从存储模块130取出第一组数据，并把第一位数据bit 0移位到第二锁存模块212。选择信号SEL一直保持为0。
CS变为低电平后，在驱动时钟域D2中，选择信号SEL在第一个发送沿之前和之后都一直保持为0，选择模块214根据选择信号SEL选择第二锁存模块212的数据输出到MISO上。
同时在系统时钟域D1中，系统时钟SYSCLK检测串行时钟信号SCLK的发送沿得到使能信号ENBIT，逻辑模块120根据使能信号ENBIT进行将存储模块130中的一个位数据进行移位得到BITDATA，该位数据BITDATA移位至第二锁存模块212。
具体的如图8所示，在第一个发送沿t0时刻之前，将存储模块130中的数据移位获得BITDATA，在t0时刻，驱动时钟信号GSCLK锁存并发送出传输开始前已经准备好的bit0，同时也是BIT1-N第二存储模块212中的bit 0，然后被选择模块214选择输出到MISO上为bit0。
同时，在t0时刻，串行时钟信号SCLK发送沿被系统时钟SYSCLK检测到，生成使能信号ENBIT(维持一个系统时钟SYSCLK周期有效时间段)，该使能信号ENBIT在t1时刻移位数据得到bit1，为第二个发送沿准备好数据。
在第二个发送沿t2时刻，驱动时钟信号GSCLK锁存并发送出传输开始前已经准备好的bit1，即在第二存储模块中的bit1，然后被选择模块214选择输出到MISO上为bit1。
同时，在t2时刻，串行时钟信号SCLK发送沿被系统时钟SYSCLK检测到，生成使能信号ENBIT，该使能信号在t3时刻移位数据得到bit2，为第三个发送沿准备好数据。
t4时刻即为第三个发送沿时刻，按照上述节拍，流水线地进行下去发送数据。第一组数据发送完毕后，从存储器取出下一组数据发送，直至本次SPI传输结束(CS从低变高成无效)。
本发明提供的用于串行通信的从设备及方法，能够大大降低系统时钟SYSCLK/串行时钟信号SCLK的频率比例，提高从设备数据发送速率，或者降低从设备系统时钟SYSCLK频率。下面通过两个实例来说明本发明与现有技术相比的有益效果。
假设从设备发送数据传输延迟(PAD/board delay)时间(图7中的T3)为15ns(其他相关细微次要延时此处不做考虑，可以统一计入此总延时)，接收端接收从设备的发送数据的建立时间(图7中的T4)最小要求为5ns，以此为例，比较两种方案：
表二：系统时钟信号SYSCLK为50MHz时能支持的SPI串行时钟信号SCLK的最高频率
Figure PCTCN2019078699-appb-000002
Figure PCTCN2019078699-appb-000003
从表二可以看出，同样系统时钟信号SYSCLK为50MHz，原方案支持SPI串行时钟信号SCLK最高频率为6.25MHz，本方案可支持SPI串行时钟信号SCLK最高频率到16.6MHz。
表三：SPI串行时钟信SCLK为10MHz时，对系统时钟信号SYSCLK最低频率要求
Figure PCTCN2019078699-appb-000004
从表三可以看出，同样SPI串行时钟信号SCLK为10MHz，原方案要求系统时钟信号SYSCLK最低频率为100MHz，本方案要求系统时钟信号SYSCLK最低频率为33MHz。
通过上述两个表格的比较，可以清楚的看出，在SPI系统时钟SYSCLK的频率确定时，本发明中对串行时钟信号SCLK的支持频率有大幅提高，因此可以提高SPI数据传输的速率；而在SPI串行时钟信号SCLK频率确定时，本发明中对系统时钟SYSCLK的频率要求大幅降低，因此可以降低功耗。因此，本发明在提高数据传输率和降低功耗方面有很好的效果。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (17)

  1. 一种用于从设备的串行通信方法，其特征在于：
    经由时钟信号端接收串行时钟信号；
    经由数据输入端接收数据，所述数据包括多个连续的位数据；
    与系统时钟信号同步，对所述数据进行移位以获得位数据；以及
    与所述串行时钟信号同步，锁存所述位数据，以及经由数据输出端发送至少一部分锁存的位数据，
    其中，所述串行时钟信号和所述系统时钟信号分别具有第一时钟周期和第二时钟周期，所述第一时钟周期大于所述第二时钟周期。
  2. 根据权利要求1所述的串行通信方法，其特征在于，在所述串行时钟信号的连续周期中，分别对所述数据的选择位数据进行移位和锁存以及发送。
  3. 根据权利要求1所述的串行通信方法，其特征在于，还包括：根据所述串行时钟信号产生驱动时钟信号，其中，在所述驱动时钟信号的边沿发送所述位数据。
  4. 根据权利要求3所述的串行通信方法，其特征在于，所述驱动时钟信号由所述串行时钟信号经过门控和/或相位变换得到。
  5. 根据权利要求1所述的串行通信方法，其特征在于，对所述数据进行移位的步骤包括：
    在所述串行时钟信号的第一时钟周期中，延迟至少一个第二时钟周期，从而获得与所述系统时钟信号同步的使能信号；以及
    根据所述使能信号，对所述数据进行移位以获得位数据。
  6. 根据权利要求5所述的串行通信方法，其特征在于，还包括：根据所述使能信号，对所述位数据进行移位以获得第一位数据，以及锁存所述第一位数据，以及发送锁存的第一位数据。
  7. 根据权利要求6所述的串行通信方法，其特征在于，还包括：根据所述串行时钟信号得到选择信号，用于选择性地将所述数据的第一位数据和其余位数据提供到数据输出端进行发送。
  8. 根据权利要求1所述的串行通信方法，其特征在于，根据所述从设备的工作模式，在所述串行时钟信号的上升沿或下降沿发送所述位数据。
  9. 根据权利要求1所述的串行方法，其特征在于，根据所述从设备的工作模式，在所述串行时钟信号的第一个边沿之前或之后发送所述第一位数据。
  10. 一种用于串行通信的从设备，所述从设备经由时钟信号端接收串行时钟信号，经由数据输入端接收数据，以及经由数据输出端发送所述数据，其特征在于，所述从设备包括：
    存储模块，用于存储所述数据；
    逻辑模块，与存储模块耦接，用于与系统时钟信号同步，对所述数据进行移位以获得位数据；
    第一锁存模块，与逻辑模块耦接，用于锁存所述数据的第一位数据；
    第二锁存模块，与逻辑模块耦接，用于锁存所述数据的其余位数据；
    选择信号生成模块，用于获得与所述串行时钟信号同步的选择信号；
    选择模块，与第一锁存模块、第二锁存模块和选择信号生成模块耦接，用于根据选择信号将所述第一位数据和所述其余位数据之一提供至所述数据输出端，
    其中，所述串行时钟信号和所述系统时钟信号分别具有第一时钟周期和第二时钟周期，所述第一时钟周期大于所述第二时钟周期。
  11. 根据权利要求10所述的从设备，其特征在于，在所述串行时钟信号的连续周期中，所述逻辑模块和所述第二锁存模块分别对所述数据的选择位数据进行移位和锁存以及发送。
  12. 根据权利要求10所述的从设备，其特征在于，还包括：
    边沿检测模块，用于在所述串行时钟信号的第一时钟周期中，延迟至少一个第二时钟周期，从而获得与所述系统时钟信号同步的使能信号。
  13. 根据权利要求10所述的从设备，其特征在于，还包括：
    时钟模块，用于对所述串行时钟信号经过门控和/或相位变换得到驱动时钟信号，
    其中，所述选择信号生成模块根据所述驱动时钟信号的边沿检测生成所述选择信号。
  14. 根据权利要求10所述的从设备，其特征在于，所述逻辑模块根据从设备的工作模式选择将所述第一位数据移位到所述第一锁存模块或所述第二锁存模块。
  15. 根据权利要求10所述的从设备，其特征在于，所述第一锁存模块包括触发器和控制逻辑，用于锁存和输出第一位数据。
  16. 根据权利要求10所述的从设备，其特征在于，所述第二锁存模块，包括触发器，所述驱动时钟信号作用于触发器的时钟端，用于锁存和输出其余位数据。
  17. 根据权利要求10所述的从设备，其特征在于，所述选择信号生成模块包括触发器和控制逻辑模块，用于控制选择信号。
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