WO2023142444A1 - 确定性现场总线网络数据转发二分频锁存缓冲电路及应用 - Google Patents

确定性现场总线网络数据转发二分频锁存缓冲电路及应用 Download PDF

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WO2023142444A1
WO2023142444A1 PCT/CN2022/112953 CN2022112953W WO2023142444A1 WO 2023142444 A1 WO2023142444 A1 WO 2023142444A1 CN 2022112953 W CN2022112953 W CN 2022112953W WO 2023142444 A1 WO2023142444 A1 WO 2023142444A1
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data
signal
flip
latch
flop
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PCT/CN2022/112953
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English (en)
French (fr)
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徐伟强
王成群
商艳娟
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浙江理工大学
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Priority to US17/938,733 priority Critical patent/US12101088B2/en
Publication of WO2023142444A1 publication Critical patent/WO2023142444A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0829—Packet loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/164—Adaptation or special uses of UDP protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40221—Profibus

Definitions

  • the invention relates to the field of circuit design, in particular to a deterministic fieldbus network data forwarding two-frequency division latch circuit and its application.
  • the linear network topology is the most widely used network connection method, and the data frame is distributed to each control node in a multi-hop manner, in order to ensure the certainty of the data obtained by the control loop and low latency, it is required that the processing time for the control data frame to pass through each control node (one hop) is determined and as small as possible. Due to the use of network transmission, in the process of each hop, the data frame needs to first receive the data from the previous control node, parse the data frame, obtain the data related to itself, reassemble the frame, and then send it to the next control node.
  • the frequency of the receiving and sending clocks of the control PHY chip is the same, and there are differences in phases. Frequency out-of-phase data across clock domains, and in addition to the control terminal’s need to receive/send data on its own nodes, it is necessary to connect a certain cross-clock domain digital circuit with fewer cache units while introducing a cross-clock domain processing circuit. Store a part of the data to realize the data sending and receiving of the control node.
  • the asynchronous FIFO method is the most commonly used data cross-domain processing method, but its empty and full signal logic is complex, and some signal control is difficult to achieve accurately.
  • the handshake mechanism although it can make the data transmit correctly, the transmission The delay is high, which is not suitable for the above application scenarios.
  • the tight coupling method can make the data be transmitted stably under the asynchronous clock, but at least three storage units are used, and the resource utilization rate is low.
  • the purpose of the present invention is to provide a deterministic field bus network data forwarding two-frequency division latch circuit and its application, which can be used as a same-frequency out-of-phase data cross-time domain circuit for the scene of network data forwarding, with high resource utilization and stability Effect.
  • this program provides a deterministic fieldbus network data forwarding two-frequency buffer circuit, including: a data buffer, two buffer units are arranged in the data buffer, and the writing ends of the data buffer are respectively Connect the receiving clock signal, write enable signal and write data, and connect the read terminal to send the clock signal, read enable signal and read data; two frequency division enable latch signal generation module, used to generate the The levels of the first frequency-divided latch signal and the second frequency-divided latch signal are opposite, and the clock frequency of the first frequency-divided latch signal and the second frequency-divided latch signal is exactly half of the receiving clock frequency, Based on the first two-frequency division latch signal, the second two-frequency division latch signal and the receiving enable signal, the data buffer units of different data buffers are selected to write the received data; the shift register includes two initializations that are opposite The first flip-flop and the second flip-flop of the output state, the first flip-flop and the second flip-flop are connected to realize the shift operation, and finally based on the low bit and
  • this solution provides an application of a deterministic fieldbus network data forwarding two-frequency buffer circuit, which is applied to a cross-clock domain data transmission scenario as a same-frequency and out-of-phase data cross-clock domain circuit.
  • this technical solution has the following characteristics and beneficial effects: it can effectively deal with the data cross-domain clock problem in the same-frequency and different-phase data forwarding process, improve the reliability of network data transmission, and reduce packet loss in the data transmission process
  • the rate is high, and the buffering time of the data at the node is fixed and extremely small, which improves the certainty of the entire network transmission.
  • the buffer used in this solution has only two cache units, which cache unit should be stored in the received data is determined by the two-frequency enabling latch signal, and which cache unit needs to be determined by the low value of the shift register Reading data in the unit does not require additional counters to calculate the read and write addresses. Since this solution omits the read and write addresses, the need for a synchronizer is correspondingly omitted, thereby greatly simplifying the circuit structure.
  • the logic of writing data is optimized.
  • This program originally designed the two-frequency division enable latch signal generation circuit to generate two different two-frequency division latch enable signals and write enable signals together as what The indicator signal of the received data is latched at the time, so that different buffer units are selected to store the received data, and the waste of resources caused by the use of a large number of data registers is reduced.
  • the logic of the read-write enable signal is optimized. This scheme synchronizes the write-enable signal under the receiving clock domain to the sending clock domain through a synchronous trigger to obtain a read-out enable signal, thereby controlling the logic through explicit synchronization. Implicit synchronous data, while completing data cross-clock domain processing, ensures that data is almost transmitted in a non-resident memory manner. In addition, this solution uniquely designs a shift register to determine which cache unit to read data from, and omits the use of other complex logic to index data read units.
  • Fig. 1 is a schematic diagram of the circuit structure of the deterministic fieldbus network data forwarding two-frequency division latch buffer circuit provided by this solution.
  • Fig. 2 is the circuit signal timing diagram of the deterministic fieldbus network data forwarding two-frequency division latch buffer circuit provided by this scheme.
  • Fig. 3 is a logic schematic diagram of controlling the data input buffer unit based on the deterministic fieldbus network data forwarding frequency-divided by two latch signal.
  • FIG. 4 is a logical schematic diagram of reading data based on a shift register.
  • the term “a” should be understood as “at least one” or “one or more”, that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element
  • the quantity can be multiple, and the term “a” cannot be understood as a limitation on the quantity.
  • This solution provides a deterministic fieldbus network data forwarding two-frequency latch cache circuit, cache method and application, which improves the existing data cross-clock domain circuit and can be applied to the actual deterministic fieldbus network data forwarding Scenario, the deterministic fieldbus network data forwarding two-frequency division latch buffer circuit originally proposed to use two different two-frequency enable latch signals to control the data writing logic, and use the shift register to realize the data writing Read logic, and then realize the cross-clock domain data transmission between the receiving clock domain and the sending clock domain.
  • Figure 1 is a schematic structural diagram of the deterministic fieldbus network data forwarding two-frequency latch buffer circuit provided by this solution.
  • the deterministic fieldbus network data forwarding two-frequency latch buffer circuit includes:
  • a data buffer the data buffer is provided with two buffer units, the write end of the data buffer is connected to the receive clock signal rx_clk, the write enable signal wr_en and the write data wr_data, and the read end is connected to the send clock Signal tx_clk, read enable signal rd_en and read data rdata;
  • the two frequency division enables the latch signal generating module, which is used to generate two levels of the first two frequency division latch signal latch1 and the second two frequency division latch signal latch2, and the first two frequency division latch signal latch2 has opposite levels, and the first two frequency division latch signal
  • the clock frequency of the signal latch1 and the second frequency-divided latch signal latch2 is exactly half of the receive clock frequency. Based on the first two-frequency division latch signal latch0, the second two-frequency division latch signal latch1 and the receiving enable signal rx_valid, the data buffer units of different data buffers are selected to write the received data;
  • the shift register includes two first flip-flops and second flip-flops initialized to opposite output states.
  • the first flip-flop and the second flip-flop are connected to realize the shift operation, and finally based on the shift operation composed of these two flip-flops
  • the low bit shift[0] in the bit register shift[1:0] and the read enable signal rd_en are used to select and read the data rdata stored in the data buffer unit.
  • two two-to-one multiplexers are built in the two-to-two frequency-to-enable latch signal, and the output of each two-to-one multiplexer
  • the terminal is connected to the D input terminal of the D flip-flop, and the output signal of the D flip-flop is inverted and then connected to the 1 input terminal of the two-to-one multiplexer, and the receiving enable signal rx_valid is connected to the selection of each two-to-one multiplexer
  • the control terminal wherein the initial values of the 0 input terminals of the two two-to-one multiplexers are opposite level signals "0" and "1".
  • the receiving enable signal rx_vaild is used to control whether the two two-to-one multiplexers select the signal output of the 0 input terminal or the signal output of the 1 input terminal, and finally the output terminals of the two two-to-one multiplexers are connected to
  • the input terminal of the flip-flop generates the first 2-frequency-divided latch signal latch_0 and the second 2-frequency-divided latch signal latch_1 .
  • the shift register includes a first flip-flop and a second flip-flop connected in sequence, and the write enable signal wr_en written into the data buffer is synchronously generated by a D flip-flop to enable a readout.
  • the enable signal rd_en, the read enable signal rd_en input to the enable control terminal of the shift register enables the shifter to perform an effective shift operation, thereby changing the output state value of the shift register, the low bit shift[0] of the shift register and
  • the read enable signal rd_en is connected to the control terminal of the multi-channel read selector through two-input AND gate signals, and the two input terminals of the multi-channel read selector are respectively connected to two cache units RAM[0] and RAM[1] , select the read cache unit data based on the low bit shift[0] of the shift register and the read enable signal rd_en.
  • the two-frequency latch buffer circuit is suitable for synchronizing the data in the receiving clock domain to the sending clock domain, especially in the transmission scenario of multiple data nodes, the data transmission between two different nodes needs to be processed across clock domains, that is, one node After receiving data from the previous node, it is sent to the next node after proper cross-clock domain processing.
  • This scheme provides improved deterministic fieldbus network data forwarding.
  • the two-frequency latch buffer circuit can be used for cross-clock domain circuit applications. .
  • This solution uniquely designs a data buffer for asynchronous data transmission.
  • the received data in the receiving clock domain is buffered in the data buffer, and then the data is read and sent out in the sending clock domain to realize asynchronous data transmission.
  • the data buffer can choose RAM buffer.
  • the write clock signal rx_clk of the write end of the data buffer is connected to the receive data clock rx_clk
  • the write enable signal wr_en is connected to the receive enable signal rx_valid
  • the write data wr_data is the received data rx_data that needs to be processed across clock domains.
  • the read clock tx_clk at the output terminal is connected to the transmit data clock tx_clk.
  • the read enable signal rd_en is a signal obtained by receiving the enable signal rx_valid after being synchronized by the D flip-flop.
  • the read data rdata is the data tx_data to be sent to the next node.
  • the two channels of frequency-by-two enable latch signals generated by the original design of the two-way frequency-division enable latch signal generation module are based on the two-way frequency division
  • the frequency enable latch signal is used to determine which cache unit the written data should be stored in; the low bit value of the original shift register is used to determine which cache unit to read the data from. It is necessary to consider which address encoding method to use to write the read and write address signals. In the traditional way, when the read and write addresses involving different clock domains are transmitted across clock domains, a synchronizer is required to realize the correct exchange of information in the two clock domains, and then generate corresponding logic control signals. However, since there is no read/write address in this solution, the need for synchronization is omitted, thereby simplifying the circuit structure.
  • the data buffer of this solution only needs two built-in cache units, which greatly reduces the number of cache units and improves the utilization rate of each cache unit.
  • the The two-frequency division enables the latch signal generating module to generate the first two-frequency division latch signal and the second two-frequency division latch signal, based on the first two-frequency division latch signal, the second two-frequency division latch signal and the receiving enable Can signal together to determine the cache location of the written data and control when to write the received data.
  • the structure of the two-frequency division enable latch signal generation module is shown in the dotted line box in Figure 1.
  • the selector in the two-frequency division enable latch signal is a two-to-one multiplexer, and two two-to-one multiplexers
  • the initial values of the 0 input terminals of the device are designed as "0" and "1" respectively. Since the generated frequency-divided-by-2 enable latch signal depends on the receive enable signal, the change of the frequency-divided-by-2 enable latch signal lags half a clock cycle of receiving valid data.
  • This design cleverly sets the initial value of the 0 input terminal of the two two-to-one multiplexers to the opposite level signal, once the receiving enable signal rx_valid is detected to jump to high level and any one of the two frequency divisions is enabled When the latch signal becomes high level, the data can be latched into the corresponding cache unit without missing the storage of the first data.
  • the receive enable signal rx_vaild When no data is received, the receive enable signal rx_vaild is low level, the output terminal of the multiplexer whose initial value is “1" at the 0 input terminal outputs a high level, and the initial value at the 0 input terminal is "0".
  • the output terminal of the multiplexer outputs a low level, and the output terminal of each two-to-one multiplexer is connected to the D input terminal of the D flip-flop, so that the two flip-flops generate the first two-frequency division latch signal and The second two-frequency division latch signal, at this moment, one signal in the first two-frequency division latch signal latch0 and the second two-frequency division latch signal latch1 is low level, and one signal is high level, and the first two The frequency-divided latch signal latch0 and the second two-frequency-divided latch signal latch1 are inverted and then connected to the 1 input end of the corresponding two-to-one multiplexer.
  • the receive enable signal rx_vaild When valid data is received, the receive enable signal rx_vaild is high level, and the high level receive enable signal rx_valid signal controls two two-to-one multiplexers to select the 1 input as the input signal, because the input of the 1 input
  • the signal is the inverse value of the last two-frequency division enable latch signal latch_0 and latch_1, so the output values of the two two-to-one multiplexers are also the last first two-frequency division enable latch signal latch_0 and The second frequency division by two enables the inversion value of the latch signal latch_1, and finally connects to the D flip-flop to generate a waveform similar to a clock signal.
  • the first frequency-divided-by-2 enabling latch signal latch_0 and the second frequency-dividing-by-2 enabling latch signal latch_1 are the frequency-divided signals of the receiving clock signal when the receiving enabling signal rx_vaild is at a high level, and this The two signals are out of phase by one receive clock period.
  • the first two-frequency division enable latch signal latch_0 and the reception enable signal rx_vaild are input to the second input
  • the AND gate obtains the first selection signal
  • the second two-frequency division latch signal and the receiving enable signal are input to the two-input AND gate to obtain the second selection signal
  • the buffer unit is selected based on the first selection signal and the second selection signal to write data.
  • the cache units corresponding to the first selection signal and the second selection signal are different.
  • the write data is selected to be stored in the second cache unit of the data buffer; when the second selection signal is at a high level, the write data is selected to be Stored in the first cache unit of the data cache.
  • the write data is directly placed in the corresponding cache unit, omitting the use of complex counters to count the write pointer.
  • FIG. 3 shows a schematic process of selecting a cache unit. Assuming that the received data are a and b, when the received data is valid, the corresponding receive enable signal is high level, and the high level receive enable signal controls the two-to-one multiplexer to input the signal from the 1 input terminal, And generate the receive clock frequency-divided by 2 signals, that is, the first 2-divided enabling signals latch_0 and latch_1. When latch_0 is high, the received second data b will be stored in the second cache unit RAM[1]. When latch_1 is high, the first received data a will be stored in the first In the cache unit RAM[0].
  • the frequency division by two of the clock is used as the clock trigger edge of the flip-flop, and the data is stored in the flip-flop, in order not to lose Any valid data storage needs to use two flip-flops to store data respectively on the rising edge and falling edge of the frequency-divided clock.
  • This design requires a large number of flip-flops to realize the synchronous registration of data.
  • the cross-clock domain method proposed in this program stores data into the data buffer RAM, and only needs to generate two different two-frequency division latch enable signals to realize data synchronization and buffering, avoiding the use of a large number of flip-flops. A waste of resources comes.
  • the frequency of the frequency-division enable latch signal is half of the receive clock frequency, and the difference between the two high levels of the frequency-divide enable latch signal is one receive clock cycle, each time the frequency-divide enable latch signal is detected When the latch signal is at a high level, the data in the cache unit in the data buffer will be updated.
  • the storage time of each data in the data buffer is 2 receiving clock cycles, and it must be read in time when the data in these two clock cycles is stable. Otherwise, the previously stored data will be overwritten by the newly updated data, resulting in data loss.
  • this program uses a D flip-flop to establish a connection between the write enable signal wr_en and the read enable signal rd_en, and uses a D flip-flop to synchronize the write enable signal wr_en under the receiving clock domain to the sending In the clock domain, the read enable signal rd_en is obtained.
  • the benefit of such a design is that the data resides in the data buffer for a short period of time. When the data is processed across the clock domain, the data is almost transmitted in a non-resident memory mode, which reduces the time for data processing at the node and meets the requirements for buffering data.
  • the output end of the first flip-flop is connected to the input end of the second flip-flop
  • the output end of the second flip-flop is connected to the input end of the first flip-flop
  • the first flip-flop and the second flip-flop The initial values of the flip-flops are set to the "0" and "1" states.
  • the read enable signal rd_en When the synchronized read enable signal rd_en is high, the read enable signal rd_en is input to the two flip-flops as a shift enable signal, so that the first flip-flop and the second flip-flop start to shift , the state value of the entire shift register will cycle between "01" and "10".
  • the data is read from the first cache unit RAM[0] of the data buffer and output to data_out, when the low bit shift[0] and the read
  • the enable signal rd_en passes through the AND gate and outputs a low level
  • the data is read from the second cache unit RAM[1] of the data cache and output to data_out, and finally the output data data_out of the multiplex read selector is connected to the data cache
  • the read data terminal of the device obtains the read data rdata, and the read data rdata data is the data tx_data to be sent to the next node.
  • FIG. 4 shows a schematic process of reading a cache unit.
  • the two data a and b just received are respectively stored in the first cache unit RAM[0] and the second cache unit RAM[1], and the read enable signal obtained synchronously according to the receive enable signal, when the read enable When the enable signal is at a high level, the shift register starts a shift cycle to obtain different shift state values. According to the state value of the lowest bit of the shift register, select to read data from different cache units. When the lowest bit shift[0] of the shift register is high level, read data a from RAM[0], and when the lowest bit shift[0] of the shift register is low level, read data a from RAM[1] b. The entire way of reading data ensures that the order of the sent data is consistent with the order of the received data.
  • the synchronization between the read and write logic of this solution only involves one D flip-flop, and the data at the read and write ends are implicitly synchronized through the explicit synchronous read and write enable signal.
  • the received data changes on the falling edge of the receive clock and remains stable on the rising edge of the receive clock.
  • the generated two-frequency enable latch signal is de-jumped at the rising edge of the receiving clock, so that the collected data can be guaranteed
  • the incoming data is stable. When reading data, it is also necessary to ensure that the data is stable. You cannot directly use the write enable signal to read data.
  • the write enable signal belongs to the receiving clock domain and the read data should be read in the sending clock domain, so the receiving The write enable signal in the clock domain jumps to a high level on the rising edge of the send clock through the D synchronous flip-flop, and then reads the data according to the read enable signal in the send clock domain, which can guarantee to a certain extent Readout data stability. In this way, the data is synchronized from the receiving clock domain to the sending clock domain, and the cross-clock domain processing of data is completed.
  • this scheme provides an application of a deterministic fieldbus network data forwarding two-frequency latch buffer circuit.
  • the deterministic fieldbus network data forwarding two-frequency latching circuit provided by this scheme is used as the Clock domain circuits are applied to data transmission scenarios across clock domains, such as network data forwarding scenarios, or other scenarios where data crosses clock domains.

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Abstract

本发明提供一种确定性现场总线网络数据转发二分频锁存电路及应用，包括数据缓冲器，所述数据缓存器内设两个缓存单元；二分频使能锁存信号产生模块，用于产生电平相反的第一二分频锁存信号和第二二分频锁存信号，基于所述第一二分频锁存信号、第二二分频锁存信号以及接收使能信号选择数据缓冲器的数据缓存单元；移位寄存器，包括两个初始化为相反输出状态的第一触发器和第二触发器，第一触发器和第二触发器之间相连实现移位操作，最终基于这两个触发器组成的移位寄存器中的低位和读出使能信号来选择读取数据缓冲器单元存储的数据，可作为同频异相数据跨时域电路应用于确定性现场总线网络数据转发的场景，具有资源利用率高且稳定的效果。

Description

确定性现场总线网络数据转发二分频锁存缓冲电路及应用 技术领域
本发明涉及电路设计领域，特别涉及一种确定性现场总线网络数据转发二分频锁存电路及应用。
背景技术
在基于以太网技术的现场总线控制网络中，线性网络拓扑结构是使用最为广泛的一种网络连接方式，数据帧以多跳的方式分发到每一个控制节点，为了保证控制回路获取数据的确定性和低时延，需要控制数据帧经过每一个控制节点(一跳)的处理时间确定并且尽可能的小。由于采用网络传输，数据帧在每一跳的过程中，需要首先接收来自上一个控制节点的数据、解析数据帧、获取和自身相关的数据、重新组帧，然后发送到下一个控制节点。在这一过程中，由于控制节点的接收和发送电路采用相互独立的PHY芯片实现，控制PHY芯片的接收和发送的时钟的频率相同，相位存在差异，进而需要引入处理跨域时钟电路来解决同频异相数据跨时钟域问题，另外考虑到控制终端接收/发送本节点数据的需求，因此在引入跨时钟域处理电路的同时需要连接一个确定的，缓存单元较少的跨时钟域数字电路来存储一部分数据实现控制节点的数据发送和接收。
在传统的处理数据跨时钟域方法中，主要有异步FIFO、握手机制方法，紧密耦合方法等。异步FIFO方法是最普遍使用的数据跨域处理方法，但是它空满信号的逻辑产生复杂，有些信号的控制很难做到准确，而对于握手机制方法，它虽然能够使数据正确传输，但是传输的延时较高，不适合上述应用场景，紧 密耦合方法能够使数据在异步时钟下稳定传输，但是使用的存储单元至少3个，资源利用率较低。
因此，需要针对上述需求的一种资源利用率高且稳定的、带有一定缓存能力的确定性现场总线网络数据转发二分频缓存电路。
发明内容
本发明的目的在于提供一种确定性现场总线网络数据转发二分频锁存电路及应用，可作为同频异相数据跨时域电路应用于网络数据转发的场景，具有资源利用率高且稳定的效果。
为实现以上目的，本方案提供了一种确定性现场总线网络数据转发二分频缓存电路，包括：数据缓冲器，所述数据缓存器内设两个缓存单元，数据缓存器的写入端分别连接接收时钟信号、写入使能信号以及写入数据，读取端连接发送时钟信号、读出使能信号以及读出数据；二分频使能锁存信号产生模块，用于产生其中所述第一二分频锁存信号和第二二分频锁存信号的电平相反，且第一二分频存信号和第二二分频锁存信号的时钟频率正好是接收时钟频率的一半，基于所述第一二分频锁存信号、第二二分频锁存信号以及接收使能信号选择不同数据缓冲器的数据缓存单元写入接收的数据；移位寄存器，包括两个初始化为相反输出状态的第一触发器和第二触发器，第一触发器和第二触发器之间相连实现移位操作，最终基于这两个触发器组成的移位寄存器中的低位和读出使能信号来选择读取数据缓冲器单元存储的数据。
第二方面，本方案提供了一种确定性现场总线网络数据转发二分频缓存电路的应用，作为同频异相数据跨时钟域电路被应用于跨时钟域的数据传输场景。
相较现有技术，本技术方案具有以下特点和有益效果：能够有效处理同频 异相数据转发过程中的数据跨域时钟问题，提高网络数据传输的可靠性，减少数据传输过程中的丢包率，且数据在节点的缓冲时间固定缺极小，提高了整个网络传输的确定性。具体的：
1.本方案采用的缓冲器仅具有两个缓存单元，通过二分频使能锁存信号来确定应当将接收的数据存入哪个缓存单元，通过移位寄存器的低位值来确定需要从哪个缓存单元中读取数据，不需要额外的计数器来计算读写地址。由于本方案省去了读写地址，故相应地省去了同步器的需要，进而极大程度地简化了电路结构。
2.优化了写入数据的逻辑，本方案独创性地设计了二分频使能锁存信号产生电路，产生两个不同的二分频锁存使能信号与写入使能信号一起作为何时锁存接收数据的指示信号，从而选择不同的缓存单元存储接收的数据，减少了大量数据寄存器的使用而带来的资源浪费。
3.优化了读写使能信号的逻辑，本方案通过同步触发器将接收时钟域下的写入使能信号同步到发送时钟域下得到读出使能信号，从而通过显性同步控制逻辑来隐性同步数据，在完成数据跨时钟域处理的同时保证了数据几乎以非驻留内存的方式传输。且本方案独创性的设计了移位寄存器来判断从哪个缓存单元中读取数据，省略了使用其他复杂逻辑来索引数据读取单元。
附图说明
图1是本方案提供的确定性现场总线网络数据转发二分频锁存缓存电路的电路结构示意图。
图2是本方案提供的确定性现场总线网络数据转发二分频锁存缓存电路的 电路信号时序图。
图3是基于确定性现场总线网络数据转发二分频锁存信号控制数据输入缓存单元的逻辑示意图。
图4是基于移位寄存器读取数据的逻辑示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
本方案提供了一种确定性现场总线网络数据转发二分频锁存缓存电路、缓存方法及应用，改进了现有的数据跨时钟域电路，可被应用于确定性现场总线网络数据转发的实际场景，该确定性现场总线网络数据转发二分频锁存缓冲电路独创的提出了利用两个不同的二分频使能锁存信号来控制数据的写入逻辑，利用移位寄存器来实现数据的读取逻辑，进而实现了接收时钟域和发送时钟域 的跨时钟域数据传输。
如图1所示，图1是本方案提供的确定性现场总线网络数据转发二分频锁存缓冲电路的结构示意图，该确定性现场总线网络数据转发二分频锁存缓冲电路包括：
数据缓冲器，所述数据缓存器内设两个缓存单元，所述数据缓存器的写入端连接接收时钟信号rx_clk、写入使能信号wr_en以及写入数据wr_data，读取端输连接发送时钟信号tx_clk、读出使能信号rd_en以及读出数据rdata；
二分频使能锁存信号产生模块，用于产生两个其中所述第一二分频锁存信号latch1和第二二分频锁存信号latch2的电平相反，且第一二分频存信号latch1和第二二分频锁存信号latch2的时钟频率正好是接收时钟频率的一半。基于所述第一二分频锁存信号latch0、第二二分频锁存信号latch1以及接收使能信号rx_valid选择不同数据缓冲器的数据缓存单元写入接收的数据；
移位寄存器，包括两个初始化为相反输出状态的第一触发器和第二触发器，第一触发器和第二触发器之间相连实现移位操作，最终基于这两个触发器组成的移位寄存器shift[1:0]中的低位shift[0]和读出使能信号rd_en来选择读取数据缓冲器单元存储的数据rdata。
关于二分频使能锁存信号产生模块的结构：具体的，所述二分频使能锁存信号内设两个二选一多路选择器，每个二选一多路选择器的输出端连接D触发器的D输入端，D触发器输出的信号取反后接入二选一多路选择器的1输入端，接收使能信号rx_valid连接每个二选一多路选择器的选择控制端，其中两个二选一多路选择器的0输入端的初始值为相反的电平信号“0”和“1”。
具体的，所述接收使能信号rx_vaild来控制两个二选一多路选择器是选择0输入端信号输出还是1输入端信号输出，最终两个二选一多路选择器的输出端 连接到触发器的输入端，产生了第一二分频锁存信号latch_0和第二二分频锁存信号latch_1。
关于移位寄存器的结构：具体的，所述移位寄存器包括依次连接的第一触发器和第二触发器，写入数据缓存器的写入使能信号wr_en通过D触发器同步生成读出使能信号rd_en，读出使能信号rd_en输入移位寄存器的使能控制端使移位器进行有效的移位操作，从而改变移位寄存器的输出状态值，移位寄存器的低位shift[0]和读出使能信号rd_en经过两输入与门信号连接到多路读取选择器的控制端，多路读取选择器的两个输入端分别连接两个缓存单元RAM[0]和RAM[1]，基于移位寄存器的低位shift[0]和读出使能信号rd_en选择读取的缓存单元数据。
二分频锁存缓冲电路适用于将接收时钟域的数据同步给发送时钟域，特别地在多数据节点的传输场景中，两个不同节点之间的数据传输需要跨时钟域处理，即一个节点从前一个节点接收到数据后，经过恰当的跨时钟域处理后，发送给下一个节点，本方案提供了改进的确定性现场总线网络数据转发二分频锁存缓冲电路可用于跨时钟域电路应用。
本方案独创性的设计了用于数据异步传输的数据缓存器，接收时钟域的接收数据缓存在数据缓冲器中再在发送时钟域读取数据发送出去以实现数据异步传输，在一些实施例中，数据缓存器可选用RAM缓冲器。
数据缓存器的写入端的写入时钟信号rx_clk与接收数据时钟rx_clk连接，写入使能信号wr_en与接收使能信号rx_valid连接，写入数据wr_data就是接收到的需要跨时钟域处理的数据rx_data。输出端的读时钟tx_clk与发送数据时钟tx_clk连接，读出使能信号rd_en是接收使能信号rx_valid经过D触发器同步后的信号，读出的数据rdata就是即将发送给下一个节点的数据tx_data。
值得说明的是，本方案的数据缓存器内仅设有两个缓存单元，通过独创设计的二分频使能锁存信号产生模块产生的两路二分频使能锁存信号，基于二分频使能锁存信号来判断写入数据应当存储在哪个缓存单元；通过独创的移位寄存器的低位值判断从哪个缓存单元中读取数据，本方案不需要计数器来计算读写地址，也不需要考虑采用哪种地址编码方式编写读写地址信号。传统的方式在涉及不同时钟域的读写地址进行跨时钟域传输时，需要经过同步器同步后才能实现两个时钟域信息的正确交换，进而产生相应的逻辑控制信号。而本方案由于没有读写地址的存在，故省去了同步的需求进而简化了电路结构。
本方案的数据缓存器仅需要内置两个缓存单元，极大程度的减少了缓存单元的数量，提高了每个缓存单元的利用率，为了合理的控制缓存单元的数据的读写，本方案的二分频使能锁存信号产生模块产生第一二分频锁存信号和第二二分频锁存信号，基于第一二分频锁存信号，第二二分频锁存信号以及接收使能信号一起判断写入数据的缓存位置以及控制何时写入接收的数据。
二分频使能锁存信号产生模块的结构如图1中虚线框所示，二分频使能锁存信号中的选择器为二选一多路选择器，两个二选一多路选择器的0输入端的初始值分别设计为“0”和“1”。由于产生的二分频使能锁存信号依赖于接收使能信号，会导致二分频使能锁存信号的变化滞后接收有效数据半个时钟周期。本设计巧妙地将两个二选一多路选择器的0输入端的初始值设置为相反的电平信号，一旦检测到接收使能信号rx_valid跳变为高电平并且任意一个二分频使能锁存信号变为高电平时，就可以锁存数据到相应的缓存单元中，不会错过第一个数据的存储。
当没有接收到任何数据时，接收使能信号rx_vaild为低电平，0输入端初始值为“1”的多路选择器的输出端输出高电平，0输入端初始值为“0”的多路 选择器的输出端输出低电平，每个二选一多路选择器的输出端连接D触发器的D输入端，以使得两个触发器分别产生第一二分频锁存信号和第二二分频锁存信号，此时第一二分频锁存信号latch0和第二二分频锁存信号latch1中的一个信号为低电平，一个信号为高电平，且第一二分频锁存信号latch0和第二二分频锁存信号latch1取反后连接到对应的二选一多路选择器的1输入端。
当接收到有效数据时，接收使能信号rx_vaild为高电平，高电平的接收使能信号rx_valid信号控制两个二选一多路选择器选择1输入端作为输入信号，因为1输入端的输入信号是上一次的二分频使能锁存信号latch_0和latch_1的取反值，所以两个二选一多路选择器的输出值也是上一次的第一二分频使能锁存信号latch_0和第二第二二分频使能锁存信号latch_1的取反值，最终连接到D触发器后会产生类似于时钟信号的波形。换言之，第一二分频使能锁存信号latch_0和第二第二二分频使能锁存信号latch_1在接收使能信号rx_vaild处于高电平时，就是接收时钟信号的二分频信号，并且这两个信号的相位相差一个接收时钟周期。
在获取第一二分频使能锁存信号latch_0和第二第二二分频使能锁存信号latch_1后，第一二分频使能锁存信号latch_0和接收使能信号rx_vaild输入到二输入与门得到第一选择信号，第二二分频锁存信号和接收使能信号输入到二输入与门得到第二选择信号，基于所述第一选择信号和第二选择信号选择缓存单元写入数据。
具体的，当第一选择信号或第二选择信号为高电平时，将写入数据写入缓存单元，且第一选择信号和第二选择信号对应的缓存单元不同。具体的，当所述第一选择信号为高电平时，选择将写入数据存储在数据缓存器的第二个缓存单元中；当所述第二选择信号为高电平时，选择将写入数据存储在数据缓存器 的第一个缓存单元中。这样类似于写指针索引写入地址一样，直接将写入数据放在对应的缓存单元中，省略了使用复杂的计数器来对写指针进行计数。
如图3所示，图3展示了选择缓存单元的示意过程。假设接收到数据为a和b，当接收到的数据有效时对应的接收使能信号为高电平，高电平的接收使能信号控制二选一多路选择器从1输入端输入信号，并产生接收时钟二分频信号即第一二分频使能信号latch_0和latch_1。当latch_0为高电平时，接收到的第二个数据b会存进第二个缓存单元RAM[1]中，当latch_1为高电平时，接收到的第一个数据a会存进第一个缓存单元RAM[0]中。
本发明人想要再次强调的是，在一般的基于二分频的跨时钟域设计方法中，采用时钟的二分频作为触发器的时钟触发边沿，将数据存储在触发器中，为了不丢失任何有效数据的存储，需要在二分频时钟的上升沿和下降沿使用两个触发器分别存储数据，这种设计需要大量的触发器来实现数据的同步寄存。本方案提出的跨时钟域方法将数据存进数据缓存器RAM中，只需要产生两个不同的二分频锁存使能信号就可以实现数据的同步和缓存，避免了大量触发器的使用带来的资源的浪费。
然而由于二分频使能锁存信号的频率是接收时钟频率的一半，二分频使能锁存信号的两个高电平之间相差一个接收时钟周期，每次检测到二分频使能锁存信号为高电平时都会更新数据缓存器中缓存单元内的数据，每个数据在数据缓存器中存储时间为2个接收时钟周期，必须要在这两个时钟周期数据稳定时及时读取数据，否则前面存储的数据会被新更新的数据覆盖，造成数据丢失现象。
本方案为了避免数据丢失，使用D触发器在写入使能信号wr_en和读出使能信号rd_en之间建立联系，使用一个D触发器将接收时钟域下的写入使能信 号wr_en同步到发送时钟域下，得到了读出使能信号rd_en。这样的设计带来的好处是数据在数据缓存器中驻留的时间短暂。数据在完成跨时钟域处理的同时保证了数据几乎以非驻留内存的方式传输，降低了数据在节点处理的时间，同时满足了缓冲数据的需求。
本方案提供的移位寄存器中第一触发器的输出端连接至第二触发器的输入端，第二触发器的输出端连接至第一触发器的输入端，且第一触发器和第二触发器的初始值设置为“0”和“1”状态。
当同步后的读出使能信号rd_en为高电平时，读出使能信号rd_en输入到两个触发器中作为移位使能信号，以使得第一触发器和第二触发器开始进行移位，整个移位寄存器的状态值将在“01”和“10”之间循环。
将移位寄存器的低位shift[0]和读出使能信号rd_en经过一个两输入与门连接到一个二选一的多路读取选择器的选择控制端，多路读取选择器的两个输入端连接到数据缓存器的两个缓存单元。
当低位shift[0]和读出使能信号rd_en同时为高电平时，从数据缓存器的第一个缓存单元RAM[0]中读取数据输出到data_out，当低位shift[0]和读出使能信号rd_en经过与门输出为低电平时，从数据缓存器的第二个缓存单元RAM[1]中读取数据输出到data_out，最终多路读取选择器的输出数据data_out连接到数据缓存器的读取数据端得到读出数据rdata,读出数据rdata数据就是即将发送给下一节点的数据tx_data。
如图4所示，图4展示了读取缓存单元的示意过程。刚刚接收的两个数据a和b分别存在第一个缓存单元RAM[0]和第二个缓存单元RAM[1]中，根据接收使能信号同步得到的读出使能信号，当读出使能信号为高电平时，移位寄存器开始移位循环，得到不同的移位状态值。根据移位寄存器最低位的状态值，选 择从不同的缓存单元读出数据。当移位寄存器最低位shift[0]为高电平时，从RAM[0]中读出数据a，当移位寄存器最低位shift[0]为低电平时，从RAM[1]中读出数据b,整个读取数据的方式保证了发送出去的数据顺序与接收到的数据的顺序相一致。
值得一提的是，本方案的读写逻辑之间的同步只涉及到一个D触发器，通过显性同步读写使能信号来隐性同步读写端的数据。接收的数据是在接收时钟的下降沿变化，在接收时钟的上升沿保持稳定。为了在接收时钟的上升沿稳定的采集数据写入数据缓存器中，产生的二分频使能锁存信号都是在接收时钟的上升沿取反跳变的，这样就能保证采集到的写入数据是稳定的。读取数据时也要保证数据是稳定的，不能直接使用写入使能信号读取数据，写入使能信号属于接收时钟域而读取数据应该是在发送时钟域下读取，所以将接收时钟域下的写入使能信号经过D同步触发器在发送时钟的上升沿跳变为高电平，根据在发送时钟域下的读出使能信号再读取数据，在一定程度上能够保证读出数据的稳定性。数据就是这样从接收时钟域下同步到发送时钟域下，完成数据的跨时钟域处理。
第二方面，本方案提供一种确定性现场总线网络数据转发二分频锁存缓冲电路的应用，本方案提供的确定性现场总线网络数据转发二分频锁存电路作为同频异相数据跨时钟域电路被应用于跨时钟域的数据传输场景，比如网络数据转发场景，或者其他数据跨时钟域的场景。
本发明不局限于上述最佳实施方式，任何人在本发明的启示下都可得出其他各种形式的产品，但不论在其形状或结构上作任何变化，凡是具有与本申请相同或相近似的技术方案，均落在本发明的保护范围之内。

Claims (10)

  1. 一种针对确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，包括：
    数据缓冲器，所述数据缓存器内设两个缓存单元，数据缓存器的写入端分别连接接收时钟信号、写入使能信号以及写入数据，读取端连接发送时钟信号、读出使能信号以及读出数据；
    二分频使能锁存信号产生模块，用于产生第一二分频锁存信号和第二二分频锁存信号，其中所述第一二分频锁存信号和第二二分频锁存信号的电平相反，且第一二分频存信号和第二二分频锁存信号的时钟频率正好是接收时钟频率的一半，基于所述第一二分频锁存信号、第二二分频锁存信号以及接收使能信号选择不同数据缓冲器的数据缓存单元写入接收的数据；
    移位寄存器，包括两个初始化为相反输出状态的第一触发器和第二触发器，第一触发器和第二触发器之间相连实现移位操作，基于第一触发器和第二触发器组成的移位寄存器中的低位和读出使能信号来选择读取数据缓冲器单元内存储的数据。
  2. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，所述确定性现场总线网络数据转发二分频使能锁存信号内设两个二选一多路选择器，每个二选一多路选择器的输出端连接D触发器的D输入端，D触发器输出的信号取反后接入二选一多路选择器的1输入端，接收使能信号连接每个二选一多路选择器的选择控制端，其中两个二选一多路选择器的0输入端的初始值为相反的电平信号“0”和“1”。
  3. 根据权利要求2所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，所述接收使能信号用以控制两个二选一多路选择器是选择0输入端信号输出还是1输入端信号输出，两个二选一多路选择器的输出 端连接到D触发器的输入端，产生了第一二分频锁存信号latch_0和第二二分频锁存信号latch_1。
  4. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，第一二分频使能锁存信号和接收使能信号输入到二输入与门得到第一选择信号，第二二分频锁存信号和接收使能信号输入二输入与门得到第二选择信号，当第一选择信号或第二选择信号为高电平时，将选择不同的数据缓冲器单元输出数据。
  5. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，数据缓存器的写入使能信号通过D触发器同步后生成读出使能信号。
  6. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，所述移位寄存器包括依次连接的第一触发器和第二触发器，第一触发器的输出端连接至第二触发器的输入端，第二触发器的输出端连接至第一触发器的输入端，且第一触发器和第二触发器的初始值设置为“0”和“1”状态。
  7. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，移位寄存器的低位和读出使能信号经过一个两输入与门信号连接到一个二选一多路选择器的选择控制端，二选一多路选择器的两个输入端连接到数据缓存器的两个缓存单元。
  8. 根据权利要求1所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，当两位移位寄存器的低位和读出使能信号同时为高电平时，从数据缓存器的第一个缓存单元中读取数据，当两位移位寄存器的低位和读出使能信号经过与门输出为低电平时，从数据缓存器的第二个缓存 单元中读取数据。
  9. 根据权利要求2所述的确定性现场总线网络数据转发二分频锁存缓冲电路，其特征在于，二分频使能锁存信号中的二选一多路选择器为具有两个选择输入端的选择器。
  10. 一种确定性现场总线网络数据转发二分频锁存缓冲电路的应用，其特征在于，作为同频异相数据跨时钟域电路被应用于跨时钟域的数据传输场景。
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