WO2020191611A1 - 跨时钟域同步电路以及方法 - Google Patents

跨时钟域同步电路以及方法 Download PDF

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Publication number
WO2020191611A1
WO2020191611A1 PCT/CN2019/079663 CN2019079663W WO2020191611A1 WO 2020191611 A1 WO2020191611 A1 WO 2020191611A1 CN 2019079663 W CN2019079663 W CN 2019079663W WO 2020191611 A1 WO2020191611 A1 WO 2020191611A1
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clock
signal
read
write
sampling
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PCT/CN2019/079663
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English (en)
French (fr)
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白玉晶
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华为技术有限公司
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Priority to PCT/CN2019/079663 priority Critical patent/WO2020191611A1/zh
Priority to CN201980094534.6A priority patent/CN113615088B/zh
Publication of WO2020191611A1 publication Critical patent/WO2020191611A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of circuits, and in particular to a cross-clock domain synchronization circuit and related methods.
  • SOC System-on-chip
  • a typical asynchronous circuit processing technology is an asynchronous first-in-first-out (fist-in-fist-out, FIFO) technology.
  • the write address generation logic circuit 101 in the write clock domain generates a binary write pointer and writes the data.
  • the read address generation logic circuit 103 in the read clock domain generates a binary read pointer, and reads the data from the FIFO storage circuit 104.
  • the full/empty indicator generating logic circuit 102 generates a read empty indicator, the read operation is no longer performed, but the write operation can be performed.
  • the full/empty indicator generating logic circuit 102 When the full/empty indicator generating logic circuit 102 generates a full indicator, the write operation is no longer performed, but it can Perform a read operation.
  • the generation of the read empty flag needs to synchronize the write pointer of the write clock domain to the read clock domain.
  • the binary write pointer First, in order to avoid glitches, the binary write pointer must first be converted to Gray code, and then the Gray code is executed with two-beat processing using two-level registers. Or use multi-level registers to perform multi-beat processing, and then convert the processed write pointer into binary, and compare it with the binary read pointer. When the address bits of the two pointers are the same and the status bits are the same, a read null signal is generated.
  • the establishment time refers to the time that the data needs to be input into the register before the rising edge of the clock signal arrives
  • the retention time is the time that the data needs to remain unchanged after the rising edge.
  • the use of the register to perform one-shot processing needs to wait until one clock cycle, then the use of the register to perform the two-beat processing, or the use of multiple registers to perform the two-multiple processing will correspond to a delay of two or more clock cycles, the write pointer is determined by The process of synchronizing the write clock domain to the read clock domain requires a delay of at least two clock cycles. Similarly, the generation of the full mark needs to synchronize the read pointer of the read clock domain to the write clock domain.
  • the synchronization process requires the register to perform two-beat or multi-beat processing, and there is a delay of at least two clock cycles.
  • the write pointer of the write clock domain when the write pointer of the write clock domain is synchronized to the read clock domain to obtain the read empty signal, a delay of at least two clock cycles will be generated.
  • the same read pointer of the read clock domain is synchronized to the write clock domain to obtain a full signal, which will also generate A delay of at least two clock cycles.
  • the full mark will control the increase of the write pointer
  • the read empty mark will also control the increase of the read pointer
  • the read/write pointer will control the writing and reading of data, thus controlling the synchronization of the data in the write clock domain to the read clock domain.
  • the data synchronization between the two clock domains will also have a delay of at least two clock cycles. Due to the above factors, the asynchronous FIFO shown in FIG. 1 has a relatively large delay when performing cross-clock domain processing, thereby reducing the efficiency of data cross-clock domain processing.
  • the first aspect provided by this application provides a cross-clock domain synchronization circuit that can synchronize input data from a write clock domain to a read clock domain.
  • the cross-clock domain synchronization circuit includes a clock domain channel circuit, a write address generation circuit, and a read clock domain.
  • Address generation circuit and data buffer circuit; the write address generation circuit can be driven by the write clock signal to obtain the write address according to the write enable signal, the write address can control the data buffer circuit to receive input data, and the input data is data in the write clock domain; clock
  • the two input terminals of the domain channel circuit respectively input the write enable signal and the clock phase difference.
  • the clock phase difference refers to the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain.
  • the channel circuit can sample the write enable signal to obtain the sampling signal set.
  • the clock domain channel circuit selects the sampling signal from the sampling signal set as the read enable signal according to the clock phase difference; the read address generation circuit can be driven by the read clock signal, The read address can be obtained according to the read enable signal.
  • the read address can control the data buffer circuit to generate output data.
  • the output data is in the read clock domain, then the cross-clock domain synchronization circuit completes the process of input data synchronization from the write clock domain to the read clock domain .
  • the data buffer circuit receives input data according to the write address and buffers the input data, and then the data buffer circuit generates output data according to the read address.
  • the write address generation circuit obtains the write address according to the write enable signal, the write address is used to control the data buffer circuit to receive data, and the data buffer circuit buffers the input data after receiving the input data, thereby completing data writing
  • the process of data caching circuit can sample the write enable signal to obtain multiple sampling results. Among the obtained multiple sampling results, some or all of the sampling results have a delay within two clock cycles relative to the write enable signal.
  • write There is a clock phase difference between the write clock signal of the clock domain and the read clock signal of the read clock domain.
  • a read enable signal is selected from multiple sampling results, and the selected read enable signal is compared with The delay of the write enable signal can be controlled within two clock cycles.
  • the read address generating circuit can obtain the read address according to the read enable signal.
  • the read address is used to control the data buffer circuit to generate output data to complete the data reading process.
  • the delay control of the read enable signal and the write enable signal Within two clock cycles, the data synchronization between the two clock domains is also within two clock cycles. Therefore, compared with the existing solution of data synchronization between two clock domains, there is a delay of at least two clock cycles.
  • the data synchronization delay can be controlled within two clock cycles, which reduces the data synchronization delay and further improves the efficiency of data processing across clock domains.
  • the clock domain channel circuit specifically includes a plurality of flip-flops, and the plurality of flip-flops can sample the write enable signal on the rising edge and the falling edge of the read clock signal to obtain a sampling signal set.
  • the sampling signal set includes at least one sampling signal
  • the clock domain channel circuit also includes a multiplex signal selector, the multiplex signal selector can be based on the clock phase difference, from the preset clock phase difference and the write enable signal mapping relationship Select the target mapping relationship, and then determine the sampling signal from the sampling signal set according to the target mapping relationship, and use the determined sampling signal as the read enable signal.
  • multiple flip-flop groups can sample a set of sampling signals, and the mapping relationship between the clock phase difference and the read enable signal is preset, so the read enable signal determined by the change of the clock phase difference will also change. Therefore, under different clock phase differences, the corresponding sampling signal can be selected from the sampling signal set as the read enable signal, and the clock delay of the read enable signal and the write enable signal obtained in this way can be controlled within two clock cycles. At the same time, the obtained clock delay of the read enable signal and the write enable signal can also ensure sufficient time to synchronize the input data from the write clock domain to the read clock domain.
  • the cross-clock domain synchronization circuit further includes a phase detector; the phase detector can determine the clock phase difference between the received write clock signal and the received read clock signal; The write enable signal can also be generated according to the write clock signal, and the write enable signal is valid only when the clock phase difference is in a stable state, otherwise, the write enable signal is invalid.
  • the phase detector outputs the clock phase difference and write enable signal to the clock domain channel circuit.
  • the clock phase difference and the write enable signal can be generated by the phase detector.
  • the clock domain channel circuit includes a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; the first flip-flop receives the write command generated by the phase detector. After the enable signal, the falling edge of the read clock signal can sample the write enable signal to obtain the first sampling signal, and the second flip-flop can sample the first sampling signal on the rising edge of the read clock signal to obtain the second sampling signal; third trigger After receiving the write enable signal generated by the phase detector, the write enable signal can be sampled on the rising edge of the read clock signal to obtain the third sampling signal; the fourth flip-flop can sample the third sample signal on the rising edge of the read clock signal The fourth sampling signal is obtained by sampling, and the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal all belong to the sampling signal set.
  • a trigger is used to sample the write enable signal. Obtain the sampling signal set.
  • the sampling signal in the sampling signal set can be used as the read enable signal. Since the trigger can sample the signal on the rising and falling edges of the clock signal, the read enable signal can be controlled by the write enable signal. In two clock cycles, the corresponding data synchronization from the write clock domain to the read clock domain can also be controlled within two clock cycles, which reduces the data synchronization delay compared to the prior art.
  • the clock domain channel circuit further includes a multiplex signal selector, and two input ends of the multiplex signal selector respectively input a sampling signal set and a clock phase difference, and output a read enable signal.
  • the multiplex signal selector is used to select the second sampling signal from the sampling signal set as the read enable signal when the value range of the clock phase difference is [0T, 1/4T).
  • the clock cycle can be the same as the clock of the read clock domain, T is the clock cycle of the write clock domain or the clock cycle of the read clock domain; or, the multiplex signal selector is used when the clock phase difference is [1/4T, 1/2T)
  • select the second sampling signal or the fourth sampling signal from the sampling signal set as the read enable signal where the second sampling signal and the fourth sampling signal have the same clock cycle delay relative to the write enable signal
  • select Either the second sampling signal or the fourth sampling signal or, a multiple signal selector, used to select the fourth sampling signal from the sampling signal set when the clock phase difference is [1/2T,3/4T)
  • a multiplex signal selector used to select the second sampling signal or the second sampling signal from the sampling signal set when the value of the clock phase difference is greater than or equal to 3/4 clock period T
  • the third sampling signal is used as the read enable signal.
  • the second sampling signal and the third sampling signal have the same delayed clock period relative to the write enable signal, and either the second sampling signal or the third sampling signal can be selected.
  • four specific ways of selecting the read enable signal under the condition of four clock phase differences are introduced, which cover all possible clock phase differences, and there are flexible implementation schemes to select the obtained read enable signal and write enable.
  • the clock delay of the enable signal can be controlled within two clock cycles, and the selected clock delays of the read enable signal and the write enable signal can also ensure sufficient time to synchronize the input data from the write clock domain to the read clock domain.
  • the cross-clock domain synchronization circuit further includes a write clock domain phase-locked loop and a read clock domain phase-locked loop, and the write clock domain phase-locked loop and the read clock domain phase-locked loop are connected in the same On the clock source; the write clock domain phase-locked loop can obtain the write clock signal according to the clock source signal, and the write clock signal is in the write clock domain; the read clock domain phase-locked loop can obtain the read clock signal and read clock signal according to the clock source signal In the read clock domain.
  • the phase-locked loop of the write clock domain and the phase-locked loop of the read clock domain are connected to the same clock source to ensure that the clock of the write clock domain and the clock of the read clock domain are of the same source, which can ensure that the two clocks are not Frequency offset, then the obtained write clock signal and read clock signal frequency are equal or the frequency division ratio of the obtained write clock signal and read clock signal is an integer multiple, and the phase difference between the two clock signals is random.
  • the data buffer circuit includes a plurality of flip-flop groups, an input multiplex data selector and an output multiplex data selector;
  • the input data selector includes multiple flip-flop groups
  • the input terminals correspond to the multiple output ports connected in one-to-one correspondence
  • the output multiplex data selector includes multiple input ports that are connected to the multiple output terminals of the multiple flip-flop groups one-to-one;
  • the input multiplexer is used to obtain After inputting data, according to the write address, output buffered data from a certain output port, and constantly change the write address, you can get multiple buffered data from multiple output ports of the input multiplexer;
  • multiple trigger groups are used in Driven by the write clock signal, it receives multiple buffered data, and stores the multiple buffered data output from multiple input multiplexer output ports in different flip-flop groups of the buffer;
  • the output multiplexer receives The multi-channel cache data output by multiple flip-flop groups, and according to the read address, select one channel of the cache data from the multi-channel cache
  • the read address is different, the selected output data is different.
  • the read enable signal changes with the phase difference of the clock, and the read enable signal can obtain the read address
  • the read address is also different under different clock phase differences.
  • the read address is used as the read address that carries address information. Address, it can be seen that there are many possible situations for the read address, so this application obtains multi-channel cache data by inputting the multi-channel data selector in data synchronization, and the multi-channel cache data is cached in different trigger groups of multiple trigger groups.
  • the buffer data of the corresponding trigger group among multiple trigger groups can be selected as the output data.
  • the clock phase difference changes, the read address changes, and the selected output data also changes, so the solution of the present application can meet the data synchronization requirements under different clock phase difference conditions.
  • the cross-clock domain synchronization circuit further includes a fifth D flip-flop; the fifth D flip-flop is used to receive the output selected by the output multiplexer under the drive of the read clock signal Data, buffer and output the output data.
  • the fifth D flip-flop is used to buffer and output the output data selected by the output multiplexer. The fifth D flip-flop can prevent external interference from affecting the accuracy of data transmission during data transmission.
  • the second aspect of the present application provides a cross-clock domain synchronization method.
  • the method includes: obtaining a write address according to a write enable signal, the write address carries address information, can receive input data according to the control of the write address, and cache the input data , So as to complete the data writing process.
  • the input data here is in the write clock domain.
  • the write enable signal can be sampled to obtain multiple sampling results, and a sampling result is selected from the multiple sampling results according to the clock phase difference.
  • Read enable signal where the clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; the read address is obtained according to the read enable signal, and the buffer is input according to the control of the read address Data output, thereby generating output data to complete the data reading process, the output data is in the read clock domain.
  • the write address is obtained according to the write enable signal, and the input data can be received and buffered according to the control of the write address, thereby completing the data writing process.
  • Multiple sampling results are obtained by sampling the write enable signal, and some or all of the multiple sampling results obtained have a delay within two clock cycles relative to the write enable signal.
  • the write clock of the write clock domain There is a clock phase difference between the signal and the read clock signal in the read clock domain. According to the clock phase difference, a read enable signal is selected from multiple sampling results, and the selected read enable signal and the write enable signal The delay can be controlled within two clock cycles.
  • the read address is obtained according to the read enable signal, and the buffered input data is output according to the control of the read address to generate output data to complete the data reading process.
  • the delay of the read enable signal and the write enable signal is controlled at two In the clock cycle, then the data synchronization between the two clock domains is also within two clock cycles. Therefore, compared with the existing solution of data synchronization between the two clock domains, there is a delay of at least two clock cycles.
  • the synchronization delay is controlled within two clock cycles, which reduces the data synchronization delay, thereby improving the efficiency of data processing across clock domains.
  • the sampling the write enable signal to obtain multiple sampling results includes: sampling the write enable signal on the rising edge of the read clock signal, and simultaneously The falling edge samples the write enable signal, and multiple sampling results can be obtained.
  • the register needs to ensure the establishment time and retention time of the data, so at least two clock cycles need to be waited.
  • the read clock signal Both the rising and falling edges can sample the signal.
  • the sampled signal can be controlled within two clock cycles, and the corresponding data can be synchronized from the write clock domain to the read clock domain or controlled within two clock cycles.
  • sampling the write enable signal on the rising edge and the falling edge of the read clock signal to obtain multiple sampling results specifically includes: sampling the write enable signal on the falling edge of the read clock signal Sampling, you can get the first sample signal; sample the first sample signal on the rising edge of the read clock signal to get the second sample signal; sample the write enable signal on the rising edge of the read clock signal to get the third sample Signal; sample the third sampling signal on the rising edge of the read clock signal to obtain the fourth sampling signal, and the multiple sampling results are specifically the obtained first sampling signal, second sampling signal, third sampling signal, and fourth sampling signal .
  • the register needs to ensure the establishment time and retention time of the data, so at least two clock cycles need to be waited.
  • the read clock signal Both the rising and falling edges can sample the signal.
  • the sampled signal can be controlled within two clock cycles, and the corresponding data can be synchronized from the write clock domain to the read clock domain or controlled within two clock cycles.
  • selecting a sampling result from multiple sampling results as the read enable signal according to the clock phase difference includes: when the value range of the clock phase difference is [0T,1/4T) In this case, the second sampling signal is selected from the multiple sampling results as the read enable signal.
  • the clock signal of the write clock domain and the clock signal of the read clock domain are generated by the same clock source, the clock period of the write clock domain or read The clock cycle of the clock domain is the same.
  • T can be the clock cycle of the write clock domain or the clock cycle of the read clock domain; or, when the value range of the clock phase difference is [1/4T, 1/2T), from more Select the second sampling signal or the fourth sampling signal as the read enable signal among the sampling results; or, when the value range of the clock phase difference is [1/2T, 3/4T), select from multiple sampling results Select the fourth sampling signal as the read enable signal; or, when the value of the clock phase difference is greater than or equal to 3/4 clock period T, select the second sampling signal or the third sampling signal from multiple sampling results As a read enable signal.
  • the clock delay of the enable signal can be controlled within two clock cycles, and the selected clock delays of the read enable signal and the write enable signal can also ensure sufficient time to synchronize the input data from the write clock domain to the read clock domain.
  • the method further includes: determining the clock phase difference between the two clock signals according to the write clock signal, the write clock signal and the read clock signal of the read clock domain; Enable signal, where the write enable signal is valid when the clock phase difference between the write clock signal and the read clock signal is in a stable state, and when the clock phase difference between the write clock signal and the read clock signal is not in a stable state , The write enable signal is invalid.
  • the clock phase difference and the acquisition method of the write enable signal can be introduced.
  • the write enable signal can be used in the data synchronization process of this application.
  • the write enable signal is valid when the clock phase difference is stable, which can avoid Data synchronization error occurs when the clock phase difference is unstable.
  • the third aspect of the present application provides a chip, which includes the cross-clock domain synchronization circuit described in the first aspect of the present application and any implementation manner thereof.
  • the write address generation circuit obtains the write address according to the write enable signal, the write address is used to control the data buffer circuit to receive data, and the data buffer circuit buffers the input data after receiving the input data, thereby completing data writing
  • the process of data caching circuit can sample the write enable signal to obtain multiple sampling results. Among the obtained multiple sampling results, some or all of the sampling results have a delay within two clock cycles relative to the write enable signal.
  • write There is a clock phase difference between the write clock signal of the clock domain and the read clock signal of the read clock domain.
  • a read enable signal is selected from multiple sampling results, and the selected read enable signal is compared with The delay of the write enable signal can be controlled within two clock cycles.
  • the read address generating circuit can obtain the read address according to the read enable signal.
  • the read address is used to control the data buffer circuit to generate output data to complete the data reading process.
  • the delay control of the read enable signal and the write enable signal Within two clock cycles, the data synchronization between the two clock domains is also within two clock cycles. Therefore, compared with the existing solution of data synchronization between two clock domains, there is a delay of at least two clock cycles.
  • the data synchronization delay can be controlled within two clock cycles, which reduces the data synchronization delay and further improves the efficiency of data processing across clock domains.
  • Figure 1 is a structural diagram of an existing asynchronous FIFO
  • Figure 2 is a structural diagram of a cross-clock domain synchronization circuit of this application.
  • FIG. 3 is a structural diagram of the clock domain channel circuit of this application.
  • Figure 4 (a) is a phase relationship of the read and write clock domains of this application.
  • Figure 4(b) is another phase relationship of the read and write clock domain of this application.
  • Figure 4(c) is another phase relationship of the read and write clock domain of this application.
  • Figure 4(d) is another phase relationship of the read and write clock domain of this application.
  • Figure 5(a) is a signal sampling result of this application.
  • Figure 5(b) is another signal sampling result of this application.
  • Figure 5(c) is another signal sampling result of this application.
  • Figure 5(d) is another signal sampling result of this application.
  • This application provides a cross-clock domain synchronization circuit, which can be applied to field-programmable gate array (FPGA), application specific integrated circuits (ASIC) chips, and can also be applied For other devices, there is no limitation here.
  • FPGA field-programmable gate array
  • ASIC application specific integrated circuits
  • the cross-clock domain synchronization circuit of the present application includes a write address generating circuit 01, a read address generating circuit 02, and a data buffer circuit.
  • the data buffer circuit includes a plurality of flip-flop groups 05 and an input multiplex data selector 06 ( multiplexer, MUX) and output multiplexer 07
  • the cross-clock domain synchronization circuit also includes a fifth D flip-flop 08, a phase detector 03, a clock domain channel circuit 04, and a write clock domain phase locked loop 09 (phase locked loop, PLL) and read clock domain phase locked loop 010.
  • the write clock domain phase-locked loop 09 can generate the write clock signal of the write clock domain
  • the read clock domain phase-locked loop 010 can generate the read clock signal of the read clock domain
  • the input terminal of the write clock domain phase-locked loop 09 and the read clock domain The input end of the phase-locked loop 010 is connected to the same clock source to ensure that the clock in the write clock domain and the clock in the read clock domain are of the same source.
  • the purpose is to ensure that the two clocks have no frequency offset and generate a write clock signal of equal frequency
  • the read clock signal or generate the write clock signal and the read clock signal whose frequency division ratio is an integer multiple, and the clock phase difference between the write clock signal and the read clock signal is random.
  • Write address generating circuit 01 Driven by the write clock signal of the write clock domain, when the write enable signal is valid, the write pointer can be continuously generated, and the write address can be used as the write address, where the write enable signal can be used by the phase detector 03 produced.
  • One input port of the write address generating circuit 01 is connected to the output port of the write clock domain phase-locked loop 09 to receive the write clock signal, and the other input port of the write address generating circuit 01 is connected to the first output port of the phase detector 03, The write enable signal can be received, the output port of the write address generating circuit 01 is connected to the input port of the input multiplexer 06, and the write address can be output.
  • the data buffer circuit includes an input multiplexer 06, multiple flip-flop groups 05, and an output multiplexer 07.
  • the data buffer circuit can receive input data according to the write address and then buffer the input data.
  • the data buffer circuit can also read Address generates output data, the specific process is:
  • the write address is input to the input multiplexer 06.
  • the buffered data can be output from a certain output port of the input multiplexer 06 according to the address information indicated by the write address , So that the cache data is written into a certain trigger group of the multiple trigger groups 05, the address information indicated by the write address can indicate that the cache data is written into the specific trigger group of the multiple trigger groups 05, a certain trigger The device group corresponds to a certain output port.
  • the address information indicated by the write address is variable, so the input multiplexer 06 can output the buffered data from the multiple ports of the input multiplexer 06 according to the instructions of the write address, and the buffered data output by the multiple ports Enter multiple trigger groups 05 respectively.
  • the two data terminals of the input multiplexer 06 respectively receive the input data and the write address generated by the write address generating circuit 01, the multiple input ports of the multiple flip-flop groups 05 and the multiple output ports of the input data multiplexer 06
  • One-to-one correspondence connection can receive buffer data, and multiple output ports of multiple flip-flop groups 05 are connected to multiple input ports of output multiplexer 07 in one-to-one correspondence, and buffer data can be output.
  • the number of D flip-flops in each group is determined by the bit width of the input data.
  • the trigger input port of the group is connected to the write clock signal.
  • the four-channel buffer data processed by the input multiplexer 06 is input to the four groups of D flip-flop groups.
  • Multiple flip-flop groups 05 buffer multiple buffered data, and then output multiple buffered data to output multiplexer 07, output multiplexer 07, you can select one channel from multiple buffered data according to the instruction of the read pointer
  • the buffered data is output as output data.
  • the specific read pointer can be used as the read address.
  • the read address carries address information.
  • the address information indicated by the read address can instruct the output multiplexer 07 to output a specific D from multiple flip-flop groups 05
  • the buffer data obtained in the flip-flop group has different read addresses, and the buffer data selected and output by the output multiplexer 07 is different.
  • One input port of the output multiplexer 07 is connected to the output ports of multiple flip-flop groups 05, which can receive buffer data, and the other input port of the output multiplexer 07 is connected to the output port of the read address generating circuit 02, Can receive read addresses.
  • the output data generated by the output multiplexer 07 is input to the fifth D flip-flop 08.
  • the fifth D flip-flop 08 can buffer and output the output data generated by the data buffer circuit.
  • the fifth D flip-flop 08 It can prevent the influence of external interference on the accuracy of data transmission during data transmission.
  • the phase detector 03 can calculate the clock phase difference between the write clock signal of the write clock domain and the read clock signal of the read clock domain.
  • the phase detector 03 Entering the working state, after several clock cycles, the phase detector 03 generates a stable clock phase difference and outputs it to the clock domain channel circuit 04.
  • the phase detector 03 can also process the write clock signal in the write clock domain to obtain the write enable signal, and output the write enable signal to the write address generation circuit 01 and the clock domain channel circuit 04, and the write enable signal is used as the phase detector
  • the device 03 stably outputs the status indication of the clock phase difference. When the clock phase difference is in a stable state, the write enable signal is valid, otherwise the write enable signal is invalid.
  • phase detector 03 One input terminal of the phase detector 03 is connected to the write clock domain phase-locked loop 09 to receive the write clock signal, and the other input terminal of the phase detector 03 is connected to the read clock domain phase-locked loop 010 during writing to receive the read clock signal ,
  • the first output port of the phase detector 03 is connected to the other input port of the write address generating circuit 01 and the first input port of the clock domain channel circuit 04, which can output a write enable signal, and the second output port of the phase detector 03 Connected to the second input port of the clock domain channel circuit 04, it can output the clock phase difference.
  • the clock domain channel circuit 04 can synchronize the write enable from the write clock domain to the read clock domain according to the four states of the clock phase difference, obtain the read enable signal, and then output the read enable signal to the read address
  • the generation circuit 02 and the read address generation circuit 02 can be driven by the read clock signal of the read clock domain, and when the read enable signal is valid, the read pointer is continuously generated and output to the multiplex data selector 07 as the read address.
  • the output port of the clock domain channel circuit 04 is connected to an input port of the read address generating circuit 02, which can output a read enable signal, and the other input port of the read address generating circuit 02 is connected to the output port of the read clock domain phase-locked loop 010. Receiving the read clock signal, the output port of the read address generating circuit 02 is connected to another input port of the output multiplexer 07 to output the read address.
  • the write address generating circuit 01 generates the write address and writes data into the data buffer circuit.
  • the clock domain channel circuit 04 can obtain the read enable signal according to the write enable signal and the clock phase difference, thereby changing the write enable signal from the write.
  • the clock domain is synchronized to the read clock domain
  • the read address generating circuit 02 obtains the read address according to the read enable signal, and reads the data from the data buffer circuit, thereby realizing the synchronization of the input data from the write clock domain to the read clock domain.
  • the read enable signal changes with the phase difference of the clock
  • the read enable signal can get the read pointer, so under different clock phase differences, the read pointer is also different, the read address changes, and the output multiplex data selector 07 selects The obtained output data also changes. Therefore, the solution of the present application sets four channels of buffered data to meet the data synchronization requirements under different clock phase differences.
  • FIG 3 is the specific structure of the clock domain channel circuit 04 of this application.
  • the clock domain channel circuit 04 includes a first flip-flop 041, a second flip-flop 042, a third flip-flop 043, a fourth flip-flop 044, and a multiplex signal selector 045 ,
  • the first output port of the phase detector 03 is specifically connected to the input port of the first trigger 041, the output port of the first trigger 041 is connected to the input port of the second trigger 042, and the first output port of the phase detector 03 Specifically, it is also connected to the input port of the third flip-flop 043, the output port of the third flip-flop 043 is connected to the input port of the fourth flip-flop 044, the output port of the first flip-flop 041, the output port of the second flip-flop 042,
  • the output port of the third flip-flop 043 and the output port of the fourth flip-flop 044 are connected to the other input port of the multiplexer, and the output port of the multiplexer 045 is connected to the input port of the read address generating circuit 02
  • the phase detector 03 generates a write enable signal
  • the write enable signal enters the write address generation circuit 01
  • the write enable signal also enters the clock domain channel circuit 04, specifically:
  • the write enable signal enters the first flip-flop 041, which uses the read clock signal as the sampling pulse.
  • the first flip-flop 041 samples the write enable signal on the falling edge of the read clock signal to obtain the first sampling signal, and then the first sampling signal Enter the second flip-flop 042, the same read clock signal as the sampling pulse, the first sampling signal is sampled on the rising edge of the read clock signal to obtain the second sampling signal, the write enable signal of the write clock domain also enters the third flip-flop 043 Taking the read clock signal as the sampling pulse, the third flip-flop 043 samples the write enable signal on the falling edge of the read clock signal to obtain the third sampling signal, and then the third sampling signal enters the fourth flip-flop 044, the same read clock The signal is used as a sampling pulse, and the third sampling signal is sampled on the rising edge of the read clock signal to obtain the fourth sampling signal.
  • the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal belong to the sampling signal set.
  • the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal are respectively output to the multiplexer 045, the clock phase difference obtained by the phase discrimination of the phase detector 03 is also input to the multiplex signal selector 045, and the multiplex signal selector 045 selects a sampling signal as the write enable according to the clock phase difference obtained by the phase discrimination of the phase detector 03
  • the energy signal is output to the read address generating circuit 02 to generate the read address.
  • a trigger is used to respond to the write enable signal.
  • the sampling signal set is obtained by sampling.
  • the sampling signal in the sampling signal set can be used as the read enable signal. Since the trigger can sample the signal on both the rising and falling edges of the clock signal, the write enable signal obtains all the sampling signals in the set Or part of the sampling signal can be controlled within two clock cycles, and the corresponding data can be synchronized from the write clock domain to the read clock domain or controlled within two clock cycles.
  • the delay of data synchronization is reduced.
  • the clock phase difference refers to the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain.
  • This application presets the mapping relationship between the clock phase difference and the read enable signal.
  • the clock phase difference is different, and the read enable signal is different. Specifically:
  • the clock phase difference obtained by the phase detector 03 is: the clock phase difference belongs to [0T, 1/4T), T is the clock period of the write clock domain, as shown in Figure 4(a), with the write clock signal
  • the clock phase difference with the read clock signal is 1/8T, which corresponds to the clock phase difference in Figure 4(a), as shown in Figure 5(a)
  • the read clock signal is used to enable the write in the manner described above
  • the third sampling signal obtained by sampling will appear metastable
  • the fourth sampling signal may also appear metastable, but the first sampling signal and the second sampling signal will not appear metastable, in order to ensure certain data Synchronization delay, so as to ensure that there is enough time to read the data, but the data synchronization delay cannot be too large.
  • the multiplex signal selector 045 selects the second sampling signal as the read enable signal and generates
  • the read address is about 1.25 clock cycles later than the write address, so the data synchronization delay from the read clock domain to the write clock domain is about 1.25 clock cycles.
  • the clock phase difference obtained by the phase detector 03 is: the clock phase difference between the write clock domain and the read clock domain belongs to [1/4T, 1/2T), T is the clock period of the write clock domain, as shown in Figure 4
  • T is the clock period of the write clock domain, as shown in Figure 4
  • the write enable signal is sampled in the manner described above, and the first sampling signal, second sampling signal, third sampling signal and fourth sampling signal obtained by sampling will not appear metastable. In order to ensure a certain data synchronization delay, This ensures that there is enough time to read the data, but the data synchronization delay cannot be too large.
  • the multiplexer 045 selects the second sampling signal or the fourth sampling signal as the read enable signal and Generate the read address, where the second sampling signal and the fourth sampling signal are delayed by the same clock cycle relative to the write enable signal.
  • the read address is about 1.5 clock cycles later than the write address, then from the read clock domain to the write clock domain
  • the data synchronization delay is about 1.5 clock cycles.
  • the clock phase difference obtained by phase detector 03 is: the clock phase difference between the write clock domain and the read clock domain belongs to [1/2T, 3/4T), and T is the clock period of the write clock domain, as shown in Figure 4.
  • T is the clock period of the write clock domain, as shown in Figure 4.
  • (c) take the clock phase difference between the write clock signal and the read clock signal of 5/8T as an example, which corresponds to the clock phase difference of Figure 4(c), as shown in Figure 5(c), using the read clock signal according to
  • the write enable signal is sampled in the manner described above, the first sampling signal and the second sampling signal obtained by sampling appear metastable, the third sampling signal and the fourth sampling signal will not appear metastable, in order to ensure certain data Synchronization delay, so as to ensure that there is enough time to read the data, but the data synchronization delay cannot be too large, generally within 2 clock cycles, the multiplex signal selector 045 selects the fourth sampling signal as the read enable signal and generates
  • the read address is about 1.5 clock cycles later than the write
  • the clock phase difference obtained by the phase detector 03 is: the value of the phase difference between the write clock domain and the read clock domain is greater than or equal to 3/4 clock cycle T, T is the clock cycle of the write clock domain, as shown in the figure
  • T is the clock cycle of the write clock domain, as shown in the figure
  • the read clock signal is used according to
  • the write enable signal is sampled in the manner described above, and the first sampling signal, second sampling signal, third sampling signal and fourth sampling signal obtained by sampling will not appear metastable. In order to ensure a certain data synchronization delay, This ensures that there is enough time to read the data, but the data synchronization delay cannot be too large.
  • the multiplexer 045 selects the second sampling signal or the third sampling signal as the read enable signal and Generate the read address, where the second sampling signal and the third sampling signal are delayed by the same clock cycle relative to the write enable signal.
  • the read address is about 1 clock cycle later than the write address, then from the read clock domain to the write clock domain
  • the data synchronization delay is about 1 clock cycle.
  • the clock domain channel circuit 04 can sample the write enable signal to obtain multiple sampling results. Among the obtained multiple sampling results, some or all of the sampling results are delayed relative to the write enable signal.
  • the clock phase difference there is a clock phase difference between the write clock signal of the write clock domain and the read clock signal of the read clock domain.
  • a read enable signal is selected from multiple sampling results, The delay of the selected read enable signal and write enable signal can be controlled within two clock cycles.
  • the data synchronization between the two clock domains is also within two clock cycles. Therefore, compared with the existing solution that there is a delay of at least two clock cycles for the data synchronization between the two clock domains, the data synchronization delay in this application is relatively small .
  • This application also provides a cross-clock domain synchronization method, which can be applied to the foregoing cross-clock domain synchronization circuit to realize the function of the foregoing cross-clock domain synchronization circuit.
  • this application can be implemented by means of software plus necessary general hardware.
  • it can also be implemented by dedicated hardware including dedicated integrated circuits, dedicated CPUs, dedicated memory, Dedicated components and so on to achieve.
  • all functions completed by computer programs can be easily implemented with corresponding hardware.
  • the specific hardware structure used to achieve the same function can also be diverse, such as analog circuits, digital circuits or dedicated Circuit etc.
  • software program implementation is a better implementation in more cases.
  • the technical solution of this application essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, such as a computer floppy disk.
  • a readable storage medium such as a computer floppy disk.
  • U disk mobile hard disk
  • read-only memory read-only memory, ROM
  • random access memory random access memory
  • magnetic disk or optical disk etc., including several instructions to make a computer device (which can be A personal computer or server, etc.) executes the method described in each embodiment of the present application.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website site, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

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Abstract

本申请实施例公开了一种跨时钟域同步电路，本申请跨时钟域同步电路包括时钟域通道电路、写地址产生电路、读地址产生电路和数据缓存电路，写地址产生电路用于根据写使能信号得到写地址，写地址用于控制数据缓存电路接收输入数据，输入数据处于写时钟域；时钟域通道电路用于对写使能信号进行采样以得到多个采样结果，并根据时钟相位差从多个采样结果中选择一个采样结果作为读使能信号，时钟相位差为处于写时钟域的写时钟信号和处于读时钟域的读时钟信号的相位差；读地址产生电路用于根据读使能信号得到读地址，读地址用于控制数据缓存电路产生输出数据，输出数据处于读时钟域；数据缓存电路用于根据写地址和读地址，将输入数据缓存并产生输出数据。

Description

跨时钟域同步电路以及方法 技术领域
本申请涉及电路领域，尤其涉及一种跨时钟域同步电路及其相关方法。
背景技术
片上系统(system-on-chip，SOC)指的是在单个芯片上集成一个完整的系统，由于芯片上承载的功能越来越多，芯片内部也会有越来越多的时钟，每个时钟的工作频率都不一样，这就导致芯片内部有多个时钟域，当多个时钟域之间通信时，需要进行时钟域的同步才能完成跨时钟域的数据交互，异步电路处理技术可以完成这一过程。
一种典型的异步电路处理技术是异步先进先出(fist-in-fist-out，FIFO)技术，参照图1，首先写时钟域中写地址产生逻辑电路101产生二进制的写指针，将数据写入FIFO存储电路104，读时钟域的读地址产生逻辑电路103产生二进制的读指针，将数据从FIFO存储电路104中读出来，每进行一次读或写操作，相应的指针就递增一次，指向下一个内存地址。当满/空标识产生逻辑电路102产生读空标识时，不再进行读操作，但是可以进行写操作，当满/空标识产生逻辑电路102产生写满标识时，不再进行写操作，但是可以进行读操作。读空标识的产生需要将写时钟域的写指针同步到读时钟域，首先，为了避免出现毛刺，二进制写指针要先转化为格雷码，再将格雷码利用两级寄存器执行打两拍处理，或利用多级寄存器执行打多拍处理，随后将处理得到的写指针转化为二进制，并与二进制的读指针比较，当两指针的地址位相同，状态位也相同时产生读空信号，上述过程中，由于寄存器寄存数据需要保证数据的建立时间和保持时间，建立时间时指在时钟信号上升沿到来前，数据需要提前输入寄存器的时间，保持时间是上升沿到来后数据需要维持不变的时间，利用寄存器打一拍处理需要等到一个时钟周期，那么利用寄存器执行打两拍处理，或利用多个寄存器执行打两多处理时会对应产生两个或多个时钟周期的延时，写指针由写时钟域同步到读时钟域的过程需要至少两个时钟周期的延时。同样的，写满标识的产生需要将读时钟域的读指针同步到写时钟域，同步过程需要寄存器进行打两拍或打多拍处理，也有至少两个时钟周期的延时。
可见，写时钟域的写指针同步到读时钟域得到读空信号，会产生至少两个时钟周期的延时，同样的读时钟域的读指针同步到写时钟域得到写满信号，也会产生至少两个时钟周期的延时。写满标识会控制写指针的增加，读空标识也会控制读指针的增加，读写指针又会控制数据的写入和读取，从而控制了写时钟域的数据同步到读时钟域，因此两时钟域间数据的同步也会有至少两个时钟周期的延时。由于上述因素，如图1所示的异步FIFO在进行跨时钟域处理时存在较大的延迟，因此降低了数据跨时钟域处理的效率。
发明内容
本申请提供了的第一方面提供了一种跨时钟域同步电路，可以将输入数据由写时钟域同步到读时钟域，该跨时钟域同步电路包括时钟域通道电路、写地址产生电路、读地址产生电路以及数据缓存电路；写地址产生电路可以在写时钟信号驱动下，根据写使能信号得 到写地址，写地址可以控制数据缓存电路接收输入数据，输入数据是写时钟域的数据；时钟域通道电路的两个输入端分别输入写使能信号和时钟相位差，时钟相位差指的是处于写时钟域的写时钟信号和处于读时钟域的读时钟信号之间的相位差，时钟域通道电路可以对写使能信号进行采样，得到采样信号集合，时钟域通道电路再根据时钟相位差从采样信号集合中选择采样信号作为读使能信号；读地址产生电路可以在读时钟信号驱动下，可以根据读使能信号得到读地址，读地址可以控制数据缓存电路产生输出数据，输出数据处于读时钟域，那么跨时钟域同步电路就完成了输入数据从写时钟域同步到读时钟域的过程。数据缓存电路根据写地址接收输入数据后缓存该输入数据，之后数据缓存电路再根据读地址产生输出数据。
本申请实施例具有以下优点：写地址产生电路根据写使能信号得到写地址，写地址用于控制数据数据缓存电路接收数据，数据缓存电路接收输入数据后将输入数据缓存，从而完成数据写入数据缓存电路的过程。时钟域通道电路可以将写使能信号采样得到多个采样结果，得到的多个采样结果中存在部分或全部的采样结果相对于写使能信号的延时在两个时钟周期内，其次，写时钟域的写时钟信号与读时钟域的读时钟信号之间的具有时钟相位差，根据该时钟相位差，从多个采样结果中选择一个读使能信号，选择得到的这个读使能信号与写使能信号的延时可以控制在两个时钟周期内。随后读地址产生电路可以根据读使能信号得到读地址，读地址用于控制数据缓存电路产生输出数据，从而完成数据的读取过程，那么由于读使能信号与写使能信号的延时控制在两个时钟周期内，那么两时钟域之间数据的同步也在两个时钟周期内，因此相对于现有两时钟域间数据的同步有至少两个时钟周期的延时的方案，本申请可以把数据同步的延时控制在两个时钟周期内，降低了数据同步的延时，进而提升了数据跨时钟域处理的效率。
在本申请的一种可选实施方式中，时钟域通道电路具体包括多个触发器，多个触发器分别在可以在读时钟信号的上升沿和下降沿对写使能信号进行采样得到采样信号集合，采样信号集合中包括至少一个采样信号，时钟域通道电路还包括多路信号选择器，多路信号选择器可以根据时钟相位差，从预先设置的时钟相位差与写使能信号的映射关系中选择目标映射关系，随后再根据目标映射关系从采样信号集合中确定采样信号，并将确定的采样信号作为读使能信号。在本实施例中，多个触发器组可以采样得到采样信号集合，同时预先设置了时钟相位差与读使能信号的映射关系，那么时钟相位差变化确定的读使能信号也会发生变化，由此可以在不同时钟相位差条件下，从采样信号集合中选择对应的采样信号作为读使能信号，这样得到的读使能信号与写使能信号的时钟延迟可以控制在两个时钟周期，同时得到的读使能信号与写使能信号的时钟延迟也可以保证足够的时间将输入数据从写时钟域同步至读时钟域。
在本申请的一种可选实施方式中，跨时钟域同步电路还包括鉴相器；鉴相器，可以依据接收的写时钟信号和接收的读时钟信号确定两者的时钟相位差；鉴相器，还可以根据写时钟信号产生写使能信号，并且在时钟相位差处于稳定状态时，写使能信号才有效，否则，写使能信号无效。鉴相器输出时钟相位差和写使能信号给时钟域通道电路。在本实施例中，可以通过鉴相器产生时钟相位差和写使能信号，方案结构更加完整，有利于方案实施。
在本申请的一种可选实施方式中，时钟域通道电路包括第一触发器、第二触发器、第三触发器以及第四触发器；第一触发器，接收鉴相器产生的写使能信号后，可以读时钟信号的下降沿对写使能信号采样得到第一采样信号，第二触发器，可以在读时钟信号的上升沿对第一采样信号采样得到第二采样信号；第三触发器，接收鉴相器产生的写使能信号后，可以在读时钟信号的上升沿对写使能信号采样得到第三采样信号；第四触发器，可以在读时钟信号的上升沿对第三采样信号采样得到第四采样信号，第一采样信号、第二采样信号、第三采样信号以及第四采样信号均属于采样信号集合。相对于现有技术利用寄存器进行写指针或读指针同步，寄存器需要保证数据的建立时间和保持时间，那么需要等待至少两个时钟周期，而本实施例中，用触发器对写使能信号采样得到采样信号集合，采样信号集合中的采样信号可以作为读使能信号，由于触发器在时钟信号的上升沿和下降沿均可以对信号采样，因此由写使能信号得到读使能信号可以控制在两个时钟周期内，对应的数据由写时钟域同步到读时钟域也可以控制在两个时钟周期内，相对于现有技术减小了数据同步的延时。
在本申请的一种可选实施方式中，时钟域通道电路还包括多路信号选择器，多路信号选择器的两个输入端分别输入采样信号集合和时钟相位差，输出读使能信号。多路信号选择器，用于当时钟相位差的取值范围在[0T,1/4T)的情况下，从采样信号集合中选择第二采样信号作为读使能信号，其中，由于写时钟的时钟周期可以与读时钟域时钟相同，T为写时钟域的时钟周期或读时钟域的时钟周期；或，多路信号选择器，用于当时钟相位差为[1/4T,1/2T)的情况下，从采样信号集合中选择第二采样信号或第四采样信号作为读使能信号，这里第二采样信号和第四采样信号相对于写使能信号延迟的时钟周期是相同的，选择第二采样信号或第四采样信号均可；或，多路信号选择器，用于当时钟相位差为[1/2T,3/4T)的情况下，从采样信号集合中选择第四采样信号作为读使能信号；或，多路信号选择器，用于当时钟相位差的取值大于或等于3/4个时钟周期T的情况下，从采样信号集合中选择第二采样信号或所述第三采样信号作为读使能信号，这里第二采样信号和第三采样信号相对于写使能信号延迟的时钟周期是相同的，选择第二采样信号或第三采样信号均可。在本实施例中，介绍了四种时钟相位差情况下选择读使能信号的具体方式，涵盖了全部可能的时钟相位差情况，有利用方案灵活实施，选择得到的读使能信号与写使能信号的时钟延迟可以控制在两个时钟周期，同时选择得到的读使能信号与写使能信号的时钟延迟也可以保证足够的时间将输入数据从写时钟域同步至读时钟域。
在本申请的一种可选实施方式中，跨时钟域同步电路还包括写时钟域锁相环和读时钟域锁相环，写时钟域锁相环和读时钟域锁相环连接在同一个时钟源上；写时钟域锁相环，可以根据时钟源信号得到写时钟信号，写时钟信号处于写时钟域；读时钟域锁相环，可以根据该时钟源信号得到读时钟信号，读时钟信号处于读时钟域。在本实施例中，写时钟域锁相环和读时钟域锁相环连接同一个时钟源，以保证写时钟域的时钟与读时钟域的时钟是同源时钟，可以保证这两个时钟没有频偏，那么得到的写时钟信号和读时钟信号频率相等或得到的写时钟信号和读时钟信号的分频比为整数倍的，同时这两个时钟信号之间相位差随机。
在本申请的一种可选实施方式中，数据缓存电路包括多个触发器组、输入多路数据选择器和输出多路数据选择器；输入数据选择器包括与多个触发器组的多个输入端一一对应连接的多个输出端口，输出多路数据选择器包括与多个触发器组的多个输出端一一对应连接的多个输入端口；输入多路数据选择器，用于获取输入数据后，根据写地址，从某一输出端口输出缓存数据，不断改变写地址，就可以从输入多路数据选择器的多个输出端口得到多路缓存数据；多个触发器组用于在写时钟信号的驱动下，接收多路缓存数据，并将从多个输入多路数据选择器输出端口输出的多路缓存数据分别在缓存不同的触发器组中；输出多路数据选择器，接收多个触发器组输出的多路缓存数据，并根据读地址，从多路缓存数据中选择一路缓存数据作为输出数据输出，读地址不同，选择得到的输出数据不同。在本实施例中，由于读使能信号是跟随时钟相位差变化的，读使能信号又可以得到读地址，那么不同时钟相位差条件下，读地址也不同，读地址作为携带地址信息的读地址，可见读地址有多种可能的情况，那么本申请在数据同步上通过输入多路数据选择器得到多路缓存数据，多路缓存数据缓存于多个触发器组的不同触发器组中，读地址变化时就可以选择多个触发器组中对应触发器组的缓存数据作为输出数据。可见时钟相位差变化，读地址变化，选择得到的输出数据也变化，那么本申请的方案可以满足不同时钟相位差条件下数据同步的需求。
在本申请的一种可选实施方式中，跨时钟域同步电路还包括第五D触发器；第五D触发器，用于在读时钟信号的驱动下，接收输出多路数据选择器选择的输出数据，缓存并输出该输出数据。在本实施例中，利用第五D触发器对输出多路数据选择器选择的输出数据缓存并输出，第五D触发器可以防止数据传输过程中，外来干扰对数据传输正确性的影响。
本申请第二方面提供了一种跨时钟域同步方法，该方法包括：根据写使能信号得到写地址，写地址携带地址信息，可以根据写地址的控制来接收输入数据，并缓存该输入数据，从而完成数据的写入过程，这里的输入数据处于写时钟域，同时可以对写使能信号进行采样以得到多个采样结果，并根据时钟相位差从多个采样结果中选择一个采样结果作为读使能信号，其中，时钟相位差为处于写时钟域的写时钟信号和处于读时钟域的读时钟信号的相位差；根据读使能信号得到读地址，根据读地址的控制将缓存的输入数据输出，从而产生输出数据，以完成数据的读取过程，输出数据处于读时钟域。
本实施例具有以下优点：根据写使能信号得到写地址，可以根据写地址的控制来接收并缓存输入数据，从而完成数据的写入过程。由写使能信号采样得到多个采样结果，得到的多个采样结果中存在部分或全部的采样结果相对于写使能信号的延时在两个时钟周期内，其次，写时钟域的写时钟信号与读时钟域的读时钟信号之间的具有时钟相位差，根据该时钟相位差，从多个采样结果中选择一个读使能信号，选择得到的这个读使能信号与写使能信号的延时可以控制在两个时钟周期内。随后根据读使能信号得到读地址，根据读地址的控制将缓存的输入数据输出以产生输出数据，完成数据读取过程，那么由于读使能信号与写使能信号的延时控制在两个时钟周期内，那么两时钟域之间数据的同步也在两个时钟周期内，因此相对于现有两时钟域间数据的同步有至少两个时钟周期的延时的方案，本申请可以把数据同步的延时控制在两个时钟周期内，降低了数据同步的延时，进而提升了 数据跨时钟域处理的效率。
在本申请的一种可选实施方式中，所述对所述写使能信号进行采样以得到多个采样结果包括：在读时钟信号的上升沿对写使能信号进行采样，同时在读时钟信号的下降沿对写使能信号进行采样，可以得到多个采样结果。在本实施例中，相对于现有技术利用寄存器进行写指针或读指针同步，寄存器需要保证数据的建立时间和保持时间，那么需要等待至少两个时钟周期，而本实施例中，在读时钟信号的上升沿和下降沿均可以对信号采样，采样得到的信号可以控制在两个时钟周期内，对应的数据由写时钟域同步到读时钟域也可以控制在两个时钟周期内，相对于现有技术减小了数据同步的延时。
在本申请的一种可选实施方式中，在读时钟信号的上升沿和下降沿分别对写使能信号进行采样，以得到多个采样结果具体包括：在读时钟信号的下降沿对写使能信号进行采样，可以得到第一采样信号；在读时钟信号的上升沿对第一采样信号进行采样，可以得到第二采样信号；在读时钟信号的上升沿对写使能信号进行采样，可以得到第三采样信号；在读时钟信号的上升沿对第三采样信号进行采样，可以得到第四采样信号，多个采样结果具体为得到的第一采样信号、第二采样信号、第三采样信号以及第四采样信号。在本实施例中，相对于现有技术利用寄存器进行写指针或读指针同步，寄存器需要保证数据的建立时间和保持时间，那么需要等待至少两个时钟周期，而本实施例中，在读时钟信号的上升沿和下降沿均可以对信号采样，采样得到的信号可以控制在两个时钟周期内，对应的数据由写时钟域同步到读时钟域也可以控制在两个时钟周期内，相对于现有技术减小了数据同步的延时。
在本申请的一种可选实施方式中，根据时钟相位差从多个采样结果中选择一个采样结果作为读使能信号包括：在时钟相位差的取值范围在[0T,1/4T)的情况下，从多个采样结果中选择第二采样信号作为读使能信号，其中，由于写时钟域的时钟信号和读时钟域的时钟信号由同一时钟源产生，写时钟域的时钟周期或读时钟域的时钟周期相同，T可以为写时钟域的时钟周期或读时钟域的时钟周期；或，在时钟相位差的取值范围在[1/4T,1/2T)的情况下，从多个采样结果中选择第二采样信号或第四采样信号作为读使能信号；或，在时钟相位差的取值范围在[1/2T,3/4T)的情况下，从多个采样结果中选择第四采样信号作为读使能信号；或，在时钟相位差的取值大于或等于3/4个时钟周期T的情况下，从多个采样结果中选择第二采样信号或第三采样信号作为读使能信号。在本实施例中，介绍了四种时钟相位差情况下选择读使能信号的具体方式，涵盖了全部可能的时钟相位差情况，有利用方案灵活实施，选择得到的读使能信号与写使能信号的时钟延迟可以控制在两个时钟周期，同时选择得到的读使能信号与写使能信号的时钟延迟也可以保证足够的时间将输入数据从写时钟域同步至读时钟域。
在本申请的一种可选实施方式中，所述方法还包括：根据写时钟信号写时钟信号和读时钟域的读时钟信号确定两时钟信号之间的时钟相位差；根据写时钟信号产生写使能信号，其中，当写时钟信号与读时钟信号之间的时钟相位差处于稳定状态时，写使能信号有效，当写时钟信号与读时钟信号之间的时钟相位差不处于稳定状态时，写使能信号无效。在本实施例中，可以介绍了时钟相位差以及写使能信号的获取方式，写使能信号可以用于本申 请的数据同步过程，在时钟相位差稳定时写使能信号才有效，可以避免时钟相位差不稳定时数据同步发生错误。
本申请第三方面提供了一种芯片，该芯片包括本申请第一方面以及其任一种实现方式所述的跨时钟域同步电路。
本申请实施例具有以下优点：写地址产生电路根据写使能信号得到写地址，写地址用于控制数据数据缓存电路接收数据，数据缓存电路接收输入数据后将输入数据缓存，从而完成数据写入数据缓存电路的过程。时钟域通道电路可以将写使能信号采样得到多个采样结果，得到的多个采样结果中存在部分或全部的采样结果相对于写使能信号的延时在两个时钟周期内，其次，写时钟域的写时钟信号与读时钟域的读时钟信号之间的具有时钟相位差，根据该时钟相位差，从多个采样结果中选择一个读使能信号，选择得到的这个读使能信号与写使能信号的延时可以控制在两个时钟周期内。随后读地址产生电路可以根据读使能信号得到读地址，读地址用于控制数据缓存电路产生输出数据，从而完成数据的读取过程，那么由于读使能信号与写使能信号的延时控制在两个时钟周期内，那么两时钟域之间数据的同步也在两个时钟周期内，因此相对于现有两时钟域间数据的同步有至少两个时钟周期的延时的方案，本申请可以把数据同步的延时控制在两个时钟周期内，降低了数据同步的延时，进而提升了数据跨时钟域处理的效率。
附图说明
图1为现有异步FIFO的结构图；
图2为本申请跨时钟域同步电路的结构图；
图3为本申请时钟域通道电路的结构图；
图4(a)为本申请读写时钟域的一种相位关系；
图4(b)为本申请读写时钟域的另一种相位关系；
图4(c)为本申请读写时钟域的另一种相位关系；
图4(d)为本申请读写时钟域的另一种相位关系；
图5(a)为本申请的一种信号采样结果；
图5(b)为本申请的另一种信号采样结果；
图5(c)为本申请的另一种信号采样结果；
图5(d)为本申请的另一种信号采样结果。
具体实施方式
本申请提供了一种跨时钟域同步电路，可以应用于现场可编程门阵(field-programmable gate array，FPGA)，也可以应用于专用集成电路(application specific integrated circuits，ASIC)芯片，还可以应用于其他设备，此处不作限定。
参照图2，本申请的跨时钟域同步电路包括写地址产生电路01、读地址产生电路02以及数据缓存电路，其中数据缓存电路包括电路多个触发器组05、输入多路数据选择器06(multiplexer，MUX)以及输出多路数据选择器07，跨时钟域同步电路还包括第五D触发 器08、鉴相器03、时钟域通道电路04、写时钟域锁相环09(phase locked loop，PLL)和读时钟域锁相环010。
首先，写时钟域锁相环09可以产生写时钟域的写时钟信号，读时钟域锁相环010可以产生读时钟域的读时钟信号，写时钟域锁相环09的输入端和读时钟域锁相环010的输入端连接同一个时钟源，以保证写时钟域的时钟与读时钟域的时钟是同源时钟，其目的是确保这两个时钟没有频偏，产生频率相等的写时钟信号和读时钟信号，或产生分频比为整数倍的写时钟信号和读时钟信号，同时写时钟信号和读时钟信号之间时钟相位差随机。
写地址产生电路01：可以在写时钟域的写时钟信号的驱动下，当写使能信号有效时，连续产生写指针，写地址可以作为写地址，其中，写使能信号可以由鉴相器03产生。写地址产生电路01的一个输入端口与写时钟域锁相环09的输出端口连接，可以接收写时钟信号，写地址产生电路01的另一个输入端口与鉴相器03的第一输出端口连接，可以接收写使能信号，写地址产生电路01的输出端口与输入多路数据选择器06的输入端口连接，可以输出写地址。
数据缓存电路包括输入多路数据选择器06、多个触发器组05以及输出多路数据选择器07，数据缓存电路可以根据写地址接收输入数据，随后缓存输入数据，数据缓存电路也可以根据读地址产生输出数据，具体过程为：
写地址输入至输入多路数据选择器06，输入多路数据选择器06获取输入数据后，可以根据写地址所指示的地址信息，从输入多路数据选择器06的某一输出端口输出缓存数据，从而将缓存数据写入多个触发器组05的某一触发器组中，写地址所指示的地址信息可以指示将缓存数据写入多个触发器组05的特定触发器组，某一触发器组与某一输出端口是相对应的。写地址指示的地址信息是可变的，那么输入多路数据选择器06可以根据写地址的指示，分别从输入多路数据选择器06的多个端口输出缓存数据，多个端口输出的缓存数据分别对应进入多个触发器组05。输入多路数据选择器06的两个数据端分别接收输入数据和写地址产生电路01产生的写地址，多个触发器组05的多个输入端口与输入数据多路选择06的多个输出端口一一对应连接，可以接收缓存数据，多个触发器组05的多个输出端口与输出多路数据选择器07的多个输入端口一一对应连接，可以输出缓存数据。
进一步的，关于上述多个触发器组05，图2中以4组D触发器组为例，每组触发器组中D触发器的个数由输入数据的位宽决定，四组D触发器组的触发输入端口连接到写时钟信号，在写时钟信号驱动下，输入多路数据选择器06处理得到的四路缓存数据分别输入到四组D触发器组。
多个触发器组05缓存多路缓存数据，随后将多路缓存数据输出至输出多路数据选择器07，输出多路数据选择器07，可以根据读指针的指示从多路缓存数据中选择一路缓存数据作为输出数据输出，具体的读指针可以作为读地址，读地址携带有地址信息，读地址所指示的地址信息可以指示输出多路数据选择器07输出从多个触发器组05的特定D触发器组中获取到的缓存数据，读地址不同，输出多路数据选择器07选择输出的缓存数据不同。输出多路数据选择器07一个输入端口与多个触发器组05的输出端口连接，可以接收缓存数据，输出多路数据选择器07的另一个输入端口与读地址产生电路02的输出端口连接，可 以接收读地址。
输出多路数据选择器07产生的输出数据输入至第五D触发器08，在读时钟信号驱动下，第五D触发器08可以缓存并输出数据缓存电路产生的输出数据，第五D触发器08可以防止数据传输过程中，外来干扰对数据传输正确性的影响。
鉴相器03(phase detector，PD)，可以计算写时钟域的写时钟信号和读时钟域的读时钟信号之间的时钟相位差，当写时钟域和读时钟域稳定后，鉴相器03进入工作状态，经过若干个时钟周期后，鉴相器03产生稳定的时钟相位差输出至时钟域通道电路04。同时鉴相器03还可以对写时钟域的写时钟信号进行处理得到写使能信号，并将写使能信号输出至写地址产生电路01和时钟域通道电路04，写使能信号作为鉴相器03稳定输出时钟相位差的状态指示，当时钟相位差处于稳定状态时，写使能信号有效，否则写使能信号无效。鉴相器03的一个输入端连接到写时钟域锁相环09，以便接收写时钟信号，鉴相器03的另一个输入端连接到写时读时钟域锁相环010，以便接收读时钟信号，鉴相器03的第一输出端口连接到写地址产生电路01的另一个输入端口以及时钟域通道电路04的第一输入端口，可以输出写使能信号，鉴相器03的第二输出端口连接到时钟域通道电路04的第二输入端口，可以输出时钟相位差。
时钟域通道电路04电路：时钟域通道电路04可以根据时钟相位差的四种状态将写使能由写时钟域同步到读时钟域，得到读使能信号，然后读使能信号输出至读地址产生电路02，读地址产生电路02可以在读时钟域的读时钟信号的驱动下，当读使能信号有效时，连续产生读指针，作为读地址输出至多路数据选择器07。时钟域通道电路04的输出端口连接到读地址产生电路02的一个输入端口，可以输出读使能信号，读地址产生电路02的另一个输入端口连接读时钟域锁相环010的输出端口，可以接收读时钟信号，读地址产生电路02的输出端口连接到输出多路数据选择器07的另一个输入端口，可以输出读地址。
基于上述结构，写地址产生电路01产生写地址，将数据写入数据缓存电路，时钟域通道电路04可以根据写使能信号和时钟相位差得到读使能信号，从而将写使能信号从写时钟域同步到了读时钟域，读地址产生电路02根据读使能信号得到读地址，将数据从数据缓存电路中读出来，从而实现了输入数据从写时钟域同步到读时钟域。
同时，由于读使能信号是跟随时钟相位差变化的，读使能信号又可以得到读指针，那么不同时钟相位差条件下，读指针也不同，读地址变化，输出多路数据选择器07选择得到的输出数据也变化，因此本申请的方案设置四路缓存数据可以满足不同时钟相位差条件下数据同步的需求。
基于上述时钟域通道电路04的功能，下面具体描述读地址的产生过程：
图3为本申请时钟域通道电路04的具体结构，时钟域通道电路04包括第一触发器041、第二触发器042、第三触发器043和第四触发器044以及多路信号选择器045，鉴相器03的第一输出端口具体与第一触发器041的输入端口连接，第一触发器041的输出端口与第二触发器042的输入端口连接，鉴相器03的第一输出端口具体还与第三触发器043的输入端口连接，第三触发器043的输出端口与第四触发器044的输入端口连接，第一触发器041的输出端口、第二触发器042的输出端口、第三触发器043的输出端口、以及第四触发器 044的输出端口与多路数据选择器的另一个输入端口连接，多路信号选择器045的输出端口与读地址产生电路02的输入端口连接，参照图3，以写时钟域与读时钟域是同源同频异步时钟为例，写时钟信号与读时钟信号之间频率相同，时钟相位差随机，本申请时钟域通道电路04将写使能信号由写时钟域同步到读时钟域的具体过程为：
如上所述，鉴相器03产生写使能信号，写使能信号进入写地址产生电路01，同时写使能信号也进入时钟域通道电路04，具体的：
写使能信号进入第一触发器041，以读时钟信号作为采样脉冲，第一触发器041在读时钟信号的下降沿对写使能信号进行采样，得到第一采样信号，随后，第一采样信号进入第二触发器042，同样读时钟信号作为采样脉冲，在读时钟信号的上升沿对第一采样信号进行采样，得到第二采样信号，写时钟域的写使能信号也进入第三触发器043，以读时钟信号作为采样脉冲，第三触发器043在读时钟信号的下降沿对写使能信号进行采样，得到第三采样信号，随后，第三采样信号进入第四触发器044，同样读时钟信号作为采样脉冲，在读时钟信号的上升沿对第三采样信号进行采样，得到第四采样信号。第一采样信号、第二采样信号、第三采样信号以及第四采样信号属于采样信号集合，第一采样信号、第二采样信号、第三采样信号以及第四采样信号分别输出至多路信号选择器045，鉴相器03的鉴相得到的时钟相位差也输入多路信号选择器045，多路信号选择器045根据鉴相器03的鉴相得到的时钟相位差，选择一路采样信号作为写使能信号输出至读地址产生电路02即可产生读地址。
相对于现有技术利用寄存器进行写指针同步或读指针同步，寄存器需要保证数据的建立时间和保持时间，那么需要等待至少两个时钟周期，而本实施例中，用触发器对写使能信号采样得到采样信号集合，采样信号集合中的采样信号可以作为读使能信号，由于触发器在时钟信号的上升沿和下降沿均可以对信号采样，因此由写使能信号得到采样信号集合中全部或部分的采样信号可以控制在两个时钟周期内，对应的数据由写时钟域同步到读时钟域也可以控制在两个时钟周期内，相对于现有技术减小了数据同步的延时。
本申请鉴相器03的时钟相位差有四种可能的情况，选择得到的读使能信号也有四种可能的情况，选择的总体思想是确保写使能信号不会出现亚稳态，下面对四种情况进行说明：
首先时钟相位差指的是写时钟域写时钟信号和读时钟域读时钟信号之间的相位差。本申请预置有时钟相位差和读使能信号的映射关系，时钟相位差不同，读使能信号不同，具体的：
一、鉴相器03鉴相得到的时钟相位差为：时钟相位差的属于[0T,1/4T)，T为写时钟域的时钟周期，如图4(a)所示，以写时钟信号与读时钟信号之间时钟相位差为1/8T为例，对应图4(a)的时钟相位差，如图5(a)所示，利用读时钟信号按照上面所描述的方式对写使能信号采样，采样得到的第三采样信号会出现亚稳态，第四采样信号也可能会出现亚稳态，但是第一采样信号和第二采样信号不会出现亚稳态，为了保证一定的数据同步延时，从而保证有足够的时间读取数据，但是数据同步延时也不能太大，一般在2个时钟周期内，多路信号选择器045选择第二采样信号作为读使能信号并产生读地址，读地址比写地址约晚1.25个时钟周期，那么从到读时钟域到写时钟域的数据同步延时约为1.25个 时钟周期。
二、鉴相器03鉴相得到的时钟相位差为：写时钟域与读时钟域间时钟相位差的属于[1/4T,1/2T)，T为写时钟域的时钟周期，如图4(b)所示，以写时钟信号与读时钟信号间时钟相位差为3/8T为例，对应图4(b)的时钟相位差，如图5(b)所示，利用读时钟信号按照上面所描述的方式对写使能信号采样，采样得到的第一采样信号、第二采样信号、第三采样信号以及第四采样信号不会出现亚稳态，为了保证一定的数据同步延时，从而保证有足够的时间读取数据，但是数据同步延时也不能太大，一般在2个时钟周期内，多路信号选择器045选择第二采样信号或第四采样信号作为读使能信号并产生读地址，这里第二采样信号和第四采样信号相对于写使能信号延迟的时钟周期是相同的，读地址比写地址约晚1.5个时钟周期，那么从到读时钟域到写时钟域的数据同步延时约为1.5个时钟周期。
三、鉴相器03鉴相得到的时钟相位差为：写时钟域与读时钟域间时钟相位差的属于[1/2T,3/4T)，T为写时钟域的时钟周期，如图4(c)所示，以写时钟信号与读时钟信号间时钟相位差为5/8T为例，对应图4(c)的时钟相位差，如图5(c)所示，利用读时钟信号按照上面所描述的方式对写使能信号采样，采样得到的第一采样信号以及第二采样信号出现亚稳态，第三采样信号以及第四采样信号不会出现亚稳态，为了保证一定的数据同步延时，从而保证有足够的时间读取数据，但是数据同步延时也不能太大，一般在2个时钟周期内，多路信号选择器045选择第四采样信号作为读使能信号并产生读地址，读地址比写地址约晚1.5个时钟周期，那么从到读时钟域到写时钟域的数据同步延时约为1.5个时钟周期。
四、鉴相器03鉴相得到的时钟相位差为：写时钟域与读时钟域间相位差的取值大于或等于3/4个时钟周期T，T为写时钟域的时钟周期，如图4(d)所示，以写时钟信号与读时钟信号间时钟相位差为7/8T为例对应图4(d)的时钟相位差，如图5(d)所示，利用读时钟信号按照上面所描述的方式对写使能信号采样，采样得到的第一采样信号、第二采样信号、第三采样信号以及第四采样信号不会出现亚稳态，为了保证一定的数据同步延时，从而保证有足够的时间读取数据，但是数据同步延时也不能太大，一般在2个时钟周期内，多路信号选择器045选择第二采样信号或第三采样信号作为读使能信号并产生读地址，这里第二采样信号和第三采样信号相对于写使能信号延迟的时钟周期是相同的，读地址比写地址约晚1个时钟周期，那么从到读时钟域到写时钟域的数据同步延时约为1个时钟周期。
基于上述跨时钟域同步电路，时钟域通道电路04可以将写使能信号采样得到多个采样结果，得到的多个采样结果中存在部分或全部的采样结果相对于写使能信号的延时在两个时钟周期内，其次，写时钟域的写时钟信号与读时钟域的读时钟信号之间的具有时钟相位差，根据该时钟相位差，从多个采样结果中选择一个读使能信号，选择得到的这个读使能信号与写使能信号的延时可以控制在两个时钟周期内。两时钟域之间数据的同步也在两个时钟周期内，因此相对于现有两时钟域间数据的同步有至少两个时钟周期的延时的方案，本申请实现数据同步的延时较小。
本申请还提供了一种跨时钟域同步方法，该方法可以应用于上述跨时钟域同步电路，以实现上述跨时钟域同步电路的功能。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机或服务器等)执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。

Claims (13)

  1. 一种跨时钟域同步电路，其特征在于，所述跨时钟域同步电路包括时钟域通道电路、写地址产生电路、读地址产生电路以及数据缓存电路，其中：
    所述写地址产生电路用于根据写使能信号得到写地址，所述写地址用于控制所述数据缓存电路接收所述输入数据，所述输入数据处于写时钟域；
    所述时钟域通道电路用于对所述写使能信号进行采样以得到多个采样结果，并根据时钟相位差从所述多个采样结果中选择一个采样结果作为读使能信号，其中，所述时钟相位差为处于所述写时钟域的写时钟信号和处于读时钟域的读时钟信号的相位差；
    所述读地址产生电路用于根据所述读使能信号得到读地址，所述读地址用于控制所述数据缓存电路产生输出数据，所述输出数据处于所述读时钟域；
    所述数据缓存电路用于根据所述写地址和所述读地址，将所述输入数据缓存并产生所述输出数据。
  2. 根据权利要求1所述的跨时钟域同步电路，其特征在于，所述时钟域通道电路包括：多个触发器，用于在所述读时钟信号的上升沿和下降沿分别对所述写使能信号进行采样，以得到所述多个采样结果；
    多路信号选择器，用于根据所述时钟相位差从所述多个采样结果中选择一个采样结果，作为所述读使能信号。
  3. 根据权利要求2所述的跨时钟域同步电路，其特征在于，所述多个触发器包括第一触发器、第二触发器、第三触发器以及第四触发器；
    所述第一触发器，用于在所述读时钟信号的下降沿对所述写使能信号进行采样，得到第一采样信号；
    所述第二触发器，用于在所述读时钟信号的上升沿对所述第一采样信号进行采样，得到第二采样信号；
    所述第三触发器，用于在所述读时钟信号的上升沿对所述写使能信号进行采样，得到第三采样信号；
    所述第四触发器，用于在所述读时钟信号的上升沿对所述第三采样信号进行采样，得到第四采样信号，其中，所述第一采样信号、所述第二采样信号、所述第三采样信号以及所述第四采样信号为所述多个采样结果。
  4. 根据权利要求2或3所述的跨时钟域同步电路，其特征在于，所述多路信号选择器具体用于：
    在所述时钟相位差为[0T,1/4T)的情况下，从所述多个采样结果中选择所述第二采样信号作为所述读使能信号，其中，所述T为所述写时钟域的时钟周期或读时钟域的时钟周期；
    或，
    在所述时钟相位差为[1/4T,1/2T)的情况下，从所述多个采样结果中选择所述第二采样信号或所述第四采样信号作为所述读使能信号；
    或，
    在所述时钟相位差为[1/2T,3/4T)的情况下，从所述多个采样结果中选择所述第四采样信号作为所述读使能信号；
    或，
    在所述时钟相位差的取值大于或等于3/4个所述时钟周期T的情况下，从所述多个采样结果中选择所述第二采样信号或所述第三采样信号作为所述读使能信号。
  5. 根据权利要求1至4任一项所述的跨时钟域同步电路，其特征在于，所述跨时钟域同步电路还包括鉴相器；
    所述鉴相器，用于根据所述写时钟信号和所述读时钟信号确定所述时钟相位差；
    所述鉴相器，还用于根据所述写时钟信号产生所述写使能信号，其中，当所述写时钟信号与所述读时钟信号之间的所述时钟相位差处于稳定状态时，所述写使能信号有效。
  6. 根据权利要求1至5任一项所述的跨时钟域同步电路，其特征在于，所述跨时钟域同步电路还包括第五D触发器；
    所述第五D触发器，用于在所述读时钟信号的驱动下，缓存并输出所述数据缓存电路产生的所述输出数据。
  7. 根据权利要求1至6任一项所述的跨时钟域同步电路，其特征在于，所述跨时钟域同步电路还包括写时钟域锁相环和读时钟域锁相环；
    所述写时钟域锁相环，用于根据时钟源信号得到所述写时钟信号；
    所述读时钟域锁相环，用于根据所述时钟源信号得到所述读时钟信号。
  8. 根据权利要求1至7任一项所述的跨时钟域同步电路，其特征在于，所述数据缓存电路包括多个触发器组、输入多路数据选择器和输出多路数据选择器，所述输入数据选择器包括与所述多个触发器组的多个输入端一一对应连接的多个输出端口，所述输出多路数据选择器包括与所述多个触发器组的多个输出端一一对应连接的多个输入端口；
    所述输入多路数据选择器，用于接收所述输入数据，并根据所述写地址，从所述输入多路数据选择器的所述多个输出端口中选择一个输出端口输出缓存数据，所述缓存数据由所述输入数据得到；
    所述多个触发器组，用于在所述写时钟信号的驱动下，缓存所述缓存数据；
    所述输出多路数据选择器，用于接收所述多个触发器组输出的多个所述缓存数据，并根据所述读地址从所述多个所述缓存数据中选择一路缓存数据作为所述输出数据输出。
  9. 一种跨时钟域同步方法，其特征在于，所述方法包括：
    根据写使能信号得到写地址，根据所述写地址的控制来接收并缓存输入数据，所述输入数据处于写时钟域；
    对所述写使能信号进行采样以得到多个采样结果，并根据时钟相位差从所述多个采样结果中选择一个采样结果作为读使能信号，其中，所述时钟相位差为处于所述写时钟域的写时钟信号和处于读时钟域的读时钟信号的相位差；
    根据所述读使能信号得到读地址，根据所述读地址的控制将缓存的所述输入数据输出以产生输出数据，所述输出数据处于所述读时钟域。
  10. 根据权利要求9所述的方法，其特征在于，所述对所述写使能信号进行采样以得 到多个采样结果包括：
    在所述读时钟信号的上升沿和下降沿分别对所述写使能信号进行采样，以得到所述多个采样结果。
  11. 根据权利要求10所述的方法，其特征在于，在所述读时钟信号的上升沿和下降沿分别对所述写使能信号进行采样，以得到所述多个采样结果包括：
    在所述读时钟信号的下降沿对所述写使能信号进行采样，得到第一采样信号；
    在所述读时钟信号的上升沿对所述第一采样信号进行采样，得到第二采样信号；
    在所述读时钟信号的上升沿对所述写使能信号进行采样，得到第三采样信号；
    在所述读时钟信号的上升沿对所述第三采样信号进行采样，得到第四采样信号，其中，所述第一采样信号、所述第二采样信号、所述第三采样信号以及所述第四采样信号为所述多个采样结果。
  12. 根据权利要求9至11中任一项所述的方法，其特征在于，所述根据所述时钟相位差从所述多个采样结果中选择一个采样结果作为所述读使能信号包括：
    在所述时钟相位差为[0T,1/4T)的情况下，从所述多个采样结果中选择所述第二采样信号作为所述读使能信号，其中，所述T为所述写时钟域的时钟周期或读时钟域的时钟周期；
    或，
    在所述时钟相位差为[1/4T,1/2T)的情况下，从所述多个采样结果中选择所述第二采样信号或所述第四采样信号作为所述读使能信号；
    或，
    在所述时钟相位差为[1/2T,3/4T)的情况下，从所述多个采样结果中选择所述第四采样信号作为所述读使能信号；
    或，
    在所述时钟相位差的取值大于或等于3/4个所述时钟周期T的情况下，从所述多个采样结果中选择所述第二采样信号或所述第三采样信号作为所述读使能信号。
  13. 根据权利要求9至12中任一项所述的方法，其特征在于，所述方法还包括：
    根据所述写时钟信号和所述读时钟信号确定所述时钟相位差；
    根据所述写时钟信号产生所述写使能信号，其中，当所述写时钟信号与所述读时钟信号之间的所述时钟相位差处于稳定状态时，所述写使能信号有效。
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