WO2020118875A1 - 阵列基板及具有该阵列基板的显示装置 - Google Patents

阵列基板及具有该阵列基板的显示装置 Download PDF

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Publication number
WO2020118875A1
WO2020118875A1 PCT/CN2019/072855 CN2019072855W WO2020118875A1 WO 2020118875 A1 WO2020118875 A1 WO 2020118875A1 CN 2019072855 W CN2019072855 W CN 2019072855W WO 2020118875 A1 WO2020118875 A1 WO 2020118875A1
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Prior art keywords
layer
hole
array substrate
opening
trace
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PCT/CN2019/072855
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English (en)
French (fr)
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胡俊艳
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武汉华星光电半导体显示技术有限公司
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Priority to US16/467,064 priority Critical patent/US10923511B2/en
Publication of WO2020118875A1 publication Critical patent/WO2020118875A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the invention relates to the field of liquid crystal display, in particular to a display panel and a display device.
  • the array substrate generally includes a display area and a bending area (pad bending).
  • the structure of the array substrate is mainly composed of a double-layer base layer, an organic layer, metal traces, organic photoresist, and UV glue from bottom to top.
  • the current single-layer base layer is generally set at about 10um, this thickness of The base layer can cover and flatten some defects to reduce the impact of defects on yield.
  • the current double-layer base structure is very thick.
  • the thickness of the double-layer base layer is close to 20um, and there is an inorganic film layer in the middle of the double-layer base layer, and because the material of the base layer is polyimide (PI)
  • PI polyimide
  • the material's Young's modulus is relatively large, generally around 10Gpa, so it is difficult to adjust the stress on the metal trace by adjusting the thickness of the organic photoresist or UV glue above the metal trace. Therefore, in the current array substrate, the neutral plane is usually located in the base layer, and the metal trace is above the neutral plane. Therefore, when bent, the metal trace is subjected to tensile stress.
  • the current display panels tend to develop in the direction of narrow bezels. Therefore, the width and bending radius of the bending area are getting smaller and smaller, so the stress on the metal wiring is also multiplied.
  • the metal wiring It is very easy to break, and after bending, it will cause abnormal picture in the display area; and the adhesion between the upper base layer and the inorganic film layer in the double-layer base layer is limited, and the base layer and the inorganic film layer are easily bent when bending. And disengagement seriously affects yield.
  • the present invention provides a display device having the array substrate, an opening is formed in the bending area, and the opening extends into the second base layer, and a metal trace is formed on the inner surface of the opening,
  • the organic photoresist is filled above the metal traces in the openings, so that the neutral plane is on the layer where the metal traces are located, reducing the stress on the metal traces in the bending area.
  • the technical solution to the above problem is to provide an array substrate, which is characterized by having a display area and a bending area surrounding the display area, the array substrate includes a first base layer; a first buffer layer covers the A first base layer; a second base layer covering the first buffer layer; at least one opening, at least a portion of the opening is located on the second base layer, and corresponds to the bending area; metal walk A line, distributed in the display area and the bending area, and at least a part of the metal trace covers the inner surface of the opening; an organic layer is filled in the opening and covered in the The metal trace in the opening.
  • the first buffer layer has a first through hole, and the first through hole corresponds to the opening.
  • the projection of the metal trace on the first buffer layer completely falls within the range of the first through hole.
  • the array substrate further includes a second buffer layer covering the second base layer; a first gate insulating layer covering the second buffer layer; a second gate An insulating layer covering the first gate insulating layer; a dielectric layer covering the second gate insulating layer; the metal trace is formed on the dielectric layer and the opening Groove surface; in the bending area, the opening penetrates from the dielectric layer into the second base layer.
  • the opening is a stepped structure or an inverted tower-like structure, which includes a plurality of holes, the holes are stacked from the dielectric layer to the second base layer, wherein The width of a hole below is less than or equal to the width of a hole above and adjacent to it.
  • the width of the hole decreases in sequence.
  • the hole body has a hole wall, a hole bottom and an orifice, the hole wall extends from the hole bottom to the hole, and the width of the hole bottom is smaller than that of the hole Width, there is an angle between the hole wall and the hole bottom, and the angle range is 45°-70°.
  • the opening includes a first hole body penetrating from the dielectric layer to the inside of the first buffer layer; a second hole body penetrating from the first buffer layer to the second base layer and at A hole bottom is formed in the second base layer, and the width of the second hole body is smaller than the width of the first hole body; the ratio of the depth of the first hole body to the depth of the second hole body is 0.1- 5.
  • the array substrate further includes a flat layer provided on the metal traces, the dielectric layer and the organic layer; a pixel definition layer provided on the flat layer; in the display area, the The array substrate further includes an active layer having a source region and a drain region, the active layer is provided on the second buffer layer, and the first gate insulating layer covers the active layer; A gate layer provided on the first gate insulating layer, the second gate insulating layer covering the first gate layer; a second gate layer provided on the second gate On the insulating layer, the dielectric layer overlies the second gate layer; a second through hole penetrates from the dielectric layer to the active layer, wherein a second through hole corresponds to the source A second via hole corresponding to the drain region; the metal trace includes a source trace and a drain trace, and the source region is correspondingly connected to the source trace, so The drain region is correspondingly connected to the drain trace; a third through hole penetrates the flat layer and the drain trace is exposed in the third through hole; an anode trace is provided on the flat
  • the invention also provides a display device including the array substrate.
  • an opening is formed in the bending area, and the opening extends into the second base layer, and a metal trace is formed on the inner surface of the opening Fill the organic photoresist above the metal traces, so that the neutral plane is at the layer where the metal traces are or as close as possible to the layer where the metal traces are, reducing the stress on the metal traces in the bending area, and bringing the metal traces closer to the neutral plane The smaller the tensile stress, the more resistant to bending.
  • the array substrate and the display device with the array substrate of the present invention only adjust the thickness of the base layer and the inorganic film layer in the bending area, without changing the thickness of the base layer of the display area, to ensure At the same time, due to the downward movement of the metal traces in the bending zone, the stress it bears becomes smaller, which is beneficial to achieve a bending with a smaller bending radius.
  • FIG. 1 is a structural diagram of a first buffer layer after forming an array substrate in an embodiment.
  • FIG. 2 is a structural diagram after the formation of the second base layer in the manufacturing process of the array substrate in the embodiment.
  • FIG. 3 is a structural diagram after the formation of the first hole in the manufacturing process of the array substrate in the embodiment.
  • FIG. 4 is a structural diagram after the formation of the second hole in the manufacturing process of the array substrate in the embodiment.
  • FIG. 5 is a structural diagram after the formation of metal traces in the manufacturing process of the array substrate in the embodiment.
  • FIG. 6 is a structural diagram after the organic layer is formed in the manufacturing process of the array substrate in the embodiment.
  • FIG. 7 is a structural diagram of a flat layer after formation of an array substrate in an embodiment.
  • FIG 8 is a structural diagram of a pixel definition layer after the formation of an array substrate in the manufacturing process of the embodiment.
  • the neutral plane is in the layer where the metal trace is located.
  • FIG. 9 is a schematic diagram of a display device in an embodiment.
  • 21a The first hole body; 21b second hole body;
  • an array substrate 10 of the present invention has a display area 101 and a bending area 102 surrounding the display area 101, wherein the array substrate 10 includes a first base layer 11.
  • the first buffer layer 12 covers the first base layer 11.
  • the second base layer 13 covers the first buffer layer 12.
  • the second buffer layer 14 covers the second base layer 13.
  • the materials of the first base layer 11 and the second base layer 13 are both polyimide materials, and the first buffer layer 12 and the second buffer layer 14 are inorganic materials that are isolated from water and oxygen. material.
  • the first gate insulating layer 15 covers the second gate insulating layer 16.
  • the dielectric layer 17 covers the second gate insulating layer 16.
  • the metal trace 18 covers the dielectric layer 17.
  • the metal trace 18 is distributed in the display area 101 and the bending area 102.
  • the flat layer 19 covers the metal trace 18 and the flat layer 19.
  • the array substrate 10 further includes an opening 2 and an organic layer 6 (see FIG. 6), and the opening 2 is separated from the dielectric
  • the layer 17 extends into the second base layer 13.
  • the metal trace 18 covers the inner surface of the opening 2
  • the organic layer 6 is filled in the opening 2 and covers the For metal traces 18, the height of the organic layer 6 does not exceed the depth of the opening 2.
  • the neutral plane 7 passes through the metal trace 18 in the bending zone 102 or the neutral plane 7 is as close as possible to the layer where the metal trace 18 is located.
  • the opening 2 is a stepped structure or an inverted tower structure, which includes a plurality of hole bodies 21 that are stacked from the dielectric layer 17 to the second base layer 13 at a level Settings. From the direction of the dielectric layer 17 to the second base layer 13, the width of the hole 21 decreases in sequence. The width of the pores formed in the lower layer is less than or equal to the width of the pores of the upper layer adjacent thereto. In this embodiment, each hole 21 has a trapezoid shape, so the width of the hole actually refers to the average width of the hole.
  • the opening 2 has a hole wall 213, a hole bottom 210 and an orifice 212.
  • the hole wall 213 extends from the hole bottom 210 to the hole 212, and the width of the hole bottom 210 is smaller than the hole 212 Width, there is an angle between the hole wall 213 and the hole bottom 210, and the angle range is 45°-70°.
  • the smaller the included angle the gentler the slope of the hole wall 213.
  • the gentler slope of the hole wall 213 is beneficial to the formation of the metal trace 18 and increases the adhesion between the metal trace 18 and the inner surface of the opening 2, Moreover, as much as possible, most of the metal traces 18 in the bending zone 102 can be close to the neutral plane 7.
  • the opening 2 includes a first hole 21a and a second hole 21b.
  • the first hole 21a penetrates from the dielectric layer 17 to the second buffer layer 14; the second hole 21b penetrates from the second buffer layer 14 into the second base layer 13, and A hole bottom 210 is formed in the second base layer 13, the width of the second hole body 21b is smaller than the width of the first hole body 21a; the depth of the first hole body 21a and the second hole body 21b The ratio of the depth is 0.1-5.
  • the depth of the hole body 21 in different layers and the slope of the hole wall 213 are combined, and the depth of the hole body 21 is set to adjust the corresponding The slope of the hole wall 213 of the hole body 21 is used to improve the stress on the metal trace 18 covering the inner surface of the opening 2.
  • the The first buffer layer 12 and the first base layer 11 and the second base layer 13 have different degrees of deformation.
  • the material of the first buffer layer 12 is an inorganic material.
  • the The first buffer layer 12 may be separated from the first base layer 11 and the second base layer 13, and the neutral plane 7 (see FIG. 8) may be easily biased toward one side of the first base layer 11 This shift affects the stress on the metal trace 18 in the bending zone 102. Therefore, in this embodiment, a first through hole 3 (see FIG.
  • the first through hole 3 is filled with a polyimide material, so that the first base layer 11 and the second base layer 13 in the bending region 102 are connected to each other.
  • the projection of the metal trace 18 on the first buffer layer 12 completely falls within the range of the first through hole 3.
  • the array substrate 10 further includes an active layer 1011, a first gate layer 1012, a second gate layer 1013, and a second through hole 4 (see FIG. 4). Third through hole 5 (see Figure 7), anode trace 110, etc.
  • the active layer 1011 has a source region 10111 and a drain region 10112, the active layer 1011 is disposed on the second buffer layer 14, and the first gate insulating layer 15 covers the active layer 1011.
  • the first gate layer 1012 is disposed on the first gate insulating layer 15, the second gate insulating layer 16 overlays the first gate layer 1012; the second gate layer 1013 Provided on the second gate insulating layer 16, the dielectric layer 17 covers the second gate layer 1013; the second through hole 4 penetrates from the dielectric layer 17 to the The source layer 1011, wherein one second through hole 4 corresponds to the source region 10111, and the other second through hole 4 corresponds to the drain region 10112; the metal trace 18 includes a source trace 181 and a drain An electrode trace 182, the source region 10111 is correspondingly connected to the source trace 181, the drain region 10112 is correspondingly connected to the drain trace 182; the third through hole 5 penetrates the A flat layer 19 and the drain trace 182 is exposed in the third through hole 5; the anode trace 110 (see FIG. 8) is provided on the flat layer 19 and passes through the third through hole 5 Connect to the drain trace 182.
  • the following embodiment provides a method for manufacturing the array substrate 10, and the method specifically includes the following steps.
  • a glass substrate 100 is provided.
  • a layer of polyimide material is coated on a surface of the glass substrate 100 to form the first base layer 11.
  • An inorganic material having a function of isolating water and oxygen is deposited on the first base layer 11 to form a first buffer layer 12.
  • the first buffer layer 12 is etched through a dry etching process to form the first through hole 3.
  • the first through hole 3 corresponds to the bending area 102.
  • the first through hole 3 is filled with a polyimide material, and a layer of polyimide material is coated on the first buffer layer 12 to form a second base layer 13.
  • a second buffer layer 14 is formed on the second base layer 13 by deposition.
  • the material used for the second buffer layer 14 and the material used for the first buffer layer 12 are both inorganic materials, and the materials may be the same or different.
  • an active layer 1011 is formed on the second buffer layer 14, and the active layer 1011 is crystallized and patterned to form a source region 10111 and a drain region 10112.
  • a first gate insulating layer 15 is formed on the active layer 1011 and the second buffer layer 14 by a deposition method.
  • a first metal layer is formed on the first gate insulating layer 15, and the first metal layer is patterned to form gates and gate traces.
  • a second gate insulating layer 16 is formed on the first metal layer and the first gate insulating layer 15 by a deposition method.
  • a second metal layer is formed on the second gate insulating layer 16, and the second metal layer is patterned to form a capacitor second electrode plate and a drain line.
  • a dielectric layer 17 is formed on the second metal layer and the second gate insulating layer 16 by a deposition method.
  • the dielectric layer 17 is etched to form a second through hole 4, and the bending area 102 is also etched Etch to form a first hole 21a.
  • the second through hole 4 extends from the dielectric layer 17 to the active layer 1011, wherein one second through hole 4 corresponds to the source region 10111, and the other second through hole 4 corresponds to The drain region 10112; the first hole 21a penetrates from the dielectric layer 17 into the second buffer layer 14.
  • the second buffer layer 14 and the second base layer 13 are etched in the first hole 21 a corresponding to the bending region 102 to form a second hole 21 b.
  • the second hole 21 b extends from the second buffer layer 14 into the second base layer 13.
  • the first hole 21 a and the second hole 21 b form a stepped opening 2.
  • the ratio of the depth of the first hole 21a to the depth of the second hole 21b is 0.1-5. Since the opening 2 is arranged in a stepped structure, the depth of the hole body 21 at different levels and the slope of the hole wall 213 are combined to adjust the corresponding hole body by setting the depth of the hole body 21
  • the slope of the hole wall 213 of 21 is to improve the stress on the metal trace 18 covering the inner surface of the opening 2.
  • metal traces 18 extending from the display area 101 to the bending area 102 are formed on the dielectric layer 17 and in the opening 2.
  • the metal trace 18 is patterned to form a source 183 connected to the source region 10111, a drain 184 connected to the drain region 10112, and a metal trace 18, the metal trace 18 includes a The source trace 181 of the source 183 and the drain trace 182 connected to the drain 184.
  • the opening 2 is filled with an organic photoresist material, and an organic layer 6 is formed.
  • the organic layer 6 covers the metal trace 18, and the height of the organic layer 6 does not exceed the depth of the opening 2.
  • an organic film layer is coated and patterned to form a flat layer 19 and corresponding The third through hole 5 in the drain region 10112.
  • the third through hole 5 penetrates the flat layer 19 and the drain trace 182 is exposed to the third through hole 5.
  • an anode metal layer is formed on the flat layer 19 by a deposition method, and patterned to form an anode trace 110 that is connected to the drain trace 182.
  • An organic photoresist is coated on the anode trace 110, and a pixel definition layer 111 is formed.
  • the present invention also provides a display device 1 including the above array substrate 10.
  • the main design point of this embodiment lies in the array substrate 10, especially the layered distribution structure of the bending region 102 in the array substrate 10, that is, the opening 2 is formed in the bending region 102, and the opening 2 extends to the second base layer 13 and the metal trace 18 is formed on the inner surface of the opening 2, the organic photoresist is filled above the metal trace 18 in the opening 2, so that the neutral plane 7 passes through the metal trace 18 to reduce the bending area 102 Of the metal trace 18 is subjected to stress.
  • the display device 1 such as the encapsulation layer, the polarizer, the color film substrate 20, etc.

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Abstract

一种阵列基板（10）及具有该阵列基板（10）的显示装置（1），阵列基板（10）具有显示区（101）以及围绕所述显示区（101）的弯折区（102），阵列基板（10）包括第一基层（11）、第一缓冲层（12）、第二基层（13）；以及开孔（2）的至少一部分位于第二基层（13）上，且对应于弯折区（102）；金属走线（18）的至少一部分覆于开孔（2）的内表面；有机层（6）填充于开孔（2）中且包覆位于开孔（2）内的金属走线（18）。阵列基板（10）及具有该阵列基板（10）的显示装置（1），在弯折区（102）形成开孔（2），且开孔（2）延伸至第二基层（13）内，并将金属走线（18）形成在开孔（2）的内表面，在开孔（2）内的金属走线（18）上方填充有机光阻，使得中性面（7）在金属走线（18）所在层，降低弯折区（102）的金属走线（18）所承受应力。

Description

阵列基板及具有该阵列基板的显示装置 技术领域
本发明涉及液晶显示领域，特别涉及一种显示面板及显示装置。
 背景技术
目前，阵列基板一般包括显示区和弯折区（pad bending），在弯折区中，阵列基板的结构从下到上主要为双层基层、有机层、金属走线、有机光阻、UV胶等；首先，因PI 涂布时，因材料本身和外界原因，容易形成一些瑕疵，而这些瑕疵基本都会严重影响产品良率，所以目前的单层的基层一般都设置在10um左右，此厚度的基层可以将一些瑕疵进行包覆和平坦，减小瑕疵对良率的影响。其次，因双层基层结构中间有一层无机膜层阻挡，其隔绝水氧能力更强，且激光剥离时，高能量的激光不容易损伤上面的薄膜晶体管。因此，以上原因会造成目前的双层基层结构非常厚，双层基层的厚度接近20um，而且，双层基层的中间还有一层无机膜层，且因为基层的材料为聚酰亚胺（PI）材料，其杨氏模量较大，一般为10Gpa左右，所以很难通过调整金属走线上方的有机光阻或者UV胶的厚度来对金属走线所受的应力进行调整。因此，在目前的阵列基板中，中性面通常位于基层中，金属走线处于中性面的上方，所以弯折时，金属走线受拉应力。
此外，目前显示面板多向窄边框的方向发展，因此，弯折区的宽度和弯折半径越来越小，由此金属走线所受的应力也是成倍增加，弯折时，金属走线极易发生断裂，弯折后，导致显示区的画面异常；而双层基层中的上层基层和无机膜层之间附着力有限，弯折时极易发生基层和无机膜层之间相互弯折且脱离，严重影响良率。
为改善上述问题，现有技术中也出现很多对基层减薄工艺，如对下层基层进行激光减薄，但因激光减薄工艺有限，基层的平坦度无法很好控制，且激光减薄时容易对上面的金属走线造成一定程度损伤。
 技术问题
为了解决上述技术问题，本发明提供一种具有该阵列基板的显示装置，在弯折区形成开孔，且开孔延伸至第二基层内，并将金属走线形成在开孔的内表面，在开孔内的金属走线上方填充有机光阻，使得中性面在金属走线所在层，降低弯折区的金属走线所承受应力。
 技术解决方案
解决上述问题的技术方案是：提供一种阵列基板，其特征在于，具有显示区以及围绕所述显示区的弯折区，所述阵列基板包括第一基层；第一缓冲层，覆于所述第一基层上；第二基层，覆于所述第一缓冲层上；至少一开孔，所述开孔的至少一部分位于所述第二基层上，且对应于所述弯折区；金属走线，分布于所述显示区和所述弯折区，且所述金属走线的至少一部分覆于所述开孔的内表面；有机层，填充于所述开孔中且包覆位于所述开孔内的所述金属走线。
在本发明一实施例中，所述第一缓冲层中具有第一通孔，所述第一通孔对应所述开孔。
在本发明一实施例中，在所述弯折区，所述金属走线在所述第一缓冲层上的投影，完全落入所述第一通孔的范围内。
在本发明一实施例中，所述的阵列基板还包括第二缓冲层，覆于所述第二基层上；第一栅极绝缘层，覆于所述第二缓冲层上；第二栅极绝缘层，覆于所述第一栅极绝缘层上；介电层，覆于所述第二栅极绝缘层上；所述金属走线形成于所述介电层上以及所述开孔的槽面上；在所述弯折区，所述开孔从所述介电层贯穿至所述第二基层内。
在本发明一实施例中，所述开孔为台阶结构或倒立的塔状结构，其包括若干孔体，所述孔体从所述介电层向所述第二基层叠加设置，其中，位于下方的一个孔体的宽度小于或等于位于上方的并与其相邻的一个孔体的宽度。
在本发明一实施例中，从所述介电层向所述第二基层，所述孔体的宽度依次减小。
在本发明一实施例中，所述孔体具有孔壁、孔底和孔口，所述孔壁从所述孔底向所述孔口延伸，所述孔底的宽度小于所述孔口的宽度，所述孔壁与所述孔底之间存在一夹角，该夹角范围为45°-70°。所述开孔包括第一孔体，从所述介电层贯穿至所述第一缓冲层的内部；第二孔体，从所述第一缓冲层贯穿至所述第二基层内，并在所述第二基层内形成孔底，所述第二孔体的宽度小于所述第一孔体的宽度；所述第一孔体的深度与所述第二孔体的深度的比值为0.1-5。
所述的阵列基板还包括平坦层，设于所述金属走线、所述介电层以及所述有机层上；像素定义层，设于所述平坦层上；在所述显示区，所述阵列基板还包括有源层，具有源极区和漏极区，所述有源层设于所述第二缓冲层上，所述第一栅极绝缘层覆于所述有源层上；第一栅极层，设于所述第一栅极绝缘层上，所述第二栅极绝缘层覆于所述第一栅极层上；第二栅极层，设于所述第二栅极绝缘层上，所述介电层覆于所述第二栅极层上；第二通孔，从所述介电层贯穿至所述有源层，其中一第二通孔对应于所述源极区，另一第二通孔对应于所述漏极区；所述金属走线包括源极走线和漏极走线，所述源极区对应的连接至所述源极走线，所述漏极区对应连接至所述漏极走线；第三通孔，贯穿所述平坦层且所述漏极走线显露于所述第三通孔；阳极走线，设于所述平坦层上且通过所述第三通孔连接至所述漏极走线。
本发明还提供了一种显示装置，包括所述的阵列基板。
 有益效果
本发明的阵列基板及具有该阵列基板的显示装置，在弯折区形成开孔，且开孔延伸至第二基层内，并将金属走线形成在开孔的内表面，在开孔内的金属走线上方填充有机光阻，使得中性面在金属走线所在层或者尽量接近金属走线所在层，降低弯折区的金属走线所承受应力，将金属走线越靠近中性面受到的拉应力越小，从而越耐弯折，本发明的阵列基板及具有该阵列基板的显示装置仅对弯折区的基层厚度和无机膜层进行了调整，没有改变显示区基层膜厚，保证了良率，同时因弯折区中的金属走线下移，所承受应力变小，利于实现更小弯曲半径的弯折。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
下面结合附图和实施例对本发明作进一步解释。
图1是实施例中的阵列基板制作过程中第一缓冲层形成后的结构图。
图2是实施例中的阵列基板制作过程中第二基层形成后的结构图。
图3是实施例中的阵列基板制作过程中第一孔体形成后的结构图。
图4是实施例中的阵列基板制作过程中第二孔体形成后的结构图。
图5是实施例中的阵列基板制作过程中金属走线形成后的结构图。
图6是实施例中的阵列基板制作过程中有机层形成后的结构图。
图7是实施例中的阵列基板制作过程中平坦层形成后的结构图。
图8是实施例中的阵列基板制作过程中像素定义层等形成后的结构图.图中，中性面在所述金属走线所在层中。
图9是实施例中的显示装置示意图。
附图标记：
1显示装置；
10阵列基板；                        20彩膜基板；
101显示区；                         102弯折区；
100玻璃基板；
11第一基层；                       12第一缓冲层；
13第二基层；                       14第二缓冲层；
15第一栅极绝缘层；                 16第二栅极绝缘层；
17介电层；                         18金属走线；
19平坦层；                         110阳极走线；
111像素定义层；
1011有源层；
10111源极区；                       10112漏极区；
1012第一栅极层；                    1013第二栅极层；
181源极走线；                       182漏极走线；
183源极；                           184漏极；
2开孔；                             21孔体；
21a第一孔体；                       21b第二孔体；
210孔底；                           212孔口；
213孔壁；
3第一通孔；                          4第二通孔；
5第三通孔；                           6有机层；
7中性面。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
以下实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图1至图8所示，在一实施例中，本发明的阵列基板10，具有显示区101以及围绕所述显示区101的弯折区102，其中，所述阵列基板10包括第一基层11、第一缓冲层12、第二基层13、第二缓冲层14、第一栅极绝缘层15、第二栅极绝缘层16、介电层17、金属走线18、平坦层19、以及像素定义层111。
如图1所示，所述第一缓冲层12覆于所述第一基层11上。
如图2所示，所述第二基层13覆于所述第一缓冲层12上。
如图3所示，所述第二缓冲层14覆于所述第二基层13上。在本实施例中，所述第一基层11和所述第二基层13的材料均为聚酰亚胺材料，所述第一缓冲层12和所述第二缓冲层14为隔绝水氧的无机材料。
参见图8所示，所述第一栅极绝缘层15覆于所述第二栅极绝缘层16上。所述介电层17覆于所述第二栅极绝缘层16上。所述金属走线18覆于所述介电层17上，所述金属走线18分布于所述显示区101和所述弯折区102。所述平坦层19覆于所述金属走线18以及所述平坦层19上。
如图3、图4、图6所示，在所述弯折区102，所述阵列基板10还包括开孔2以及有机层6（参见图6），所述开孔2从所述介电层17延伸至所述第二基层13内。在所述弯折区102的所述开孔2位置，所述金属走线18覆于所述开孔2的内表面，所述有机层6填充于所述开孔2中且包覆所述金属走线18，所述有机层6的高度不超过所述开孔2的深度。中性面7经过所述弯折区102中的所述金属走线18或者中性面7尽量接近所述金属走线18所在层。
本实施例中，所述开孔2为台阶结构或倒立的塔状结构，其包括若干孔体21，所述若干孔体21按层级从所述介电层17向所述第二基层13叠加设置。从所述介电层17向所述第二基层13的方向，所述孔体21的宽度依次减小。其中，形成于下层的孔体的宽度小于或等于与其相邻的上层的孔体的宽度。在本实施例中，每一孔体21均呈梯状，因此所述孔体的宽度实际上是指所述孔体的平均宽度。所述开孔2具有孔壁213、孔底210和孔口212，所述孔壁213从所述孔底210向所述孔口212延伸，所述孔底210的宽度小于所述孔口212的宽度，所述孔壁213与所述孔底210之间存在一夹角，该夹角范围为45°-70°。该夹角越小，则为所述孔壁213的坡度越平缓，所述孔壁213的坡度平缓有利于金属走线18的形成以及增加金属走线18与开孔2内表面的附着力，而且能够尽量使得弯折区102大部分的金属走线18能够靠近中性面7。
如图4所示，本实施例以两层的孔体作为示例，对所述台阶结构进行详细说明。即所述开孔2包括第一孔体21a和第二孔体21b。所述第一孔体21a从所述介电层17贯穿至所述第二缓冲层14；所述第二孔体21b从所述第二缓冲层14贯穿至所述第二基层13内，并在所述第二基层13内形成孔底210，所述第二孔体21b的宽度小于所述第一孔体21a的宽度；所述第一孔体21a的深度与所述第二孔体21b的深度的比值为0.1-5。本实施例，由于所述弯折区102的宽度有限，将不同层的所述孔体21的深度与所述孔壁213的坡度结合起来，通过设定孔体21的深度来调节对应所述孔体21的孔壁213的坡度，以改善覆于所述开孔2的内表面的金属走线18所承受的应力。
如图2所示，并同时参见图8，由于所述第一缓冲层12和所述第一基层11、第二基层13的材料特性不同，在所述弯折区102在弯折时，所述第一缓冲层12和所述第一基层11及所述第二基层13发生的形变程度不同，所述第一缓冲层12的材料为无机材料，所述弯折区102弯折时，所述第一缓冲层12会与所述第一基层11及所述第二基层13之间发生脱离现象，而且容易使得中性面7（参见图8）向所述第一基层11的一侧偏移，影响弯折区102中金属走线18所承受的应力。因此，本实施例中，在所述第一缓冲层12上开设第一通孔3（见图1），所述第一通孔3对应开孔2（见图3）。所述第一通孔3由聚酰亚胺材料填充，这样使得在弯折区102的所述第一基层11和第二基层13相互连接。
在弯折区102中，为了使得中性面7尽可能的经过所述金属走线18，使得所述金属走线18大部分都邻近或者部分落入中性面7上，本实施例中，在所述弯折区102，所述金属走线18在所述第一缓冲层12上的投影，完全落入所述第一通孔3的范围内。
如图3至图8所示，在所述显示区101，所述阵列基板10还包括有源层1011、第一栅极层1012、第二栅极层1013、第二通孔4（见图4）、第三通孔5（见图7）、阳极走线110等。所述有源层1011具有源极区10111和漏极区10112，所述有源层1011设于所述第二缓冲层14上，所述第一栅极绝缘层15覆于所述有源层1011上。所述第一栅极层1012设于所述第一栅极绝缘层15上，所述第二栅极绝缘层16覆于所述第一栅极层1012上；所述第二栅极层1013设于所述第二栅极绝缘层16上，所述介电层17覆于所述第二栅极层1013上；所述第二通孔4从所述介电层17贯穿至所述有源层1011，其中一第二通孔4对应于所述源极区10111，另一第二通孔4对应于所述漏极区10112；所述金属走线18包括源极走线181和漏极走线182，所述源极区10111对应的连接至所述源极走线181，所述漏极区10112对应连接至所述漏极走线182；所述第三通孔5贯穿所述平坦层19且所述漏极走线182暴露于所述第三通孔5中；所述阳极走线110（见图8）设于所述平坦层19上且通过所述第三通孔5连接至所述漏极走线182。
为了更加清楚的解释本发明，下面本实施例提供一种阵列基板10的制作方法，该方法具体包括如下步骤。
如图1所示，提供一玻璃基板100。
参见图1，在玻璃基板100的一表面涂布一层聚酰亚胺材料，形成第一基层11。在第一基层11上沉积具有隔绝水氧功能的无机材料，形成第一缓冲层12。通过干刻工艺对所述第一缓冲层12进行刻蚀，形成第一通孔3。其中，所述第一通孔3对应于所述弯折区102。
参见图2，在所述第一通孔3中填充聚酰亚胺材料，以及在所述第一缓冲层12上涂布一层聚酰亚胺材料形成第二基层13。
参见图3.在所述第二基层13上沉积法形成第二缓冲层14，第二缓冲层14所用材料与第一缓冲层12所用材料均为无机材料，材料可以相同也可以不同。对应所述显示区101，在所述第二缓冲层14上形成有源层1011，并对所述有源层1011进行结晶和图案化，形成源极区10111和漏极区10112。在所述有源层1011上和所述第二缓冲层14上通过沉积法形成第一栅极绝缘层15。对应所述显示区101，在所述第一栅极绝缘层15上形成第一金属层，并对第一金属层进行图案化，形成栅极和栅极走线。在所述第一金属层和所述第一栅极绝缘层15上通过沉积法形成第二栅极绝缘层16。对应所述显示区101，在所述第二栅极绝缘层16上形成第二金属层，并对第二金属层进行图案化，形成电容第二极板和泄放线。在所述第二金属层和所述第二栅极绝缘层16上通过沉积法形成介电层17。
参见图3所示，对应所述显示区101的所述有源层1011所在区域，对所述介电层17进行刻蚀，形成第二通孔4，同时对所述弯折区102进行刻蚀，形成第一孔体21a。其中，所述第二通孔4从所述介电层17延伸至所述有源层1011，其中一第二通孔4对应于所述源极区10111，另一第二通孔4对应于所述漏极区10112；所述第一孔体21a从所述介电层17贯穿至所述第二缓冲层14中。
参见图4所示，对应所述弯折区102的所述第一孔体21a内，对所述第二缓冲层14以及所述第二基层13进行刻蚀，形成第二孔体21b。所述第二孔体21b从所述第二缓冲层14延伸至所述第二基层13中。所述第一孔体21a和所述第二孔体21b形成台阶结构的开孔2。所述第一孔体21a的深度与所述第二孔体21b的深度的比值为0.1-5。由于所述开孔2设置成台阶结构，因此，将不同层级的所述孔体21的深度与所述孔壁213的坡度结合起来，通过设定孔体21的深度来调节对应所述孔体21的孔壁213的坡度，以改善覆于所述开孔2的内表面的金属走线18所承受的应力。
参见图5所示，在所述介电层17上以及开孔2中形成从所述显示区101延伸至所述弯折区102的金属走线18。对所述金属走线18图案化，形成连接于所述源极区10111的源极183、连接于所述漏极区10112的漏极184以及金属走线18，该金属走线18包括连接于所述源极183的源极走线181和连接于所述漏极184的漏极走线182。
参见图6所示，在所述开孔2中填充有机光阻材料，并形成有机层6。所述有机层6包覆所述金属走线18，所述有机层6的高度不超过所述开孔2的深度。
参见图7所示，在所述介电层17以及所述介电层17上的金属走线18以及所述有机层6上，涂布有机膜层，并进行图案化形成平坦层19以及对应于所述漏极区10112的第三通孔5。所述第三通孔5贯穿所述平坦层19且所述漏极走线182暴露于所述第三通孔5。
参见图8所示，在所述平坦层19上通过沉积法形成阳极金属层，并图案化，形成阳极走线110，所述阳极走线110连接于所述漏极走线182。在所述阳极走线110上方涂布有机光阻，并形成像素定义层111等。
如图9所示，本发明还提供了一种显示装置1，包括所述的阵列基板10。本实施例的主要设计要点在于阵列基板10，特别是阵列基板10中所述弯折区102的层状分布结构，即在弯折区102形成开孔2，且开孔2延伸至第二基层13内，并将金属走线18形成在开孔2的内表面，在开孔2内的金属走线18上方填充有机光阻，使得中性面7经过金属走线18，降低弯折区102的金属走线18所承受应力。对于所述显示装置1的其他结构，（如封装层、偏光片、彩膜基板20等）就不再一一赘述。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种阵列基板，其具有显示区以及围绕所述显示区的弯折区，所述阵列基板包括
    第一基层；
    第一缓冲层，覆于所述第一基层上；
    第二基层，覆于所述第一缓冲层上；
    至少一开孔，所述开孔的至少一部分位于所述第二基层上，且对应于所述弯折区；
    金属走线，分布于所述显示区和所述弯折区，且所述金属走线的至少一部分覆于所述开孔的内表面；
    有机层，填充于所述开孔中且包覆位于所述开孔内的所述金属走线。
  2. 根据权利要求1所述的阵列基板，其中，所述第一缓冲层中具有第一通孔，所述第一通孔对应所述开孔。
  3. 根据权利要求2所述的阵列基板，其中，在所述弯折区，所述金属走线在所述第一缓冲层上的投影，完全落入所述第一通孔内。
  4. 根据权利要求1所述的阵列基板，其还包括
    第二缓冲层，覆于所述第二基层上；
    第一栅极绝缘层，覆于所述第二缓冲层上；
    第二栅极绝缘层，覆于所述第一栅极绝缘层上；
    介电层，覆于所述第二栅极绝缘层上；
    所述金属走线形成于所述介电层上以及所述开孔中；
    在所述弯折区，所述开孔从所述介电层贯穿至所述第二基层内。
  5. 根据权利要求4所述的阵列基板，其中，所述开孔为台阶结构或倒立的塔状结构，其包括若干孔体，所述孔体从所述介电层向所述第二基层叠加设置，其中，位于下方的一个孔体的宽度小于或等于位于上方的并与其相邻的一个孔体的宽度。
  6. 根据权利要求5所述的阵列基板，其中，从所述介电层向所述第二基层，所述孔体的宽度依次减小。
  7. 根据权利要求5所述的阵列基板，其中，所述开孔具有孔壁、孔底和孔口，所述孔壁从所述孔底向所述孔口延伸，所述孔底的宽度小于所述孔口的宽度，所述孔壁与所述孔底之间存在一夹角，该夹角范围为45°-70°。
  8. 根据权利要求5所述的阵列基板，其中，所述开孔包括
    第一孔体，从所述介电层贯穿至所述第一缓冲层；
    第二孔体，从所述第一缓冲层贯穿至所述第二基层内，并在所述第二基层内形成孔底，所述第二孔体的宽度小于所述第一孔体的宽度；
    所述第一孔体的深度与所述第二孔体的深度的比值为0.1-5。
  9. 根据权利要求4所述的阵列基板，其还包括
    平坦层，设于所述金属走线、所述介电层以及所述有机层上；
    像素定义层，设于所述平坦层上；
    在所述显示区，所述阵列基板还包括
    有源层，具有源极区和漏极区，所述有源层设于所述第二缓冲层上，所述第一栅极绝缘层覆于所述有源层上；
    第一栅极层，设于所述第一栅极绝缘层上，所述第二栅极绝缘层覆于所述第一栅极层上；
    第二栅极层，设于所述第二栅极绝缘层上，所述介电层覆于所述第二栅极层上；
    第二通孔，从所述介电层贯穿至所述有源层，其中一第二通孔对应于所述源极区，另一第二通孔对应于所述漏极区；
    所述金属走线包括源极走线和漏极走线，所述源极区对应的连接至所述源极走线，所述漏极区对应连接至所述漏极走线；
    第三通孔，贯穿所述平坦层且所述漏极走线显露于所述第三通孔；
    阳极走线，设于所述平坦层上且通过所述第三通孔连接至所述漏极走线。
  10. 一种显示装置，其包括如权利要求1所述的阵列基板。
PCT/CN2019/072855 2018-12-14 2019-01-23 阵列基板及具有该阵列基板的显示装置 WO2020118875A1 (zh)

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