WO2020116499A1 - Transistor à couches minces et son procédé de production - Google Patents

Transistor à couches minces et son procédé de production Download PDF

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Publication number
WO2020116499A1
WO2020116499A1 PCT/JP2019/047389 JP2019047389W WO2020116499A1 WO 2020116499 A1 WO2020116499 A1 WO 2020116499A1 JP 2019047389 W JP2019047389 W JP 2019047389W WO 2020116499 A1 WO2020116499 A1 WO 2020116499A1
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semiconductor layer
oxide semiconductor
thin film
film transistor
layer
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PCT/JP2019/047389
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English (en)
Japanese (ja)
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松尾　大輔
靖典 安東
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日新電機株式会社
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Priority to KR1020217016500A priority Critical patent/KR20210080549A/ko
Priority to CN201980080222.XA priority patent/CN113169232A/zh
Publication of WO2020116499A1 publication Critical patent/WO2020116499A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a thin film transistor having an oxide semiconductor film and a method for manufacturing the thin film transistor.
  • TFT thin film transistor
  • IGZO In—Ga—Zn—O-based oxide semiconductor film
  • Patent Document 1 After forming an oxide semiconductor film on a gate insulating layer by sputtering or the like, a metal film is formed on the oxide semiconductor film. And forming a source electrode and a drain electrode by etching the metal film.
  • an insulating film such as SiO 2 that functions as an etching stopper is formed using an oxide so as to protect the oxide semiconductor film from an etching solution or the like. It needs to be separately formed on the semiconductor film. Since the oxide semiconductor film functioning as a channel layer and the insulating film functioning as an etching stopper have different compositions, it is necessary to change a sputtering target or change a film formation chamber, which results in an increase in the number of steps and a thin film transistor. Cannot be manufactured with high productivity.
  • the present invention has been made in view of such problems, and a main object thereof is to manufacture a thin film transistor having an oxide semiconductor film with high productivity.
  • etching resistance resistance to etching due to their high crystallinity (that is, crystallinity).
  • crystallinity that is, crystallinity
  • sex crystallinity
  • the thin film transistor according to the present invention is a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and the oxide semiconductor layer is , A first semiconductor layer and a second semiconductor layer made of oxide semiconductor films containing the same constituent elements are provided in order from the substrate side, and the crystallinity of the oxide semiconductor film forming the second semiconductor layer is The crystallinity is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer.
  • the crystallinity of the oxide semiconductor film forming the second semiconductor layer functioning as a channel layer is higher than that of the oxide semiconductor film forming the first semiconductor layer.
  • the second semiconductor layer can function as an etching stopper to protect the first semiconductor layer. Therefore, it is not necessary to form a film by CVD or sputtering in order to separately provide an insulating film made of, for example, SiO 2 as an etching stopper.
  • the first semiconductor layer and the second semiconductor layer are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target is used to change the sputtering conditions. Since the film formation can be continuously performed, it is not necessary to change the target or change the film formation chamber, and the thin film transistor can be manufactured with high productivity.
  • the first semiconductor layer is made of the amorphous oxide semiconductor film
  • the second semiconductor layer is made of the crystalline oxide semiconductor film.
  • both the first semiconductor layer and the second semiconductor layer are made of an oxide semiconductor film containing In, and a Cu-K ⁇ ray for the second semiconductor layer is used.
  • the full width at half maximum of can be mentioned.
  • the diffraction angle 2 ⁇ 31 in the X-ray diffraction measurement by the ⁇ -2 ⁇ method using Cu-K ⁇ ray on the second semiconductor layer.
  • the full width at half maximum of the peak confirmed in the vicinity of ° is preferably 4.5° or less, more preferably 3.0° or less, and further preferably 2.5° or less.
  • the etching resistance of the oxide semiconductor film forming the second semiconductor layer is preferably higher than the etching resistance of the material forming the source electrode and the drain electrode. With such a structure, the function of the second semiconductor layer as an etching stopper can be made more prominent.
  • a method for manufacturing a thin film transistor of the invention is a method for manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and a plasma And a semiconductor layer forming step of forming a first semiconductor layer and a second semiconductor layer made of oxide semiconductor films having different crystallinities from each other on the gate insulating layer in order from the substrate side by sputtering a target using And a step of forming the source/drain electrodes by performing etching using the second semiconductor layer as an etching stopper to form the source electrode and the drain electrode on the oxide semiconductor layer.
  • a thin film transistor having an oxide semiconductor layer can be manufactured with high productivity.
  • FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment.
  • FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment. It is a figure which shows typically the structure of the sputtering device used in the semiconductor layer formation process of the thin-film transistor of the same embodiment.
  • 3 is a graph showing the relationship between the crystallinity of the oxide semiconductor layer and the etching resistance of the thin film transistor of the same embodiment.
  • a thin film transistor according to an embodiment of the present invention and a method for manufacturing the thin film transistor will be described below.
  • the thin film transistor 1 of this embodiment is a so-called bottom gate type. Specifically, as shown in FIG. 1, the substrate 2, the gate electrode 3, the gate insulating layer 4, the oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 are provided, and the substrate 2 side Are arranged (formed) in this order.
  • the thin film transistor 1 of the present embodiment is a so-called etching stopper type, and a part of the oxide semiconductor layer 5 that functions as a channel layer functions as an etching stopper in the manufacturing process as described later. Hereinafter, each part will be described in detail.
  • the substrate 2 is made of a material capable of transmitting light, and includes, for example, plastics (synthetic resin) such as polyethylene terephthalate (PET), polyethylene terephthalate (PEN), polyether sulfone (PES), acrylic, and polyimide. It may be made of glass or the like.
  • plastics synthetic resin
  • PET polyethylene terephthalate
  • PEN polyethylene terephthalate
  • PES polyether sulfone
  • acrylic acrylic
  • polyimide polyimide
  • the gate electrode 3 is provided on the surface of the substrate 2.
  • the gate electrode 3 is made of a material having high conductivity, and may be made of, for example, one or more kinds of metal selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. Further, the conductivity of metal oxides such as Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In—Ga—Zn—O (IGZO). It may be composed of a membrane.
  • the gate electrode 3 may have a single layer structure of these conductive films or a laminated structure of two or more layers.
  • a gate insulating layer 4 is arranged on the gate electrode 3.
  • the gate insulating layer 4 is made of a material having a high insulating property, and is selected from, for example, SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , and Hf 2. It may be an insulating film containing one or more oxides.
  • the gate insulating layer 4 may have such a conductive film as a single layer structure or a laminated structure of two or more layers.
  • the oxide semiconductor layer 5 is arranged on the gate insulating layer 4.
  • the oxide semiconductor layer 5 has a two-layer structure in which the first semiconductor layer 5a and the second semiconductor layer 5b are sequentially arranged from the substrate 2 side.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films containing the same constituent elements, and are composed of oxide semiconductor films composed of the same constituent elements and unavoidable impurities. Is preferred.
  • each of the first semiconductor layer 5a and the second semiconductor layer 5b is made of an oxide semiconductor film containing an oxide containing In as a main component, and the oxide containing In is, for example, In—Ga—Zn—O. , In-Al-Mg-O, In-Al-Zn-O, In-Hf-Zn-O, and the like.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films having different crystallinity levels (degrees).
  • the degree of crystallinity (degree) of this oxide semiconductor layer is determined by the full width at half maximum (FWHM) of the peak that can be confirmed in XRD (X-ray diffraction) measurement by the ⁇ -2 ⁇ method using a Cu light source (Cu-K ⁇ ray). You can check.
  • IGZO In—Ga—Zn—O
  • the first semiconductor layer 5a is a layer made of an amorphous oxide semiconductor film
  • the second semiconductor layer 5b is a layer made of a crystalline oxide semiconductor film. That is, the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a.
  • the second semiconductor layer 5b functions as an etching stopper that protects the first semiconductor layer 5a.
  • a source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5.
  • the source electrode 6 and the drain electrode 7 are each made of a material having high conductivity so as to function as an electrode.
  • the source electrode 6 and the drain electrode 7 may have a single-layer structure of metal or conductive oxide, or may have a laminated structure of two or more layers.
  • the source electrode 6 and the drain electrode 7 of the present embodiment are made of a material having a lower etching resistance than the second semiconductor layer 5b (that is, a faster etching rate).
  • the source electrode 6 and the drain electrode 7 include zinc indium oxide (IZO), gallium indium oxide (IGO), and amorphous IGZO. It is composed of a metal oxide such as a film or a conductive film of a metal such as Mo.
  • a protective film may be disposed on the oxide semiconductor 5, the source electrode 6, and the drain electrode 7 to protect them.
  • the protective film may be made of, for example, a silicon oxide film (SiO 2 ), a fluorinated silicon nitride film (SiN:F) containing fluorine in the silicon nitride film, or the like.
  • the method of manufacturing the thin film transistor 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, and a source/drain electrode forming step. Hereinafter, each step will be described.
  • a substrate 2 made of, for example, quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2.
  • the method of forming the gate electrode 3 is not particularly limited, and may be formed by a known method such as a vacuum vapor deposition method or a DC sputtering method.
  • the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3.
  • the method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.
  • the semiconductor layer forming step includes a first film forming step of forming the first semiconductor layer 5a and a second film forming step of forming the second semiconductor layer 5b.
  • an oxide semiconductor film is formed by sputtering a target with plasma.
  • a sputtering apparatus 100 for forming a film by sputtering a target T using inductively coupled plasma P is used.
  • the sputtering apparatus 100 includes a vacuum container 20, a substrate holding unit 30 that holds the substrate 2 in the vacuum container 20, a target holding unit 40 that faces the substrate 2 and holds the target T in the vacuum container 20, and a substrate holding unit.
  • a plurality of antennas 50 arranged along the surface of the substrate 2 held by the unit 30 and generating the plasma P are provided.
  • the high frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, the bias voltage can be set to a low voltage such that the ions in the plasma are attracted to the target and sputtered independently of the generation of the plasma P, and the negative bias voltage applied to the target T during sputtering is -1 kV. It is possible to set the negative voltage above (that is, the absolute value is 1 kV or less).
  • the target T is arranged in the target holding part 40 and the substrate 2 is arranged in the substrate holding part 30.
  • a conductive oxide sintered body such as InGaZnO that is a raw material of the oxide semiconductor 5 is used.
  • the first semiconductor layer 5a is formed on the gate insulating layer 4. Specifically, after the vacuum container 20 of the sputtering apparatus 100 is evacuated to 3 ⁇ 10 ⁇ 6 Torr or less, the pressure in the vacuum container 20 is 0.5 Pa or more 3 while introducing the sputtering gas at 50 sccm or more and 200 sccm or less. It is adjusted so that it becomes 1 Pa or less. Then, high frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate/maintain inductively coupled plasma. A DC voltage pulse is applied to the target to sputter the target.
  • the voltage applied to the target T is set to a negative voltage of ⁇ 1 kV or more from the viewpoint of suppressing generation of sputtered particles from which oxygen is desorbed and forming the oxide semiconductor film 5a with few oxygen defects in the film.
  • the first semiconductor layer 5 a is formed on the gate insulating layer 4.
  • the pressure inside the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna may be changed as appropriate.
  • the second semiconductor layer 5b is formed on the first semiconductor layer 5a.
  • the second semiconductor layer 5b is formed by sputtering the target T using the sputtering apparatus 100, as in the first film forming step.
  • the voltage applied to the target T in the second film forming step be a negative voltage of ⁇ 1 kV or more.
  • Conditions such as the pressure in the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna in the second film forming step may be the same as those in the first film forming step, and may be appropriately changed.
  • the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step is the oxygen gas contained in the sputtering gas supplied in the first film forming step. Make it higher than the concentration.
  • the second film forming step as compared with the first film forming step, it is possible to further suppress the generation of sputtered particles from which oxygen is desorbed and to form a film while maintaining the oxidation state of the target more.
  • the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b can be made higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a.
  • the oxygen gas concentration contained in the sputtering gas supplied in the second film formation step is 20 vol% or more in terms of volume fraction. Is preferable, and more preferably 50 vol% or more. Most preferably, only oxygen gas (that is, the volume fraction is 99.999 vol% or more) is supplied as the sputtering gas.
  • the oxygen gas concentration contained in the sputtering gas supplied in the first film forming step may be lower than the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step.
  • the oxygen gas concentration contained in the sputtering gas is preferably 2 vol% or less in volume fraction, and only argon gas is supplied as the sputtering gas. Is preferred.
  • the source electrode 6 and the drain electrode 7 are formed on the oxide semiconductor layer 5.
  • the source electrode 6 and the drain electrode 7 are formed by forming the conductive film M on the second semiconductor layer 5b and then performing patterning by photolithography.
  • a conductive film M made of a metal or a conductive oxide is formed so as to cover the gate insulating layer 4 and the second semiconductor layer 5b.
  • the conductive film M may be formed by a known method such as DC sputtering or RF sputtering.
  • a resist R is applied on the conductive film M, and then exposure and development are performed to form the source electrode 6 and the drain electrode 7 on the conductive film M later, as shown in FIG.
  • the resist R is left only on the part.
  • the portions of the conductive film M to which the resist R is not applied are removed by etching to form the source electrode 6 and the drain electrode 7.
  • etching method dry etching using CF 4 gas or the like may be performed, or wet etching using acid such as HCl may be performed.
  • the second conductive layer 5b has better etching resistance than the first conductive layer 5a and the conductive film M, and functions as an etching stopper to protect the first conductive layer 5a from an etchant. Is becoming
  • a protective film is formed so as to cover the upper surfaces of the formed oxide semiconductor layer 5, the source electrode 6, and the drain electrode 7 by using, for example, a plasma CVD method.
  • heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure.
  • the temperature in the furnace during the heat treatment is not particularly limited and is, for example, 150° C. or higher and 300° C. or lower.
  • the heat treatment time is not particularly limited and is, for example, 1 hour or more and 3 hours or less.
  • the thin film transistor 1 of this embodiment can be obtained.
  • the protective film forming step and the heat treatment step are not essential steps and may be omitted.
  • sample making Specifically, a plurality of silicon substrates are prepared, and an oxide semiconductor film made of In-Ga-Zn-O (IGZO1114) is formed on the substrate by sputtering based on the "semiconductor manufacturing process" of the manufacturing method described above. Multiple samples were prepared.
  • IGZO1114 oxide semiconductor film made of In-Ga-Zn-O
  • the pressure inside the vacuum container is reduced to 0.9 Pa or less, high-frequency power of 7 kW is supplied to the plurality of antennas, and a DC pulse voltage of ⁇ 400 V is applied to the target.
  • the voltage was applied and sputtering of the target was performed to form an oxide semiconductor film.
  • one or two samples (total of 5 vol%, 5 vol%, 20 vol%, 50 vol%, and 100 vol%, respectively) of 5 kinds of samples with different oxygen gas concentrations in the supplied sputtering gas (total volume fraction, respectively) (total: 9) were created.
  • the manufacturing conditions not particularly described are the same as those described in the above-described manufacturing method.
  • the oxide semiconductor film forming the second semiconductor layer 5b functioning as a channel layer has a crystallinity forming the first semiconductor layer 5a. Since the crystallinity of the film is higher than that of the film, when the electrode source electrode 6 and the drain electrode 7 are formed by etching in the source/drain electrode forming step, the second semiconductor layer 5b functions as an etching stopper to form the first semiconductor layer 5a. It can be protected from the etching solution. Therefore, it is not necessary to perform sputtering to separately provide an insulating film made of, for example, SiO 2 as an etching stopper.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target T is used in the sputtering gas. Since it is possible to continue film formation simply by changing the sputtering conditions such as the oxygen gas concentration, it is possible to manufacture the thin film transistor 1 with high productivity without changing the target T or changing the film forming chamber. ..
  • the configuration has the plurality of target holding units 40, but the configuration may have one target holding unit 40. Even in this case, the configuration having the plurality of antennas 50 is desirable, but the configuration having one antenna 50 may be used.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un transistor à couches minces comportant, disposées dans l'ordre sur un substrat : une électrode grille ; une couche d'isolation de grille ; une couche semi-conductrice à oxyde ; et une électrode source et une électrode drain. Le transistor à couches minces est caractérisé en ce que : la couche semi-conductrice à oxyde comprend, dans l'ordre depuis le côté substrat, une première couche semi-conductrice et une seconde couche semi-conductrice qui comprennent un film semi-conducteur à oxyde ayant le même élément constitutif dans les deux couches ; et la cristallinité du film semi-conducteur à oxyde constituant la seconde couche semi-conductrice est supérieure à la cristallinité du film semi-conducteur à oxyde constituant la première couche semi-conductrice.
PCT/JP2019/047389 2018-12-07 2019-12-04 Transistor à couches minces et son procédé de production WO2020116499A1 (fr)

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KR1020217016500A KR20210080549A (ko) 2018-12-07 2019-12-04 박막 트랜지스터 및 그 제조 방법
CN201980080222.XA CN113169232A (zh) 2018-12-07 2019-12-04 薄膜晶体管及其制造方法

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JP2018-229754 2018-12-07
JP2018229754A JP2020092222A (ja) 2018-12-07 2018-12-07 薄膜トランジスタ及びその製造方法

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JP2022097013A (ja) * 2020-12-18 2022-06-30 日新電機株式会社 酸化物半導体の成膜方法及び薄膜トランジスタの製造方法

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WO2009157535A1 (fr) * 2008-06-27 2009-12-30 出光興産株式会社 Cible de pulvérisation pour semi-conducteur aux oxydes, comprenant une phase cristalline d’ingao<sb>3</sb> (zno) et procédé de production de la cible de pulvérisation
JP2016074580A (ja) * 2014-02-21 2016-05-12 株式会社半導体エネルギー研究所 半導体膜、トランジスタ及び半導体装置、並びに表示装置、電子機器
JP2018190949A (ja) * 2016-09-12 2018-11-29 株式会社半導体エネルギー研究所 表示装置及び電子機器
WO2018061969A1 (fr) * 2016-09-27 2018-04-05 シャープ株式会社 Dispositif semi-conducteur et son procédé de fabrication

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