WO2020114409A1 - 半导体器件制备方法 - Google Patents

半导体器件制备方法 Download PDF

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WO2020114409A1
WO2020114409A1 PCT/CN2019/122847 CN2019122847W WO2020114409A1 WO 2020114409 A1 WO2020114409 A1 WO 2020114409A1 CN 2019122847 W CN2019122847 W CN 2019122847W WO 2020114409 A1 WO2020114409 A1 WO 2020114409A1
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layer
conductivity type
semiconductor
dielectric layer
region
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French (fr)
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廖远宝
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements

Definitions

  • the invention relates to the field of semiconductors, in particular to a method for manufacturing semiconductor devices.
  • MOS tube Metal-Oxide-Semiconductor Field-Effect Transistor
  • field oxygen is usually formed in the non-cell region of the semiconductor substrate, and the semiconductor substrate is subjected to self-aligned well implantation using the field oxygen as a mask to form a well region in the cell region, and A semiconductor layer is deposited on the field oxygen, the semiconductor layer is doped to form a protective structure on the non-primary cell region, and the well region is doped to form a working structure in the primary cell region, and then an interlayer dielectric layer is deposited And a contact hole is formed in the interlayer dielectric layer to lead out the electrode.
  • the field oxygen needs to reach a certain thickness, set to h1, and the semiconductor layer deposited on the field oxygen also has a certain thickness, set to h2, that is, on the semiconductor substrate, the original
  • the surface of the protection structure on the cell area is h1+h2 higher than the surface of the working structure in the original cell area, and the upper surface of the interlayer dielectric layer is flat, which makes the interlayer above the protection structure on the non-cell area
  • the thickness of the dielectric layer is smaller than the thickness of the interlayer dielectric layer above the primary cell region by h1+h2, resulting in a thinner interlayer dielectric layer above the protective structure.
  • subsequent processes such as forming a metal layer and etching the metal layer In the process, the interlayer dielectric layer above the protective structure is easily worn away, which exposes the protective structure to damage the protective structure.
  • a method for manufacturing a semiconductor device is provided.
  • a preparation method of a semiconductor device includes a working structure and a protection structure that protects the working structure, the preparation method includes:
  • a semiconductor substrate is provided, the semiconductor substrate includes a cell region and a non-cell region, an isolation dielectric layer is formed on the semiconductor substrate of the non-cell region, and a first conductivity type is formed on the isolation dielectric layer Doped semiconductor layer;
  • the working structure and the protection structure are connected by the metal interconnection layer and the contact hole.
  • FIGS. 1a to 1c are device state diagrams corresponding to the relevant steps of the conventional technology semiconductor device manufacturing method
  • FIG. 2 is a flowchart of steps in a method for manufacturing a semiconductor device in an embodiment of the present application
  • 3a to 3d are device state diagrams corresponding to each step of the semiconductor device manufacturing method in this application.
  • VDMOS tube Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, hereinafter referred to as VDMOS tube
  • VDMOS tube Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor
  • Step S110 A semiconductor substrate is provided.
  • the semiconductor substrate includes a primary cell region and a non-primary cell region, and field oxygen is formed on the non-primary cell region.
  • the semiconductor substrate 110 includes a cell region B and a non-cell region A. After a layer of field oxygen is formed on the semiconductor substrate 110, the field oxygen in the cell region is removed by photolithography and etching processes. The field oxygen 120 in the non-cell area A is retained.
  • Step S120 forming a trench in the semiconductor substrate of the cell region and forming a gate oxide layer on the inner wall of the trench, filling the gate with polysilicon in the trench, and using field oxygen as a mask for the cell region
  • the semiconductor substrate performs well implantation of the first conductivity type to form a well region.
  • a trench is formed in the semiconductor substrate 110 of the cell region by a photolithography and etching process, a gate oxide layer 111 is formed on the inner wall of the trench, a gate polysilicon 112 is filled in the trench, and field oxygen 120 is used as The mask performs self-aligned well implantation on the semiconductor substrate in the cell region to form a well region 113.
  • the field oxygen 120 needs to reach a certain thickness h1 to be used as a self-aligned mask for well implantation, that is, the thickness of the field oxygen 120 is h1.
  • Step S130 forming a semiconductor layer on the field oxygen, doping the semiconductor layer with a first conductivity type to form a first conductivity type semiconductor structure, and doping the semiconductor layer with a second conductivity type to form a second conductivity type semiconductor structure, the first conductivity
  • the type semiconductor structure and the second conductivity type semiconductor structure form a P junction, doping the well region with the second conductivity type to form a source region, forming an interlayer dielectric layer on the semiconductor layer, trench and source region, and forming an interlayer dielectric
  • a contact hole is formed in the layer, the first electrode of the diode is drawn from the first conductivity type semiconductor structure through the contact hole, the second electrode of the diode is drawn from the second conductivity type semiconductor structure, the source electrode is drawn from the source region, and the gate polysilicon
  • the gate is drawn out to form a metal interconnection layer on the interlayer dielectric layer, and the first electrode and the gate are connected through the metal interconnection layer, and the second electrode and the source are connected.
  • a semiconductor layer is deposited on the field oxygen 120, the thickness of the semiconductor layer is h2, and the semiconductor layer is doped with the first conductivity type and the second conductivity type to make part of the semiconductor layer semiconductor
  • Has a first conductivity type, part of the semiconductor has a second conductivity type, that is, the semiconductor layer is formed with a first conductivity type semiconductor structure 131 and a second conductivity type semiconductor structure 132, a first conductivity type semiconductor structure 131 and a second conductivity type semiconductor structure 132
  • a PN junction is formed, which is structured as a diode.
  • the well region is doped with the second conductivity type to form the source region 114.
  • An interlayer dielectric layer 140 is covered over the source region 114, the trench and the semiconductor layer, and a contact hole 150 is formed in the interlayer dielectric layer 140, specifically, the interlayer dielectric layer 140 above the first conductivity type semiconductor 131 forms a contact
  • the hole leads to the first electrode of the diode
  • the interlayer dielectric layer 140 above the second conductivity type semiconductor 132 forms a contact hole to lead out the second electrode of the diode
  • the interlayer dielectric layer 140 above the source region 114 forms a contact hole to lead out the source
  • a contact hole is formed to lead out the gate (not shown in the figure).
  • VDMOS devices with diode electrostatic protection are formed.
  • the thickness of the field oxygen 120 is h1
  • the thickness of the semiconductor layer is h2
  • the thickness of the interlayer dielectric layer 140 above the semiconductor layer is d1
  • the size of the contact hole is limited by the process line width, so that the thickness of the interlayer dielectric layer above the primary cell region cannot exceed a certain value, so that the layer above the non-primary cell region The dielectric layer is thinner. In subsequent processes, such as metal etching, the interlayer dielectric layer will be lost. When the interlayer dielectric layer above the non-primary cell region is thin, the interlayer dielectric layer above the non-primary cell region is likely to be in the metal It is removed during the etching process and damages the protective structure under the interlayer dielectric layer.
  • this solution proposes a new semiconductor preparation method, which can increase the thickness of the interlayer dielectric layer on the protection structure as shown in FIG. 2, the preparation method includes:
  • Step S210 providing a semiconductor substrate, the semiconductor substrate includes a primary cell region and a non-primary cell region, an isolation dielectric layer is formed on the semiconductor substrate of the non-primary cell region, and a first conductivity type doped is formed on the isolation dielectric layer Semiconductor layer.
  • a semiconductor substrate 210 is provided.
  • the semiconductor substrate 210 includes a cell region N and a non-cell region M.
  • the cell region N is located in the middle of the semiconductor substrate 210.
  • the region M is located on the periphery of the semiconductor substrate 210 and surrounds the primary cell region N, thereby isolating the structure within the primary cell region.
  • An isolation dielectric layer 220 is formed on the semiconductor substrate of the non-cell region M, and a semiconductor layer 230 having a doping of the first conductivity type is formed on the isolation dielectric layer 220.
  • the semiconductor layer 230 is a first conductive type polysilicon layer, and the semiconductor layer 230 may also be other polycrystalline semiconductor materials.
  • the thickness of the semiconductor layer 230 In an embodiment, the thickness H3 of the isolation dielectric layer 220 ranges from to Optional In one embodiment, the isolation dielectric layer 220 is a silicon oxide layer. In a specific embodiment, when the isolation dielectric layer 220 is a silicon oxide layer and the semiconductor layer 230 is a polysilicon layer, a silicon oxide layer is formed on the semiconductor substrate 210 in the non-cell region and a first layer is formed on the silicon oxide layer
  • the specific method of the conductive type polysilicon layer may be: forming a thermal oxidation layer on the semiconductor substrate 210 through a thermal oxidation process, depositing a polysilicon layer on the thermal oxidation layer through a deposition process, and applying a doping process to the polysilicon layer Doping the first conductivity type to form a polysilicon layer of the first conductivity type, etching away the polycrystalline silicon in the primary cell region and retaining the polycrystalline silicon in the non-primary cell region through the first photolithography and etching process, and through the
  • the thermal oxide layer can be etched a second time using the polysilicon layer as a mask, thereby The photolithography process can be omitted once.
  • the process steps of forming an isolation dielectric layer on the semiconductor substrate in the non-cell region and forming a semiconductor layer doped with the first conductivity type on the isolation dielectric layer are not limited thereto, and in other embodiments, it may be performed first Photolithography and etching process, and then doping process.
  • Step S220 perform a first conductivity type well implantation on the semiconductor substrate using the semiconductor layer and the isolation dielectric layer as a mask, and form a well region in the semiconductor substrate of the cell region.
  • the first conductivity type well implantation is performed on the semiconductor substrate 210, and a well region 213 is formed in the semiconductor substrate of the primary cell region.
  • the total thickness H2+H3 of the isolation dielectric layer 220 and the semiconductor layer 230 ranges from to This thickness can prevent the well implanted particles from entering the semiconductor substrate in the non-primary cell region during well implantation.
  • the dose of the first conductivity type doping of the semiconductor layer is at least an order of magnitude greater than the dose of the first conductivity type well implant of the semiconductor substrate, wherein the dose of the first conductivity type well implant does not exceed 2E13/cm 2 , which can be 5E12/cm 2 to 2E13/cm 2 , and the dosage of the first conductive type doping of the semiconductor layer 230 is not less than 4E14/cm 2 , which can be 4E14/cm 2 to 8E14/cm 2 , that is, the semiconductor layer 230
  • the dose of the first conductivity type doping is at least ten times the dose of the first conductivity type well implant.
  • the first conductivity type well implanted particles have less effect on the semiconductor layer.
  • the protection structure requires high accuracy of the doping concentration of the first conductivity type in the semiconductor layer, when doping the first conductivity type of the semiconductor layer, the influence of the subsequent well implantation process may be considered to appropriately reduce the doping dose.
  • the method when the working structure is a VDMOS tube, before the well implantation process, the method further includes the steps of forming a trench in the primary cell region, forming a gate oxide layer on the inner wall of the trench and filling the gate polysilicon in the trench. As shown in FIG.
  • a plurality of trenches are formed on the semiconductor substrate 210 in the primary cell region by photolithography and etching processes, a gate oxide layer 212 is formed on the inner wall of the trenches by a thermal oxidation process, and deposited by a deposition process A layer of polysilicon, the polysilicon is filled in the trench, the polysilicon outside the trench is removed by an etch-back process and the polysilicon in the trench is retained to form the gate polysilicon 212.
  • Step S230 doping the well region to form a working structure in the primary cell region, and doping the semiconductor layer to form a protective structure on the non-primary cell region.
  • the working structure is formed on the semiconductor substrate 210 based on the semiconductor substrate in the cell region, and the protective structure is formed on the semiconductor substrate 210 based on the semiconductor layer on the semiconductor substrate in the non-cell region.
  • the semiconductor layer 230 and the well region 213 are formed in step S220, a working structure is formed in the primary cell region through doping and other processes, and a protective structure is formed on the non-primary cell region.
  • Step S240 forming an interlayer dielectric layer on the working structure and the protection structure, and forming a contact hole in the interlayer dielectric layer, forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, through the metal interconnection layer and The contact hole connects the working structure and the protection structure.
  • a working structure and a protective structure are formed, wherein the protective structure is formed in the semiconductor layer 230, and the working structure is formed in the semiconductor substrate 210 of the cell area.
  • an interlayer dielectric layer 240 needs to be deposited, and a contact hole is formed in the interlayer dielectric layer 240, and each electrode of the working structure and the protective structure is led out through the contact hole.
  • a metal interconnect layer is deposited on the interlayer dielectric layer, the metal interconnect layer is connected with the contact hole, and the working structure and the protection structure are connected through the metal interconnect layer and the contact hole.
  • steps S230 and S240 will be described, in which the semiconductor substrate has the second conductivity type.
  • step S230 the step of doping the well region to form a working structure in the primary cell region and doping the semiconductor layer to form a protective structure on the non-primary cell region specifically includes:
  • the well region is doped with a second conductivity type to form a source region, and a partial region of the semiconductor layer is doped with a second conductivity type to form a parallel first conductivity type semiconductor structure and a second conductivity type semiconductor structure.
  • the well region 213 is doped to form the source region 214, and a part of the semiconductor layer is doped with the second conductivity type to convert the part of the first conductivity type semiconductor to the second conductivity type semiconductor, thereby
  • the semiconductor layer is formed into a parallel first conductivity type semiconductor structure 231 and a second conductivity type semiconductor structure 232, wherein the first conductivity type semiconductor structure 231 is a region where the semiconductor layer is not doped with the second conductivity type, the second conductivity type semiconductor
  • the structure 232 is a region in the semiconductor layer where the second conductivity type is doped, and the parallel first conductivity type semiconductor structure 231 and the second conductivity type semiconductor structure 232 form a PN junction.
  • the semiconductor layer is formed with a plurality of first conductivity type semiconductor structures 231 and a plurality of second conductivity type semiconductor structures 232, and the first conductivity type semiconductor structures 231 and the second conductivity type semiconductor structures
  • the number of 232 is equal, the first conductivity type semiconductor structure 231 and the second conductivity type semiconductor structure 232 are alternately arranged, and the first pole of the diode is led out from the first conductivity type semiconductor structure 231 and the second conductivity type semiconductor structure 232 located at the outermost end, respectively And the second pole, thereby forming a plurality of PN junctions connected in series.
  • the step of doping the well region with the second conductivity type to form the source region, and the step of doping the second conductivity type with a partial region of the semiconductor layer specifically includes: sharing a mask plate on the well region and the semiconductor layer A doping window is formed, and the well region and the semiconductor layer are simultaneously doped with the second conductivity type.
  • a mask plate is shared to form a doping window above the cell area and part of the semiconductor layer, and at the same time doping the well region and part of the semiconductor layer with the second conductivity type can save process steps.
  • step S240 an interlayer dielectric layer is formed on the working structure and the protection structure, and a contact hole is formed in the interlayer dielectric layer, and a metal interconnection layer connected to the contact hole is formed on the interlayer dielectric layer.
  • the steps of connecting the working structure and the protection structure by the layer and the contact hole specifically include:
  • an interlayer dielectric layer on the source region, the trench, the first conductivity type semiconductor structure and the second conductivity type semiconductor structure Forming an interlayer dielectric layer on the source region, the trench, the first conductivity type semiconductor structure and the second conductivity type semiconductor structure, forming a first contact hole on the interlayer dielectric layer above the source region and leading out the source connected to the source region Electrode, forming a second contact hole in the interlayer dielectric layer above the trench and leading out the gate connected to the gate polysilicon, forming a third contact hole in the interlayer dielectric layer above the first conductivity type semiconductor structure and leading out the diode
  • the first pole forming a fourth contact hole on the interlayer dielectric layer above the second conductivity type semiconductor structure and leading out the second pole of the diode, forming a metal interconnection layer on the interlayer dielectric layer to make the first pole and the gate Connected, the second pole is connected to the source.
  • an interlayer dielectric layer 240 is deposited on the source region, the trench, the first conductivity type semiconductor structure and the second conductivity type semiconductor structure, and is formed in the interlayer dielectric layer 240 above the source region 214
  • the first contact hole 251 leads to the source electrode connected to the source region 214, forms a second contact hole in the interlayer dielectric layer 240 above the trench and leads to the gate electrode connected to the gate polysilicon 212, in the first conductivity type semiconductor structure
  • a third contact hole 253 is formed in the interlayer dielectric layer above 231 and leads out of the first pole of the diode
  • a fourth contact hole 254 is formed on the interlayer dielectric layer 240 above the second conductivity type semiconductor structure 232 and leads out of the second diode pole.
  • a metal interconnect layer is formed on the interlayer dielectric layer 240.
  • the metal interconnect layer includes a first metal strip 261 connected to the first contact hole, a second metal strip connected to the second contact hole (not shown in the figure),
  • the third metal strip 263 connected to the third contact hole 253 and the fourth metal strip 264 connected to the fourth contact hole 254 connect the first electrode to the gate through the metal interconnection layer and the contact hole, and the second electrode to Source connection.
  • the first contact hole 251 leading to the source penetrates the source region 214 and extends to the well region 213, and the third contact hole 253 leading to the first electrode of the diode penetrates the first conductive type semiconductor structure 231 and stops at On the isolation dielectric layer 220, a fourth contact hole 254 leading to the second electrode of the diode penetrates the second conductive type semiconductor structure 232 and stops on the isolation dielectric layer 220.
  • a drain is formed on the side of the semiconductor substrate 210 facing away from the interlayer dielectric layer, thereby completing the parallel connection of the VDMOS tube and the diode, and using the diode to realize the electrostatic protection function of the VDMOS.
  • the semiconductor substrate includes an epitaxial layer grown from the semiconductor substrate.
  • the first conductivity type may be P-type
  • the second conductivity type may be N-type
  • the first conductivity type may be N-type
  • the second conductivity type may be P-type.
  • the VDMOS tube formed by the above method is an N-type VDMOS tube
  • the first electrode in the diode is formed as an anode and a second electrode as a cathode.
  • the first conductivity type is N-type
  • the The VDMOS tube formed by the method is a P-type VDMOS tube
  • the first pole of the formed diode is the cathode and the second pole is the anode.
  • VDMOS tube As a working structure.
  • VDMOS tube may also be a lateral double-diffused metal oxide semiconductor field effect tube (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor (LDMOS tube for short)) or
  • LDMOS tube for short
  • the isolation dielectric layer and the semiconductor layer in the protective structure are used as masks to replace the field oxygen during the well implantation to implement self-aligned well implantation, all falling within the protection scope of the present application.
  • the isolation dielectric layer 220 and the semiconductor layer 230 are formed in the non-cell region M, and the isolation dielectric layer 220 and the semiconductor layer 230 are used as
  • the self-aligned mask performs well implantation on the semiconductor substrate 210 to form a well region in the primary cell region N, while the non-primary cell region M is not affected by the well implant due to the shielding effect of the isolation dielectric layer 220 and the semiconductor layer 230 .
  • the protective structure on the non-primary cell area is formed on the field oxygen, and the field oxygen is used as a self-aligned mask, the thickness of the field oxygen h1 is thicker, and in this application, the The protection structure is formed on the isolation dielectric layer 220. Since the isolation dielectric layer 220 and the semiconductor layer 230 forming the protection structure are used as a self-alignment mask, as long as the isolation dielectric layer 220 and the semiconductor layer 230 as a whole reach a certain thickness, they can be used as self-alignment.
  • the height of the step formed by the protective structure of the protective structure and the working structure in the primary cell area is reduced.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请涉及一种半导体器件制备方法，包括：在半导体衬底的非原胞区(M)上依次形成隔离介质层(220)和具有第一导电类型掺杂的半导体层(230)；以半导体层(230)和隔离介质层(220)为掩膜进行第一导电类型阱注入，在原胞区(N)形成阱区(213)；在阱区(213)内形成工作结构，在半导体层(230)内形成保护结构；在工作结构和保护结构上形成层间介质层(240)，并在层间介质层(240)内形成接触孔，在层间介质层(240)上形成与接触孔连接的金属互连层，通过金属互连层和接触孔连接工作结构和保护结构。

Description

半导体器件制备方法
相关申请
本申请要求于2018年12月5日提交中国专利局的、申请号为201811478102.9、申请名称为“半导体器件制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种半导体器件制备方法。
背景技术
半导体器件通常包括工作结构和对工作结构进行保护的保护结构，如金属-氧化物-半导体场效应管(Metal-Oxide-Semiconductor Field-Effect Transistor，以下简称MOS管)在生产、组装、测试或搬运过程中都可能生成静电，当静电电压较高时，会损坏MOS管，因此通常增加二极管作为静电保护结构与MOS管并联以保护MOS管。在半导体器件的具体的制备工艺中，通常是在半导体衬底的非原胞区域形成场氧，以场氧为掩膜对半导体衬底进行自对准阱注入以在原胞区形成阱区，并在场氧上淀积半导体层，对半导体层进行掺杂而在非原胞区上形成保护结构，以及在阱区进行掺杂而在原胞区内形成工作结构，接着淀积一层层间介质层并在层间介质层中形成接触孔以引出电极。为实现自对准掩膜阱注入，场氧需达到一定的厚度，设为h1，而淀积在场氧上的半导体层也具有一定的厚度，设为h2，即在半导体衬底上，非原胞区上的保护结构的表面比原胞区内的工作结构的表面高h1+h2，而层间介质层的上表面是平整的，这就使得非原胞区上的保护结构上方的层间介质层的厚度 比原胞区上方的层间介质层厚度小h1+h2，导致保护结构上方的层间介质层较薄，在后续工艺中，如在形成金属层并对金属层进行刻蚀的过程中，保护结构上方的层间介质层容易被损耗，使保护结构暴露在外而损伤保护结构。
发明内容
根据本申请的各种实施例提供一种半导体器件制备方法。
一种半导体器件制备方法，所述半导体器件包括工作结构和对所述工作结构进行保护的保护结构，所述制备方法包括：
提供半导体衬底，所述半导体衬底包括原胞区和非原胞区，在所述非原胞区的半导体衬底上形成隔离介质层，在所述隔离介质层上形成具有第一导电类型掺杂的半导体层；
以所述半导体层和所述隔离介质层为掩膜对所述半导体衬底进行第一导电类型阱注入，在所述原胞区的半导体衬底内形成阱区；
对所述阱区进行掺杂以在所述原胞区内形成工作结构，对所述半导体层进行掺杂以在所述非原胞区上形成所述保护结构；
在所述工作结构和所述保护结构上形成层间介质层，并在所述层间介质层内形成接触孔，在所述层间介质层上形成与所述接触孔连接的金属互连层，通过所述金属互连层和所述接触孔连接所述工作结构和所述保护结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1a至图1c为传统技术半导体器件制备方法的相关步骤对应的器件状态图；
图2为本申请一实施例中半导体器件制备方法的步骤流程图；
图3a至图3d为本申请中半导体器件制备方法各步骤对应的器件状态图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本申请，将在下列的描述中提出详细步骤以及结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
以垂直双扩散金属氧化物半导体场效应管(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor，以下简称VDMOS管)连接二极管为例说明目前制备半导体器件的工艺步骤，其中，VDMOS管为工作结构，二极管为静电保护结构，该制备步骤包括：
步骤S110：提供半导体衬底，半导体衬底包括原胞区和非原胞区，在非原胞区上形成场氧。
如图1a所示，半导体衬底110包括原胞区B和非原胞区A，在半导体衬底110上形成一层场氧后，通过光刻、刻蚀工艺去除原胞区域的场氧，保留非原胞区域A的场氧120。
步骤S120：在所述原胞区的半导体衬底内形成沟槽并在所述沟槽内壁形 成栅氧化层，在所述沟槽内填充栅多晶硅，以场氧为掩膜对原胞区域的半导体衬底进行第一导电类型阱注入，形成阱区。
如图1b所示，通过光刻与刻蚀工艺在原胞区的半导体衬底110内形成沟槽，在沟槽内壁形成栅氧化层111，在沟槽内填充栅多晶硅112，以场氧120为掩膜对原胞区域的半导体衬底进行自对准阱注入，形成阱区113。其中，场氧120需达到一定厚度h1才能作为阱注入的自对准掩膜，即场氧120的厚度为h1。
步骤S130：在场氧上形成半导体层，并对半导体层进行第一导电类型掺杂形成第一导电类型半导体结构，对半导体层进行第二导电类型掺杂形成第二导电类型半导体结构，第一导电类型半导体结构和第二导电类型半导体结构形成P N结，对阱区进行第二导电类型掺杂形成源区，在半导体层、沟槽和源区上形成层间介质层，并在层间介质层内形成接触孔，通过接触孔从第一导电类型半导体结构处引出二极管的第一极，从第二导电类型半导体结构处引出二极管的第二极，从源区引出源极，从栅多晶硅处引出栅极，在所述层间介质层上形成金属互连层，通过所述金属互连层连接第一极和栅极，连接第二极和源极。
如图1c所示，在场氧120上淀积一层半导体层，半导体层的厚度为h2，,并对半导体层进行第一导电类型掺杂和第二导电类型掺杂，使半导体层的部分半导体具有第一导电类型，部分半导体具有第二导电类型，即半导体层形成有第一导电类型半导体结构131和第二导电类型半导体结构132，第一导电类型半导体结构131和第二导电类型半导体结构132形成PN结，该PN结构成二极管。同时，对阱区进行第二导电类型掺杂形成源区114。在源区114、沟槽及半导体层上方覆盖一层层间介质层140，在层间介质层140内形成接触孔150，具体为在第一导电类型半导体131上方的层间介质层140形成接触孔以引出二极管的第一极，在第二导电类型半导体132上方的层间介质层140形成接触孔引出二极管的第二极，在源区114上方的层间介质层140形成接触孔引出源极，在栅多晶硅112上方的层间介质层140形成接触孔引出 栅极(图中未示出)。在层间介质层140上形成金属互连层160，通过金属互连层160连接第一极和栅极，并连接第二极和源极，并在半导体衬底的背面形成漏极，由此形成具有二极管静电保护的VDMOS器件。
上述半导体制备方法形成的半导体器件，场氧120的厚度为h1，半导体层的厚度为h2，半导体层上方的层间介质层140的厚度为d1，源区114上方的层间介质层140的厚度为d2，则d2-d1＝h1+h2，即非原胞区A上方的层间介质层的厚度比原胞区上方的层间介质层的厚度薄h1+h2。而由于在层间介质层中需形成接触孔，接触孔的尺寸受工艺线宽的限制，使得原胞区上方的层间介质层的厚度不能超过一定值，从而使得非原胞区上方的层间介质层较薄。在后续的工艺中如金属刻蚀工艺中，层间介质层会有所损失，当非原胞区上方的层间介质层较薄时，非原胞区上方的层间介质层很可能在金属刻蚀工艺中被去除而损伤层间介质层下方的保护结构。
基于此，本方案提出了一种新的半导体制备方法，可以增大保护结构上的层间介质层的厚度如图2所示，该制备方法包括：
步骤S210：提供半导体衬底，半导体衬底包括原胞区和非原胞区，在非原胞区的半导体衬底上形成隔离介质层，在隔离介质层上形成具有第一导电类型掺杂的半导体层。
如图3a所示，提供半导体衬底210，半导体衬底210包括原胞区N和非原胞区M，在一实施例中，原胞区N位于半导体衬底210的中间位置，非原胞区M位于半导体衬底210的外围且包围原胞区N，由此对原胞区内的结构进行隔离。在非原胞区M的半导体衬底上形成隔离介质层220，在隔离介质层220上形成具有第一导电类型掺杂的半导体层230。在一实施例中，半导体层230为第一导电类型多晶硅层，半导体层230也可为其他多晶半导体材料。半导体层230的厚度
Figure PCTCN2019122847-appb-000001
在一实施例中，隔离介质层220的厚度H3的范围为
Figure PCTCN2019122847-appb-000002
至
Figure PCTCN2019122847-appb-000003
可选约
Figure PCTCN2019122847-appb-000004
在一实施例中，隔离介质层220为氧化硅层。在一具体的实施例中，当隔离介质层220为氧化硅层，且半导体层230为多晶硅层，在非原胞区的半导体衬底210上形成氧化硅层 并在氧化硅层上形成第一导电类型多晶硅层的具体方法可为：通过热氧化工艺在半导体衬底210上形成一层热氧化层，通过淀积工艺在热氧化层上淀积一层多晶硅层，通过掺杂工艺对多晶硅层进行第一导电类型掺杂，形成第一导电类型多晶硅层，通过第一次光刻和刻蚀工艺刻蚀掉原胞区的多晶硅并保留非原胞区的多晶硅，通过第二次刻蚀工艺刻蚀掉原胞区域的热氧层并保留非原胞区域的热氧化层，在第二次刻蚀工艺中，可以以多晶硅层为掩膜对热氧化层进行第二次刻蚀，由此可以省略一次光刻工艺。在非原胞区的半导体衬底上形成隔离介质层并在隔离介质层上形成具有第一导电类型掺杂的半导体层的工艺步骤并不限于此，在其他实施例中，也可以是先进行光刻与刻蚀工艺，再进行掺杂工艺。
步骤S220：以半导体层和隔离介质层为掩膜对所述半导体衬底进行第一导电类型阱注入，在所述原胞区的半导体衬底内形成阱区。
如图3b所示，以半导体层230和隔离介质层220为掩膜，对半导体衬底210进行第一导电类型阱注入，在原胞区的半导体衬底内形成阱区213。在一实施例中，隔离介质层220和半导体层230的总厚度H2+H3的范围为
Figure PCTCN2019122847-appb-000005
至
Figure PCTCN2019122847-appb-000006
该厚度可以在阱注入时避免阱注入粒子进入非原胞区的半导体衬底内。在一实施例中，半导体层的第一导电类型掺杂的剂量比半导体衬底的第一导电类型阱注入的剂量至少大一个数量级，其中，第一导电类型阱注入的剂量不超过2E13/cm 2，可为5E12/cm 2～2E13/cm 2，半导体层230的第一导电类型掺杂的剂量不低于4E14/cm 2，可为4E14/cm 2～8E14/cm 2，即半导体层230的第一导电类型掺杂的剂量是第一导电类型阱注入的剂量的至少十倍。当以半导体层230和隔离介质层220为掩膜进行第一导电类型阱注入时，第一导电类型阱注入粒子对半导体层的影响较小。当保护结构对半导体层中的第一导电类型掺杂浓度的准确性要求较高时，在进行半导体层的第一导电类型掺杂时，可考虑后续阱注入工艺的影响适当降低掺杂剂量。
在一实施例中，当工作结构为VDMOS管时，在阱注入工艺之前，还包括在原胞区形成沟槽，在沟槽内壁形成栅氧层并在沟槽内填充栅多晶硅的步 骤。如图3b所示，通过光刻与刻蚀工艺在原胞区内的半导体衬底210上形成若干沟槽，通过热氧化工艺在沟槽内壁形成一层栅氧层212，通过淀积工艺淀积一层多晶硅，该多晶硅填充于沟槽内，通过回蚀工艺去除沟槽外的多晶硅并保留沟槽内的多晶硅形成栅多晶硅212。
步骤S230：对阱区进行掺杂以在原胞区内形成工作结构，对半导体层进行掺杂以在非原胞区上形成保护结构。
工作结构是以原胞区的半导体衬底为基底，形成于半导体衬底210内，保护结构是以非原胞区的半导体衬底上的半导体层为基底，形成于半导体衬底210上。在步骤S220中形成半导体层230和阱区213后，经过掺杂等工艺在原胞区内形成工作结构，在非原胞区上形成保护结构。
步骤S240：在工作结构和保护结构上形成层间介质层，并在层间介质层内形成接触孔，在层间介质层上形成与接触孔连接的金属互连层，通过金属互连层和接触孔连接工作结构和保护结构。
通过步骤S230，形成工作结构和保护结构，其中，保护结构形成于半导体层230内，工作结构形成于原胞区的半导体衬底210内。如图3d所示，形成工作结构和保护结构后，需淀积一层层间介质层240，并在层间介质层240内形成接触孔，通过接触孔引出工作结构和保护结构的各个电极，然后在层间介质层上淀积一层金属互连层，金属互连层与接触孔连接，通过金属互连层和接触孔连接工作结构和保护结构。
以工作结构为VDMOS管，保护结构为二极管为例对步骤S230和步骤S240进行说明，其中，半导体衬底具有第二导电类型。
在步骤S230中，对阱区进行掺杂以在原胞区内形成工作结构，对半导体层进行掺杂以在非原胞区上形成保护结构的步骤具体包括：
对阱区进行第二导电类型掺杂形成源区，对半导体层的部分区域进行第二导电类型掺杂以形成并列的第一导电类型半导体结构和第二导电类型半导体结构。
如图3c所示，对阱区213进行掺杂形成源区214，对半导体层的部分区 域进行第二导电类型掺杂以使部分区域的第一导电类型半导体转变为第二导电类型半导体，从而使半导体层形成并列的第一导电类型半导体结构231和第二导电类型半导体结构232，其中，第一导电类型半导体结构231为半导体层未进行第二导电类型掺杂的区域，第二导电类型半导体结构232为半导体层中进行第二导电类型掺杂的区域，并列的第一导电类型半导体结构231和第二导电类型半导体结构232形成PN结。在一实施例中，继续参见图3c，半导体层形成有多个第一导电类型半导体结构231和多个第二导电类型半导体结构232，且第一导电类型半导体结构231与第二导电类型半导体结构232的数目相等，第一导电类型半导体结构231与第二导电类型半导体结构232交替设置，分别从位于最外端的第一导电类型半导体结构231和第二导电类型半导体结构232引出二极管的第一极和第二极，由此形成多个串联的PN结。
在一实施例中，对阱区进行第二导电类型掺杂形成源区，对半导体层的部分区域进行第二导电类型掺杂的步骤具体包括：共用一片掩膜板在阱区和半导体层上形成掺杂窗口，并同时对阱区和半导体层进行第二导电类型掺杂。共用一片掩膜板，在原胞区域上方以及部分半导体层上形成掺杂窗口，同时对阱区和部分半导体层进行第二导电类型掺杂，可节省工艺步骤。
在步骤S240中，在工作结构和保护结构上形成层间介质层，并在层间介质层内形成接触孔，在层间介质层上形成与接触孔连接的金属互连层，通过金属互连层和接触孔连接工作结构和保护结构的步骤具体包括：
在源区、沟槽及第一导电类型半导体结构和第二导电类型半导体结构上形成层间介质层，在源区上方的层间介质层上形成第一接触孔并引出与源区连接的源极，在沟槽上方的层间介质层上形成第二接触孔并引出与栅多晶硅连接的栅极，在第一导电类型半导体结构上方的层间介质层上形成第三接触孔并引出二极管的第一极，在第二导电类型半导体结构上方的层间介质层上形成第四接触孔并引出二极管的第二极，在层间介质层上形成金属互连层，使第一极与栅极连接，第二极与源极连接。
如图3d所示，在源区、沟槽及第一导电类型半导体结构和第二导电类型半导体结构上淀积一层层间介质层240，在源区214上方的层间介质层240内形成第一接触孔251并引出与源区214连接的源极，在沟槽上方的层间介质层240内形成第二接触孔并引出与栅多晶硅212连接的栅极，在第一导电类型半导体结构231上方的层间介质层内形成第三接触孔253并引出二极管的第一极，在第二导电类型半导体结构232上方的层间介质层240上形成第四接触孔254并引出二极管的第二极。在层间介质层240上形成金属互连层，金属互连层包括与第一接触孔连接的第一金属条261、与第二接触孔连接的第二金属条(图中未示出)、与第三接触孔253连接的第三金属条263以及与第四接触孔254连接的第四金属条264，通过金属互连层和接触孔，使第一极与栅极连接，第二极与源极连接。在一实施例中，引出源极的第一接触孔251穿透源区214并延伸至阱区213，引出二极管第一极的第三接触孔253穿透第一导电类型半导体结构231并停止于隔离介质层220上，引出二极管第二极的第四接触孔254穿透第二导电类型半导体结构232并停止于隔离介质层220上。同时，在半导体衬底210背离层间介质层的一侧形成漏极，由此完成VDMOS管与二极管的并联，利用二极管实现对VDMOS的静电保护功能。
在一实施例中，半导体衬底包括半导体基底自半导体基底生长的外延层。在一实施例中，第一导电类型可为P型，第二导电类型可为N型，或第一导电类型可为N型，第二导电类型可为P型。当第一导电类型为P型时，通过上述方法形成的VDMOS管为N型VDMOS管，形成的二极管中的第一极为阳极，第二极为阴极，当第一导电类型为N型时，通过上述方法形成的VDMOS管为P型VDMOS管，形成的二极管中的第一极为阴极，第二极为阳极。上述实施例具体以VDMOS管作为工作结构，在其他实施例中，也可以是横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor，简称LDMOS管)或者其他具有阱注入工艺的半导体器件，在阱注入时以保护结构中的隔离介质层和 半导体层为掩膜代替场氧实现自对准阱注入的方案均落入本申请的保护范围之内。
上述半导体器件制备方法，在对原胞区N的半导体衬底210进行阱注入之前，先在非原胞区M形成隔离介质层220和半导体层230，以隔离介质层220和半导体层230共同作为自对准掩膜，对半导体衬底210进行阱注入，从而在原胞区N形成阱区，而非原胞区M由于受隔离介质层220和半导体层230的屏蔽作用而不受阱注入的影响。在传统技术中，非原胞区域上的保护结构形成于场氧上，且使用场氧作为自对准掩膜，场氧的厚度h1较厚，而在本申请中，非原胞区域上的保护结构形成于隔离介质层220上，由于以隔离介质层220和形成保护结构的半导体层230作为自对准掩膜，只要隔离介质层220和半导体层230整体达到一定厚度即可作为自对准掩膜，即隔离介质层220的厚度H3可以比较薄，隔离介质层的厚度H3小于场氧的厚度h1，而半导体层的厚度保持不变时，即H2＝h2时，使得非原胞区上的保护结构与原胞区内的工作结构形成的台阶高度减小，当原胞区上方的层间介质层的厚度不变时，即D2＝d2时，本申请中的非原胞区上的保护结构上方的层间介质层的厚度增大，即D1＞d1，使得层间介质层对保护结构的隔离作用增强。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件制备方法，所述半导体器件包括工作结构和对所述工作结构进行保护的保护结构，所述制备方法包括：
    提供半导体衬底，所述半导体衬底包括原胞区和非原胞区，在所述非原胞区的半导体衬底上形成隔离介质层，在所述隔离介质层上形成具有第一导电类型掺杂的半导体层；
    以所述半导体层和所述隔离介质层为掩膜对所述半导体衬底进行第一导电类型阱注入，在所述原胞区的半导体衬底内形成阱区；
    对所述阱区进行掺杂以在所述原胞区内形成所述工作结构，对所述半导体层进行掺杂以在所述非原胞区上形成所述保护结构；以及
    在所述工作结构和所述保护结构上形成层间介质层，并在所述层间介质层内形成接触孔，在所述层间介质层上形成与所述接触孔连接的金属互连层，通过所述金属互连层和所述接触孔连接所述工作结构和所述保护结构。
  2. 如权利要求1所述的制备方法，其中，所述半导体层的第一导电类型掺杂的剂量比所述半导体衬底的第一导电类型阱注入的剂量至少大一个数量级。
  3. 如权利要求2所述的制备方法，其中，所述第一导电类型掺杂的剂量不低于4E14/cm 2，所述第一导电类型阱注入的剂量不超过2E13/cm 2。
  4. 如权利要求1所述的制备方法，其中，所述隔离介质层的厚度范围为
    Figure PCTCN2019122847-appb-100001
    至
    Figure PCTCN2019122847-appb-100002
  5. 如权利要求4所述的制备方法，其中，所述隔离介质层和所述半导体层的总厚度的范围为
    Figure PCTCN2019122847-appb-100003
    至
    Figure PCTCN2019122847-appb-100004
  6. 如权利要求1所述的制备方法，其中，所述隔离介质层为氧化硅层。
  7. 如权利要求6所述的制备方法，其中，所述半导体层为第一导电类型多晶硅层。
  8. 如权利要求1所述的制备方法，其中，所述原胞区位于所述半导体衬 底的中间位置，非原胞区位于所述半导体衬底的外围且包围所述原胞区。
  9. 如权利要求1所述的制备方法，其中，所述工作结构为VDMOS管，在对所述原胞区的半导体衬底进行第一导电类型阱注入的步骤之前，还包括：
    在所述原胞区形成沟槽，在所述沟槽内壁形成栅氧层并在所述沟槽内填充栅多晶硅。
  10. 如权利要求9所述的制备方法，其中，所述保护结构为二极管，所述半导体衬底具有第二导电类型；
    所述对所述阱区进行掺杂以在所述原胞区内形成所述工作结构，对所述半导体层进行掺杂以在所述非原胞区上形成所述保护结构的步骤具体包括：
    对所述阱区进行第二导电类型掺杂形成源区，对所述半导体层的部分区域进行第二导电类型掺杂以形成并列的第一导电类型半导体结构和第二导电类型半导体结构；
    所述在所述工作结构和所述保护结构上形成层间介质层，并在所述层间介质层内形成接触孔，在所述层间介质层上形成与所述接触孔连接的金属互连层，通过所述金属互连层和所述接触孔连接所述工作结构和所述保护结构的步骤具体包括：
    在所述源区、沟槽及所述第一导电类型半导体结构和第二导电类型半导体结构上形成层间介质层，在所述源区上方的层间介质层上形成第一接触孔并引出与所述源区连接的源极，在所述沟槽上方的层间介质层上形成第二接触孔并引出与所述栅多晶硅连接的栅极，在所述第一导电类型半导体结构上方的层间介质层上形成第三接触孔并引出所述二极管的第一极，在所述第二导电类型半导体结构上方的层间介质层上形成第四接触孔并引出所述二极管的第二极，在所述层间介质层上形成金属互连层，使所述第一极与所述栅极连接，所述第二极与所述源极连接。
  11. 如权利要求10所述的制备方法，其中，所述对所述阱区进行第二导电类型掺杂形成源区，对所述半导体层的部分区域进行第二导电类型掺杂的步骤具体包括：
    共用一片掩膜板在所述阱区和所述半导体层上形成掺杂窗口，并同时对所述阱区和所述半导体层进行第二导电类型掺杂。
  12. 如权利要求10所述的制备方法，其中，所述第一接触孔穿透所述源区并延伸至所述阱区内。
  13. 如权利要求10所述的制备方法，其中，所述半导体层形成多个所述第一导电类型半导体结构和多个所述第二导电类型半导体结构，且所述第一导电类型半导体结构与所述第二导电类型半导体结构的数目相等，所述第一导电类型半导体结构与所述第二导电类型半导体结构交替设置，分别从位于最外端的第一导电类型半导体结构和第二导电类型半导体结构引出二极管的第一极和第二极。
  14. 如权利要求10所述的制备方法，其中，在所述半导体衬底背离所述层间介质层的一侧形成漏极。
  15. 如权利要求7所述的制备方法，其中，所述在所述非原胞区的半导体衬底上形成隔离介质层，在所述隔离介质层上形成具有第一导电类型掺杂的半导体层的步骤具体包括：
    通过热氧化工艺在所述半导体衬底上形成一层热氧化层；
    通过淀积工艺在所述热氧化层上淀积一层多晶硅层；
    通过掺杂工艺对所述多晶硅层进行第一导电类型掺杂；
    通过第一次光刻和刻蚀工艺刻蚀掉原胞区的多晶硅层并保留非原胞区的多晶硅层；以及
    以保留的多晶硅层为掩膜，通过第二次刻蚀工艺刻蚀掉原胞区域的所述热氧层并保留非原胞区域的热氧化层，保留的所述热氧化层和保留的所述多晶硅层分别为隔离介质层和半导体层。
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