WO2020113771A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020113771A1
WO2020113771A1 PCT/CN2019/071346 CN2019071346W WO2020113771A1 WO 2020113771 A1 WO2020113771 A1 WO 2020113771A1 CN 2019071346 W CN2019071346 W CN 2019071346W WO 2020113771 A1 WO2020113771 A1 WO 2020113771A1
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Prior art keywords
layer
gate
metal layer
insulating layer
gate insulating
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English (en)
French (fr)
Inventor
余赟
杨薇薇
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/462,546 priority Critical patent/US10950677B2/en
Publication of WO2020113771A1 publication Critical patent/WO2020113771A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to the technical field of flexible display devices, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • OLED Organic Light-Emitting Diode
  • OLED display device is more and more widely used due to its advantages of light weight, self-illumination, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption and fast response speed, especially flexible OLED display
  • the device has the characteristics of being bendable and easy to carry, and has become the main field of research and development in the field of display technology.
  • the flexible array substrate driving the OLED display device to emit light is one of the key technologies.
  • Existing common flexible array substrates generally include a flexible substrate, a barrier layer, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate layer arranged in order from bottom to top , Interlayer insulation layer, source and drain.
  • the specific manufacturing process flow is: forming a flexible substrate, then depositing a barrier layer on the flexible substrate, then depositing an active layer on the barrier layer, depositing and crystallizing the active layer, and then depositing a first gate insulating layer and a first gate Sputter-depositing the first gate layer on the insulating layer and patterning the first gate layer by yellow etching; then performing a self-aligned process to heavily dope the P-type active layer; then depositing a second gate insulating layer and Sputter-depositing the second gate layer on the second gate insulating layer and patterning the second gate layer by yellow etching; then depositing an interlayer insulating layer and then performing hydrogenation activation treatment on the active layer; afterwards, yellow etching is formed Contact holes and deposit source and drain.
  • the material used in the first gate layer and the second gate layer is usually molybdenum, and the thickness is about 250 nm.
  • the thickness of the first gate layer and the second gate layer is relatively thick.
  • the bending resistance of the gate in the second gate layer is poor. Because the thicknesses of the first gate layer and the second gate layer are relatively thick, the activation hydrogenation process is usually carried out continuously. During the activation hydrogenation process, the activation temperature or the hydrogenation temperature is higher, and the process is more difficult.
  • the present invention provides an array substrate, a method for manufacturing the same, and a display panel.
  • a multi-layer composite metal layer replaces a single layer of molybdenum as a gate layer to solve the problem of gate wiring in the existing gate layer. It is brittle and has poor bending resistance. When it has the same resistance, the existing gate layer is thick and other defects, and at the same time, the defects of the array substrate manufacturing process are improved.
  • the technical solution for solving the above technical problems is to provide an array substrate including a flexible substrate; an active layer covering the flexible substrate; a first gate insulating layer covering the active layer; the first The gate layer is provided on the first gate insulating layer, the first gate layer is a multi-layer composite metal layer; the second gate insulating layer covers the first gate insulating layer and the The first gate layer; the second gate layer is provided on the second gate insulating layer, and the second gate layer is a multi-layer composite metal layer.
  • the multilayer composite metal layer includes a first metal layer and a second metal layer; a third metal layer is provided between the first metal layer and the second metal layer; wherein, The metal used for the first metal layer and the second metal layer is titanium or molybdenum; the metal used for the second metal layer is aluminum.
  • the thickness of the third metal layer is 100-120 nm; the thickness of the first metal layer and the second metal layer are both 30- 50nm.
  • the material used for the active layer is amorphous silicon;
  • the first gate insulating layer is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack;
  • the second gate The electrode insulating layer is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the active layer has a source region and a drain region;
  • the array substrate further includes an interlayer insulating layer covering the second gate insulating layer and the second gate ;
  • Contact holes from the interlayer insulating layer to the active layer, wherein one of the contact holes corresponds to the source region, and the other contact hole corresponds to the drain region;
  • the source provided in The interlayer insulating layer is connected to the source region through the corresponding contact hole;
  • the drain is provided on the interlayer insulating layer and connected to the drain region through the corresponding contact hole ;
  • the flexible substrate includes a flexible base layer; a barrier layer is provided on the flexible base layer, and the active layer is provided on the barrier layer.
  • the invention also provides a method for manufacturing the array substrate, including the following steps: S1) fabricating a flexible substrate; S2) depositing an active layer on the flexible substrate by meteorological deposition and crystallizing the active layer S3) depositing a first gate insulating layer on the flexible substrate and the active layer by a weather deposition method; S4) depositing a first gate layer on the first gate insulating layer, the first The gate layer is a multi-layer composite metal layer; and a first gate mask is overlaid on the first gate insulating layer, and the first gate layer is patterned by yellow light etching to form a first gate; S5) Depositing a second gate insulating layer on the first gate insulating layer and the first gate layer; S6) depositing a second gate layer on the second gate insulating layer, the second gate The layer is a multi-layer composite metal layer; and a second gate mask is covered above the second gate insulating layer, and the second gate layer is formed by yellow light etching and patterning the second gate layer.
  • the active layer includes a source region and a drain region; between the step S3) and the step S4), the following step is further included: S100) the first gate is insulated A first gate mask is covered above the layer, and the source region and the drain region in the active layer are heavily doped P-type; S200) The P-type heavily doped In the source region and the drain region, the activation temperature is 450° C., and the activation time is 30-60 minutes.
  • step S6) depositing an interlayer insulating layer on the second gate insulating layer and the second gate layer; S8) hydrogenation Treat the activated first gate insulating layer and second gate insulating layer, wherein the hydrogenation temperature is 330-370°C and the hydrogenation time is 30-60min; S9) covering a contact over the interlayer insulation layer A hole mask, and forming contact holes penetrating from the interlayer insulating layer to the active layer in the source region and the drain region by yellow etching; S10) in the interlayer insulating layer Source and drain electrodes are deposited on the top and the contact holes.
  • the multilayer composite metal layer includes a first metal layer and a second metal layer; a third metal layer is provided between the first metal layer and the second metal layer; wherein, The metal used for the first metal layer and the second metal layer is titanium or molybdenum; the metal used for the second metal layer is aluminum.
  • the invention also provides a display panel, including the array substrate.
  • the array substrate and the display panel of the present invention effectively improve the bending resistance of the gate wiring in the display panel by using the first gate layer and the second gate layer with multiple composite metal layers instead of molybdenum as the gate wiring.
  • the thickness of the first gate layer and the second gate layer of the present invention is thin compared to the prior art, and the thickness of the film layer is significantly reduced compared to the prior art, or
  • the line width can be made small, and high-resolution display can be achieved.
  • the manufacturing method of the array substrate of the present invention advances the P-type heavy doping and activation process before depositing the first gate layer, which effectively prevents the first gate layer from being activated at a high temperature (the activation temperature is generally 450 °C, the activation time is 60 minutes)
  • the activation temperature is generally 450 °C, the activation time is 60 minutes
  • the impedance becomes larger, the P-type heavily doped is doped with the first grid photomask, no additional photomask is needed, and the manufacturing process is simple and convenient.
  • the activation and hydrogenation processes are separated, and after the interlayer insulating layer is formed, a low-temperature hydrogenation process of 330-370°C is used to not only avoid the continuous impact of the first gate layer on the high-temperature process, but also ensure the hydrogenation and Activation.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, which mainly embodies the correspondence between contact holes and source and drain regions.
  • FIG. 3 is a layered structure diagram of a multilayer composite metal layer according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of manufacturing steps of an array substrate according to an embodiment of the invention.
  • FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the invention.
  • the first gate insulating layer 14 First gate layer;
  • Second gate insulating layer 16 second gate layer
  • the array substrate 10 of the present invention includes a flexible substrate 11, an active layer 12, a first gate insulating layer 13, a first gate layer 14, and a second gate insulating layer 15. Second gate layer 16, interlayer insulating layer 17, source electrode 18 and drain electrode 19.
  • the flexible substrate 11 includes a flexible base layer 111 and a barrier layer 112.
  • the barrier layer 112 is provided on the flexible substrate 11.
  • the active layer 12 is provided on the barrier layer 112.
  • the material used for the flexible substrate 11 may be a polyimide material, and the barrier layer 112 may be one of a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the active layer 12 covers the flexible substrate 11; the active layer 12 has a source region 121 and a drain region 122.
  • the material used for the active layer 12 is amorphous silicon (a-Si), and the first gate insulating layer 13 overlies the active layer 12.
  • the first A gate insulating layer 13 is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the first gate layer 14 is disposed on the first gate insulating layer 13, the first gate layer 14 is a multilayer composite metal layer 2; the second gate insulating layer 15 covers the On the first gate insulating layer 13 and the first gate layer 14, in this embodiment, the second gate insulating layer 15 is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the second gate layer 16 is disposed on the second gate insulating layer 15.
  • the second gate layer 16 is a multilayer composite metal layer 2.
  • the interlayer insulating layer 17 covers the second gate insulating layer 15 and the second gate.
  • the array substrate 10 of this embodiment further includes a contact hole 101 penetrating from the interlayer insulating layer 17 to the active layer 12, wherein one of the contact holes 101 corresponds to the source region 121, and the other of the contact holes 101 corresponds to the drain region 122 (see FIG. 2); the source electrode 18 is provided on the interlayer insulating layer 17 and connected to the source region 121 through the corresponding contact hole 101; the drain The electrode 19 is provided on the interlayer insulating layer 17 and connected to the drain region 122 through the corresponding contact hole 101.
  • the multi-layer composite metal layer 2 includes a first metal layer 21, a second metal layer 22, and a third metal layer 23.
  • the third metal layer 23 is provided on the first metal layer 21 And the second metal layer 22; wherein, the metal used for the first metal layer 21 and the second metal layer 22 is titanium or molybdenum; the metal used for the third metal layer 23 is aluminum.
  • the thickness of the third metal layer 23 is 100-120 nm; the thickness of the first metal layer 21 and the second metal layer 22 are both 30- 50nm.
  • the material used for the first metal layer 21 and the second metal layer 22 is titanium, and the material used for the third metal layer 23 is aluminum.
  • the first gate layer 14 forms a metal layer structure of titanium-aluminum-titanium.
  • the material used for the first metal layer 21 and the second metal layer 22 is molybdenum
  • the material used for the third metal layer 23 is aluminum, therefore, the second gate layer 16 Form a layered structure of molybdenum-aluminum-molybdenum.
  • the thickness of the gate layer or the gate layer made of molybdenum is 250 nm or more.
  • the multilayer composite metal layer 2 is used instead, and the third metal layer 23 ( The thickness of the aluminum layer) is set between 100-120 nm to obtain the same impedance; meanwhile, the first metal layer 21 and the second metal layer 22 can protect the third metal layer 23.
  • the thickness of the film layer is significantly reduced compared with the prior art, or the thickness of the multilayer composite metal layer 2 is equivalent to the thickness of the existing gate layer
  • the line width can be made small, high-resolution display can be realized, and meanwhile, the bending resistance of the wiring in the display panel 1 can be improved.
  • the material configuration of the multilayer composite metal layer 2 described in this embodiment is not limited to the above solution, and there may be more other options.
  • the material used for the first metal layer 21 and the second metal layer 22 is preferably molybdenum, and the material used for the third metal layer 23 is aluminum.
  • the material used for the first metal layer 21 and the second metal layer 22 is titanium, and the material used for the third metal layer 23 is aluminum.
  • the material used for the first metal layer 21 is titanium and the material used for the second metal layer 22 is molybdenum
  • the material used for the third metal layer 23 is aluminum.
  • the material used for the first metal layer 21 and the second metal layer 22 is molybdenum, and the material used for the third metal layer 23 is aluminum. Of course, there are other combinations, so I won't repeat them one by one.
  • the materials used for the first metal layer 21 and the second metal layer 22 are not limited to titanium and molybdenum, but may also be metals such as silver, copper, and tungsten.
  • the present invention also provides a method for manufacturing the array substrate 10, which includes the following steps S1)-step S9) and steps S100)-step S200).
  • a substrate is first provided, a polyimide material is coated on the substrate to form a flexible base layer 111, and silicon oxide or silicon nitride material is deposited on the surface of the flexible base layer 111 to form a silicon oxide layer Or a silicon nitride layer or a silicon nitride stack is used as the barrier layer 112.
  • the material used for the active layer 12 is amorphous silicon (a-Si), and the active layer 12 is deposited by a meteorological deposition method.
  • the first gate insulating layer 13 is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the first gate insulating layer 13 is deposited by a weather deposition method.
  • step S200 Activating the P-type heavily doped source region 121 and the drain region 122, wherein the activation temperature is 450° C. and the activation time is 30-60 minutes.
  • the manufacturing method of the array substrate of the present invention advances the P-type heavy doping and activation processes, namely step S100) and step S200) to step S4), that is, to advance to the deposition of the first gate layer 14, so as to prevent all After the first gate layer 14 is activated at a high temperature (the activation temperature is generally 450° C. and the activation time is 60 minutes), the impedance of the first gate layer 14 becomes larger.
  • the first gate light for P-type heavy doping The mask is used for doping without adding a photomask.
  • a first gate layer 14 is deposited on the first gate insulating layer 13, and the first gate layer 14 is etched and patterned to form a first gate 14a (see FIG. 1).
  • the first gate layer 14 is a multi-layer composite metal layer 2, and the first gate layer 14 forms a titanium-aluminum-titanium metal layer structure.
  • the second gate insulating layer 15 is a silicon oxide layer, a silicon nitride layer, or a silicon nitride stack.
  • the first gate insulating layer 13 is covered with a first gate mask, and the first gate layer 14 is etched and patterned with yellow light to form the first gate ⁇ 14a.
  • a second gate insulating layer 15 is deposited on the first gate insulating layer 13 and the first gate layer 14.
  • a second gate layer 16 Depositing a second gate layer 16 on the second gate insulating layer 15, and etching and patterning the second gate layer 16 to form a second gate 16a (see FIG. 1).
  • the second gate layer 16 is a multilayer composite metal layer 2, and the second gate layer 16 forms a metal layer structure of molybdenum-aluminum-molybdenum.
  • a second gate mask is covered above the second gate insulating layer 15, and the second gate layer 16 is etched and patterned with yellow light to form the second gate 16a.
  • interlayer insulating layer 17 is a silicon oxide layer, a silicon nitride layer or a silicon nitride stack Floor.
  • the first gate insulating layer 13 and the second gate insulating layer 15 after hydrogenation activation wherein the hydrogenation temperature is 330-370°C and the hydrogenation time is 30-60min; in this embodiment, the activation is mainly To rearrange the crystal structure of the active layer 12, the doping element ions uniformly diffuse to the lattice position of the doped region, which requires a higher temperature; and hydrogenation is to supplement the gate insulating layer with hydrogen to reduce the gate insulating layer and the active
  • the interface defect of layer 12 can be hydrogenated at a relatively low temperature, and the activation and hydrogenation processes are separated, that is, activation is performed after the P-type doping is completed, and the hydrogenation process is performed after the formation of the interlayer insulating layer 17 In the hydrogenation process, a low-temperature hydrogenation process of 330-370°C is used, which not only prevents the first gate layer 14 from continuously undergoing a high-temperature process, but also ensures the hydrogenation and activation of the array substrate 10.
  • the array substrate 10 may further include other devices or functional layers such as anode traces and pixel definition layers.
  • the improvement of the array substrate 10 of the present invention lies in the improvement of the gate layer and activation in the manufacturing method And the improvement of the sequence of hydrogenation steps, therefore, for other devices or functional layers such as anode traces and pixel definition layers, reference may be made to the prior art, which will not be elaborated one by one.
  • the present invention also provides a display panel 1 including the array substrate 10 and the color filter substrate 20 opposite to the array substrate 10.
  • the display panel 1 in the present invention may also include a polarizer Device.
  • the main improvement of the display panel 1 in this embodiment lies in the array substrate 10, therefore, other devices such as polarizers will not be described in detail.

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Abstract

一种阵列基板及其制作方法、显示面板。所述阵列基板（10）包括柔性基板（11）；有源层（12）覆于所述柔性基板（11）上；第一栅极绝缘层（13）覆于所述有源层（12）上；第一栅极层（14）设于所述第一栅极绝缘层（13）上，第一栅极层（14）为多层复合金属层；第二栅极绝缘层（15）覆于所述第一栅极绝缘层（13）和所述第一栅极层（14）上；以及第二栅极层（16）设于所述第二栅极绝缘层（15）上，所述第二栅极层（16）为多层复合金属层。通过将所述第一栅极层（14）和所述第二栅极层（16）用多层复合金属层代替钼作为栅极走线，有效地提高了显示面板中栅极走线的耐弯折性能，将P型重掺杂和活化工艺提前到沉积所述第一栅极层（14）之前，有效地防止了第一栅极层（14）经活化的高温后，其阻抗会变大的情况。

Description

阵列基板及其制作方法、显示面板 技术领域
本发明涉及柔性显示装置的技术领域，具体为一种阵列基板及其制作方法、显示面板。
 背景技术
OLED（Organic Light-Emitting Diode）显示装置由于其重量轻，自发光，广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，尤其是柔性OLED显示装置具有可弯折易携带的特点，成为显示技术领域研究和开发的主要领域。其中驱动OLED显示装置发光的柔性阵列基板是关键技术之一。
如何提高柔性阵列基板的抗弯折性能、做到高解析度、高良率是目前主要研究方向。
现有常用柔性阵列基板一般包括从下到上依次设置的柔性基板、阻隔层、有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间绝缘层、源漏极。具体制备工艺流程为：形成柔性基板，然后在柔性基板上沉积阻隔层，再在阻隔层上沉积有源层沉积并晶化有源层，然后沉积第一栅极绝缘层以及在第一栅极绝缘层上溅射沉积第一栅极层并对第一栅极层黄光蚀刻图案化；然后自对准工艺对有源层进行P型重掺杂；然后沉积第二栅极绝缘层以及在第二栅极绝缘层上溅射沉积第二栅极层并对第二栅极层黄光蚀刻图案化；然后沉积层间绝缘层，然后对有源层进行氢化活化处理；之后黄光蚀刻形成接触孔，并沉积源极和漏极。
 技术问题
现有技术中，第一栅极层、第二栅极层中所用材料通常为钼，厚度在250nm左右，第一栅极层、第二栅极层的厚度较厚，第一栅极层、第二栅极层中栅极的耐弯折性较差。由于第一栅极层、第二栅极层厚度较厚，活化氢化处理工艺通常连续进行，在活化氢化处理过程中，活化温度或氢化温度较高，制程较为困难。
 技术解决方案
为了解决上述技术问题：本发明提供一种阵列基板及其制作方法、显示面板，通过多层复合金属层替代单层的钼作为栅极层，以解决现有栅极层中栅极走线较脆、耐弯折性较差，在具有相同抗阻时，现有栅极层较厚等缺陷，同时以改善阵列基板的制程的缺陷。
解决上述技术问题的的技术方案是：提供一种阵列基板，包括柔性基板；有源层，覆于所述柔性基板上；第一栅极绝缘层，覆于所述有源层上；第一栅极层，设于所述第一栅极绝缘层上，所述第一栅极层为多层复合金属层；第二栅极绝缘层，覆于所述第一栅极绝缘层和所述第一栅极层上；第二栅极层，设于所述第二栅极绝缘层上，所述第二栅极层为多层复合金属层。
在本发明的一实施例中，所述多层复合金属层包括第一金属层和第二金属层；第三金属层，设于所述第一金属层和第二金属层之间；其中，所述第一金属层和第二金属层所用金属为钛或钼；所述第二金属层所用金属为铝。
在本发明的一实施例中，所述多层复合金属层中，所述第三金属层的厚度为100-120nm；所述第一金属层和所述第二金属层的厚度均为30-50nm。
在本发明的一实施例中，所述有源层所用材料为无定形硅；所述第一栅极绝缘层为氧化硅层、氮化硅层或氮化硅叠层；所述第二栅极绝缘层为氧化硅层、氮化硅层或氮化硅叠层。
在本发明的一实施例中，所述有源层具有源极区和漏极区；所述阵列基板还包括层间绝缘层，覆于所述第二栅极绝缘层和第二栅极上；接触孔，从所述层间绝缘层贯穿至所述有源层，其中一所述接触孔对应所述源极区，另一所述接触孔对应所述漏极区；源极，设于所述层间绝缘层上并通过对应的所述接触孔连接至所述源极区；漏极，设于所述层间绝缘层上并通过对应的所述接触孔连接至所述漏极区；
在本发明的一实施例中，所述柔性基板包括柔性基层；阻隔层，设于所述柔性基层上，所述有源层设于所述阻隔层上。
本发明还提供了一种所述阵列基板的制作方法，包括以下步骤：S1）制作一柔性基板；S2）在所述柔性基板上通过气象沉积法沉积有源层以及晶化所述有源层；S3）在所述柔性基板以及所述有源层上通过气象沉积法沉积第一栅极绝缘层；S4）在所述第一栅极绝缘层上沉积第一栅极层，所述第一栅极层为多层复合金属层；以及在所述第一栅极绝缘层上方覆盖一第一栅极光罩，黄光蚀刻图案化所述第一栅极层形成第一栅极；S5）在所述第一栅极绝缘层和所述第一栅极层上沉积第二栅极绝缘层；S6）在所述第二栅极绝缘层上沉积第二栅极层，所述第二栅极层为多层复合金属层；以及在所述第二栅极绝缘层上方覆盖一第二栅极光罩，黄光蚀刻图案化所述第二栅极层形成第二栅极。
在本发明的一实施例中，所述有源层包括源极区和漏极区；在所述步骤S3）和步骤S4）之间还包括以下步骤：S100）在所述第一栅极绝缘层上方覆盖一第一栅极光罩，并对所述有源层中的所述源极区和所述漏极区进行P型重掺杂；S200）活化处理P型重掺杂后的所述源极区和所述漏极区，其中活化温度为450℃，活化时间为30-60分钟。
在本发明的一实施例中，在所述步骤S6）之后还包括以下步骤：S7）在所述第二栅极绝缘层和所述第二栅极层上沉积层间绝缘层；S8）氢化处理活化后的所述第一栅极绝缘层和第二栅极绝缘层，其中，氢化温度为330-370℃，氢化时间为30-60min；S9）在所述层间绝缘层上方覆盖一接触孔光罩，并在所述源极区和所述漏极区通过黄光蚀刻形成从所述层间绝缘层贯穿至所述有源层上的接触孔；S10）在所述层间绝缘层上以及所述接触孔中沉积源极和漏极。
在本发明的一实施例中，所述多层复合金属层包括第一金属层和第二金属层；第三金属层，设于所述第一金属层和第二金属层之间；其中，所述第一金属层和第二金属层所用金属为钛或钼；所述第二金属层所用金属为铝。
本发明还提供了一种显示面板，包括所述的阵列基板。
 有益效果
本发明的阵列基板和显示面板通过将第一栅极层和第二栅极层用多层复合金属层代替钼作为栅极走线，有效地提高了显示面板中栅极走线的耐弯折性能，同时，在具有相同阻抗时，本发明的第一栅极层和第二栅极层相比于现有技术厚度较薄，其膜层厚度与现有技术相比明显降低，或者所述多层复合金属层的厚度与现有栅极层的厚度相当情况下，其线宽可以做到很小，可以实现高解析度显示。本发明的阵列基板的制作方法，将P型重掺杂和活化工艺提前到沉积所述第一栅极层之前，有效地防止了第一栅极层经活化的高温后（活化温度一般为450℃，活化时间为60分钟）其阻抗会变大的情况，P型重掺杂用第一栅极光罩去实现掺杂，不需新增光罩，制程简单方便。将活化和氢化工艺分离，在层间绝缘层成膜后，采用低温氢化工艺330-370℃，既可避免第一栅极层连续的经受高温制程的影响，又可保证对阵列基板进行氢化和活化作用。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
下面结合附图和实施例对本发明作进一步解释。
图1是本发明实施例的阵列基板的结构示意图。
图2是本发明实施例的阵列基板的结构示意图，主要体现接触孔与源极区、漏极区的对应关系。
图3是本发明实施例的多层复合金属层的层状结构图。
图4是本发明实施例的阵列基板制作步骤流程图。
图5是本发明实施例的显示面板的结构示意图。
附图标记：
1显示面板；                    2多层复合金属层；
10阵列基板；                   20彩膜基板；
11柔性基板；                   12有源层；
13第一栅极绝缘层；               14第一栅极层；
15第二栅极绝缘层；               16第二栅极层；
14a第一栅极；                    16a第二栅极；
17层间绝缘层；                  18源极；
19漏极；                        101接触孔；
111柔性基层；                   112阻隔层；
121源极区；                     122漏极区；
21第一金属层；                  22第二金属层；
23第三金属层。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
以下实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图1所示，在一实施例中，本发明的阵列基板10，包括柔性基板11、有源层12、第一栅极绝缘层13、第一栅极层14、第二栅极绝缘层15、第二栅极层16、层间绝缘层17、源极18以及漏极19。
所述柔性基板11包括柔性基层111、阻隔层112，所述阻隔层112设于所述柔性基板11上，所述有源层12设于所述阻隔层112上。所述柔性基板11所用材料可选择聚酰亚胺材料，阻隔层112可为氧化硅层、氮化硅层或氮化硅叠层中的一种。
所述有源层12覆于所述柔性基板11上；所述有源层12具有源极区121和漏极区122。本实施例中，所述有源层12所用材料为无定形硅（a-Si），所述第一栅极绝缘层13覆于所述有源层12上，本实施例中，所述第一栅极绝缘层13为氧化硅层、氮化硅层或氮化硅叠层。所述第一栅极层14设于所述第一栅极绝缘层13上，所述第一栅极层14为多层复合金属层2；所述第二栅极绝缘层15覆于所述第一栅极绝缘层13和所述第一栅极层14上，本实施例中，所述第二栅极绝缘层15为氧化硅层、氮化硅层或氮化硅叠层。所述第二栅极层16设于所述第二栅极绝缘层15上，所述第二栅极层16为多层复合金属层2。所述层间绝缘层17覆于所述第二栅极绝缘层15和第二栅极上。本实施例的阵列基板10还包括接触孔101从所述层间绝缘层17贯穿至所述有源层12，其中一所述接触孔101对应所述源极区121，另一所述接触孔101对应所述漏极区122（参见图2）；所述源极18设于所述层间绝缘层17上并通过对应的所述接触孔101连接至所述源极区121；所述漏极19设于所述层间绝缘层17上并通过对应的所述接触孔101连接至所述漏极区122。
如图3所示，所述多层复合金属层2包括第一金属层21、第二金属层22、以及第三金属层23，所述第三金属层23设于所述第一金属层21和第二金属层22之间；其中，所述第一金属层21和第二金属层22所用金属为钛或钼；所述第三金属层23所用金属为铝。
本实施例中，所述多层复合金属层2中，所述第三金属层23的厚度为100-120nm；所述第一金属层21和所述第二金属层22的厚度均为30-50nm。在所述第一栅极层14中，所述第一金属层21和第二金属层22所用材料为钛，所述第三金属层23所用材料为铝。所述第一栅极层14形成钛-铝-钛的金属层状结构。在所述第二栅极层16中，所述第一金属层21和第二金属层22所用材料为钼，所述第三金属层23所用材料为铝，因此，所述第二栅极层16形成钼-铝-钼的金属层状结构。与钼相比，铝的电阻率较低、柔韧性较好，而钼容易脆裂，阻抗相对于铝较大。现有工艺中，用钼制成的栅极层或栅极层的厚度为250nm或以上，而本实施例中，用所述多层复合金属层2替代，其中所述第三金属层23（铝层）的厚度设置在100-120nm之间即可获得相同阻抗；同时，所述第一金属层21和所述第二金属层22能够起到保护第三金属层23的作用。故用所述多层复合金属层2获得相同走线阻抗时，其膜层厚度与现有技术相比明显降低，或者所述多层复合金属层2的厚度与现有栅极层的厚度相当情况下，其线宽可以做到很小，可以实现高解析度显示，同时能够提高显示面板1中走线耐弯折性能。
本实施例所述多层复合金属层2的材料配置并不限于上述方案，还可以有更多其他的选择方案。例如，在所述第一栅极层14中，所述第一金属层21和第二金属层22所用材料优选为钼，所述第三金属层23所用材料为铝。在所述第二栅极层16中，所述第一金属层21和第二金属层22所用材料为钛，所述第三金属层23所用材料为铝。或者如在所述第一栅极层14中，所述第一金属层21所用材料为钛和第二金属层22所用材料为钼，所述第三金属层23所用材料为铝。在所述第二栅极层16中，所述第一金属层21和第二金属层22所用材料为钼，所述第三金属层23所用材料为铝。当然还有其他的组合，对此不再一一赘述。而所述多层复合金属层2中，第一金属层21和第二金属层22所用材料也不仅限于钛、钼，也可以是银、铜、钨等金属。
如图4所示，同时参见图1至图3所示，本发明还提供了一种所述阵列基板10的制作方法，包括以下步骤S1）- 步骤S9）以及步骤S100）-步骤S200）。
S1）制作一柔性基板11。在制作所述柔性基板11步骤中，先提供一基板，在基板上涂覆聚亚酰胺材料，形成柔性基层111，在所述柔性基层111的表面沉积氧化硅或氮化硅材料形成氧化硅层或氮化硅层或氮化硅叠层以作为所述阻隔层112。
S2）在所述柔性基板11上沉积有源层12以及晶化所述有源层12。所述有源层12所用材料为无定形硅（a-Si），并且所述有源层12是通过气象沉积法沉积而成。
S3）在所述柔性基板11以及所述有源层12上沉积第一栅极绝缘层13。所述第一栅极绝缘层13为氧化硅层、氮化硅层或氮化硅叠层。所述第一栅极绝缘层13是通过气象沉积法沉积而成。
S100）对所述有源层12中的源极区121和漏极区122进行P型重掺杂。具体地讲，就是在所述第一栅极绝缘层13上方覆盖一第一栅极光罩，对所述有源层12中的源极区121和漏极区122进行P型重掺杂。
S200）活化处理P型重掺杂后的所述源极区121和所述漏极区122，其中活化温度为450℃，活化时间为30-60分钟。本发明阵列基板的制作方法将P型重掺杂和活化工艺，即步骤S100）和步骤S200），提前到步骤S4），也就是提前到沉积所述第一栅极层14之前，从而防止所述第一栅极层14经活化的高温后（活化温度一般为450℃，活化时间为60分钟），其阻抗会变大的情况，本实施例中，P型重掺杂用第一栅极光罩去实现掺杂，不需新增光罩。
S4）在所述第一栅极绝缘层13上沉积第一栅极层14，并蚀刻图案化所述第一栅极层14形成第一栅极14a（见图1）。其中，所述第一栅极层14为多层复合金属层2，所述第一栅极层14形成钛-铝-钛的金属层状结构。所述第二栅极绝缘层15为氧化硅层、氮化硅层或氮化硅叠层。在本实施例中，通过在所述第一栅极绝缘层13上方覆盖一第一栅极光罩，并利用黄光对所述第一栅极层14进行蚀刻图案化以形成所述第一栅极14a。
S5）在所述第一栅极绝缘层13和所述第一栅极层14上沉积第二栅极绝缘层15。
S6）在所述第二栅极绝缘层15上沉积第二栅极层16，，并蚀刻图案化所述第二栅极层16形成第二栅极16a（见图1）。其中，所述第二栅极层16为多层复合金属层2，所述第二栅极层16形成钼-铝-钼的金属层状结构。在本实施例中，在所述第二栅极绝缘层15上方覆盖一第二栅极光罩，并利用黄光对所述第二栅极层16进行蚀刻图案化以形成所述第二栅极16a。
S7）在所述第二栅极绝缘层15和所述第二栅极层16上沉积层间绝缘层17；所述层间绝缘层17为氧化硅层、氮化硅层或氮化硅叠层。
S8）氢化处理活化后的所述第一栅极绝缘层13和第二栅极绝缘层15，其中，氢化温度为330-370℃，氢化时间为30-60min；本实施例中，活化主要是使有源层12晶体结构重排，掺杂元素离子均匀扩散到掺杂区晶格位置，需要较高的温度；而氢化就是对栅极绝缘层进行补氢，减少栅极绝缘层与有源层12界面缺陷，相对较低的温度就可起到氢化效果，将活化和氢化工艺分离，即 P型掺杂完成后就做活化，而氢化工艺在所述层间绝缘层17成膜后进行，氢化工艺中采用低温氢化工艺330-370℃，既可避免所述第一栅极层14连续的经受高温制程，又可保证对阵列基板10进行氢化和活化作用。
S9）在所述源极区121和所述漏极区122蚀刻形成从所述层间绝缘层17贯穿至所述有源层12上的接触孔101。在本实施例中，在所述层间绝缘层17上方覆盖一接触孔101光罩，然后在所述源极区121和所述漏极区122通过黄光蚀刻形成所述接触孔101。
S10）在所述层间绝缘层17上以及所述接触孔101中沉积源极18和漏极19。
本实施例中，所述阵列基板10还可以包括如阳极走线、像素定义层等其他的器件或功能层，而本发明的阵列基板10的改进点在于栅极层的改进以及制作方法中活化和氢化步骤顺序的改进，因此，对于阳极走线、像素定义层等其他的器件或功能层可以参照现有技术，对此不在一一赘述。
如图5所示，本发明还提供了一种显示面板1，包括所述的阵列基板10以及与阵列基板10相对设置的彩膜基板20，当然本发明中显示面板1还可以包括偏光片等器件。本实施例中的显示面板1主要的改进在于阵列基板10，因此，对于其他的如偏光片等器件就不在赘述。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种阵列基板，其包括
    柔性基板；
    有源层，覆于所述柔性基板上；
    第一栅极绝缘层，覆于所述有源层上；
    第一栅极层，设于所述第一栅极绝缘层上，所述第一栅极层为多层复合金属层；
    第二栅极绝缘层，覆于所述第一栅极绝缘层和所述第一栅极层上；以及
    第二栅极层，设于所述第二栅极绝缘层上，所述第二栅极层为多层复合金属层。
  2. 根据权利要求1所述的阵列基板，其中，所述多层复合金属层包括
    第一金属层和第二金属层；以及
    第三金属层，设于所述第一金属层和第二金属层之间；
    其中，所述第一金属层和第二金属层所用金属为钛或钼；所述第二金属层所用金属为铝。
  3. 根据权利要求2所述的阵列基板，其中，所述多层复合金属层中，所述第三金属层的厚度为100-120nm；所述第一金属层和所述第二金属层的厚度均为30-50nm。
  4. 根据权利要求1所述的阵列基板，其中，所述有源层所用材料为无定形硅；所述第一栅极绝缘层为氧化硅层、氮化硅层或氮化硅叠层；所述第二栅极绝缘层为氧化硅层、氮化硅层或氮化硅叠层。
  5. 根据权利要求1所述的阵列基板，其中，所述有源层具有源极区和漏极区；所述阵列基板还包括
    层间绝缘层，覆于所述第二栅极绝缘层和第二栅极上；
    接触孔，从所述层间绝缘层贯穿至所述有源层，其中一所述接触孔对应所述源极区，另一所述接触孔对应所述漏极区；
    源极，设于所述层间绝缘层上并通过对应的所述接触孔连接至所述源极区；以及
    漏极，设于所述层间绝缘层上并通过对应的所述接触孔连接至所述漏极区；
    所述柔性基板包括
    柔性基层；以及
    阻隔层，设于所述柔性基层上，所述有源层设于所述阻隔层上。
  6. 一种所述阵列基板的制作方法，其包括以下步骤：
    S1）制作一柔性基板；
    S2）在所述柔性基板上沉积有源层以及晶化所述有源层；
    S3）在所述柔性基板以及所述有源层上沉积第一栅极绝缘层；
    S4）在所述第一栅极绝缘层上沉积第一栅极层，并蚀刻图案化所述第一栅极层形成第一栅极，其中所述第一栅极层为多层复合金属层；
    S5）在所述第一栅极绝缘层和所述第一栅极层上沉积第二栅极绝缘层；以及
    S6）在所述第二栅极绝缘层上沉积第二栅极层，并蚀刻图案化所述第二栅极层形成第二栅极；其中所述第二栅极层为多层复合金属层。
  7. 根据权利要求6所述的阵列基板的制作方法，其中，所述有源层包括源极区和漏极区；
    在所述步骤S3）和步骤S4）之间还包括以下步骤：
    S100）对所述有源层中的所述源极区和所述漏极区进行P型重掺杂；以及
    S200）活化处理P型重掺杂后的所述源极区和所述漏极区，其中活化温度为450℃，活化时间为30-60分钟。
  8. 根据权利要求7所述的阵列基板的制作方法，其中，在所述步骤S6）之后还包括以下步骤：
      S7）在所述第二栅极绝缘层和所述第二栅极层上沉积层间绝缘层；
      S8）氢化处理活化后的所述第一栅极绝缘层和第二栅极绝缘层，其中，氢化温度为330-370℃,氢化时间为30-60min；
      S9）在所述源极区和所述漏极区蚀刻形成从所述层间绝缘层贯穿至所述有源层上的接触孔；以及
      S10）在所述层间绝缘层上以及所述接触孔中沉积源极和漏极。
  9. 根据权利要求6所述的阵列基板的制作方法，其中，所述多层复合金属层包括
    第一金属层；
    第二金属层；以及
    第三金属层，设于所述第一金属层和第二金属层之间；
    其中，所述第一金属层和第二金属层所用金属为钛或钼；所述第二金属层所用金属为铝。
  10. 一种显示面板，其包括如权利要求1所述的阵列基板。
PCT/CN2019/071346 2018-12-05 2019-01-11 阵列基板及其制作方法、显示面板 Ceased WO2020113771A1 (zh)

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CN110610967A (zh) 2019-08-28 2019-12-24 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN110828478A (zh) * 2019-10-29 2020-02-21 武汉华星光电半导体显示技术有限公司 一种tft阵列基板、其显示面板及其终端装置
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