WO2020113681A1 - 阵列基板的制备方法、阵列基板及显示面板 - Google Patents

阵列基板的制备方法、阵列基板及显示面板 Download PDF

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Publication number
WO2020113681A1
WO2020113681A1 PCT/CN2018/121895 CN2018121895W WO2020113681A1 WO 2020113681 A1 WO2020113681 A1 WO 2020113681A1 CN 2018121895 W CN2018121895 W CN 2018121895W WO 2020113681 A1 WO2020113681 A1 WO 2020113681A1
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Prior art keywords
array substrate
area
terminal
insulating film
insulating
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English (en)
French (fr)
Inventor
何怀亮
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HKC Co Ltd
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HKC Co Ltd
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Priority to US17/043,678 priority Critical patent/US11289516B2/en
Publication of WO2020113681A1 publication Critical patent/WO2020113681A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers

Definitions

  • the present application relates to the field of liquid crystal panels, and in particular, to a method for preparing an array substrate, an array substrate, and a display panel.
  • LCD Liquid Crystal Display
  • TFT Thin Film Transistor
  • the thin film transistors are electrically connected and provided with wiring lines of driving terminals arranged to apply voltage to the TFTs, which are closely arranged.
  • the drive terminals are easily affected by dust and other particles, so that the drive terminals are electrically connected to each other, that is, a short circuit occurs between the drive terminals.
  • the main purpose of the present application is to provide a method for preparing an array substrate, an array substrate and a display panel, aiming to solve the problem that the distance between the drive terminals is too small, and the drive terminals are easily affected by dust and other particles, so that the drive terminals There is a problem of short circuit.
  • the present application proposes an array substrate.
  • the array substrate includes a display area and a terminal area provided at an edge of the display area;
  • a plurality of thin film transistor structures are provided in the display area, and a plurality of drive terminals are provided at intervals in the terminal area, and the drive terminals are electrically connected to the thin film transistor structure;
  • an insulating film is provided above the spacing area of the plurality of driving terminals to shield the spacing area.
  • the present application also proposes a display panel, the display panel including an array substrate;
  • the array substrate includes a display area and a terminal area provided at the edge of the display area;
  • the display area is provided with a plurality of thin film transistor structures, and the terminal area is provided with a plurality of drive terminals at intervals, and the drive terminals are electrically connected to the thin film transistor structure; a plurality of drive terminals are provided above the spaced area There is an insulating film to cover the space area,
  • the technical solution provided by the present application includes a display area and a terminal area provided at the edge of the display area.
  • the display area is provided with a plurality of thin film transistor structures
  • the terminal area is provided with a plurality of drive terminals at intervals.
  • the drive terminal and the thin film transistor structure are electrically
  • an insulating film is provided above the spacing area of the plurality of drive terminals to shield the spacing area.
  • an insulating film may be formed above the spaced region of the drive terminal to block particles such as ash layer from falling into the spaced region, so as to reduce the occurrence of short circuit of the drive terminal.
  • the present application also proposes a method for preparing an array substrate.
  • the method for preparing the array substrate includes:
  • Insulating photoresist is coated on the side of the array substrate on which the drive terminals are provided, and the insulating photoresist is exposed, developed, and baked to form an insulating film over the space between the drive terminals .
  • the technical solution provided by the present application includes depositing a metal layer on the array substrate, so that the metal layer forms a plurality of spaced drive terminals in the terminal area of the array substrate, and the drive is provided on the array substrate An insulating photoresist is coated on one side of the terminal, and the insulating photoresist is exposed, developed, and baked to form an insulating film over the spaced region of the drive terminal.
  • an insulating film can be formed above the spacing area of the driving terminal to block particles such as the ash layer from falling into the spacing area, so as to reduce the occurrence of short-circuiting of the driving terminal.
  • 1 is a schematic structural diagram of an array substrate of the present application.
  • FIG. 2 is a schematic diagram of the structure of the drive terminal and the insulating film of this application;
  • FIG. 3 is a flow chart of steps of an embodiment of a method for manufacturing an array substrate of the present application
  • FIG. 4 is a flow chart of steps of another embodiment of a method for manufacturing an array substrate of the present application.
  • FIG. 5 is a flow chart of steps of still another embodiment of a method for manufacturing an array substrate of the present application.
  • FIG. 6 is a flowchart of steps of still another embodiment of a method for manufacturing an array substrate of the present application.
  • FIG. 1 is a schematic structural diagram of an array substrate of the present application
  • FIG. 2 is a schematic structural diagram of a driving terminal 21 and an insulating film 3 of the present application.
  • the present application proposes an array substrate.
  • the array substrate includes a display area 1 and a terminal area 2 disposed on the edge of the display area 1.
  • the display area 1 is provided with a plurality of thin film transistor structures 4, and the terminal area 2 is provided with a plurality of drive terminals 21 at intervals, the drive terminals 21 are electrically connected to the thin film transistor structure 4; wherein, the plurality of drive terminals 21 An insulating film 3 is provided above the partition area to shield the partition area.
  • the middle area on the array substrate is the display area 1, and the A, B, C, and D areas around the display area 1 are non-display areas, and the A, B, and C areas with connection circuits are the terminal areas 2.
  • D area without connecting circuit is non-COF (Chip On Flex flip chip) edge.
  • the driving terminal 21 is provided on the terminal area 2 through the manufacturing process of the driving terminal 21, wherein, as shown in FIG. 1, the array substrate is a rectangular substrate, that is, the regions A and B in the figure are the short sides of the rectangular substrate. Its length is short, that is, in FIG. 1, the terminal area 2 where the areas A and B only show a group of drive terminals 21, and each drive terminal 21 in the group of drive terminals 21 is spaced apart.
  • one set of driving terminals 21 is not limited, but may also be two sets, five sets, etc. Specifically, it can be set according to the length of the A and B areas, and there is no limitation here.
  • the area C is the long side of the rectangular substrate, and its length is longer than that of the areas A and B. That is, in FIG. 1, the terminal area 2 where the area C is located shows five sets of drive terminals 21, the five sets The drive terminals 21 of the drive terminals 21 are arranged at intervals, and the drive terminals 21 of each group are arranged at larger intervals to prevent the drive terminals 21 of the drive terminals 21 of each group from being connected to cause a short circuit.
  • five groups of driving terminals 21 are not limited, and more groups, such as six groups and seven groups, may be set, which may be set according to the length of the C region, which is not limited herein.
  • the array substrate may also be a substrate such as a square, and the number of driving terminals 21 is also selected according to the length of the terminal area 2, which is not limited herein.
  • a plurality of thin film transistor structures 4 are provided in the display area 1, the thin film transistor structures are electrically connected to the driving terminal 21, and the driving terminal 21 is configured to connect to an external voltage generating device and transmit the voltage generated by the voltage generating device To the thin film transistor structure 4, that is, an external voltage generating device applies a voltage to the thin film transistor structure 4 through the drive terminal 21, so that the thin film transistor structure 4 works normally.
  • a space area is provided between each drive terminal 21, and the smaller the space area between the drive terminals 21 in each group, the more traces electrically connected to the thin film transistor structure 4 and Finer, that is, the resolution and resolution of the display area 1 can be improved.
  • the spacing area between the drive terminals 21 in each group is small.
  • two adjacent drive terminals 21 of the same group are turned on and short-circuited.
  • an insulating film 3 is provided above the space between two adjacent drive terminals 21 of the same group to shield the space and prevent particles such as ash layer from falling into the space, which can effectively reduce the short circuit of the drive terminals 21 happening.
  • the technical solution provided by the present application includes a display area 1 and a terminal area 2 provided at the edge of the display area 1, a plurality of thin film transistor structures 4 are provided in the display area 1, and a plurality of drive terminals 21 are provided at intervals in the terminal area 2,
  • the driving terminal 21 is electrically connected to the thin film transistor structure 4, wherein an insulating film 3 is provided above the spacing area of the plurality of driving terminals 21 to shield the spacing area.
  • the insulating film 3 can be formed above the spaced region of the driving terminal 21 to block particles such as the ash layer from falling into the spaced region, so as to reduce the occurrence of short circuit of the driving terminal 21.
  • the projection of the insulating film 3 on the spaced region is greater than the spaced distance of the spaced region.
  • the spacing area is the distance between two adjacent drive terminals 21 of the same group, that is, the lateral width D1 of the insulating film 3 is greater than the spacing distance D2 of the spacing area, so that the insulating film 3 can cover the Space the area and cover it.
  • the insulating film 3 is a transparent film and is adhered to two adjacent drive terminals 21 in the same group.
  • the insulating film 3 has insulating properties, and the insulating properties prevent the two adjacent drive terminals 21 of the same group from communicating with each other.
  • the insulating film 3 is a photoresist of polytetrafluoroethylene material, that is, the insulating film 3 is PFA (Polytetrafluoro) ethylene polytetrafluoroethylene) photoresist.
  • PFA Polytetrafluoro
  • the PFA photoresist material is applied on the drive terminal 21 by a coating method, and the coated PFA photoresist material is exposed, developed, and baked to form the drive terminal
  • An insulating film 3 is formed above 21 to block particles such as ash layer from falling into the spaced area, thereby reducing the occurrence of short circuit of the drive terminal 21.
  • a avoidance area is also formed between the driving terminals 21, and the distance of the escape area is greater than the separation distance of the separation area. That is, an avoidance area is formed between the adjacent two sets of drive terminals 21, for example, the terminal area 2 where the area C is located is provided with five sets of drive terminals 21, and two avoidance areas are formed between the five sets of drive terminals 21. The distance is greater than the separation distance between the two adjacent drive terminals 21 of the same group to ensure that there is no conduction between the adjacent two sets of drive terminals 21, thereby avoiding the occurrence of a short circuit.
  • the technical solution provided by the present application includes a display area 1 and a terminal area 2 provided at the edge of the display area 1, a plurality of thin film transistor structures 4 are provided in the display area 1, and a plurality of drive terminals 21 are provided at intervals in the terminal area 2,
  • the driving terminal 21 is electrically connected to the thin film transistor structure 4, wherein an insulating film 3 is provided above the spacing area of the plurality of driving terminals 21 to shield the spacing area.
  • the insulating film 3 may be formed above the spaced region of the driving terminal 21 to block particles such as the ash layer from falling into the spaced region, so as to reduce the occurrence of short-circuiting of the driving terminal 21.
  • the embodiments of the present application further provide a display panel, which includes an array substrate.
  • the array substrate includes a display area and a terminal area provided at the edge of the display area;
  • a plurality of thin film transistor structures are provided in the display area, a plurality of drive terminals are spaced in the terminal area, and the drive terminals are electrically connected to the thin film transistor structure; an insulating film is provided above the space area of the plurality of drive terminals to shield the space area .
  • the display panel according to an embodiment of the present application has all the technical features of the array substrate of the above embodiment, it should be understood that the display panel of this embodiment has all the technical features and technical effects of the array substrate of the above embodiment. For specific reference to the above embodiment, I will not repeat them here.
  • FIG. 3 is a flow chart of steps of an embodiment of a method for manufacturing an array substrate of the present application.
  • the present application proposes a method for preparing an array substrate. Based on the above embodiment, the method for preparing the array substrate includes:
  • a metal layer is deposited on the array substrate.
  • the material of the metal layer may be chromium, molybdenum, aluminum, copper, titanium, tantalum, or tungsten, etc., and a photo mask is used to pattern the metal layer , So that the metal layer forms a plurality of spaced drive terminals in the terminal area of the array substrate.
  • the middle area on the array substrate is the display area, and the A, B, C, and D areas around the display area are the non-display areas, and there are A, B, and C areas connected to the circuit. It is a terminal area, and the D area where no circuit is connected is the non-COF side. That is, the drive terminals are provided in the areas A, B, and C.
  • an insulating photoresist is coated on the side of the array substrate on which the drive terminals are provided, and the insulating photoresist is exposed, developed, and baked to form an insulating film over the space between the drive terminals.
  • the insulating film is a photoresist of polytetrafluoroethylene, that is, the insulating film is PFA (Polytetrafluoro) ethylene polytetrafluoroethylene) photoresist.
  • PFA Polytetrafluoro
  • the PFA photoresist material is applied on the top of the drive terminal by coating, and the coated PFA photoresist material is exposed, developed, and baked to form An insulating film is formed on the top to block particles such as ash layer from falling into the space area, thereby reducing the occurrence of short-circuiting of the drive terminals.
  • step S10 a space area is provided between each drive terminal.
  • the space area between the drive terminals in each group is smaller, there are more traces electrically connected to the thin film transistor structure and Finer, that is, it can improve the resolution and resolution of the display area.
  • the space area between the drive terminals in each group is small.
  • two adjacent drive terminals of the same group are turned on and short-circuited.
  • An insulating film is formed by coating, exposing, developing, and baking the insulating photoresist above the spacing area of two adjacent drive terminals of the same group to block the spacing area and prevent particles such as ash layer from falling into the spacing area, That can effectively reduce the occurrence of short-circuiting of the drive terminals.
  • the technical solution provided by the present application includes depositing a metal layer on the array substrate, so that the metal layer forms a plurality of spaced drive terminals in the terminal area of the array substrate, and the drive is provided on the array substrate An insulating photoresist is coated on one side of the terminal, and the insulating photoresist is exposed, developed, and baked to form an insulating film over the spaced region of the drive terminal.
  • an insulating film can be formed above the spacing area of the driving terminal to block particles such as the ash layer from falling into the spacing area, so as to reduce the occurrence of short-circuiting of the driving terminal.
  • the step of S20 further includes:
  • the developing solution reacts with and dissolves the unexposed insulating photoresist, and the exposed insulating photoresist is retained and cured by baking to form an insulating film above the spacing area of the driving terminal.
  • an insulating photoresist is coated on the side of the array substrate where the drive terminals are provided, and a photomask is provided above the insulating photoresist, and the photomask is provided with an opening corresponding to the position of the space between the drive terminals, wherein, The size of the opening is greater than the separation distance of the separation area.
  • the methods of coating the insulating photoresist include spin coating (Spin Coater), blade coating and spin coating (Sit & Spin Coater) and Fine Slit Coater) Three types, in this embodiment, a fine scraping method is used to ensure the uniformity of the thickness of the formed insulating film.
  • spin Coater spin Coater
  • blade coating and spin coating spin coating
  • Fine Slit Coater Three types, in this embodiment, a fine scraping method is used to ensure the uniformity of the thickness of the formed insulating film.
  • a photomask is provided above the insulating photoresist, wherein the photomask is provided with an opening corresponding to the position of the driving terminal spacing area, wherein the size of the opening is greater than the spacing distance of the spacing area
  • the spacing area of the driving terminals should be the spacing area between two adjacent driving terminals of the same group.
  • the insulating photoresist in the spaced region of the driving terminal is irradiated with ultraviolet light through a photomask to expose the insulating material in the spaced region. Since the photomask is provided with an opening, that is, when the insulating photoresist is exposed to ultraviolet light, the area corresponding to the opening of the insulating photoresist is the exposed photoresist, and the other part is the unexposed insulating photoresist.
  • the developing solution reacts with and dissolves the unexposed insulating photoresist, and the exposed insulating photoresist is retained and cured by baking to form an insulating film over the spaced region of the driving terminal.
  • the developer is an alkaline developer.
  • the alkaline developer is a strong alkaline developer based on a KOH (potassium hydroxide) developer.
  • the developing solution may also be other types of developing solutions, such as a bicarbonate-based weak alkaline developing solution.
  • the developer reacts quickly with the unexposed insulating photoresist and is dissolved, and the exposed insulating photoresist is retained, that is, the insulating photoresist on the space between the two drive terminals is retained After that, the remaining insulating photoresist is cured by baking, so that an insulating film is formed above the space area of the drive terminal, and particles such as the gray layer are blocked from falling into the space area to reduce the short circuit of the drive terminal happening.
  • the method further includes:
  • the array substrate is cleaned by a physical method to avoid the dirt on the array substrate affecting the metal layer deposition or insulating photoresist coating. Uniformity will inevitably cause pollution to the drive terminals or the insulating film.
  • the array substrate can be cleaned by a physical method, that is, the physical cleaning method includes the extreme violet light (Excimer UV) cleaning, atmospheric pressure plasma (Atmosphere Pressure Plasma) cleaning, etc., there is no limit here.
  • the physical cleaning method includes the extreme violet light (Excimer UV) cleaning, atmospheric pressure plasma (Atmosphere Pressure Plasma) cleaning, etc., there is no limit here.
  • the surface contact angle of the array substrate can be reduced, thereby enhancing the hydrophilicity of the formed insulating film and the array substrate.
  • the method further includes:
  • the array substrate is chemically cleaned to avoid contamination on the array substrate by metal layer deposition or insulating photoresist coating. Uniformity will inevitably cause pollution to the drive terminals or the insulating film.
  • the array substrate can be cleaned by a chemical method, that is, the chemical cleaning method includes shower (shower) and bubble jet (cavitation) Jat) Wait, there is no limit here.
  • the chemical cleaning method includes shower (shower) and bubble jet (cavitation) Jat) Wait, there is no limit here.
  • the surface contact angle of the array substrate can be reduced, thereby enhancing the hydrophilicity of the formed insulating film and the array substrate.
  • the technical solution provided by the present application includes depositing a metal layer on the array substrate, so that the metal layer forms a plurality of spaced drive terminals in the terminal area of the array substrate, and the drive is provided on the array substrate An insulating photoresist is coated on one side of the terminal, and the insulating photoresist is exposed, developed, and baked to form an insulating film over the spaced region of the drive terminal.
  • an insulating film can be formed above the spacing area of the driving terminal to block particles such as the ash layer from falling into the spacing area, so as to reduce the occurrence of short-circuiting of the driving terminal.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

一种阵列基板，所述阵列基板包括显示区（1）以及设置在显示区（1）边缘的端子区（2），显示区（1）中设置有多个薄膜晶体管结构（4），端子区（2）中间隔设置有多个驱动端子（21），驱动端子（21）与薄膜晶体管结构（4）电连接，其中，多个驱动端子（21）的间隔区域上方设置有绝缘薄膜（3），以遮挡间隔区域。

Description

阵列基板的制备方法、阵列基板及显示面板
技术领域
本申请涉及液晶面板领域，特别涉及一种阵列基板的制备方法、阵列基板及显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
LCD ( Liquid Crystal Display )显示器技术越来越成熟，为了追求显示面板高解析度以及高分辨率，一般将显示面板上与TFT(Thin Film Transistor 薄膜晶体管)电连接并设置为给TFT施加电压的驱动端子的走线排布得很密集。
而由于驱动端子之间距离过小，导致驱动端子之间容易受到灰尘等颗粒的影响，使驱动端子之间相互导通，即驱动端子之间出现短路的情况。
申请内容
本申请的主要目的是提供一种阵列基板的制备方法、阵列基板及显示面板，旨在解决由于驱动端子之间距离过小，导致驱动端子之间容易受到灰尘等颗粒的影响，使驱动端子之间出现短路情况的问题。
为实现上述目的，本申请提出了一种阵列基板，所述阵列基板包括显示区以及设置在所述显示区边缘的端子区；
所述显示区中设置有多个薄膜晶体管结构，所述端子区中间隔设置有多个驱动端子，所述驱动端子与所述薄膜晶体管结构电连接；
其中，多个所述驱动端子的间隔区域上方设置有绝缘薄膜，以遮挡所述间隔区域。
此外，本申请还提出了一种显示面板，所述显示面板包括阵列基板；
其中，所述阵列基板包括显示区以及设置在所述显示区边缘的端子区；
所述显示区中设置有多个薄膜晶体管结构，所述端子区中间隔设置有多个驱动端子，所述驱动端子与所述薄膜晶体管结构电连接；多个所述驱动端子的间隔区域上方设置有绝缘薄膜，以遮挡所述间隔区域，
在本申请提供的技术方案中包括显示区以及设置在显示区边缘的端子区，显示区中设置有多个薄膜晶体管结构，端子区中间隔设置有多个驱动端子，驱动端子与薄膜晶体管结构电连接，其中，多个驱动端子的间隔区域上方设置有绝缘薄膜，以遮挡间隔区域。这样，本申请可以通过在所述驱动端子的间隔区域上方形成绝缘薄膜的设置，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子出现短路的情况。
此外，本申请还提出了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子；以及
在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。
在本申请提供的技术方案中包括在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子，在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。这样，本申请可以在所述驱动端子的间隔区域上方形成绝缘薄膜，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子出现短路的情况。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的获得其他的附图。
图1为本申请阵列基板的结构示意图；
图2为本申请驱动端子与绝缘薄膜的结构示意图；
图3为本申请阵列基板的制备方法一实施例的步骤流程图；
图4为本申请阵列基板的制备方法另一实施例的步骤流程图；
图5为本申请阵列基板的制备方法又一实施例的步骤流程图；
图6为本申请阵列基板的制备方法再一实施例的步骤流程图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
如图1为本申请阵列基板的结构示意图，如图2为本申请驱动端子21与绝缘薄膜3的结构示意图。参照图1和图2，本申请提出了一种阵列基板，阵列基板包括显示区1以及设置在显示区1边缘的端子区2。
在一实施例中，显示区1中设置有多个薄膜晶体管结构4，端子区2中间隔设置有多个驱动端子21，驱动端子21与薄膜晶体管结构4电连接；其中，多个驱动端子21的间隔区域上方设置有绝缘薄膜3，以遮挡间隔区域。
如图1所示，阵列基板上的中间区域为显示区1，显示区1周边的A、B、C、D区域为非显示区，其中有连接电路的A、B、C区域为端子区2，没有连接电路的D区域为非COF(Chip On Flex覆晶薄膜)边。
在一实施例中，通过驱动端子21制程将驱动端子21设于端子区2上，其中，如图1，阵列基板为长方形基板，即在图示中A、B区域为长方形基板的短边，其长度较短，即在图1中，A、B区域所在的端子区2仅示出了一组驱动端子21，该组驱动端子21中的各个驱动端子21均间隔设置，当然，在一实施例中，并不限定设置一组驱动端子21，还可以是两组、五组等，具体可以根据A、B区域的长度来设置，在此并无限制。
而在图示中C区域为长方形基板的长边，其长度比A、B区域的长度长，即在图1中，C区域所在的端子区2示出了五组驱动端子21，该五组驱动端子21中的各个驱动端子21均间隔设置，且各组驱动端子21之间以更大的间隔设置，防止各组驱动端子21中的驱动端子21连接，以造成短路。当然，在其他实施例中，并不限定设置五组驱动端子21，还可以设置成更多组，比如六组、七组等，具体可以根据C区域的长度来设置，在此并无限制。
在一实施例中，阵列基板还可以为正方形等基板，而驱动端子21数量的设置也是根据端子区2的长度来选定，在此并无限制。
在一实施例中，显示区1中设置有多个薄膜晶体管结构4，薄膜晶体管结构与驱动端子21电连接，驱动端子21设置为连接外部的电压发生装置，并将电压发生装置产生的电压传输至薄膜晶体管结构4，即外部的电压发生装置通过驱动端子21将电压施加于薄膜晶体管结构4，从而使薄膜晶体管结构4正常工作。
在一实施例中，每个驱动端子21之间都设置有间隔区域，当每一组中的驱动端子21之间的间隔区域越小，即与其电连接薄膜晶体管结构4的走线更多且更精细，即能够提高显示区1的分辨率以及解析度。
在一实施例中，在每一组中的驱动端子21之间的间隔区域较小，为了防止灰层等颗粒掉入间隔区域导致同一组相邻的两个驱动端子21导通而出现短路的情况，在同一组相邻的两个驱动端子21的间隔区域上方设置有绝缘薄膜3，以遮挡间隔区域，防止灰层等颗粒掉入该间隔区域，即能有效地降低驱动端子21出现短路的情况。
在本申请提供的技术方案中包括显示区1以及设置在显示区1边缘的端子区2，显示区1中设置有多个薄膜晶体管结构4，端子区2中间隔设置有多个驱动端子21，驱动端子21与薄膜晶体管结构4电连接，其中，多个驱动端子21的间隔区域上方设置有绝缘薄膜3，以遮挡间隔区域。这样，本申请可以通过在所述驱动端子21的间隔区域上方形成绝缘薄膜3的设置，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子21出现短路的情况。
在一实施例中，如图2所示，绝缘薄膜3在间隔区域的投影大于间隔区域的间隔距离。具体地，该间隔区域为同一组相邻的两个驱动端子21之间的距离，即绝缘薄膜3横向的宽度D1大于该间隔区域的间隔距离D2，从而使该绝缘薄膜3能够盖设于该间隔区域，并遮挡住该间隔区域。
在一实施例中，绝缘薄膜3为透明薄膜，且粘附于同一组相邻的两个驱动端子21上。绝缘薄膜3具有绝缘性，并通过其绝缘性防止同一组相邻的两个驱动端子21之间相互连通。
在一实施例中，绝缘薄膜3为聚四氟乙烯材料的光阻，即绝缘薄膜3为PFA（Polytetrafluoro ethylene 聚四氟乙烯）光阻。
在一实施例中，将PFA光阻材料通过涂布的方法，涂布于驱动端子21的上方，并对涂布的PFA光阻材料进行曝光、显影和烘烤的制程后，从而在驱动端子21的上方形成一层绝缘薄膜3，以遮挡住灰层等颗粒掉入该间隔区域，从而降低驱动端子21出现短路的情况。
在一实施例中，驱动端子21之间还形成避让区域，避让区域的距离大于间隔区域的间隔距离。即在相邻两组驱动端子21之间形成避让区域，如，C区域所在的端子区2设置了五组驱动端子21，该五组驱动端子21之间形成两个避让区域，该避让区域的距离大于同组相邻的两个驱动端子21之间的间隔区域的间隔距离，以保证相邻两组驱动端子21之间不会导通，从而避免发生短路的情况。
在本申请提供的技术方案中包括显示区1以及设置在显示区1边缘的端子区2，显示区1中设置有多个薄膜晶体管结构4，端子区2中间隔设置有多个驱动端子21，驱动端子21与薄膜晶体管结构4电连接，其中，多个驱动端子21的间隔区域上方设置有绝缘薄膜3，以遮挡间隔区域。这样，本申请可以通过在所述驱动端子21的间隔区域上方形成绝缘薄膜3的设置，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子21出现短路的情况。
基于上述实施例，本申请实施例还提供了一种显示面板，该显示面板包括阵列基板。
其中，阵列基板包括显示区以及设置在显示区边缘的端子区；
显示区中设置有多个薄膜晶体管结构，端子区中间隔设置有多个驱动端子，驱动端子与薄膜晶体管结构电连接；多个驱动端子的间隔区域上方设置有绝缘薄膜，以遮挡所述间隔区域。
由于本申请一实施例显示面板具备上述实施例阵列基板的所有技术特征，即应该理解的是，本实施例显示面板具备上述实施例阵列基板的所有技术特征以及技术效果，具体参照上述实施例，在此不再赘述。
参照图3为本申请阵列基板的制备方法一实施例的步骤流程图。参阅图3，本申请提出了一种阵列基板的制备方法，基于上述的实施例，所述阵列基板的制备方法包括：
S10、在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子；
S20、在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。
在一实施例中，该阵列基板上沉积金属层，本实施例中金属层的材料可为锘、钼、铝、铜、钛、钽或钨等，并使用光罩对金属层进行图形化处理，以使金属层在阵列基板的端子区形成多个间隔设置的驱动端子。
在一实施例中，如图1所示，阵列基板上的中间区域为显示区，显示区周边的A、B、C、D区域为非显示区，其中有连接电路的A、B、C区域为端子区，没有连接电路的D区域为非COF边。即驱动端子设置在A、B、C区域中。
在一实施例中，在阵列基板上设有驱动端子的一侧涂布绝缘光阻，并对绝缘光阻进行曝光、显影以及烘烤后，以在驱动端子的间隔区域上方形成绝缘薄膜。
在一实施例中，绝缘薄膜为聚四氟乙烯材料的光阻，即绝缘薄膜为PFA（Polytetrafluoro ethylene 聚四氟乙烯）光阻。
在一实施例中，将PFA光阻材料通过涂布的方法，涂布于驱动端子的上方，并对涂布的PFA光阻材料进行曝光、显影和烘烤的制程后，从而在驱动端子的上方形成一层绝缘薄膜，以遮挡住灰层等颗粒掉入该间隔区域，从而降低驱动端子出现短路的情况。
在一实施例中，S10步骤中每个驱动端子之间都设置有间隔区域，当每一组中的驱动端子之间的间隔区域越小，即与其电连接薄膜晶体管结构的走线更多且更精细，即能够提高显示区的分辨率以及解析度。
在一实施例中，在每一组中的驱动端子之间的间隔区域较小，为了防止灰层等颗粒掉入间隔区域导致同一组相邻的两个驱动端子导通而出现短路的情况，在同一组相邻的两个驱动端子的间隔区域上方通过对绝缘光阻进行涂布、曝光、显影以及烘烤形成有绝缘薄膜，以遮挡间隔区域，防止灰层等颗粒掉入该间隔区域，即能有效地降低驱动端子出现短路的情况。
在本申请提供的技术方案中包括在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子，在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。这样，本申请可以在所述驱动端子的间隔区域上方形成绝缘薄膜，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子出现短路的情况。
在一实施例中，参照图4，在S20的步骤中还包括：
S21、在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并在所述绝缘光阻的上方设置光罩，所述光罩对应于所述驱动端子间隔区域的位置设置有开口，其中，所述开口的尺寸大于所述间隔区域间隔距离；
S22、通过所述光罩对所述驱动端子间隔区域的绝缘光阻进行紫外光照射，以对该间隔区域的所述绝缘材料进行曝光；
S23、通过显影液与未被曝光的绝缘光阻发生反应并溶解，且曝光后的绝缘光阻保留并通过烘烤后进行固化，以在所述驱动端子的间隔区域上方形成绝缘薄膜。
在一实施例中，在阵列基板上设有驱动端子的一侧涂布绝缘光阻，并在绝缘光阻的上方设置光罩，光罩对应于驱动端子间隔区域的位置设置有开口，其中，开口的尺寸大于间隔区域间隔距离。
具体地，涂布绝缘光阻的方法包括旋涂法（Spin Coater）、刮涂和旋涂结合法（Sit＆Spin Coater）以及精细刮涂法（Fine Slit Coater）三种，本实施例中采用精细刮涂法，以保证形成的绝缘薄膜厚度的均匀性。当整个阵列基板上均涂布好绝缘光阻后，在绝缘光阻的上方设置光罩，其中，光罩对应于驱动端子间隔区域的位置设置有开口，其中，开口的尺寸大于间隔区域间隔距离，该驱动端子间隔区域应该为同组相邻的两个驱动端子之间的间隔区域。
在一实施例中，通过光罩对驱动端子间隔区域的绝缘光阻进行紫外光照射，以对该间隔区域的绝缘材料进行曝光。由于光罩上设置有开口，即当绝缘光阻进行紫外线曝光时，绝缘光阻部分对应于开口的区域为曝光后的绝缘光阻，其他部分为未被曝光的绝缘光阻。
在一实施例中，通过显影液与未被曝光的绝缘光阻发生反应并溶解，且曝光后的绝缘光阻保留并通过烘烤后进行固化，以在驱动端子的间隔区域上方形成绝缘薄膜。
在一实施例中，该显影液为碱性的显影液，可选地，该碱性的显影液为KOH（氢氧化钾）显影液系的强碱显影液。当然，该显影液还可以为其他类型的显影液，比如，碳酸氢盐系的弱碱显影液。
在一实施例中，该显影液与未被曝光的绝缘光阻迅速发生反应，并被溶解，而曝光后的绝缘光阻被保留，即在两个驱动端子间隔区域上的绝缘光阻被保留，之后，将被保留的绝缘光阻通过烘烤后进行固化，从而使在驱动端子的间隔区域上方形成绝缘薄膜，并遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子出现短路的情况。
在一实施例中，参照图5，在S10的步骤之前还包括：
S01、通过物理的方法对所述阵列基板进行清洗。
在本步骤中，对阵列基板进行金属层沉积或者绝缘光阻涂布之前，通过物理的方法对阵列基板进行清洗，以避免阵列基板上的脏污物影响金属层沉积或者绝缘光阻涂布的均匀性，不免给驱动端子或者绝缘薄膜造成污染。
在一实施例中，可通过物理的方法对阵列基板进行清洗，即物理清洗方法包括极紫光（Excimer UV）清洗、常压等离子体（Atmosphere Pressure Plasma）清洗等，在此并无限制。
在一实施例中，通过对阵列基板的清洗，可以降低阵列基板的表面接触角，从而增强形成的绝缘薄膜与阵列基板的亲水性。
在一实施例中，参照图6，在S10的步骤之前还包括：
S02、通过化学的方法对所述阵列基板进行清洗。
在本步骤中，对阵列基板进行金属层沉积或者绝缘光阻涂布之前，通过化学的方法对阵列基板进行清洗，以避免阵列基板上的脏污物影响金属层沉积或者绝缘光阻涂布的均匀性，不免给驱动端子或者绝缘薄膜造成污染。
在一实施例中，可通过化学的方法对阵列基板进行清洗，即化学清洗方法包括喷淋（Shower）、气泡射流（Cavitation Jat）等，在此并无限制。
在一实施例中，通过对阵列基板的清洗，可以降低阵列基板的表面接触角，从而增强形成的绝缘薄膜与阵列基板的亲水性。
在本申请提供的技术方案中包括在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子，在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。这样，本申请可以在所述驱动端子的间隔区域上方形成绝缘薄膜，遮挡住灰层等颗粒掉入该间隔区域，以降低驱动端子出现短路的情况。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的构思下，利用本申请说明书及附图内容所作的等效变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括显示区以及设置在所述显示区边缘的端子区；
    所述显示区中设置有多个薄膜晶体管结构，所述端子区中间隔设置有多个驱动端子，所述驱动端子与所述薄膜晶体管结构电连接；
    其中，多个所述驱动端子的间隔区域上方设置有绝缘薄膜，以遮挡所述间隔区域。
  2. 根据权利要求1所述的阵列基板，其中，所述绝缘薄膜在所述间隔区域的投影大于所述间隔区域的间隔距离。
  3. 根据权利要求1所述的阵列基板，其中，所述绝缘薄膜为聚四氟乙烯材料的光阻。
  4. 根据权利要求1所述的阵列基板，其中，所述驱动端子之间还形成避让区域，所述避让区域的距离大于所述间隔区域的间隔距离。
  5. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管结构通过所述驱动端子与外部的电压发生装置连接。
  6. 根据权利要求1所述的阵列基板，其中，所述绝缘薄膜为透明薄膜，且所述绝缘薄膜粘附于相邻的两个所述驱动端子上。
  7. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括设于所述显示区周边的非显示区，所述端子区设于所述非显示区的区域。
  8. 一种显示面板，其中，所述显示面板包括阵列基板；
    其中，所述阵列基板包括显示区以及设置在所述显示区边缘的端子区；
    所述显示区中设置有多个薄膜晶体管结构，所述端子区中间隔设置有多个驱动端子，所述驱动端子与所述薄膜晶体管结构电连接；多个所述驱动端子的间隔区域上方设置有绝缘薄膜。
  9. 根据权利要求8所述的显示面板，其中，所述绝缘薄膜在所述间隔区域的投影大于所述间隔区域的间隔距离。
  10. 根据权利要求8所述的显示面板，其中，所述绝缘薄膜为聚四氟乙烯材料的光阻。
  11. 根据权利要求8所述的显示面板，其中，所述驱动端子之间还形成避让区域，所述避让区域的距离大于所述间隔区域的间隔距离。
  12. 根据权利要求8所述的显示面板，其中，所述薄膜晶体管结构通过所述驱动端子与外部的电压发生装置连接。
  13. 根据权利要求8所述的显示面板，其中，所述绝缘薄膜为透明薄膜，且所述绝缘薄膜粘附于相邻的两个所述驱动端子上。
  14. 根据权利要求8所述的显示面板，其中，所述阵列基板包括设于所述显示区周边的非显示区，所述端子区设于所述非显示区的区域。
  15. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子；以及
    在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜。
  16. 根据权利要求15所述的阵列基板的制备方法，其中，所述在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并对所述绝缘光阻进行曝光、显影以及烘烤后，以在所述驱动端子的间隔区域上方形成绝缘薄膜的步骤包括：
    在所述阵列基板上设有所述驱动端子的一侧涂布绝缘光阻，并在所述绝缘光阻的上方设置光罩，所述光罩对应于所述驱动端子间隔区域的位置设置有开口，其中，所述开口的尺寸大于所述间隔区域间隔距离；
    通过所述光罩对所述驱动端子间隔区域的绝缘光阻进行紫外光照射，以对该间隔区域的所述绝缘材料进行曝光；以及
    通过显影液与未被曝光的绝缘光阻发生反应并溶解，且曝光后的绝缘光阻保留并通过烘烤后进行固化，以在所述驱动端子的间隔区域上方形成绝缘薄膜。
  17. 根据权利要求16所述的阵列基板的制备方法，其中，所述涂布绝缘光阻采用精细刮涂法。
  18. 根据权利要求15所述的阵列基板的制备方法，其中，所述在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子的步骤之前，还包括：
    通过物理的方法对所述阵列基板进行清洗。
  19. 根据权利要求15所述的阵列基板的制备方法，其中，所述在阵列基板上沉积金属层，使所述金属层在所述阵列基板的端子区形成多个间隔设置的驱动端子的步骤之前，还包括：
    通过化学的方法对所述阵列基板进行清洗。
  20. 根据权利要求15所述的阵列基板的制备方法，其中，所述绝缘薄膜为聚四氟乙烯材料的光阻。
PCT/CN2018/121895 2018-12-05 2018-12-19 阵列基板的制备方法、阵列基板及显示面板 Ceased WO2020113681A1 (zh)

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